diff --git a/CPE212/Project 1.1/DateType.cpp b/CPE212/Project 1.1/DateType.cpp new file mode 100644 index 0000000..1af449c --- /dev/null +++ b/CPE212/Project 1.1/DateType.cpp @@ -0,0 +1,36 @@ +#include +#include "DateType.h" + +using namespace std; +void DateType::Initialize (int newMonth, int newDay, int newYear) +{ + year=newYear; + month=newMonth; + day=newDay; +} + +int DateType::GetMonth() const +{ + return month; +} + +int DateType::GetYear() const +{ + return year; +} + +int DateType::GetDay() const +{ + return day; +} + +int main() +{ + DateType today; + DateType anotherDay; + today.Initialize(9,24,2003); + anotherDay.Initialize(9,25,2003); + + cout << "Today is " << today.GetMonth() << "/" << today.GetDay() << "/" << today.GetYear()<< endl; + cout << "Another date is " << anotherDay.GetMonth() << "/" << anotherDay.GetDay() << "/" << anotherDay.GetYear() << endl; +} \ No newline at end of file diff --git a/CPE212/Project 1.1/DateType.exe b/CPE212/Project 1.1/DateType.exe new file mode 100755 index 0000000..98ea767 Binary files /dev/null and b/CPE212/Project 1.1/DateType.exe differ diff --git a/CPE212/Project 1.1/DateType.h b/CPE212/Project 1.1/DateType.h new file mode 100644 index 0000000..883524d --- /dev/null +++ b/CPE212/Project 1.1/DateType.h @@ -0,0 +1,12 @@ +class DateType +{ +private: + int year; + int month; + int day; +public: + void Initialize(int newMonth, int newDay, int newYear); + int GetYear() const; + int GetMonth() const; + int GetDay() const; +}; \ No newline at end of file diff --git a/CPE212/Project 1.1/DateType.o b/CPE212/Project 1.1/DateType.o new file mode 100644 index 0000000..5cd1853 Binary files /dev/null and b/CPE212/Project 1.1/DateType.o differ diff --git a/CPE212/Project 1.1/Project1.1a.png b/CPE212/Project 1.1/Project1.1a.png new file mode 100644 index 0000000..d594b00 Binary files /dev/null and b/CPE212/Project 1.1/Project1.1a.png differ diff --git a/CPE212/Project 1.1/Project1.1b.png b/CPE212/Project 1.1/Project1.1b.png new file mode 100644 index 0000000..73f6131 Binary files /dev/null and b/CPE212/Project 1.1/Project1.1b.png differ diff --git a/CPE212/Project_01/main.cpp b/CPE212/Project_01/main.cpp new file mode 100644 index 0000000..ab4ac2d --- /dev/null +++ b/CPE212/Project_01/main.cpp @@ -0,0 +1,173 @@ +// +// main.cpp -- Project01, CPE212 Fall 2010 -- C++ Review Project +// +// Driver program for Image Processing Program which is used to test each +// image processing operation. +// +// DO NOT SUBMIT OR SUBMIT THIS FILE +// + +// List of allowed include files appear below +#include +#include +#include + +using namespace std; // Global using declaration + +// Global Constants -- you may use these global constants in your code +const int MAXROWS = 10; // Maximum number of rows in image +const int MAXCOLS = 10; // Maximum number of columns in image + +// Function Prototypes for functions included at the end of main.cpp +void Print(const int image[MAXROWS][MAXCOLS]); +void Bars(); + +// Function Prototypes for the functions you must implement in project01.cpp +void LoadImage(const string imagefile, int image[MAXROWS][MAXCOLS]); +void FlipHorizontal(int image[MAXROWS][MAXCOLS]); +void FlipVertical(int image[MAXROWS][MAXCOLS]); +void RotateCW(int image[MAXROWS][MAXCOLS]); +void RotateCCW(int image[MAXROWS][MAXCOLS]); +void Transpose(int image[MAXROWS][MAXCOLS]); + + +// Start of main() function + +int main (int argc, char * const argv[]) // Command-line arguments (more on this later) +{ + ifstream inputs; // Input file stream variable for test file + char op, ch; // Hold operation and optional char input from test file + string comment; // Holds comment string input from test file + int image[MAXROWS][MAXCOLS]; // Array of integers representing image + string imagefile; // Name of image file + + + // Output usage message if test input file name is not provided + if (argc != 2) + { + cout << "Usage:\n project01 \n"; + return 1; + } + + // Attempt to open test input file -- terminate if file does not open + inputs.open(argv[1]); + if (!inputs) + { + cout << "Error - unable to open input file" << endl; + return 1; + } + + // Process comment line from input file + getline(inputs, comment); // Input file header comment + cout << endl << comment << endl << endl; // Output file header comment + + + // Below is primary loop that processes each operation appearing within the test file. + // Starts with an initial priming read of first operation + + inputs >> op; // Attempt to input first test operation from file + + while (inputs) // While Not-EOF + { + switch (op) // Process operation input from test file + { + case '#': // Test file comment + getline(inputs, comment); // Input and echo the comment appearing in the test file + cout << '#' << comment << endl; + break; + + case 'p': // Print Grid + Print(image); // Function definition appears at the end of this file + break; + + case 'b': // Print Bars + Bars(); // Function definition appears at the end of this file + break; + + case 'i': // Load Image + inputs >> imagefile; // Input name of imagefile from test file + LoadImage(imagefile, image); // Implement this function in project01.cpp + break; + + case '+': // Rotate Image Clockwise 90 Degrees + RotateCW(image); // Implement this function in project01.cpp + break; + + case '-': // Rotate Image Counterclockwise 90 Degrees + RotateCCW(image); // Implement this function in project01.cpp + break; + + case 'v': // Flip Image Vertical + FlipVertical(image); // Implement this function in project01.cpp + break; + + case 'h': // Flip Image Horizontal + FlipHorizontal(image); // Implement this function in project01.cpp + break; + + case 't': // Transpose Image Across Major Diagonal + Transpose(image); // Implement this function in project01.cpp + break; + + default: // Error + cout << "Error - unrecognized operation '" << op << "'" << endl; + cout << "Terminating now..." << endl; + return 1; + break; + } + cout << endl; + + inputs >> op; // Attempt to input next command + } + + + return 0; +} + +/************** Implementation of Print() and Bars() functions ********************/ + +// DO NOT MODIFY THIS CODE + +void Print(const int image[MAXROWS][MAXCOLS]) +// Print() -- outputs image row-by-row in desired format substituting +// * for 1 and - for 0. +{ + for(int r=0; r < MAXROWS; r++) // Loop to visit each row in image + { + for(int c=0; c < MAXCOLS; c++) // Loop to output every element on crrent row + { + if (image[r][c] == 1) // Output appropriate symbol + { + cout << '*'; + } + else if (image[r][c] == 0) + { + cout << '-'; + } + else + { + cout << 'X'; + } + } + cout << endl; + } + +} // End Print() + +void Bars() +// Bars() -- prints two horizontal rows of bars +{ + cout << "#################################################################" << endl; + cout << "#################################################################" << endl; +} // End Bars() + +/************** DO NOT DELETE *************/ +// The preprocessor directive below will import the function definitions +// from the file project01.cpp and place them at the end of this file creating an +// Expanded Source File which is forwarded to the compiler for compilation. + +#include "project01.cpp" + +/************** End of main.cpp ***************/ + + diff --git a/CPE212/Project_01/makefile b/CPE212/Project_01/makefile new file mode 100644 index 0000000..5b33648 --- /dev/null +++ b/CPE212/Project_01/makefile @@ -0,0 +1,9 @@ +# Project01 -- Fall 2010 CPE212-01 + +project01: project01.cpp main.cpp + g++ main.cpp -o project01 + +clean: + rm project01 + + diff --git a/CPE212/Project_01/p01image1.txt b/CPE212/Project_01/p01image1.txt new file mode 100644 index 0000000..1a2fda4 --- /dev/null +++ b/CPE212/Project_01/p01image1.txt @@ -0,0 +1,13 @@ +# p01image1.txt -- Sample Image #1 + +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 1 1 0 0 0 0 +0 0 0 0 1 1 0 0 0 0 +0 0 1 1 1 1 0 0 0 0 +0 0 1 1 1 1 0 0 0 0 +0 0 0 0 0 0 1 1 0 0 +0 0 0 0 0 0 1 1 0 0 +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 + diff --git a/CPE212/Project_01/p01image2.txt b/CPE212/Project_01/p01image2.txt new file mode 100644 index 0000000..968a314 --- /dev/null +++ b/CPE212/Project_01/p01image2.txt @@ -0,0 +1,13 @@ +# p01image2.txt -- Sample Image #2 + +0 1 1 1 0 1 0 0 0 1 +0 0 0 0 0 0 0 0 0 0 +0 0 0 1 1 0 0 0 0 1 +0 0 0 1 1 0 0 0 0 0 +0 0 0 1 1 1 1 0 0 1 +1 0 0 1 1 1 1 0 0 0 +1 0 0 1 1 0 0 0 0 0 +0 0 0 1 1 0 0 0 0 0 +1 0 0 0 0 0 0 0 0 0 +1 0 0 0 0 1 1 1 1 0 + diff --git a/CPE212/Project_01/p01image3.txt b/CPE212/Project_01/p01image3.txt new file mode 100644 index 0000000..e85aa58 --- /dev/null +++ b/CPE212/Project_01/p01image3.txt @@ -0,0 +1,13 @@ +# p01image3.txt -- Sample Image #3 + +0 0 0 0 0 0 0 0 0 1 +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 +0 0 1 0 0 0 0 0 0 0 +0 1 1 0 0 0 0 0 0 0 +1 1 1 0 0 0 0 0 0 0 + diff --git a/CPE212/Project_01/p01input1.txt b/CPE212/Project_01/p01input1.txt new file mode 100644 index 0000000..1ff0f42 --- /dev/null +++ b/CPE212/Project_01/p01input1.txt @@ -0,0 +1,77 @@ +# p01input1.txt -- Test of Transpose Image + +# Draw Bars +b + +# Load Image1 +i p01image1.txt + +# Print Image1 +p + +# Transpose Image1 +t + +# Print Image1 +p + +# Transpose Image1 +t + +# Print Image1 +p + + +# Draw Bars +b + + +# Load Image2 +i p01image2.txt + +# Print Image2 +p + +# Transpose Image2 +t + +# Print Image2 +p + +# Transpose Image2 +t + +# Print Image2 +p + + +# Draw Bars +b + + +# Load Image3 +i p01image3.txt + +# Print Image3 +p + +# Transpose Image3 +t + +# Print Image3 +p + +# Transpose Image3 +t + +# Print Image3 +p + + +# Draw Bars +b + + + + + diff --git a/CPE212/Project_01/p01input2.txt b/CPE212/Project_01/p01input2.txt new file mode 100644 index 0000000..a92102c --- /dev/null +++ b/CPE212/Project_01/p01input2.txt @@ -0,0 +1,74 @@ +# p01input2.txt -- Test of Horizontal Flip + +# Draw Bars +b + + +# Load Image1 +i p01image1.txt + +# Print Image1 +p + +# Horizontal Flip Image1 +h + +# Print Flipped Image1 +p + +# Horizontal Flip Image1 +h + +# Print Flipped Image1 +p + + +# Draw Bars +b + + +# Load Image2 +i p01image2.txt + +# Print Image2 +p + +# Horizontal Flip Image2 +h + +# Print Flipped Image2 +p + +# Horizontal Flip Image2 +h + +# Print Flipped Image2 +p + + +# Draw Bars +b + +# Load Image3 +i p01image3.txt + +# Print Image3 +p + +# Horizontal Flip Image3 +h + +# Print Flipped Image3 +p + +# Horizontal Flip Image3 +h + +# Print Flipped Image3 +p + + +# Draw Bars +b + + diff --git a/CPE212/Project_01/p01input3.txt b/CPE212/Project_01/p01input3.txt new file mode 100644 index 0000000..f707198 --- /dev/null +++ b/CPE212/Project_01/p01input3.txt @@ -0,0 +1,74 @@ +# p01input3.txt -- Test of Vertical Flip + +# Draw Bars +b + + +# Load Image1 +i p01image1.txt + +# Print Image1 +p + +# Vertical Flip Image1 +v + +# Print Flipped Image1 +p + +# Vertical Flip Image1 +v + +# Print Flipped Image1 +p + + +# Draw Bars +b + + +# Load Image2 +i p01image2.txt + +# Print Image2 +p + +# Vertical Flip Image2 +v + +# Print Flipped Image2 +p + +# Vertical Flip Image2 +v + +# Print Flipped Image2 +p + + +# Draw Bars +b + + +# Load Image3 +i p01image3.txt + +# Print Image3 +p + +# Vertical Flip Image3 +v + +# Print Flipped Image3 +p + +# Vertical Flip Image3 +v + +# Print Flipped Image3 +p + +# Draw Bars +b + + diff --git a/CPE212/Project_01/p01input4.txt b/CPE212/Project_01/p01input4.txt new file mode 100644 index 0000000..1f2a3f9 --- /dev/null +++ b/CPE212/Project_01/p01input4.txt @@ -0,0 +1,117 @@ +# p01input4.txt -- Test of Rotate Clockwise + +# Draw Bars +b + + +# Load Image1 +i p01image1.txt + +# Print Image1 +p + +# Rotate Clockwise 90 Degrees Image1 ++ + +# Print Rotated Image1 +p + +# Rotate Clockwise 90 Degrees Image1 ++ + +# Print Rotated Image1 +p + +# Rotate Clockwise 90 Degrees Image1 ++ + +# Print Rotated Image1 +p + +# Rotate Clockwise 90 Degrees Image1 ++ + +# Print Rotated Image1 +p + + +# Draw Bars +b + + +# Load Image2 +i p01image2.txt + +# Print Image2 +p + +# Rotate Clockwise 90 Degrees Image2 ++ + +# Print Rotated Image2 +p + +# Rotate Clockwise 90 Degrees Image2 ++ + +# Print Rotated Image2 +p + +# Rotate Clockwise 90 Degrees Image2 ++ + +# Print Rotated Image2 +p + +# Rotate Clockwise 90 Degrees Image2 ++ + +# Print Rotated Image2 +p + + +# Draw Bars +b + + + +# Load Image3 +i p01image3.txt + +# Print Image3 +p + +# Rotate Clockwise 90 Degrees Image3 ++ + +# Print Rotated Image3 +p + +# Rotate Clockwise 90 Degrees Image3 ++ + +# Print Rotated Image3 +p + +# Rotate Clockwise 90 Degrees Image3 ++ + +# Print Rotated Image3 +p + +# Rotate Clockwise 90 Degrees Image3 ++ + +# Print Rotated Image3 +p + + +# Draw Bars +b + + + + + + + diff --git a/CPE212/Project_01/p01input5.txt b/CPE212/Project_01/p01input5.txt new file mode 100644 index 0000000..4c4b9f5 --- /dev/null +++ b/CPE212/Project_01/p01input5.txt @@ -0,0 +1,117 @@ +# p01input5.txt -- Test of Rotate Counter Clockwise + + +# Draw Bars +b + + +# Load Image1 +i p01image1.txt + +# Print Image1 +p + +# Rotate Counter Clockwise 90 Degrees Image1 +- + +# Print Rotated Image1 +p + +# Rotate Counter Clockwise 90 Degrees Image1 +- + +# Print Rotated Image1 +p + +# Rotate Counter Clockwise 90 Degrees Image1 +- + +# Print Rotated Image1 +p + +# Rotate Counter Clockwise 90 Degrees Image1 +- + +# Print Rotated Image1 +p + + +# Draw Bars +b + + +# Load Image2 +i p01image2.txt + +# Print Image2 +p + +# Rotate Counter Clockwise 90 Degrees Image2 +- + +# Print Rotated Image2 +p + +# Rotate Counter Clockwise 90 Degrees Image2 +- + +# Print Rotated Image2 +p + +# Rotate Counter Clockwise 90 Degrees Image2 +- + +# Print Rotated Image2 +p + +# Rotate Counter Clockwise 90 Degrees Image2 +- + +# Print Rotated Image2 +p + + +# Draw Bars +b + + +# Load Image3 +i p01image3.txt + +# Print Image3 +p + +# Rotate Counter Clockwise 90 Degrees Image3 +- + +# Print Rotated Image3 +p + +# Rotate Counter Clockwise 90 Degrees Image3 +- + +# Print Rotated Image3 +p + +# Rotate Counter Clockwise 90 Degrees Image3 +- + +# Print Rotated Image3 +p + +# Rotate Counter Clockwise 90 Degrees Image3 +- + +# Print Rotated Image3 +p + + +# Draw Bars +b + + + + + + + diff --git a/CPE212/Project_01/project01 b/CPE212/Project_01/project01 new file mode 100644 index 0000000..50d4f1a Binary files /dev/null and b/CPE212/Project_01/project01 differ diff --git a/CPE212/Project_01/project01.cpp b/CPE212/Project_01/project01.cpp new file mode 100644 index 0000000..fdb6469 --- /dev/null +++ b/CPE212/Project_01/project01.cpp @@ -0,0 +1,155 @@ +/* +Noah Woodlee +CPE212-01 +Project 1, due Sunday, Febuary 21, 2020 +*/ +#include +#include +#include + +// LoadImage defintion +void LoadImage(const string imagefile, int image[MAXROWS][MAXCOLS]) +{ + ifstream input; + input.open(imagefile.c_str()); + if (!input) + { + cout << "Error - File unable to be opened." << endl; + return; + } + int rows, cols, nums; + string str; + getline(input, str); + //cout << str; + for (int r = 0; r < MAXROWS ; r++) // iterate number of rows + { + for (int c = 0; c < MAXCOLS; c++) // iterate number of columns + { + input >> nums; + image[r][c]=nums; + } + } + +} // End of LoadImage + +// Flip Horozontal defintion +void FlipHorizontal(int image[MAXROWS][MAXCOLS]) +{ + int temp; + for (int r = 0; r < MAXROWS; r++) // loop for columns 1 & 10 + { + temp=image[r][0]; + image[r][0]=image[r][MAXCOLS-1]; + image[r][MAXCOLS-1]=temp; + } + for (int r = 0; r < MAXROWS; r++) // loop for columns 2 & 9 + { + temp=image[r][1]; + image[r][1]=image[r][MAXCOLS-2]; + image[r][MAXCOLS-2]=temp; + } + for (int r = 0; r < MAXROWS; r++) // loop for columns 3 & 8 + { + temp=image[r][2]; + image[r][2]=image[r][MAXCOLS-3]; + image[r][MAXCOLS-3]=temp; + } + for (int r = 0; r < MAXROWS; r++) // loop for column 4 & 7 + { + temp=image[r][3]; + image[r][3]=image[r][MAXCOLS-4]; + image[r][MAXCOLS-4]=temp; + } + for (int r = 0; r < MAXROWS; r++) // loop for column 5 & 6 + { + temp=image[r][4]; + image[r][4]=image[r][MAXCOLS-5]; + image[r][MAXCOLS-5]=temp; + } +} // End of FlipHorizontal function + +// FlipVertical defintion +void FlipVertical(int image[MAXROWS][MAXCOLS]) +{ + int temp; + for (int c = 0; c < MAXCOLS; c++) // loop for rows 1 & 10 + { + temp = image[0][c]; + image[0][c] = image[MAXROWS-1][c]; + image[MAXROWS-1][c] = temp; + } + for (int c = 0; c < MAXCOLS; c++) // loop for rows 2 & 9 + { + temp = image[1][c]; + image[1][c] = image[MAXROWS-2][c]; + image[MAXCOLS-2][c] = temp; + } + for (int c = 0; c < MAXCOLS; c++) // loop for rows 3 & 8 + { + temp = image[2][c]; + image[2][c] = image[MAXROWS-3][c]; + image[MAXCOLS-3][c]=temp; + } + for (int c = 0; c < MAXCOLS; c++) // loop for rows 4 & 7 + { + temp = image[3][c]; + image[3][c] = image[MAXROWS-4][c]; + image[MAXCOLS-4][c] = temp; + } + for (int c = 0; c < MAXCOLS; c++) // loop for rows 5 & 6 + { + temp = image[4][c]; + image[4][c] = image[MAXROWS-5][c]; + image[MAXCOLS-5][c] = temp; + } +} + +// RotateCW defintion +void RotateCW(int image[MAXROWS][MAXCOLS]) +{ + int n = MAXCOLS; + for (int i = 0; i < n/2; i++) + { + for (int j = i; j < n-i-1; j++) + { + int temp = image[i][j]; + image[i][j]=image[n-1-j][i]; + image[n - 1 - j][i] = image[n - 1 - i][n - 1 - j]; + image[n - 1 - i][n - 1 - j] = image[j][n - 1 - i]; + image[j][n - 1 - i] = temp; + } + + } + +} + +// RotateCCW defintion +void RotateCCW(int image[MAXROWS][MAXCOLS]) +{ + int n=MAXROWS; + for(int i=0;i +#include +#include "card.h" + +Card::Card() +// Default Constructor: Initializes value to 0, color to "unknown", and suit to 'U' +{ + value=0; + color = "Unknown"; + suit = 'U'; +} + + +Card::Card(int v) +// Parameterized Constructor: Initializes value to v, color to "unknown", and suit to 'U' +{ + value=v; + color = "Unknown"; + suit = 'U'; +} + + +int Card::GetValue() const +// Returns variable value +{ + return value; +} + + +string Card::GetColor() const +// Returns variable color +{ + return color; +} + + +char Card::GetSuit() const +// Returns variable suit +{ + return suit; +} + + +void Card::SetValue(int v) +// Sets value to v +{ + value = v; +} + + +void Card::SetColor(string c) +// Sets color to c +{ + color = c; +} + + +void Card::SetSuit(char s) +// Sets suit to s +{ + suit = s; +} + + +string Card::Description() const +// Outputs card characteristics - value as a string +// DO NOT MODIFY THIS METHOD !!!! +{ + string d = "Value = "; // temporary variable used to accumulate result + + switch (value) // Append card value to variable's value + { + case 2: d = d + "2"; break; // Number cards + case 3: d = d + "3"; break; + case 4: d = d + "4"; break; + case 5: d = d + "5"; break; + case 6: d = d + "6"; break; + case 7: d = d + "7"; break; + case 8: d = d + "8"; break; + case 9: d = d + "9"; break; + case 10: d = d + "10"; break; + case 11: d = d + "J"; break; // Face cards + case 12: d = d + "Q"; break; + case 13: d = d + "K"; break; + case 14: d = d + "A"; break; + + default: d = d + "?"; break; // Unknown card + } + + return d; // Return string describing card value +} + diff --git a/CPE212/Project_02/card.h b/CPE212/Project_02/card.h new file mode 100644 index 0000000..51f64f1 --- /dev/null +++ b/CPE212/Project_02/card.h @@ -0,0 +1,48 @@ +// +// card.h -- CPE 212-01, Fall 2010 -- Project02 -- Classes +// +// Add the missing statements to complete the class declaration below +// and SUBMIT this file for grading !!! +// + +#include +using namespace std; + +#ifndef CARD_H +#define CARD_H + +class Card // Class modeling Card ADT +{ + private: + int value; // Card value: 2-10 for number cards, 11-14 for JQKA; 0 for unknown + string color; // Card color: "red", "black", or "unknown" + char suit; // Card suit: 'H' for hearts, 'D' for diamonds, 'C' for clubs, 'S' for spades or 'U' for unknown + + public: + //******** Add Constructor Prototypes Below *********// + Card(); // Default constructor prototype: creates card with value v, color unknown, and suit U + + Card(int v); // Parameterized constructor prototype: creates card with value v, color unknown, and suit U + + //******** Add Transformer Prototypes Below *********// + void SetValue(int v); // SetValue prototype: Sets card value equal to v + + void SetColor(string c); // SetColor prototype: Sets color value equal to c + + void SetSuit(char s); // SetSuit prototype: Sets suit value equal to s + + //******** Add Observer Prototypes Below *********// + int GetValue() const; // GetValue prototype: Returns current value of value + + string GetColor() const; // GetColor prototype: Returns current value of color + + char GetSuit() const; // GetSuit prototype: Returns current value of suit + + virtual string Description() const; // Description prototype: Polymorphic Function!!! + // Outputs card characteristics - value as a string (see sample output from p01input1.txt) +}; + + +#endif + + diff --git a/CPE212/Project_02/card.o b/CPE212/Project_02/card.o new file mode 100644 index 0000000..9cd7a6b Binary files /dev/null and b/CPE212/Project_02/card.o differ diff --git a/CPE212/Project_02/club.cpp b/CPE212/Project_02/club.cpp new file mode 100644 index 0000000..2406276 --- /dev/null +++ b/CPE212/Project_02/club.cpp @@ -0,0 +1,51 @@ +// club inherits from blackcard +#include "club.h" + +Club::Club(int v) : BlackCard::BlackCard(v) // Parameterized constructor that creates a black card with value v and unknown suit +{ + Club::SetSuit('C'); // sets suit to C + BlackCard::SetColor("black"); +} + +string Club::Description() const // Outputs card characteristics - value and color and suit as a string +{ + int Cval = BlackCard::GetValue(); + string Ccol = BlackCard::GetColor(); + char Cst = BlackCard::GetSuit(); + string d = "Value = "; // temporary variable used to accumulate result + + switch (Cval) // Append card value to variable's value + { + case 2: d = d + "2"; break; // Number cards + case 3: d = d + "3"; break; + case 4: d = d + "4"; break; + case 5: d = d + "5"; break; + case 6: d = d + "6"; break; + case 7: d = d + "7"; break; + case 8: d = d + "8"; break; + case 9: d = d + "9"; break; + case 10: d = d + "10"; break; + + case 11: d = d + "J"; break; // Face cards + case 12: d = d + "Q"; break; + case 13: d = d + "K"; break; + case 14: d = d + "A"; break; + + default: d = d + "?"; break; // Unknown card + } + d = d + ", Color = "; // adds color to output string + if (Ccol=="black") d = d + "black"; + if (Ccol=="red") d = d + "red"; + else d=+ "unknown"; + // appends suit to output string + d =+ ", Suit = "; + switch (Cst) + { + case 'H': d =+ "H"; break; + case 'C': d =+ 'C'; break; + case 'D': d =+ 'D'; break; + case 'U': d =+ 'U'; break; + } + + return d; // Return string describing card value +} \ No newline at end of file diff --git a/CPE212/Project_02/club.h b/CPE212/Project_02/club.h new file mode 100644 index 0000000..ab5a32f --- /dev/null +++ b/CPE212/Project_02/club.h @@ -0,0 +1,27 @@ +// +// club.h -- CPE 212-01, Fall 2010 -- Project02 -- Classes +// +// DO NOT MODIFY OR SUBMIT THIS FILE!!! +// + +#ifndef CLUB_H +#define CLUB_H + +#include "blackcard.h" + +class Club : public BlackCard +{ + private: + // No additional private members + + public: + // Constructors + Club(int v); // Creates a black club card with value v + + string Description() const; // Outputs card characteristics - value, color, suit + // Hint: use base class Description method to generate part of + // the description and append the suit information at the end +}; + +#endif + diff --git a/CPE212/Project_02/club.o b/CPE212/Project_02/club.o new file mode 100644 index 0000000..6a1e264 Binary files /dev/null and b/CPE212/Project_02/club.o differ diff --git a/CPE212/Project_02/diamond.cpp b/CPE212/Project_02/diamond.cpp new file mode 100644 index 0000000..ea52f55 --- /dev/null +++ b/CPE212/Project_02/diamond.cpp @@ -0,0 +1,51 @@ +// Diamond inherits from redcard +#include "diamond.h" + +Diamond::Diamond(int v) : RedCard::RedCard(v) // Parameterized constructor that creates a black card with value v and suit s +{ + Card::SetSuit('D'); // sets suit to D +} +RedCard::Card di; // allows access to functions in Card + +string Diamond::Description() const // Outputs card characteristics - value and color and suit as a string +{ + int Dval = Card::GetValue(); + string Dcol = Card::GetColor(); + char Dst = Card::GetSuit(); + string d = "Value = "; // temporary variable used to accumulate result + + switch (Dval) // Append card value to variable's value + { + case 2: d = d + "2"; break; // Number cards + case 3: d = d + "3"; break; + case 4: d = d + "4"; break; + case 5: d = d + "5"; break; + case 6: d = d + "6"; break; + case 7: d = d + "7"; break; + case 8: d = d + "8"; break; + case 9: d = d + "9"; break; + case 10: d = d + "10"; break; + + case 11: d = d + "J"; break; // Face cards + case 12: d = d + "Q"; break; + case 13: d = d + "K"; break; + case 14: d = d + "A"; break; + + default: d = d + "?"; break; // Unknown card + } + d = d + ", Color = "; // adds color to output string + if (Dcol=="black") d = d + "black"; + if (Dcol=="red") d = d + "red"; + else d=+ "unknown"; + // appends suit to output string + d =+ ", Suit = "; + switch (Dst) + { + case 'H': d =+ "H"; break; + case 'C': d =+ 'C'; break; + case 'D': d =+ 'D'; break; + case 'U': d =+ 'U'; break; + } + + return d; // Return string describing card value +} \ No newline at end of file diff --git a/CPE212/Project_02/diamond.h b/CPE212/Project_02/diamond.h new file mode 100644 index 0000000..7e68ef2 --- /dev/null +++ b/CPE212/Project_02/diamond.h @@ -0,0 +1,27 @@ +// +// diamond.h -- CPE 212-01, Fall 2010 -- Project02 -- Classes +// +// DO NOT MODIFY OR SUBMIT THIS FILE!!! +// + +#ifndef DIAMOND_H +#define DIAMOND_H + +#include "redcard.h" + +class Diamond : public RedCard +{ + private: + // No additional private members + + public: + // Constructors + Diamond(int v); // Creates a red diamond card with value v + + string Description() const; // Outputs card characteristics - value, color, suit + // Hint: use base class Description method to generate part of + // the description and append the suit information at the end +}; + +#endif + diff --git a/CPE212/Project_02/diamond.o b/CPE212/Project_02/diamond.o new file mode 100644 index 0000000..800ab58 Binary files /dev/null and b/CPE212/Project_02/diamond.o differ diff --git a/CPE212/Project_02/heart.cpp b/CPE212/Project_02/heart.cpp new file mode 100644 index 0000000..05551cb --- /dev/null +++ b/CPE212/Project_02/heart.cpp @@ -0,0 +1,51 @@ +// heart inherits from redcard +#include "heart.h" + +Heart::Heart(int v) : RedCard::RedCard(v) // Parameterized constructor that creates a black card with value v and unknown suit +{ + Card::SetSuit('H'); // sets suit to H +} +RedCard::Card ht; // allows access to functions in Card + +string Heart::Description() const // Outputs card characteristics - value and color and suit as a string +{ + int Hval = Card::GetValue(); + string Hcol = Card::GetColor(); + char Hst = Card::GetSuit(); + string d = "Value = "; // temporary variable used to accumulate result + + switch (Hval) // Append card value to variable's value + { + case 2: d = d + "2"; break; // Number cards + case 3: d = d + "3"; break; + case 4: d = d + "4"; break; + case 5: d = d + "5"; break; + case 6: d = d + "6"; break; + case 7: d = d + "7"; break; + case 8: d = d + "8"; break; + case 9: d = d + "9"; break; + case 10: d = d + "10"; break; + + case 11: d = d + "J"; break; // Face cards + case 12: d = d + "Q"; break; + case 13: d = d + "K"; break; + case 14: d = d + "A"; break; + + default: d = d + "?"; break; // Unknown card + } + d = d + ", Color = "; // adds color to output string + if (Hcol=="black") d = d + "black"; + if (Hcol=="red") d = d + "red"; + else d=+ "unknown"; + // appends suit to output string + d =+ ", Suit = "; + switch (Hst) + { + case 'H': d =+ "H"; break; + case 'C': d =+ 'C'; break; + case 'D': d =+ 'D'; break; + case 'U': d =+ 'U'; break; + } + + return d; // Return string describing card value +} \ No newline at end of file diff --git a/CPE212/Project_02/heart.h b/CPE212/Project_02/heart.h new file mode 100644 index 0000000..d367f6b --- /dev/null +++ b/CPE212/Project_02/heart.h @@ -0,0 +1,28 @@ +// +// heart.h -- CPE 212-01, Fall 2010 -- Project02 -- Classes +// +// DO NOT MODIFY OR SUBMIT THIS FILE!!! +// + +#ifndef HEART_H +#define HEART_H + +#include "redcard.h" + +class Heart : public RedCard +{ + private: + // No additional private members + + public: + // Constructors + Heart(int v); // Creates a red heart card with value v + + string Description() const; // Outputs card characteristics - value, color, suit + // Hint: use base class Description method to generate part of + // the description and append the suit information at the end +}; + +#endif + + diff --git a/CPE212/Project_02/heart.o b/CPE212/Project_02/heart.o new file mode 100644 index 0000000..25115f8 Binary files /dev/null and b/CPE212/Project_02/heart.o differ diff --git a/CPE212/Project_02/main.cpp b/CPE212/Project_02/main.cpp new file mode 100644 index 0000000..850a127 --- /dev/null +++ b/CPE212/Project_02/main.cpp @@ -0,0 +1,148 @@ +// +// main.cpp -- Project02, CPE212 Fall 2010 -- Classes +// +// Driver program for Card program which is used to test each +// class member function. +// +// DO NOT MODIFY OR SUBMIT THIS FILE +// + +// List of allowed include files appear below +#include +#include +#include +#include "card.h" +#include "heart.h" +#include "diamond.h" +#include "club.h" +#include "spade.h" + + +using namespace std; // Global using declaration + +void Bar(); // Prototype for Bar function +void Print(Card* someCard); // Prototype for Print function + + + +// Start of main() function + +int main (int argc, char * const argv[]) // Command-line arguments (more on this later) +{ + ifstream inputs; // Input file stream variable for test file + char op, ch; // Hold operation and optional char input from test file + string comment; // Holds comment string input from test file + Card* ptr = NULL; // Pointer to the current card + int v; // Holds card value input from test file + + + // Output usage message if test input file name is not provided + if (argc != 2) + { + cout << "Usage:\n project02 \n"; + return 1; + } + + // Attempt to open test input file -- terminate if file does not open + inputs.open(argv[1]); + if (!inputs) + { + cout << "Error - unable to open input file" << endl; + return 1; + } + + // Process comment line from input file + getline(inputs, comment); // Input file header comment + cout << endl << comment << endl << endl; // Output file header comment + + + // Below is the primary loop that processes each operation appearing within the test file. + // Starts with an initial priming read of first operation + + inputs >> op; // Attempt to input first test operation from file + + while (inputs) // While Not-EOF + { + switch (op) // Process operation input from test file + { + case '#': // Test file comment + getline(inputs, comment); // Input and echo the comment appearing in the test file + cout << '#' << comment << endl; + break; + + case 'p': // Print Card + Print(ptr); + cout << endl; + break; + + case 'b': // Print Bar + Bar(); // Function definition appears at the end of this file + break; + + case '+': // Constructor + inputs >> op; // Input card type into op + + try + { + switch (op) // Invoke requested constructor with argument as required + { + case 'h': inputs >> v; cout << "Heart(" << v << ") -- "; ptr = new Heart(v); break; + case 'd': inputs >> v; cout << "Diamond(" << v << ") -- "; ptr = new Diamond(v); break; + case 'c': inputs >> v; cout << "Club(" << v << ") -- "; ptr = new Club(v); break; + case 's': inputs >> v; cout << "Spade(" << v << ") -- "; ptr = new Spade(v); break; + case 'b': inputs >> v; cout << "BlackCard(" << v << ") -- "; ptr = new BlackCard(v); break; + case 'r': inputs >> v; cout << "RedCard(" << v << ") -- "; ptr = new RedCard(v); break; + case 'x': inputs >> v; cout << "Card(" << v << ") -- "; ptr = new Card(v); break; + case 'z': cout << "Card() -- "; ptr = new Card; break; + default: cout << "Error: Unknown Card Type"; ptr = NULL; break; + } + cout << "Successful"; + } + catch ( ... ) // Catch any exception thrown above + { + cout << "Failed"; + } + + cout << endl; + break; + + case '-': // Destructor + delete ptr; // Deallocate card + ptr = NULL; // Make sure that ptr is not a dangling pointer + break; + + default: // Error + cout << "Error - unrecognized operation '" << op << "'" << endl; + cout << "Terminating now..." << endl; + return 1; + break; + } + //cout << endl; + + inputs >> op; // Attempt to input next command + } + + + return 0; +} + +/************** Implementation of Print() and Bar() functions ********************/ + +// DO NOT MODIFY THIS CODE + +void Bar() +// Bar() -- prints horizontal bar +{ + cout << "#################################################################" << endl; +} // End Bar() + + +void Print(Card* someCard) +// Writes description of card to stdout +{ + cout << someCard->Description(); // Hint: Polymorphic function +} + +/************** End of main.cpp ***************/ + + diff --git a/CPE212/Project_02/main.o b/CPE212/Project_02/main.o new file mode 100644 index 0000000..a1e12ec Binary files /dev/null and b/CPE212/Project_02/main.o differ diff --git a/CPE212/Project_02/makefile b/CPE212/Project_02/makefile new file mode 100644 index 0000000..2ebd2f3 --- /dev/null +++ b/CPE212/Project_02/makefile @@ -0,0 +1,43 @@ +# Project02 Makefile -- CPE 212-01, Fall 2010 + +project02: main.o card.o redcard.o blackcard.o heart.o diamond.o club.o spade.o + g++ main.o card.o redcard.o blackcard.o heart.o diamond.o club.o spade.o -o project02 + + +main.o: main.cpp card.h redcard.h blackcard.h heart.h diamond.h club.h spade.h + g++ -c main.cpp + + +card.o: card.cpp card.h + g++ -c card.cpp + + +redcard.o: redcard.cpp redcard.h card.h + g++ -c redcard.cpp + + +blackcard.o: blackcard.cpp blackcard.h card.h + g++ -c blackcard.cpp + + +heart.o: heart.cpp heart.h redcard.h card.h + g++ -c heart.cpp + + +diamond.o: diamond.cpp diamond.h redcard.h card.h + g++ -c diamond.cpp + + +club.o: club.cpp club.h blackcard.h card.h + g++ -c club.cpp + + +spade.o: spade.cpp spade.h blackcard.h card.h + g++ -c spade.cpp + + +# Remove executable and all object files if they exist +clean: + rm *.o project02 + + diff --git a/CPE212/Project_02/p02input1.txt b/CPE212/Project_02/p02input1.txt new file mode 100644 index 0000000..6864575 --- /dev/null +++ b/CPE212/Project_02/p02input1.txt @@ -0,0 +1,67 @@ +# p02input1.txt - Test Card Class + +b + +# Test of default constructor ++ z +p +- + +b + +# Test of parameterized constructor ++ x 2 +p +- + +b + +# Test of parameterized constructor ++ x 9 +p +- + +b + +# Test of parameterized constructor ++ x 10 +p +- + +b + +# Test of parameterized constructor ++ x 11 +p +- + +b + +# Test of parameterized constructor ++ x 12 +p +- + +b + +# Test of parameterized constructor ++ x 13 +p +- + +b + +# Test of parameterized constructor ++ x 14 +p +- + +b + +# Test of parameterized constructor ++ x 15 +p +- + +b + diff --git a/CPE212/Project_02/p02input2.txt b/CPE212/Project_02/p02input2.txt new file mode 100644 index 0000000..b27a346 --- /dev/null +++ b/CPE212/Project_02/p02input2.txt @@ -0,0 +1,67 @@ +# p02input2.txt - Test RedCard Class + +b + +# Test of parameterized constructor ++ r 1 +p +- + +b + +# Test of parameterized constructor ++ r 2 +p +- + +b + +# Test of parameterized constructor ++ r 9 +p +- + +b + +# Test of parameterized constructor ++ r 10 +p +- + +b + +# Test of parameterized constructor ++ r 11 +p +- + +b + +# Test of parameterized constructor ++ r 12 +p +- + +b + +# Test of parameterized constructor ++ r 13 +p +- + +b + +# Test of parameterized constructor ++ r 14 +p +- + +b + +# Test of parameterized constructor ++ r 15 +p +- + +b + diff --git a/CPE212/Project_02/p02input3.txt b/CPE212/Project_02/p02input3.txt new file mode 100644 index 0000000..c09fccb --- /dev/null +++ b/CPE212/Project_02/p02input3.txt @@ -0,0 +1,68 @@ +# p02input3.txt - Test BlackCard Class + +b + +# Test of parameterized constructor ++ b 1 +p +- + +b + +# Test of parameterized constructor ++ b 2 +p +- + +b + +# Test of parameterized constructor ++ b 9 +p +- + +b + +# Test of parameterized constructor ++ b 10 +p +- + +b + +# Test of parameterized constructor ++ b 11 +p +- + +b + +# Test of parameterized constructor ++ b 12 +p +- + +b + +# Test of parameterized constructor ++ b 13 +p +- + +b + +# Test of parameterized constructor ++ b 14 +p +- + +b + +# Test of parameterized constructor ++ b 15 +p +- + +b + + diff --git a/CPE212/Project_02/p02input4.txt b/CPE212/Project_02/p02input4.txt new file mode 100644 index 0000000..f4d3cfb --- /dev/null +++ b/CPE212/Project_02/p02input4.txt @@ -0,0 +1,141 @@ +# p02input4.txt - Test Heart and Diamond Classes + +b + +# Test of Heart Class + +b + +# Test of parameterized constructor ++ h 1 +p +- + +b + +# Test of parameterized constructor ++ h 2 +p +- + +b + +# Test of parameterized constructor ++ h 9 +p +- + +b + +# Test of parameterized constructor ++ h 10 +p +- + +b + +# Test of parameterized constructor ++ h 11 +p +- + +b + +# Test of parameterized constructor ++ h 12 +p +- + +b + +# Test of parameterized constructor ++ h 13 +p +- + +b + +# Test of parameterized constructor ++ h 14 +p +- + +b + +# Test of parameterized constructor ++ h 15 +p +- + +b +b + + +# Test of Diamond Class + +b + +# Test of parameterized constructor ++ d 1 +p +- + +b + +# Test of parameterized constructor ++ d 2 +p +- + +b + +# Test of parameterized constructor ++ d 9 +p +- + +b + +# Test of parameterized constructor ++ d 10 +p +- + +b + +# Test of parameterized constructor ++ d 11 +p +- + +b + +# Test of parameterized constructor ++ d 12 +p +- + +b + +# Test of parameterized constructor ++ d 13 +p +- + +b + +# Test of parameterized constructor ++ d 14 +p +- + +b + +# Test of parameterized constructor ++ d 15 +p +- + +b + + diff --git a/CPE212/Project_02/p02input5.txt b/CPE212/Project_02/p02input5.txt new file mode 100644 index 0000000..359615a --- /dev/null +++ b/CPE212/Project_02/p02input5.txt @@ -0,0 +1,141 @@ +# p02input5.txt - Test Club and Spade Classes + +b + +# Test of Club Class + +b + +# Test of parameterized constructor ++ c 1 +p +- + +b + +# Test of parameterized constructor ++ c 2 +p +- + +b + +# Test of parameterized constructor ++ c 9 +p +- + +b + +# Test of parameterized constructor ++ c 10 +p +- + +b + +# Test of parameterized constructor ++ c 11 +p +- + +b + +# Test of parameterized constructor ++ c 12 +p +- + +b + +# Test of parameterized constructor ++ c 13 +p +- + +b + +# Test of parameterized constructor ++ c 14 +p +- + +b + +# Test of parameterized constructor ++ c 15 +p +- + +b +b + + +# Test of Spade Class + +b + +# Test of parameterized constructor ++ s 1 +p +- + +b + +# Test of parameterized constructor ++ s 2 +p +- + +b + +# Test of parameterized constructor ++ s 9 +p +- + +b + +# Test of parameterized constructor ++ s 10 +p +- + +b + +# Test of parameterized constructor ++ s 11 +p +- + +b + +# Test of parameterized constructor ++ s 12 +p +- + +b + +# Test of parameterized constructor ++ s 13 +p +- + +b + +# Test of parameterized constructor ++ s 14 +p +- + +b + +# Test of parameterized constructor ++ s 15 +p +- + +b + + diff --git a/CPE212/Project_02/project02 b/CPE212/Project_02/project02 new file mode 100644 index 0000000..0e096aa Binary files /dev/null and b/CPE212/Project_02/project02 differ diff --git a/CPE212/Project_02/redcard.cpp b/CPE212/Project_02/redcard.cpp new file mode 100644 index 0000000..9f91ef7 --- /dev/null +++ b/CPE212/Project_02/redcard.cpp @@ -0,0 +1,40 @@ +// redcard inherits from card +#include "redcard.h" + +RedCard::RedCard(int v) : Card::Card(v) // Parameterized constructor that creates a red card with value v and unknown suit +{ + Card::SetColor("red"); +} + + + +string RedCard::Description() const // Outputs card characteristics - value and color as a string +{ + int Rval = Card::GetValue(); + string Rcol = Card::GetColor(); + string d = "Value = "; // temporary variable used to accumulate result + + switch (Rval) // Append card value to variable's value + { + case 2: d = d + "2"; break; // Number cards + case 3: d = d + "3"; break; + case 4: d = d + "4"; break; + case 5: d = d + "5"; break; + case 6: d = d + "6"; break; + case 7: d = d + "7"; break; + case 8: d = d + "8"; break; + case 9: d = d + "9"; break; + case 10: d = d + "10"; break; + case 11: d = d + "J"; break; // Face cards + case 12: d = d + "Q"; break; + case 13: d = d + "K"; break; + case 14: d = d + "A"; break; + + default: d = d + "?"; break; // Unknown card + } + d = d + ", Color = "; // adds color to output string + if (Rcol=="black") d = d + "black"; + if (Rcol=="red") d = d + "red"; + else d=+ "unknown"; + return d; // Return string describing card value +} \ No newline at end of file diff --git a/CPE212/Project_02/redcard.h b/CPE212/Project_02/redcard.h new file mode 100644 index 0000000..6e7e523 --- /dev/null +++ b/CPE212/Project_02/redcard.h @@ -0,0 +1,27 @@ +// +// redcards.h -- CPE 212-01, Fall 2010 -- Project02 -- Classes +// +// DO NOT MODIFY OR SUBMIT THIS FILE!!! +// + +#ifndef REDCARD_H +#define REDCARD_H + +#include "card.h" + +class RedCard : public Card +{ + private: + // No additional private members + + public: + // Constructors + RedCard(int v); // Creates a red card with value v and unknown suit + + string Description() const; // Outputs card characteristics - value and color as a string + // Hint: use base class Description method to generate part of + // the description and append the color information at the end +}; + +#endif + diff --git a/CPE212/Project_02/redcard.o b/CPE212/Project_02/redcard.o new file mode 100644 index 0000000..0bb425e Binary files /dev/null and b/CPE212/Project_02/redcard.o differ diff --git a/CPE212/Project_02/spade.cpp b/CPE212/Project_02/spade.cpp new file mode 100644 index 0000000..1b3d3d6 --- /dev/null +++ b/CPE212/Project_02/spade.cpp @@ -0,0 +1,52 @@ +// spade inherits from blackcard +#include "spade.h" + +Spade::Spade(int v) : BlackCard::BlackCard(v) // Parameterized constructor that creates a black card with value v and unknown suit +{ + Card::SetSuit('S'); // sets suit to S + +} +Spade::Card sp; // allows access to functions in Card + +string Spade::Description() const // Outputs card characteristics - value and color and suit as a string +{ + int Sval = Card::GetValue(); + string Scol = Card::GetColor(); + char Sst = Card::GetSuit(); + string d = "Value = "; // temporary variable used to accumulate result + + switch (Sval) // Append card value to variable's value + { + case 2: d = d + "2"; break; // Number cards + case 3: d = d + "3"; break; + case 4: d = d + "4"; break; + case 5: d = d + "5"; break; + case 6: d = d + "6"; break; + case 7: d = d + "7"; break; + case 8: d = d + "8"; break; + case 9: d = d + "9"; break; + case 10: d = d + "10"; break; + + case 11: d = d + "J"; break; // Face cards + case 12: d = d + "Q"; break; + case 13: d = d + "K"; break; + case 14: d = d + "A"; break; + + default: d = d + "?"; break; // Unknown card + } + d = d + ", Color = "; // adds color to output string + if (Scol=="black") d = d + "black"; + if (Scol=="red") d = d + "red"; + else d=+ "unknown"; + // appends suit to output string + d =+ ", Suit = "; + switch (Sst) + { + case 'H': d =+ "H"; break; + case 'C': d =+ 'C'; break; + case 'D': d =+ 'D'; break; + case 'U': d =+ 'U'; break; + } + + return d; // Return string describing card value +} \ No newline at end of file diff --git a/CPE212/Project_02/spade.h b/CPE212/Project_02/spade.h new file mode 100644 index 0000000..9867e6e --- /dev/null +++ b/CPE212/Project_02/spade.h @@ -0,0 +1,26 @@ +// +// spade.h -- CPE 212-01, Fall 2010 -- Project02 -- Classes +// +// DO NOT MODIFY OR SUBMIT THIS FILE!!! +// + +#ifndef SPADE_H +#define SPADE_H + +#include "blackcard.h" + +class Spade : public BlackCard +{ + private: + // No additional private members + + public: + // Constructors + Spade(int v); // Creates a black spade card with value v + + string Description() const; // Outputs card characteristics - value, color, suit + // Hint: use base class Description method to generate part of + // the description and append the suit information at the end +}; + +#endif \ No newline at end of file diff --git a/CPE212/Project_02/spade.o b/CPE212/Project_02/spade.o new file mode 100644 index 0000000..c862011 Binary files /dev/null and b/CPE212/Project_02/spade.o differ diff --git a/CPE212/Project_03/main.cpp b/CPE212/Project_03/main.cpp new file mode 100644 index 0000000..03daaf6 --- /dev/null +++ b/CPE212/Project_03/main.cpp @@ -0,0 +1,212 @@ +// +// main.cpp -- 2010 Fall -- Project03 -- Stacks +// +// Driver program for Stack ADT -- The text files (read by this code) contain a series of commands +// that will help you test your Stack ADT code by triggering various Stack class methods. +// +// DO NOT MODIFY OR SUBMIT THIS FILE +// +#include +#include +#include +#include +#include "stack.h" + +using namespace std; + +int main(int argc, char* argv[]) +{ + ifstream inputs; // Input file for commands + char op; // Hold operation and optional char input + int value; // Value input from file + string comment; // Holds comment from file + Stack* sPtr = NULL; // Will point to TemplateQ object + + // Output usage message if one input file name is not provided + if (argc != 2) + { + cout << "Usage:\n project03 \n"; + return 1; + } + + // Attempt to open input file -- terminate if file does not open + inputs.open(argv[1]); + if (!inputs) + { + cout << "Error - unable to open input file" << endl; + return 1; + } + + // Input and echo header comment from file + getline(inputs, comment); + cout << endl << '#' << comment << endl; + + // Process commands from input file + inputs >> op; // Attempt to input first command + while (inputs) + { + switch (op) // Process operation input from file + { + case '#': // Test file comment + getline(inputs, comment); // Input and echo the comment appearing in the test file + cout << '#' << comment << endl; + break; + + case 'c': // Parameterized Constructor + inputs >> value; + cout << endl << "Stack(" << value << ")"; + try + { + sPtr = new Stack(value); // Attempt to create a stack object with array size value + cout << " -- Successful" << endl; + } + catch ( std::bad_alloc ) + { + cout << "Failed : Terminating now..." << endl; + return 1; + } + break; + + case '+': // Push + inputs >> value; + cout << "Push(" << value << ")"; + try + { + sPtr->Push(value); + cout << " -- successful"; + } + catch (StackFull) + { + cout << " -- Failed Full Stack"; + } + cout << endl; + break; + + case '-': // Pop + cout << "Pop() -- "; + try + { + sPtr->Pop(); + cout << "successful"; + } + catch (StackEmpty) + { + cout << "Failed Empty Stack"; + } + cout << endl; + break; + + case 'f': // IsFull + cout << "IsFull() -- "; + try + { + if (sPtr->IsFull()) + cout << "true"; + else + cout << "false"; + } + catch ( ... ) + { + cout << "operation failed"; + } + cout << endl; + break; + + case 'e': // IsEmpty + cout << "IsEmpty() -- "; + try + { + if (sPtr->IsEmpty()) + cout << "true"; + else + cout << "false"; + } + catch ( ... ) + { + cout << "operation failed"; + } + cout << endl; + break; + + case 'm': // Make Empty + sPtr->MakeEmpty(); + cout << "MakeEmpty()" << endl; + break; + + case 'p': // Print Stack + cout << "Print() -- "; + sPtr->Print(); + break; + + case 't': // Top of Stack + try + { + cout << "Top() -- " << sPtr->Top() << endl; + } + catch (StackEmpty) + { + cout << "Top() -- Failed Empty Stack" << endl; + } + break; + + case '>': // Max value within Stack + try + { + cout << "Max() -- " << sPtr->Max() << endl; + } + catch (StackEmpty) + { + cout << "Max() -- Failed Empty Stack" << endl; + } + break; + + case '<': // Min value within Stack + try + { + cout << "Min() -- " << sPtr->Min() << endl; + } + catch (StackEmpty) + { + cout << "Min() -- Failed Empty Stack" << endl; + } + break; + + case '?': // Peek(n) Stack + inputs >> value; + try + { + cout << "Peek(" << value << ") -- " << sPtr->Peek(value) << endl; + } + catch (StackInvalidPeek) + { + cout << "Peek(" << value << ") -- Failed Invalid Peek" << endl; + } + break; + + case 's': // Size of Stack + cout << "Size() -- " << sPtr->Size() << endl; + break; + + case 'z': // Capacity of Stack + cout << "Capacity() -- " << sPtr->Capacity() << endl; + break; + + case 'd': // Destructor + delete sPtr; + sPtr = NULL; + cout << "~Stack()" << endl << endl; + break; + + default: // Error + cout << "Error - unrecognized operation '" << op << "'" << endl; + cout << "Terminating now..." << endl; + return 1; + break; + } + + inputs >> op; // Attempt to input next command + } + + return 0; +} // End main() + diff --git a/CPE212/Project_03/main.o b/CPE212/Project_03/main.o new file mode 100644 index 0000000..002f0cf Binary files /dev/null and b/CPE212/Project_03/main.o differ diff --git a/CPE212/Project_03/makefile b/CPE212/Project_03/makefile new file mode 100644 index 0000000..12a233d --- /dev/null +++ b/CPE212/Project_03/makefile @@ -0,0 +1,15 @@ +# Project03 makefile + +project03: stack.o main.o + g++ stack.o main.o -o project03 + +stack.o: stack.h stack.cpp + g++ -c stack.cpp + +main.o: stack.h main.cpp + g++ -c main.cpp + +clean: + rm *.o project03 + + diff --git a/CPE212/Project_03/p03input1.txt b/CPE212/Project_03/p03input1.txt new file mode 100644 index 0000000..1d40456 --- /dev/null +++ b/CPE212/Project_03/p03input1.txt @@ -0,0 +1,43 @@ +# p03input1.txt -- Test: Stack(), Push(), Pop(), and Top() + +c 8 +p +t ++ 5 ++ 10 ++ 15 +p +t ++ 20 ++ 25 ++ 30 +p +t +- +- +p ++ 35 ++ 40 +t ++ 45 +t +p +- +- +- +- +- +- +- +- +p +t +d + + +c 4 +p +- +t +d + diff --git a/CPE212/Project_03/p03input2.txt b/CPE212/Project_03/p03input2.txt new file mode 100644 index 0000000..ad369f6 --- /dev/null +++ b/CPE212/Project_03/p03input2.txt @@ -0,0 +1,38 @@ +# p03input2.txt -- Test IsFull(), IsEmpty(), and MakeEmpty() + +c 8 +e +f ++ 5 ++ 10 ++ 15 ++ 20 ++ 25 ++ 30 +p +e +f +m +p +e +f ++ 35 ++ 40 ++ 45 ++ 50 +p +e +f +- +- +- +p +e +f +m +p +e +f +d + + diff --git a/CPE212/Project_03/p03input3.txt b/CPE212/Project_03/p03input3.txt new file mode 100644 index 0000000..a0b02f0 --- /dev/null +++ b/CPE212/Project_03/p03input3.txt @@ -0,0 +1,58 @@ +# p03input3.txt -- Test Size(), Capacity() + +# Test Size() +c 6 +p +s ++ 5 ++ 10 +p +s ++ 15 ++ 20 +p +s ++ 25 ++ 30 +p +s +- +- +- +p +s +- +- +- +p +s +d + +# Test Capacity() +c 2 +z ++ 5 +z ++ 10 +z ++ 15 +z ++ 20 +z ++ 25 +z ++ 30 +z +p +- +- +- +z +p +- +- +- +z +p +d + diff --git a/CPE212/Project_03/p03input4.txt b/CPE212/Project_03/p03input4.txt new file mode 100644 index 0000000..2aa5486 --- /dev/null +++ b/CPE212/Project_03/p03input4.txt @@ -0,0 +1,34 @@ +# p03input4.txt -- Test Min() and Max() + +c 8 +< +> ++ 5 ++ 30 ++ 15 ++ 20 ++ 50 ++ 10 +p +< +> ++ 20 ++ 50 ++ 5 +p +< +> +- +- +- +p +< +> +- +- +- +p +< +> +d + diff --git a/CPE212/Project_03/p03input5.txt b/CPE212/Project_03/p03input5.txt new file mode 100644 index 0000000..20d99ea --- /dev/null +++ b/CPE212/Project_03/p03input5.txt @@ -0,0 +1,51 @@ +# p03input5.txt -- Test Peek(n) + +c 8 +? 0 ++ 5 ++ 30 ++ 15 ++ 20 ++ 50 ++ 10 +p +? 0 +? 1 +? 2 +? 3 +? 4 +? 5 +? 6 +p +- +- +- +p +? 0 +? 1 +? 2 +? 5 +p +- +- +- +p +? 0 +? 1 +? 2 +? 3 +? 4 +? 5 ++ 25 ++ 9 ++ 8 +p +? 0 +? 1 +? 2 +? 3 +? 4 +? 5 +d + + diff --git a/CPE212/Project_03/project03 b/CPE212/Project_03/project03 new file mode 100644 index 0000000..2eb512f Binary files /dev/null and b/CPE212/Project_03/project03 differ diff --git a/CPE212/Project_03/stack.cpp b/CPE212/Project_03/stack.cpp new file mode 100644 index 0000000..3478769 --- /dev/null +++ b/CPE212/Project_03/stack.cpp @@ -0,0 +1,157 @@ +#include +#include +#include "stack.h" + + +int Max_Stack; // Global variable for stack size +Stack::Stack(int n) // Parameterized constructor dynamically allocates an empty stack array +{ // that may hold no more than n elements and initializes other private variables + Max_Stack=n; + array = new int[n]; + top=-1; + num=n; +} + +void Stack::Resize(int n) // Attempts to increase size of stack array to 2*num and then push n onto stack +{ // If unable to resize, throw StackFull exception + try + { + int largerArry[2*Max_Stack]; + for (int i = 0; i < num; i++) + { + largerArry[i]=array[i]; + } + delete [] array; + num= num * 2; // num to twice original size + Max_Stack=num; + array = largerArry; + array[top]=n; + //top++; + } + catch( ... ) + { + throw StackFull(); + //return; + } +} + +Stack::~Stack() +{ + delete [] array; +} + +void Stack::Push(int n) +{ + bool full = IsFull(); + if (full) + { + Resize(n); + array[top]=n; + } + //array[top]=n; + top++; + array[top]=n; +} + +void Stack::Pop() +{ + bool empty=IsEmpty(); + if (empty) + { + throw StackEmpty(); + } + top--; +} + +bool Stack::IsEmpty() const +{ + return (top == -1); +} + +bool Stack::IsFull() const +{ + return (top == Max_Stack); +} + +void Stack::MakeEmpty() +{ + top = -1; +} + +int Stack::Top() const +{ + bool empty=IsEmpty(); + if (empty) + { + throw StackEmpty(); + //return; + } + return array[top]; +} + +int Stack::Size() const // Returns number of items on stack WITHOUT modifying the stack +{ + return top; +} + +int Stack::Max() const // Returns value of largest integer on stack WITHOUT modifying the stack +{ // If stack is empty, throws StackEmpty + bool empty=IsEmpty(); + if (empty) + { + throw StackEmpty(); + } + + int i; + + // Initialize maximum element + int max = array[0]; + + // Traverse array elements + // from second and compare + // every element with current max + for (i = 1; i < top; i++) + { + if (array[i] > max) + max = array[i]; + } + return max; +} + +int Stack::Min() const // Returns value of smallest integer on stack WITHOUT modifying the stack +{ // If stack is empty, throws StackEmpty + bool empty=IsEmpty(); + if (empty) + { + throw StackEmpty(); + } + + int i; + + // Initialize minimum element + int min = array[0]; + + // Traverse array elements + // from second and compare + // every element with current min + for (i = 1; i < top; i++) + { + if (array[i] < min) + min = array[i]; + } + return min; +} + +int Stack::Peek(unsigned int n) const // Returns stack value n levels down from top of stack. Peek(0) = Top() +{ // If position n does not exist, throws StackInvalidPeek + + if(!array[top-n]) + throw StackInvalidPeek(); + int st=array[top-n]; + return st; +} + +int Stack::Capacity() const // Returns total num of elements that maybe stored in stack array +{ + return Max_Stack; +} \ No newline at end of file diff --git a/CPE212/Project_03/stack.h b/CPE212/Project_03/stack.h new file mode 100644 index 0000000..1d2dc2f --- /dev/null +++ b/CPE212/Project_03/stack.h @@ -0,0 +1,103 @@ +// +// stack.h 2010 Fall CPE 212 -- Project03 -- Stacks +// +// The comments have been updated, but there have been no changes to the code. +// +// Specification file for Stack class, a stack of integers implemented +// as a linked list of nodes. +// +// ***** DO NOT MODIFY OR SUBMIT THIS FILE ***** +// +#include +using namespace std; + + +#ifndef STACK_H +#define STACK_H + +class StackEmpty +{ + // Exception class - throw an object of this type when stack is empty + // Hint: there is no code for exception classes +}; + + +class StackFull +{ + // Exception class - throw an object of this type when stack is full +}; + +class StackInvalidPeek +{ + // Exception class - throw an object of this type when invalid peek position is used +}; + + +class Stack // Models stack of integers ADT implemented as a dynamically allocated array +{ + private: + int* array; // Points to the stack array + int num; // Holds max number of elements that may be stored in stack array + int top; // Holds the index of the top data value stored on the stack + void Resize(int n); // Attempts to increase size of stack array to 2*num and then push n onto stack + // If unable to resize, throw StackFull exception + + public: + Stack(int n); // Parameterized constructor dynamically allocates an empty stack array + // that may hold no more than n elements and initializes other private variables + + + ~Stack(); // Destructor deallocates all dynamically-allocated memory + // associated with the object + + void Push(int n); // Pushes integer n onto top of stack. If stack is full, attempts to + // resize stack and then push n. If unable to resize, throws StackFull exception. + + void Pop(); // Removes top integer from stack + // If stack is empty, throws StackEmpty exception + + bool IsEmpty() const; // Returns true if stack is empty; false otherwise + + bool IsFull() const; // Returns true if stack is full; false otherwise + + void MakeEmpty(); // Removes all items from stack leaving an empty, but usable stack with capacity num + // If stack is already empty, MakeEmpty() does nothing + + int Top() const; // Returns value of top integer on stack WITHOUT modifying the stack + // If stack is empty, throws StackEmpty exception + + int Size() const; // Returns number of items on stack WITHOUT modifying the stack + + + int Max() const; // Returns value of largest integer on stack WITHOUT modifying the stack + // If stack is empty, throws StackEmpty + + int Min() const; // Returns value of smallest integer on stack WITHOUT modifying the stack + // If stack is empty, throws StackEmpty + + int Peek(unsigned int n) const; // Returns stack value n levels down from top of stack. Peek(0) = Top() + // If position n does not exist, throws StackInvalidPeek + + int Capacity() const; // Returns total num of elements that maybe stored in stack array + + /******* DO NOT MODIFY ANY OF THE CODE FOR PRINT() *******/ + /****** DO NOT PLACE A COPY OF PRINT() CODE IN STACK.CPP!!! *******/ + + void Print() const // Writes stack contents to stdout, separated by a space, followed by endl + { + int index = top; + cout << "Top { "; + + while (index != -1) // Loop to output any values stored on stack + { + cout << array[index] << " "; + index--; + } + cout << "} Bottom" << endl; + } // End Print() + +}; // End Class Stack + +#endif + + diff --git a/CPE212/Project_03/stack.o b/CPE212/Project_03/stack.o new file mode 100644 index 0000000..2b29799 Binary files /dev/null and b/CPE212/Project_03/stack.o differ diff --git a/CPE212/Project_04/list.cpp b/CPE212/Project_04/list.cpp new file mode 100644 index 0000000..152526c --- /dev/null +++ b/CPE212/Project_04/list.cpp @@ -0,0 +1,154 @@ +#include +#include +#include "list.h" + + +Node list; +List::List() +{ + head = NULL; + num=0; +} + +List::~List() +{ + delete head; +} + +void List::Append(string newword) +{ + Node* tempPtr=new Node; + tempPtr->word= newword; + tempPtr->next= NULL; + //num++; + if (head==NULL) + { + head=tempPtr; + num++; + return; + //head->next=NULL; + } + else + { + Node *current=head; + while(current ->next) current=current->next; + current->next = tempPtr; + } + + num++; +} + +void List::InsertAt(int pos, string newword) +{ + Node* prev = new Node(); + Node* curr = new Node(); + Node* newNode = new Node(); + newNode->word = newword; + + int tempPos = 0; // Traverses through the list + + curr = head; // Initialize current to head; + if(head != NULL) + { + while(curr->next != NULL && tempPos != pos) + { + prev = curr; + curr = curr->next; + tempPos++; + } + if(pos==0) + { + + } + else if(curr->next == NULL && pos == tempPos+1) + { + Append(newword); + // Call function to append + } + else if(pos > tempPos+1 || pos>num || pos<0) throw ListBadPosition(); + //Position not valid + else + { + prev->next = newNode; + newNode->next = curr; + } + } + else + { + head = newNode; + newNode->next=NULL; + } +} + + +void List::Delete(string someword) +{ + Node *prev=head; + Node *current=head->next; + int wordNotFound=0; + while (current != NULL) + { + // If current word is in list, break out of loop + if(current->word == someword) break; + else + { + prev=current; + prev=current->next; + } + } + if(current==NULL) throw ListNotFound(); + // Error handling: if current word is not in list, throw ListNotFound + else + { + prev->next = current ->next; + delete current; + } + +} + +void List::Replace(string oldword, string newword) +{ + Node *current=head; + int oldWordNotFound=0; + while (current != NULL) + { + // if oldword is found in list, replace oldword with newword + if(current->word==oldword) + { + current->word = newword; + return; + } + // if oldword not= to current word, increment wordNotFound + oldWordNotFound++; + current = current -> next; + if(oldWordNotFound==num) + break; + } + // if oldWordNotFound==num, throw ListNotFound + + throw ListNotFound(); +} + +int List::Length() const +{ + return num; +} + +bool List::Find(string someword) const +{ + Node *current=head; + int wordNotFound=0; + while (current != NULL) + { + // if current word does not equal someword, increment wordNotFound + if(current->word != someword) + { + wordNotFound++; + } + // If current word is in list, return true + if(current->word == someword) return true; + current = current->next; + } + // if wordNotFound == num, return false + if(wordNotFound == num) return false; +} \ No newline at end of file diff --git a/CPE212/Project_04/list.h b/CPE212/Project_04/list.h new file mode 100644 index 0000000..af82e54 --- /dev/null +++ b/CPE212/Project_04/list.h @@ -0,0 +1,101 @@ +// +// list.h -- 2010 Fall CPE 212 -- Project04 -- Lists +// +// DO NOT MODIFY OR SUBMIT THIS FILE +// + +#ifndef LIST_H +#define LIST_H + +#include +using namespace std; + +class ListEmpty { /*** Empty Error Class ***/ }; +class ListFull { /*** Empty Error Class ***/ }; +class ListNotFound { /*** Empty Error Class ***/ }; +class ListBadPosition { /*** Empty Error Class ***/ }; + +struct Node +{ + string word; // A word in a phrase + Node* next; // Pointer to next node in sequence +}; + +class List // List ADT used to store words in a phrase +{ + private: + Node* head; // Pointer to head of word list + int num; // Number of words stored in list + + public: + /***** Constructor and Destructor *****/ + List(); + // Description of List() + // Constructor sets state of list to empty + + ~List(); + // Description of ~List() + // Destructor must deallocate all list nodes + + + /***** Transformer Methods *****/ + void Append(string newword); + // Description of Append(...) + // Appends newword to the end of the current phrase + // Error Handling: If list is full, throw ListFull object. + + void InsertAt(int pos, string newword); + // Description of InsertAt(...) + // Inserts newword at position pos. + // Positions numbered starting with zero (0 <= pos <= num). + // Hint: pos == num ==> append + // Word previously at pos should now be at position pos+1 + // Error Handling: If list is full, throws ListFull object + // If pos out of range, throws ListBadPosition object + + void Delete(string someword); + // Description of Delete(...) + // Deletes the first instance of someword if it is present. + // Error Handling: If someword is not in list, throws ListNotFound object + + void Replace(string oldword, string newword); + // Description of Replace(...) + // Replaces the first instance of oldword with newword. + // Error Handling: If oldword not found, throws ListNotFound object + + + /***** Observer Methods *****/ + int Length() const; + // Description of Length() + // Returns number of words in the list + // Error Handling: none + + bool Find(string someword) const; + // Description of Find(...) + // Returns true if someword is in list, false otherwise + // Error Handling: none + + + // DO NOT MODIFY OR SUBMIT Print() + void Print() const + // Description of Print() + // Prints the entire phrase to stdout + { + Node* temp = head; // Temp variable for scanning through list starting at head + + cout << "Head {"; // Output open brace + while (temp != NULL) // While there are words that must be printed... + { + cout << ' ' << temp->word; // ... print the next word + temp = temp->next; // ... and advance to the next node. + } + + cout << " }"; // Output close brace + } +}; + +#endif + + + + diff --git a/CPE212/Project_04/list.o b/CPE212/Project_04/list.o new file mode 100644 index 0000000..2caa695 Binary files /dev/null and b/CPE212/Project_04/list.o differ diff --git a/CPE212/Project_04/main.cpp b/CPE212/Project_04/main.cpp new file mode 100644 index 0000000..d74c0b3 --- /dev/null +++ b/CPE212/Project_04/main.cpp @@ -0,0 +1,168 @@ +// +// main.cpp -- 2010 Fall -- Project04 -- Lists +// +// Driver program for List ADT -- The text files (read by this code) contain a series of commands +// that will help you test your List ADT code by triggering various List class methods. +// +// DO NOT MODIFY OR SUBMIT THIS FILE +// +#include +#include +#include +#include +#include "list.h" + +using namespace std; + +int main(int argc, char* argv[]) +{ + ifstream inputs; // Input file for commands + char op; // Hold operation and optional char input + string value, value2; // Values input from file + string comment; // Holds comment from file + int pos; // Holds position value from file + List* ptr = NULL; // Will point to List object + + // Output usage message if one input file name is not provided + if (argc != 2) + { + cout << "Usage:\n project04 \n"; + return 1; + } + + // Attempt to open input file -- terminate if file does not open + inputs.open(argv[1]); + if (!inputs) + { + cout << "Error - unable to open input file" << endl; + return 1; + } + + // Input and echo header comment from file + getline(inputs, comment); // Input and echo the comment appearing in the test file + cout << endl << '#' << comment << endl << endl; + + // Process commands from input file + inputs >> op; // Attempt to input first command + while (inputs) + { + switch (op) // Process operation input from file + { + case '#': // Test file comment + getline(inputs, comment); // Input and echo the comment appearing in the test file + cout << '#' << comment << endl; + break; + + case 'c': // Parameterized Constructor + cout << endl << "List()"; + try + { + ptr = new List(); // Attempt to create a List object + cout << " -- Successful" << endl; + } + catch ( std::bad_alloc ) + { + cout << "Failed : Terminating now..." << endl; + return 1; + } + break; + + case 'a': // Append + inputs >> value; + cout << "Append(" << value << ")"; + try + { + ptr->Append(value); + cout << " -- successful"; + } + catch (ListFull) + { + cout << " -- Failed Full List"; + } + cout << endl; + break; + + case '-': // Delete word + inputs >> value; + cout << "Delete(" << value << ") -- "; + try + { + ptr->Delete(value); + cout << "successful"; + } + catch (ListNotFound) + { + cout << "Failed Not In List"; + } + cout << endl; + break; + + case '+': // Insert at position + inputs >> pos >> value; + cout << "InsertAt(" << pos << ", " << value << ") -- "; + try + { + ptr->InsertAt(pos, value); + cout << "Successful" << endl; + } + catch (ListBadPosition) + { + cout << "Failed Bad Position" << endl; + } + break; + + case 'p': // Print List + cout << "Print() -- "; + ptr->Print(); + cout << endl; + break; + + case 'r': // Replace word + inputs >> value >> value2; + try + { + cout << "Replace(" << value << ", " << value2 << ") -- "; + ptr->Replace(value, value2); + cout << "Successful" << endl; + } + catch (ListNotFound) + { + cout << "Failed Not Found in List" << endl; + } + break; + + case '?': // Find in List + inputs >> value; + if ( ptr->Find(value) ) + { + cout << "Find(" << value << ") -- True" << endl; + } + else + { + cout << "Find(" << value << ") -- False" << endl; + } + break; + + case 'l': // Length of List + cout << "Length() -- " << ptr->Length() << endl; + break; + + case 'd': // Destructor + delete ptr; + ptr = NULL; + cout << "~List()" << endl << endl; + break; + + default: // Error + cout << "Error - unrecognized operation '" << op << "'" << endl; + cout << "Terminating now..." << endl; + return 1; + break; + } + + inputs >> op; // Attempt to input next command + } + + return 0; +} // End main() + diff --git a/CPE212/Project_04/main.o b/CPE212/Project_04/main.o new file mode 100644 index 0000000..5bf51d3 Binary files /dev/null and b/CPE212/Project_04/main.o differ diff --git a/CPE212/Project_04/makefile b/CPE212/Project_04/makefile new file mode 100644 index 0000000..6e5d338 --- /dev/null +++ b/CPE212/Project_04/makefile @@ -0,0 +1,15 @@ +# Project04 makefile + +project04: list.o main.o + g++ list.o main.o -o project04 + +list.o: list.h list.cpp + g++ -c list.cpp + +main.o: list.h main.cpp + g++ -c main.cpp + +clean: + rm *.o project04 + + diff --git a/CPE212/Project_04/p04input1.txt b/CPE212/Project_04/p04input1.txt new file mode 100644 index 0000000..87b38e0 --- /dev/null +++ b/CPE212/Project_04/p04input1.txt @@ -0,0 +1,38 @@ +# p04input1.txt -- Test List(), ~List(), Length(), Append() + +# Test Append() +c +p +a See +p +a Spot +p +a run +p +d + + +# Test Length() +c +l +p +a Observe +l +p +a Spot +l +p +a running +l +p +a swiftly +l +p +a away +l +p +d + + + + diff --git a/CPE212/Project_04/p04input2.txt b/CPE212/Project_04/p04input2.txt new file mode 100644 index 0000000..3e12c99 --- /dev/null +++ b/CPE212/Project_04/p04input2.txt @@ -0,0 +1,44 @@ +# p04input2.txt -- Test List(), ~List(), Append(), Find() + +# Test successful find +c +p +a See +p +a Spot +p +a run +p +? See +p +? Spot +p +? run +p +d + + +# Test unsuccessful find +c +p +a Observe +p +a Spot +p +a running +p +a swiftly +p +a away +p +? slowly +p +? run +p +? spot +p +d + + + + diff --git a/CPE212/Project_04/p04input3.txt b/CPE212/Project_04/p04input3.txt new file mode 100644 index 0000000..9559f97 --- /dev/null +++ b/CPE212/Project_04/p04input3.txt @@ -0,0 +1,51 @@ +# p04input3.txt -- Test List(), ~List(), Delete() + +# Test successful delete +c +p +a See +p +a Spot +p +a run +p +a swiftly +p +a away +p +- run +p +- Spot +p +- See +p +- away +p +- swiftly +p +d + + + +# Test unsuccessful delete +c +p +a See +p +a Spot +p +a run +p +a slowly +p +a away +p +- Observe +p +- spot +p +d + + + + diff --git a/CPE212/Project_04/p04input4.txt b/CPE212/Project_04/p04input4.txt new file mode 100644 index 0000000..6e72cbe --- /dev/null +++ b/CPE212/Project_04/p04input4.txt @@ -0,0 +1,38 @@ +# p04input4.txt -- Test Replace() + +# Test successful replace +c +p +a See +p +a Spot +p +a run +p +p +r run walk +p +r See Observe +p +r Spot Dot +p +d + + +# Test unsuccessful replace +c +a See +a Spot +a run +a swiftly +a away +p +r spot goat +p +r goat boat +p +d + + + + diff --git a/CPE212/Project_04/p04input5.txt b/CPE212/Project_04/p04input5.txt new file mode 100644 index 0000000..3067034 --- /dev/null +++ b/CPE212/Project_04/p04input5.txt @@ -0,0 +1,31 @@ +# p04input5.txt -- Test InsertAt() + +# Test successful InsertAt +c +a See +a Spot +a run +p ++ 0 Zero +p ++ 1 One +p ++ 4 Four +p ++ 5 Five +p ++ 7 Seven +p + +# Test unsuccessful InsertAt ++ -1 Bad +p ++ 10 Ten +p ++ 20 Twenty +p +d + + + + diff --git a/CPE212/Project_04/project04 b/CPE212/Project_04/project04 new file mode 100644 index 0000000..3a3039a Binary files /dev/null and b/CPE212/Project_04/project04 differ diff --git a/CPE212/Project_04/project04_materials.zip b/CPE212/Project_04/project04_materials.zip new file mode 100644 index 0000000..a1db0ca Binary files /dev/null and b/CPE212/Project_04/project04_materials.zip differ diff --git a/CPE212/Project_05/bstree.cpp b/CPE212/Project_05/bstree.cpp new file mode 100644 index 0000000..df2301e --- /dev/null +++ b/CPE212/Project_05/bstree.cpp @@ -0,0 +1,329 @@ +#include +#include +#include "bstree.h" + + +template +BSTree::BSTree() +{ + BSTreeNode* rootPtr = NULL; +} + +template +// start of Delete(...) +// Recursive function that traverses the tree starting at treePtr to locate the data value to be removed +// Once located, DeleteNode is invoked to remove the value from the tree +// If tree is not empty and item is NOT present, throw NotFoundBSTree +void BSTree::Delete(BSTreeNode*& treePtr, SomeType& item) +{ + if(item < treePtr->data) + Delete(treePtr->leftPtr, item); // Look in left subtree + else if(item > treePtr->data) + Delete(treePtr->rightPtr, item); // Look in right subtree + else if (treePtr->data == item) + DeleteNode(treePtr); // Node found; call DeleteNode + else + NotFoundBSTree(); +} + + +template +void BSTree::DeleteNode(BSTreeNode*& treePtr) +// start of DeleteNode() +// Removes the node pointed to by treePtr from the tree +// Hint: calls GetPredecessor and Delete +{ + SomeType data; + BSTreeNode* tempPtr; + + if (treePtr->leftPtr==NULL) + { + treePtr=treePtr->rightPtr; + delete tempPtr; + } + else if (treePtr->rightPtr==NULL) + { + treePtr = treePtr->leftPtr; + delete tempPtr; + } + else + { + GetPredecessor(treePtr->leftPtr); + treePtr->data = data; + Delete(treePtr->leftPtr, data); + } +} // end of DeleteNode(...) + +template +void BSTree::Insert(BSTreeNode*& ptr, SomeType item) +// Start of Insert(...) +// Recursive function that finds the correct position of item and adds it to the tree +// Throws FoundInBSTree if item is already in the tree +{ + if (ptr==NULL) + { + ptr = new BSTreeNode; + ptr->rightPtr = NULL; + ptr->leftPtr = NULL; + ptr->data = item; + } + else if (item < ptr->data) + Insert(ptr->leftPtr, item); + else + Insert(ptr->rightPtr, item); + //else if (ptr->data == item) FoundInBSTree(); +} + +template +void BSTree::Destroy(BSTreeNode*& ptr) +// Destroy() +// Recursively deallocates every node in the tree pointed to by ptr +{ + if (&ptr==NULL) + { + Destroy(ptr->leftPtr); + Destroy(ptr->rightPtr); + delete ptr; + } +} // end of Destroy() + +template +void BSTree::CopyTree(BSTreeNode*& copy, const BSTreeNode* originalTree) +// CopyTree() +// Recursively copies all data from original tree into copy +{ + if (originalTree == NULL) + copy = NULL; + else + { + copy = new BSTreeNode; + copy->data = originalTree->data; + CopyTree(copy->leftPtr, originalTree->leftPtr); + CopyTree(copy->rightPtr, originalTree->rightPtr); + } +} + +template +SomeType BSTree::GetPredecessor(BSTreeNode* treePtr) const +// GetPredecessor() +// Finds the largest data value in the tree pointed to by treePtr and returns that data value +// as the functions return value +{ + while (treePtr->rightPtr != NULL) + treePtr = treePtr->rightPtr; + return (treePtr->data); +} + +template +int BSTree::CountNodes(BSTreeNode* treePtr) const +// CountNodes() +// Recursive function that counts every node in the tree pointed to by treePtr and returns the +// count as the function return value +{ + if (&treePtr == NULL) + return 0; + else + return CountNodes(treePtr->leftPtr) + CountNodes(treePtr->rightPtr) + 1; +} + +template +int BSTree::LevelCount(BSTreeNode* treePtr) const +// LevelCount() +// Recursive function that traverses the entire tree to determine the total number of levels in the tree +{ + if(treePtr->leftPtr == NULL && treePtr->rightPtr == NULL) + return 0; + + int left = 0; + if (treePtr->leftPtr != NULL) + left = LevelCount(treePtr->leftPtr); + + int right = 0; + if (treePtr->rightPtr != NULL) + right = LevelCount(treePtr->rightPtr); + + return (max(left, right) + 1); +} + +template +int BSTree::FindLevel(BSTreeNode* treePtr, SomeType item) const +// FindLevel() +// Recursive function that traverses the tree looking for item and returns the level where +// item was found +{ + int static level = 0; + // if (treePtr == NULL) + // return 0; + + // int left = 0; + // if (treePtr->leftPtr != NULL && item != treePtr->data) + // left = LevelCount(treePtr->leftPtr); + + // int right = 0; + // if (treePtr->rightPtr != NULL) + // right = LevelCount(treePtr->rightPtr); + + // return (max(left, right)); +} + + + +template +//start of BSTree(...) +BSTree::BSTree(const BSTree& someTree) +// BSTree() +// Copy constructor for BSTree +// Hint: calls CopyTree +{ + if (someTree.rootPtr==NULL) + { + rootPtr=NULL; + } + else + CopyTree(this->rootPtr, someTree.rootPtr); +} + +template +void BSTree::operator=(const BSTree& originalTree) +// operator=() +// Overloaded assignment operator for BSTree. +// Hint: calls CopyTree +{ + if (&originalTree == this) + return; + + Destroy(rootPtr); + CopyTree(rootPtr, originalTree.rootPtr); +} + +template +BSTree::~BSTree() + // ~BSTree() + // Destructor deallocates all tree nodes + // Hint: calls the private helper function Destroy +{ + Destroy(rootPtr); +} + +template +void BSTree::InsertItem(SomeType item) +// InsertItem() +// Inserts item into BSTree; if tree already full, throws FullBSTree exception +// If item is already in BSTree, throw FoundInBSTree exception +// Hint: calls the private helper function Insert +{ + Insert(rootPtr,item); +} + +template +SomeType BSTree::DeleteItem(SomeType item) +// DeleteItem() +// Deletes item from BSTree if item is present AND returns object via function return value +// If tree is empty, throw the EmptyBSTree exception +// If tree is not empty and item is NOT present, throw NotFoundBSTree +// Hint: calls the private helper function Delete +{ + //if (&rootPtr == NULL) EmptyBSTree(); + if (IsEmpty()) + throw EmptyBSTree(); + else + SomeType itemCopy = item; // Make an copy for item + Delete(rootPtr, item); // Delete item in tree + // return itemCopy; +} + + +template +void BSTree::MakeEmpty() +// MakeEmpty() +// Deallocates all BSTree nodes and sets root pointer to NULL +// Hint: calls the private helper function Destroy +{ + Destroy(rootPtr); + rootPtr=NULL; +} + +template +int BSTree::Size() const +// Size() +// Returns total number of data values stored in tree +{ + return CountNodes(rootPtr); +} + +template +bool BSTree::IsFull() const +{ + BSTreeNode* location; + try + { + location = new BSTreeNode; + delete location; + return false; + } + catch( bad_alloc ) + { + return true; + } +} + +template +bool BSTree::IsEmpty() const +{ + if (rootPtr == NULL) return true; + return false; +} + +template +SomeType BSTree::Min() const +{ + // if (rootPtr == NULL) EmptyBSTree(); + + + // BSTreeNode* current; + // ¤t = rootPtr; + // while (current > current->data != NULL) + // { + // current = current->leftPtr; + // } + // return(current->leftPtr); +} + +template +SomeType BSTree::Max() const +{ + // if (rootPtr == NULL) EmptyBSTree(); + + // BSTreeNode* current; + // current = rootPtr; + // while (current > current->data != NULL) + // { + // current = current->rightPtr; + // } + // return(¤t->rightPtr); +} + +template +int BSTree::TotalLevels() const +// TotalLevels() +// Returns the maximum level value for current tree contents +// Levels are numbered 0, 1, ..., N-1. This function returns N +// Throws EmptyBSTree if empty +// Hint: calls the private helper function LevelCount +{ + if (&rootPtr == NULL) EmptyBSTree(); + int level = LevelCount(rootPtr); + return level+1; +} + +template +int BSTree::Level(SomeType item) const +// Level() +// Returns the level within the BSTree at which the value item is found +// If tree is empty, throws EmptyBSTree +// If tree is not empty and item is not found, throws NotFoundBSTree +// Hint: calls the private helper funtion FindLevel +{ + if (rootPtr == NULL) EmptyBSTree(); + return FindLevel(rootPtr, item); +} \ No newline at end of file diff --git a/CPE212/Project_05/bstree.cpp.bak b/CPE212/Project_05/bstree.cpp.bak new file mode 100644 index 0000000..8453f07 --- /dev/null +++ b/CPE212/Project_05/bstree.cpp.bak @@ -0,0 +1,316 @@ +#include +#include +#include "bstree.h" + + +template +// start of Delete(...) +// Recursive function that traverses the tree starting at treePtr to locate the data value to be removed +// Once located, DeleteNode is invoked to remove the value from the tree +// If tree is not empty and item is NOT present, throw NotFoundBSTree +void BSTree::Delete(BSTreeNode*& treePtr, SomeType& item) +{ + if(item < treePtr->data) + Delete(treePtr->leftPtr, item); // Look in left subtree + else if(item > treePtr->data) + Delete(treePtr->rightPtr, item); // Look in right subtree + else if (treePtr == item) + DeleteNode(treePtr); // Node found; call DeleteNode + else + NotFoundBSTree(); +} + + +template +void BSTree::DeleteNode(BSTreeNode*& treePtr) +// start of DeleteNode() +// Removes the node pointed to by treePtr from the tree +// Hint: calls GetPredecessor and Delete +{ + SomeType data; + BSTreeNode* tempPtr; + + if (treePtr->leftPtr==NULL) + { + treePtr=treePtr->rightPtr; + delete tempPtr; + } + else if (treePtr->rightPtr==NULL) + { + treePtr = treePtr->leftPtr; + delete tempPtr; + } + else + { + GetPredecessor(treePtr->leftPtr, data); + treePtr->data = data; + Delete(treePtr->leftPtr, data); + } +} // end of DeleteNode(...) + +template +void BSTree::Insert(BSTreeNode*& ptr, SomeType item) +// Start of Insert(...) +// Recursive function that finds the correct position of item and adds it to the tree +// Throws FoundInBSTree if item is already in the tree +{ + if (ptr == item) FoundInBSTree(); + if (ptr==NULL) + { + ptr = new BSTreeNode; + ptr->rightPtr = NULL; + ptr->leftPtr = NULL; + ptr->data = item; + } + else if (item < ptr->data) + Insert(ptr->leftPtr, item); + else + Insert(item->rightptr, item); + if (ptr ==item) FoundInBSTree(); +} + +template +void BSTree::Destroy(BSTreeNode*& ptr) +// Destroy() +// Recursively deallocates every node in the tree pointed to by ptr +{ + if (ptr==NULL) + { + Destroy(ptr->leftPtr); + Destroy(ptr->rightPtr); + delete ptr; + } +} // end of Destroy() + +template +void BSTree::CopyTree(BSTreeNode*& copy, const BSTreeNode* originalTree) +// CopyTree() +// Recursively copies all data from original tree into copy +{ + if (originalTree == NULL) + copy = NULL; + else + { + copy = new BSTreeNode; + copy->data = originalTree->data; + CopyTree(copy->leftPtr, originalTree->leftPtr); + CopyTree(copy->rightPtr, originalTree->rightPtr); + } +} + +template +SomeType BSTree::GetPredecessor(BSTreeNode* treePtr) const +// GetPredecessor() +// Finds the largest data value in the tree pointed to by treePtr and returns that data value +// as the functions return value +{ + while (treePtr->rightPtr != NULL) + treePtr = treePtr->rightPtr; + data = treePtr->data; +} + +template +int BSTree::CountNodes(BSTreeNode* treePtr) const +// CountNodes() +// Recursive function that counts every node in the tree pointed to by treePtr and returns the +// count as the function return value +{ + if (treePtr == NULL) + return 0; + else + return CountNodes(treePtr->leftPtr) + CountNodes(treePtr->rightPtr) + 1; +} + +template +int BSTree::LevelCount(BSTreeNode* treePtr) const +// LevelCount() +// Recursive function that traverses the entire tree to determine the total number of levels in the tree +{ + if(treePtr->leftPtr == NULL && treePtr->rightPtr == NULL) + return 0; + + int left = 0; + if (treePtr->leftPtr != NULL) + left = LevelCount(treePtr->leftPtr); + + int right = 0; + if (treePtr->rightPtr != NULL) + right = LevelCount(treePtr->rightPtr); + + return (max(left, right) + 1); +} + +template +int BSTree::FindLevel(BSTreeNode* treePtr, SomeType item) const +// FindLevel() +// Recursive function that traverses the tree looking for item and returns the level where +// item was found +{ + int static level = 0; + if (treePtr == NULL) + return 0; + + int left = 0; + if (treePtr->leftPtr != NULL && treePtr->data != item) + left = LevelCount(treePtr->leftPtr); + + int right = 0; + if (treePtr->rightPtr != NULL) + right = LevelCount(treePtr->rightPtr); + + return (max(left, right)); +} + +template +BSTree::BSTree() +{ + rootPtr=NULL; +} + + +template +//start of BSTree(...) +BSTree::BSTree(const BSTree& someTree) +// BSTree() +// Copy constructor for BSTree +// Hint: calls CopyTree +{ + CopyTree(someTree); +} + +template +void BSTree::operator=(const BSTree& originalTree) +// operator=() +// Overloaded assignment operator for BSTree. +// Hint: calls CopyTree +{ + if (originalTree==this) + return; + + Destroy(rootPtr); + CopyTree(originalTree); +} + +template +BSTree::~BSTree() + // ~BSTree() + // Destructor deallocates all tree nodes + // Hint: calls the private helper function Destroy +{ + Destroy(rootPtr); +} + +template +void BSTree::InsertItem(SomeType item) +// InsertItem() +// Inserts item into BSTree; if tree already full, throws FullBSTree exception +// If item is already in BSTree, throw FoundInBSTree exception +// Hint: calls the private helper function Insert +{ + Insert(item); +} + +template +SomeType BSTree::DeleteItem(SomeType item) +// DeleteItem() +// Deletes item from BSTree if item is present AND returns object via function return value +// If tree is empty, throw the EmptyBSTree exception +// If tree is not empty and item is NOT present, throw NotFoundBSTree +// Hint: calls the private helper function Delete +{ + if (rootPtr == NULL) EmptyBSTree(); + Delete(item); +} + +template +void BSTree::MakeEmpty() +// MakeEmpty() +// Deallocates all BSTree nodes and sets root pointer to NULL +// Hint: calls the private helper function Destroy +{ + Delete(rootPtr); + rootPtr=NULL; +} + +template +int BSTree::Size() const +// Size() +// Returns total number of data values stored in tree +{ + return CountNodes(rootPtr); +} + +template +bool BSTree::IsFull() const +{ + BSTreeNode* location; + try + { + location = new BSTreeNode; + delete location; + return false; + } + catch( bad_alloc ) + { + return true; + } +} + +template +bool BSTree::IsEmpty() const +{ + if (rootPtr == NULL) return true; + return false; +} + +template +SomeType BSTree::Min() const +{ + if (rootPtr == NULL) EmptyBSTree(); + + int res = rootPtr->data; + BSTreeNode* current; + while (current->leftPtr != NULL) + { + current = current->leftPtr; + } + return(current->leftPtr); +} + +template +SomeType BSTree::Max() const +{ + if (rootPtr == NULL) EmptyBSTree(); + + BSTreeNode* current; + while (current->rightPtr != NULL) + { + current = current->rightPtr; + } + return(current->rightPtr); +} + +template +int BSTree::TotalLevels() const +// TotalLevels() +// Returns the maximum level value for current tree contents +// Levels are numbered 0, 1, ..., N-1. This function returns N +// Throws EmptyBSTree if empty +// Hint: calls the private helper function LevelCount +{ + if (rootPtr == NULL) EmptyBSTree(); + int level = LevelCount(rootPtr); + return level+1; +} + +template +int BSTree::Level(SomeType item) const +// Level() +// Returns the level within the BSTree at which the value item is found +// If tree is empty, throws EmptyBSTree +// If tree is not empty and item is not found, throws NotFoundBSTree +// Hint: calls the private helper funtion FindLevel +{ + if (rootPtr == NULL) EmptyBSTree(); + return FindLevel(rootPtr, item); +} \ No newline at end of file diff --git a/CPE212/Project_05/bstree.h b/CPE212/Project_05/bstree.h new file mode 100644 index 0000000..22a623e --- /dev/null +++ b/CPE212/Project_05/bstree.h @@ -0,0 +1,187 @@ +// +// bstree.h 2010 Fall CPE 212 - Project05 - Binary Search Tree Template +// +// Provides a declaration of the BSTree class template. +// +// DO NOT MODIFY OR SUBMIT THIS FILE +// + +#ifndef BSTREE_H +#define BSTREE_H + +#include +#include +#include + +using namespace std; + +class FullBSTree // Exception class models full BSTree condition +{ + /* No code here */ +}; + +class EmptyBSTree // Exception class models empty BSTree condition +{ + /* No code here */ +}; + +class NotFoundBSTree // Exception class models not found in BSTree condition +{ + /* No code here */ +}; + +class FoundInBSTree // Exception class models found in BSTree condition +{ + /* No code here */ +}; + +template +struct BSTreeNode // Node of BSTree +{ + SomeType data; // Data stored in node + BSTreeNode* leftPtr; // Pointer to left subtree + BSTreeNode* rightPtr; // Pointer to right subtree +}; + +template +class BSTree // BSTree Abstract Data Type +{ +private: + BSTreeNode* rootPtr; // Pointer to root of BSTree + + /************** Start of Private Helper Functions You Must Implement ****************/ + void Delete(BSTreeNode*& treePtr, SomeType& item); + // Delete() + // Recursive function that traverses the tree starting at treePtr to locate the data value to be removed + // Once located, DeleteNode is invoked to remove the value from the tree + // If tree is not empty and item is NOT present, throw NotFoundBSTree + + void DeleteNode(BSTreeNode*& treePtr); + // DeleteNode() + // Removes the node pointed to by treePtr from the tree + // Hint: calls GetPredecessor and Delete + + void Insert(BSTreeNode*& ptr, SomeType item); + // Insert() + // Recursive function that finds the correct position of item and adds it to the tree + // Throws FoundInBSTree if item is already in the tree + + void Destroy(BSTreeNode*& ptr); + // Destroy() + // Recursively deallocates every node in the tree pointed to by ptr + + void CopyTree(BSTreeNode*& copy, const BSTreeNode* originalTree); + // CopyTree() + // Recursively copies all data from original tree into copy + + SomeType GetPredecessor(BSTreeNode* treePtr) const; + // GetPredecessor() + // Finds the largest data value in the tree pointed to by treePtr and returns that data value + // as the functions return value + + int CountNodes(BSTreeNode* treePtr) const; + // CountNodes() + // Recursive function that counts every node in the tree pointed to by treePtr and returns the + // count as the function return value + + int LevelCount(BSTreeNode* treePtr) const; + // LevelCount() + // Recursive function that traverses the entire tree to determine the total number of levels in the tree + + int FindLevel(BSTreeNode* treePtr, SomeType item) const; + // FindLevel() + // Recursive function that traverses the tree looking for item and returns the level where + // item was found + + + /************** End of Private Helper Functions You Must Implement ****************/ + +public: + + /************** Start of Public Interface Functions You Must Implement ****************/ + + BSTree(); + // BSTree() + // Default constructor initializes root pointer to NULL + + BSTree(const BSTree& someTree); + // BSTree() + // Copy constructor for BSTree + // Hint: calls CopyTree + + void operator=(const BSTree& originalTree); + // operator=() + // Overloaded assignment operator for BSTree. + // Hint: calls CopyTree + + ~BSTree(); + // ~BSTree() + // Destructor deallocates all tree nodes + // Hint: calls the private helper function Destroy + + void InsertItem(SomeType item); + // InsertItem() + // Inserts item into BSTree; if tree already full, throws FullBSTree exception + // If item is already in BSTree, throw FoundInBSTree exception + // Hint: calls the private helper function Insert + + SomeType DeleteItem(SomeType item); + // DeleteItem() + // Deletes item from BSTree if item is present AND returns object via function return value + // If tree is empty, throw the EmptyBSTree exception + // If tree is not empty and item is NOT present, throw NotFoundBSTree + // Hint: calls the private helper function Delete + + void MakeEmpty(); + // MakeEmpty() + // Deallocates all BSTree nodes and sets root pointer to NULL + // Hint: calls the private helper function Destroy + + int Size() const; + // Size() + // Returns total number of data values stored in tree + + bool IsFull() const; + // IsFull() + // Returns true if BSTree is full; returns false otherwise + + bool IsEmpty() const; + // IsEmpty() + // Returns true if BSTree is empty; returns false otherwise + + SomeType Min() const; + // Min() + // Returns minimum value in tree; throws EmptyBSTree if tree is empty + + SomeType Max() const; + // Max() + // Returns maximum value in tree; throws EmptyBSTree if tree is empty + + int TotalLevels() const; + // TotalLevels() + // Returns the maximum level value for current tree contents + // Levels are numbered 0, 1, ..., N-1. This function returns N + // Throws EmptyBSTree if empty + // Hint: calls the private helper function LevelCount + + int Level(SomeType item) const; + // Level() + // Returns the level within the BSTree at which the value item is found + // If tree is empty, throws EmptyBSTree + // If tree is not empty and item is not found, throws NotFoundBSTree + // Hint: calls the private helper funtion FindLevel + + /************** End of Functions You Must Implement ****************/ + + + + void Print() const; // DO NOT WRITE THIS FUNCTION + // Print() + // Prints binary search tree contents in inorder, preorder, and postorder forms + // NOTE: THIS CODE HAS BEEN INCLUDED AT THE END OF main.cpp +}; + +#include "bstree.cpp" // Note: Template classes cannot be compiled on their own + // since the data type argument is found in the client code. + +#endif diff --git a/CPE212/Project_05/main.cpp b/CPE212/Project_05/main.cpp new file mode 100644 index 0000000..9615d8f --- /dev/null +++ b/CPE212/Project_05/main.cpp @@ -0,0 +1,320 @@ +// +// main.cpp 2010 Fall CPE 212 - Project05 - Binary Search Tree Template +// +// Driver program for BSTree ADT Template -- The text files (read by this code) contain a series +// of commands that will help you test your BSTree ADT Template code by triggering various class methods. +// +// DO NOT SUBMIT THIS FILE +// +#include +#include +#include +#include "bstree.h" +#include "student.h" + + +using namespace std; + + +int main (int argc, char * const argv[]) +{ + ifstream inputs; // Input file for commands + char op, ch; // Hold operation and optional char input + BSTree* tPtr = NULL; // Will point to BSTree object + string comment; + + + // Output usage message if one input file name is not provided + if (argc != 2) + { + cout << "Usage:\n project05 \n"; + return 1; + } + + // Attempt to open input file -- terminate if file does not open + inputs.open(argv[1]); + if (!inputs) + { + cout << "Error - unable to open input file" << endl; + return 1; + } + + // Process commands from input file + getline(inputs, comment); + cout << endl << comment << endl << endl; // Output header comment + inputs >> op; // Attempt to input first command + while (inputs) + { + // Select and perform operation input from file + + switch (op) + { + case '#': // Test file comment + getline(inputs, comment); + cout << '#' << comment; + break; + + case 'c': // Constructor + cout << endl << "Constructor()"; + try + { + tPtr = new BSTree; + cout << endl; + } + catch ( std::bad_alloc ) + { + cout << "Failed : Terminating now..." << endl; + return 1; + } + break; + + case '!': // Test copy constructor + try + { + cout << endl << "*** Start Copy Constructor Test ***" << endl; + BSTree dummy = *tPtr; + Student s; + inputs >> s; + cout << "Print Copy without new value" << endl; + dummy.Print(); + dummy.InsertItem(s); + cout << "Print Copy plus new value" << endl; + dummy.Print(); + cout << "Print Original without new value" << endl; + tPtr->Print(); + cout << "CopyConstructor -- successful" << endl; + } + catch (...) + { + cout << "CopyConstructor -- Failed: copy constructor" << endl; + } + cout << "*** End Copy Constructor Test ***" << endl; + break; + + case '=': // Test overloaded assignment operator + try + { + cout << endl << "*** Start Operator= Test ***" << endl; + BSTree dummy; + dummy = *tPtr; + Student s; + inputs >> s; + cout << "Print Copy without new value" << endl; + dummy.Print(); + dummy.InsertItem(s); + cout << "Print Copy plus new value" << endl; + dummy.Print(); + cout << "Print Original without new value" << endl; + tPtr->Print(); + cout << "Operator= -- successful" << endl; + } + catch (...) + { + cout << "Operator= -- Failed: assignment operator" << endl; + } + cout << "*** End Operator= Test ***" << endl; + break; + case '+': // InsertItem + + try + { + Student s; // Create temporary object to hold student info from file + inputs >> s; // Use overloaded operator to populate temporary object + cout << "InsertItem('"; + s.Print(); + cout << "')"; + tPtr->InsertItem(s); + } + catch (FullBSTree) + { + cout << " -- Failed Full BSTree"; + } + catch (FoundInBSTree) + { + cout << " -- Failed Item Already Found In BSTree"; + } + cout << endl; + break; + + case '-': // DeleteItem + try + { + int id; + inputs >> id; + Student s(id, "NULL", "NULL"); + cout << "DeleteItem('" << id << "') -- "; + s = tPtr->DeleteItem(s); + cout << "Deleted "; + s.Print(); + } + catch (EmptyBSTree) + { + cout << " -- Failed Empty BSTree"; + } + catch (NotFoundBSTree) + { + cout << " -- Failed Not Found in BSTree"; + } + cout << endl; + break; + + case 'p': // Print BSTree + tPtr->Print(); + break; + + case 's': // Size of BSTree + cout << "Size() -- " << tPtr->Size() << endl; + break; + + case 'm': // Make BSTree Empty + tPtr->MakeEmpty(); + cout << "MakeEmpty()"<< endl; + break; + + case 'd': // Destructor + delete tPtr; + tPtr = NULL; + cout << "Destructor()" << endl << endl; + break; + + case '<': // Minimum + cout << "Min() -- "; + try + { + cout << tPtr->Min() << endl; + } + catch ( EmptyBSTree ) + { + cout << "Failed Empty BSTree" << endl; + } + break; + + case '>': // Maximum + cout << "Max() -- "; + try + { + cout << tPtr->Max() << endl; + } + catch ( EmptyBSTree ) + { + cout << "Failed Empty BSTree" << endl; + } + break; + + case 'l': // Size of BSTree + try + { + cout << "TotalLevels() -- " << tPtr->TotalLevels() << endl; + } + catch ( EmptyBSTree ) + { + cout << "TotalLevels() -- Failed Empty BSTree" << endl; + } + break; + + case '?': // Size of BSTree + try + { + int id; + inputs >> id; + Student s(id, "NULL", "NULL"); + cout << "Level('" << s << "') -- "; + cout << tPtr->Level(s) << endl; + } + catch ( EmptyBSTree ) + { + cout << "Failed Empty BSTree" << endl; + } + break; + + default: // Error + cout << "Error - unrecognized operation '" << op << "'" << endl; + cout << "Terminating now..." << endl; + return 1; + break; + } + + inputs >> op; // Attempt to input next command + } + + + return 0; +} + +/************** Implementation of Print() function ********************/ + +// DO NOT MODIFY THIS CODE + +#include + +// This code uses the Standard Template Libary queue class, container adapter wrapper +// that makes the deque (double-ended queue) look more like a single-ended queue. +// Note the different names used for the enqueue and dequeue operations. + +template +void PreOrder(BSTreeNode* tree, queue& preorder) +// Post: preorder contains the tree items in preorder. +{ + if (tree != NULL) + { + preorder.push(tree->data); + PreOrder(tree->leftPtr, preorder); + PreOrder(tree->rightPtr, preorder); + } +} + +template +void InOrder(BSTreeNode* tree, queue& inorder) +// Post: inorder contains the tree items in inorder. +{ + if (tree != NULL) + { + InOrder(tree->leftPtr, inorder); + inorder.push(tree->data); + InOrder(tree->rightPtr, inorder); + } +} + +template +void PostOrder(BSTreeNode* tree, queue& postorder) +// Post: postorder contains the tree items in postorder. +{ + if (tree != NULL) + { + PostOrder(tree->leftPtr, postorder); + PostOrder(tree->rightPtr, postorder); + postorder.push(tree->data); + } +} + +template +void BSTree::Print() const +{ + queue preorder, inorder, postorder; + + PreOrder(rootPtr, preorder); + InOrder(rootPtr, inorder); + PostOrder(rootPtr, postorder); + + cout << "Print() \n-- Inorder = { "; + while (!inorder.empty()) + { + cout << inorder.front() << " "; + inorder.pop(); + } + cout << "} \n-- Preorder = { "; + while (!preorder.empty()) + { + cout << preorder.front() << " "; + preorder.pop(); + } + cout << "} \n-- Postorder = { "; + while (!postorder.empty()) + { + cout << postorder.front() << " "; + postorder.pop(); + } + cout << "}" << endl; +} + + diff --git a/CPE212/Project_05/main.o b/CPE212/Project_05/main.o new file mode 100644 index 0000000..8e1ddb7 Binary files /dev/null and b/CPE212/Project_05/main.o differ diff --git a/CPE212/Project_05/makefile b/CPE212/Project_05/makefile new file mode 100644 index 0000000..bf27bc6 --- /dev/null +++ b/CPE212/Project_05/makefile @@ -0,0 +1,19 @@ +# Project06 makefile +# To disable the gcov options use a # to comment out the +# following line and uncomment the line below it +#CC = g++ -fprofile-arcs -ftest-coverage +CC = g++ + +project05: main.o student.o + $(CC) main.o student.o -o project05 + +main.o: main.cpp bstree.h + $(CC) -c main.cpp + +student.o: student.cpp student.h + $(CC) -c student.cpp + +clean: + rm *.o *.gcda *.gcno *.gcov project05 + + diff --git a/CPE212/Project_05/p05input1.txt b/CPE212/Project_05/p05input1.txt new file mode 100644 index 0000000..ddf8e69 --- /dev/null +++ b/CPE212/Project_05/p05input1.txt @@ -0,0 +1,68 @@ +// p05input1.txt - Test BSTree(), InsertItem(), ~BSTree() + +# Test creating empty binary search tree +c +p +d + + +# Test adding one student object to binary search tree +c ++ 5678 Washington George +p +d + + +# Test adding student objects pre-sorted highest to lowest id +c ++ 5678 Washington George +p ++ 1234 Jefferson Thomas +p ++ 1000 Madison James +p ++ 888 Nixon Richard +p ++ 555 Lincoln Abraham +p +d + + +# Test adding student objects pre-sorted lowest to highest id +c ++ 555 Lincoln Abraham +p ++ 888 Nixon Richard +p ++ 1000 Madison James +p ++ 1234 Jefferson Thomas +p ++ 5678 Washington George +p +d + + +# Test adding an unsorted sequence of student objects +c ++ 1234 Jefferson Thomas +p ++ 888 Nixon Richard +p ++ 5678 Washington George +p ++ 555 Lincoln Abraham +p ++ 1000 Madison James +p +d + + +# Test adding duplicate student object to tree +c ++ 1234 Jefferson Thomas +p ++ 1234 Jefferson Thomas +p +d + diff --git a/CPE212/Project_05/p05input2.txt b/CPE212/Project_05/p05input2.txt new file mode 100644 index 0000000..4f8b395 --- /dev/null +++ b/CPE212/Project_05/p05input2.txt @@ -0,0 +1,125 @@ +// p05input2.txt - Test BSTree(), InsertItem(), DeleteItem(), MakeEmpty(), ~BSTree() + +# Test deleting leaf node that is the left child of its parent +c ++ 5678 Washington George ++ 1234 Jefferson Thomas ++ 1000 Madison James ++ 555 Lincoln Abraham +p +- 555 +p +d + + +# Test deleting leaf node that is the right child of its parent +c ++ 555 Lincoln Abraham ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 5678 Washington George +p +- 5678 +p +d + + +# Test deleting parent node that has only a left child +c ++ 5678 Washington George ++ 1234 Jefferson Thomas ++ 1000 Madison James ++ 555 Lincoln Abraham +p +- 1000 +p +d + + +# Test deleting parent node that has only a right child +c ++ 555 Lincoln Abraham ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 5678 Washington George +p +- 1234 +p +d + + +# Test deleting parent node that has two children +c ++ 555 Lincoln Abraham ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 5678 Washington George ++ 888 Nixon Richard +p +- 1000 +p +d + + +# Test deleting root node +c ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 555 Lincoln Abraham +p +- 1000 +p +d + + +# Test deleting only node leaving empty tree +c ++ 888 Nixon Richard +p +- 888 +p +d + + +# Test deleting value not in tree +c ++ 888 Nixon Richard +p +- 555 +p +d + + +# Test deleting value from empty tree +c +- 333 +p +d + + + +# Test MakeEmpty deallocating all nodes +c ++ 1234 Jefferson Thomas ++ 888 Nixon Richard ++ 5678 Washington George ++ 555 Lincoln Abraham ++ 1000 Madison James +p +m +p +d + + +# Test MakeEmpty deallocating nodes from empty tree +c +p +m +p +d + + + + + + diff --git a/CPE212/Project_05/p05input3.txt b/CPE212/Project_05/p05input3.txt new file mode 100644 index 0000000..2432415 --- /dev/null +++ b/CPE212/Project_05/p05input3.txt @@ -0,0 +1,28 @@ +// p05input3.txt - Test BSTree(), CopyConstructor, = , ~BSTree() + +# Test Copy Constructor +c ++ 1234 Jefferson Thomas ++ 888 Nixon Richard ++ 5678 Washington George ++ 555 Lincoln Abraham ++ 1000 Madison James +p +! 007 Bond James +d + + +# Test Assignment Operator +c ++ 1234 Jefferson Thomas ++ 888 Nixon Richard ++ 5678 Washington George ++ 555 Lincoln Abraham ++ 1000 Madison James +p += 007 Bond James +d + + + + diff --git a/CPE212/Project_05/p05input4.txt b/CPE212/Project_05/p05input4.txt new file mode 100644 index 0000000..041ea52 --- /dev/null +++ b/CPE212/Project_05/p05input4.txt @@ -0,0 +1,83 @@ +// p05input4.txt - Test Size() + +# Test correctness of size when adding student objects +c +p +s ++ 1234 Jefferson Thomas +p +s ++ 888 Nixon Richard +p +s ++ 5678 Washington George +p +s ++ 555 Lincoln Abraham +p +s ++ 1000 Madison James +p +s +d + + +# Test correctness of size when deleting student objects +c +s ++ 1234 Jefferson Thomas ++ 888 Nixon Richard ++ 5678 Washington George ++ 555 Lincoln Abraham ++ 1000 Madison James +p +s +- 555 +p +s +- 1234 +p +s +- 888 +p +s +- 5678 +p +s +- 1000 +p +s +d + + +# Test correctness of size when adding and deleting student objects +c ++ 1234 Jefferson Thomas +s ++ 888 Nixon Richard +s ++ 5678 Washington George +p +s +- 888 +p +s ++ 555 Lincoln Abraham +p +s ++ 1000 Madison James +p +s +- 1234 +p +s +d + + + +# Test correctness of size for empty tree +c +p +s +d + diff --git a/CPE212/Project_05/p05input5.txt b/CPE212/Project_05/p05input5.txt new file mode 100644 index 0000000..5f34780 --- /dev/null +++ b/CPE212/Project_05/p05input5.txt @@ -0,0 +1,132 @@ +// p05input5.txt - Test Min(), Max() + +# Test when min is a left child +c ++ 5678 Washington George ++ 1234 Jefferson Thomas +p +< ++ 1000 Madison James ++ 555 Lincoln Abraham +p +< +d + + +# Test when min is root +c ++ 555 Lincoln Abraham ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 5678 Washington George +p +< +d + + +# Test deleting parent node that has two children +c ++ 1234 Jefferson Thomas ++ 555 Lincoln Abraham ++ 1000 Madison James +p +< ++ 5678 Washington George ++ 888 Nixon Richard +p +< +d + + +# Test when min has a right child +c ++ 1000 Madison James ++ 1234 Jefferson Thomas +p +< ++ 555 Lincoln Abraham ++ 888 Nixon Richard +p +< +d + + +# Test when min is the only value +c ++ 888 Nixon Richard +p +< +d + + +# Test min when tree is empty +c +p +< +d + + +# Test when max is a left child +c ++ 5678 Washington George ++ 1234 Jefferson Thomas ++ 1000 Madison James ++ 555 Lincoln Abraham +p +> +d + + +# Test when max is root +c ++ 555 Lincoln Abraham ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 5678 Washington George +p +> +d + + +# Test max when parent node that has two children +c ++ 1234 Jefferson Thomas ++ 555 Lincoln Abraham ++ 1000 Madison James +p +> ++ 5678 Washington George ++ 888 Nixon Richard +p +> +d + + +# Test when max has a right child +c ++ 1000 Madison James ++ 1234 Jefferson Thomas +p +> ++ 555 Lincoln Abraham ++ 888 Nixon Richard +p +> +d + + +# Test when max is the only value +c ++ 888 Nixon Richard +p +> +d + + +# Test max when tree is empty +c +p +> +d + + diff --git a/CPE212/Project_05/p05input6.txt b/CPE212/Project_05/p05input6.txt new file mode 100644 index 0000000..25c2fe9 --- /dev/null +++ b/CPE212/Project_05/p05input6.txt @@ -0,0 +1,46 @@ +// p05input6.txt - Test TotalLevels() + +# Test totallevels as tree grows level by level +c ++ 555 Lincoln Abraham +p +l ++ 1000 Madison James +p +l ++ 1234 Jefferson Thomas +p +l ++ 5678 Washington George +p +l +d + + +# Test totallevels as with a more balance tree +c ++ 555 Lincoln Abraham ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 5678 Washington George ++ 888 Nixon Richard +p +l +d + + +# Test totallevels with single node tree +c ++ 888 Nixon Richard +p +l +d + + +# Test totallevels with empty tree +c +p +l +d + + diff --git a/CPE212/Project_05/p05input7.txt b/CPE212/Project_05/p05input7.txt new file mode 100644 index 0000000..11ea677 --- /dev/null +++ b/CPE212/Project_05/p05input7.txt @@ -0,0 +1,47 @@ +// p05input7.txt - Test Level() + +# Test level as tree grows level by level +c ++ 555 Lincoln Abraham ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 5678 Washington George +p +? 555 +? 1000 +? 1234 +? 5678 +d + + +# Test level as with a more balance tree +c ++ 555 Lincoln Abraham ++ 1000 Madison James ++ 1234 Jefferson Thomas ++ 5678 Washington George ++ 888 Nixon Richard +p +? 555 +? 1000 +? 1234 +? 5678 +? 888 +d + + +# Test level with single node tree +c ++ 888 Nixon Richard +p +? 888 +d + + +# Test level with empty tree +c +p +? 888 +d + + diff --git a/CPE212/Project_05/project05 b/CPE212/Project_05/project05 new file mode 100644 index 0000000..0272abd Binary files /dev/null and b/CPE212/Project_05/project05 differ diff --git a/CPE212/Project_05/project05_materials.zip b/CPE212/Project_05/project05_materials.zip new file mode 100644 index 0000000..472d4a9 Binary files /dev/null and b/CPE212/Project_05/project05_materials.zip differ diff --git a/CPE212/Project_05/student.cpp b/CPE212/Project_05/student.cpp new file mode 100644 index 0000000..acaaad5 --- /dev/null +++ b/CPE212/Project_05/student.cpp @@ -0,0 +1,66 @@ +// +// student.cpp CPE 212 Fall 2010 -- Project05 - Binary Search Tree Template +// +// DO NOT MODIFY OR SUBMIT THIS FILE +// + +#include "student.h" + +Student::Student() +// Constructor initializes sid to -1, lastname and firstname to empty string +{ + sid = -1; + lastname = ""; + firstname = ""; +} // End Student::Student() + + +Student::Student(int id, string lname, string fname) +// Constructor initializes sid, lastname, firstname to id, lname, and fname respectively +{ + sid = id; + lastname = lname; + firstname = fname; +} // End Student::Student() + + +Student::Student(const Student& s) +// Copy constructor -- copies attributes of s into attribute variables of current object +{ + sid = s.sid; + lastname = s.lastname; + firstname = s.firstname; +} + + +bool operator==(const Student& leftop, const Student& rightop) +// Overloaded SAME AS operator +// Returns true if leftop.sid == rightop.sid. Returns false otherwise +{ + return (leftop.sid == rightop.sid); +} // End operator== for Student class + + +bool operator<(const Student& leftop, const Student& rightop) +// Overloaded LESS THAN operator +// Returns true if leftop.sid < rightop.sid. Returns false otherwise +{ + return (leftop.sid < rightop.sid); +} // End operator < for Student class + + +bool operator>(const Student& leftop, const Student& rightop) +// Overloaded GREATER THAN operator +// Returns true if leftop.sid > rightop.sid. Returns false otherwise +{ + return (leftop.sid > rightop.sid); +} // End operator < for Student class + + +void Student::operator=(const Student& op) // Overloaded ASSIGNMENT operator +// Sets this->sid = op.sid, this->lastname = op.lastname, this->firstname = op.firstname +{ + this->sid = op.sid; + this->lastname = op.lastname; + this->firstname = op.firstname; +} // End Student::operator=() diff --git a/CPE212/Project_05/student.h b/CPE212/Project_05/student.h new file mode 100644 index 0000000..d0c28a0 --- /dev/null +++ b/CPE212/Project_05/student.h @@ -0,0 +1,83 @@ +// +// student.h CPE 212 Fall 2010 -- Project05 - Binary Search Tree Template +// +// DO NOT MODIFIY OR SUBMIT THIS FILE +// + +#include +using namespace std; + +#ifndef STUDENT_H +#define STUDENT_H + +class Student +{ +private: + int sid; // Student ID number + string lastname; // Student last name + string firstname; // Student first name + +public: + /**** Start of functions to implement ****/ + + Student(); + // Default constructor initializes sid to -1, firstname and lastname to empty string + + Student(int id, string lname, string fname); + // Constructor initializes sid, lastname, firstname to id, lname, and fname respectively + + Student(const Student& s); + // Copy constructor -- copies attributes of s into attribute variables of current object + + friend bool operator==(const Student& leftop, const Student& rightop); // Overloaded SAME AS operator + // Returns true if leftop.sid == rightop.sid. Returns false otherwise + + friend bool operator<(const Student& leftop, const Student& rightop); // Overloaded LESS THAN operator + // Returns true if leftop.sid < rightop.sid. Returns false otherwise + + friend bool operator>(const Student& leftop, const Student& rightop); // Overloaded GREATER THAN operator + // Returns true if leftop.sid > rightop.sid. Returns false otherwise + + void operator=(const Student& op); // Overloaded ASSIGNMENT operator + // Sets this->sid = op.sid, this->lastname = op.lastname, this->firstname = op.firstname + + /***** End of functions to implement *****/ + + /***** Below are additional functions for your Student class -- DO NOT MOVE OR MODIFY THE CODE BELOW *****/ + + friend istream& operator>>(istream& leftop, Student& rightop) // Overloaded >> operator + // This allows all data associated with a Student object to be input simultaneously from an input stream + { + leftop >> rightop.sid >> rightop.lastname >> rightop.firstname; + + return leftop; + } + + friend ostream& operator<<(ostream& leftop, const Student& rightop) // Overloaded << operator + // This allows all data associated with a Student object to be output simultaneously to an output stream + { + leftop << "(" << rightop.sid << ", " << rightop.firstname << " " << rightop.lastname << ")"; + + return leftop; + } + + void Print() const // Outputs student information in desired format. DO NOT MOVE OR MODIFY + { + cout << "SID: " << sid << " Name: "; + + if (lastname == "") + cout << "NULL"; + else + cout << lastname; + cout << ", "; + + if (firstname == "") + cout << "NULL"; + else + cout << firstname; + } // End Print() +}; + +#endif + + diff --git a/CPE212/Project_05/student.o b/CPE212/Project_05/student.o new file mode 100644 index 0000000..ca96966 Binary files /dev/null and b/CPE212/Project_05/student.o differ diff --git a/CPE212/Project_06/graph.cpp b/CPE212/Project_06/graph.cpp new file mode 100644 index 0000000..ee55e08 --- /dev/null +++ b/CPE212/Project_06/graph.cpp @@ -0,0 +1,164 @@ +#include "graph.h" + + +// Graph +Graph::Graph() +// Constructor initializes vertices linked list to empty +{ + vertices = NULL; +} + +//~Graph() +Graph::~Graph() +// For each VertexNode in the vertices list, Destructor deallocates all EdgeNodes before +// deallocating the VertexNode itself +{ + VertexNode* delV = vertices; + EdgeNode* delE = delV->edgePtr; + + + while (delV != NULL) + { + while (delE != NULL) + { + delE = NULL; + delE = delE->nextPtr; + } + delV = NULL; + delV = delV->nextVertex; + } +} + +// Graph::AddVertex() - adds vertex name to vertices array; assumes space is available +void Graph::AddVertex(string v) +{ + VertexNode* newVert = new VertexNode; // creates memeory for newVert + newVert->vname = v; // assigns the vertex name to v + newVert->edgePtr = NULL; // sets edgePtr to NULL + newVert->nextVertex = NULL; // Sets nextVertex to NULL +} + +// Graph::AddEdge() - adds edge from source to destination vertex with specified weight +// assuming source and destination are already in vertices array +void Graph::AddEdge(string s, string d, int w) +{ + VertexNode* Vertex_S = WhereIs(s); + VertexNode* Vertex_D = WhereIs(d); + + // Initialize newEdge + EdgeNode* newEdge = new EdgeNode; + newEdge->destination = Vertex_D; + newEdge->weight = w; + newEdge->nextPtr = NULL; + if (Vertex_S->edgePtr == NULL) + { + Vertex_S->edgePtr = newEdge; + } + else + { + // Go the the end of edgePtr and add the newEdge to it + while (Vertex_S->edgePtr->nextPtr != NULL) + { + Vertex_S->edgePtr = Vertex_S->edgePtr->nextPtr; + } + Vertex_S->edgePtr->nextPtr = newEdge; + } +} + +// Graph::IsPresent() - returns true if vertex in graph, false otherwise +bool Graph::IsPresent(string v) +{ + VertexNode* vertPresent = vertices; + + //Traverse vertices + while (vertPresent != NULL) + { + if (vertPresent->vname == v) + return true; // found + vertPresent = vertPresent->nextVertex; // advance through graph + } + + // not found + return false; +} + +// WhereIs() - returns pointer to specified vertex, throws exception if vertex not present +VertexNode* Graph::WhereIs(string v) +{ + VertexNode* tempVertex = vertices; + + + // If found + while (tempVertex != NULL) + { + if (tempVertex->vname == v) + return tempVertex; // Found + tempVertex = tempVertex->nextVertex; + } + + // If not found + throw GraphVertexNotFound(); +} + +// Graph::WeightIs() -- returns edge weight if it exists; otherwise, throws GraphEdgeNotFound +int Graph::WeightIs(string s, string d) +{ + VertexNode* sourceV = WhereIs(s); + VertexNode* destV = WhereIs(d); + + // search through edge nodes + while (sourceV->edgePtr != NULL) + { + if (sourceV->edgePtr->destination == destV) + { + return sourceV->edgePtr->weight; + } + sourceV->edgePtr = sourceV->edgePtr; + } + + throw GraphEdgeNotFound(); +} + +void Graph::MarkVertex(string v) +{ + // MarkVertex() + // Marks vertex V as visited + VertexNode* vistedV = WhereIs(v); + vistedV->mark = true; +} + +// Graph::IsMarked() - returns mark status of vertex; assumes vertex is present +bool Graph::IsMarked(string v) +{ + VertexNode* markedV = WhereIs(v); + return markedV->mark; +} + +// Graph::GetToVertices() - returns a queue q of vertices adjacent to vertex named s +void Graph::GetToVertices(string s, queue& q) +{ + VertexNode* tempV = WhereIs(s); + tempV = tempV->nextVertex; + + while (tempV != NULL) + { + q.push(tempV->vname); + tempV = tempV->nextVertex; + } +} + +// DepthFirstSearch() - Finds path through graph from start vertex to destination vertex +void Graph::DepthFirstSearch(string startVertex, string endVertex, queue& path) +{ + stack s; + queue q; + + if ( !( IsPresent(startVertex) && IsPresent(endVertex) ) ) + throw GraphVertexNotFound(); + + bool found = false; + string vertex; + string item; + + // more here if required +} diff --git a/CPE212/Project_06/graph.h b/CPE212/Project_06/graph.h new file mode 100644 index 0000000..bd16b79 --- /dev/null +++ b/CPE212/Project_06/graph.h @@ -0,0 +1,154 @@ +// +// graph.h 2010 Fall CPE 212 - Project06 - Graphs and STL +// +// Specification file for Graph class +// +// DO NOT MODIFY OR SUBMIT THIS FILE +// + +#ifndef GRAPH_H + +#define GRAPH_H + +#include +#include +#include +#include +#include // For STL stack +#include // For STL queue +#include +using namespace std; + + +class GraphPathNotFound { }; // Exception class represents path-not-found condition + +class GraphEdgeNotFound { }; // Exception class represents edge-not-found condition + +class GraphVertexNotFound { }; // Exception class represents vertex-not-found condition + +class GraphFull { }; // Exception class represents graph-full condition + +struct VertexNode; // Forward declaration of VertexNode type + +struct EdgeNode // Structure representing an edge +{ + VertexNode* destination; // Pointer to destination vertex + int weight; // Edge weight + EdgeNode* nextPtr; // Pointer to next edge +}; + +struct VertexNode // Structure representing a vertex +{ + string vname; // Name of vertex + bool mark; // Marked flag + EdgeNode* edgePtr; // Pointer to list of outgoing edges + VertexNode* nextVertex; // Pointer to next vertex in vertices list +}; + + +class Graph // Graph ADT using adjacency list representation +{ + private: //***** Private class members below *****// + VertexNode* vertices; // Linked list of vertex nodes + + public: //***** Public members below *****// + Graph(); + // Graph() + // Constructor initializes vertices linked list to empty + + ~Graph(); + // ~Graph() + // For each VertexNode in the vertices list, Destructor deallocates all EdgeNodes before + // deallocating the VertexNode itself + + void AddVertex(string v); + // AddVertex() + // Adds vertex to graph assuming vertex not already present + + void AddEdge(string s, string d, int w); + // AddEdge() + // Adds edge from source S to destination D with specified weight W. + // If there is not enough memory to add the edge, throw the GraphFull exception + + bool IsPresent(string v); + // IsPresent() + // Returns true if vertex V in graph, false otherwise + + VertexNode* WhereIs(string v); /* Note: This function replaces IndexIs */ + // WhereIs() + // Returns pointer to the vertex node that stores vertex v in the vertices linked list; + // Throws GraphVertexNotFound if V is not present in the vertices list + + int WeightIs(string s, string d); + // WeightIs() + // Returns weight of edge (s,d). Throws GraphEdgeNotFound if edge not present. + + void ClearMarks(); + // ClearMarks() + // Clears all vertex marks + + void MarkVertex(string v); + // MarkVertex() + // Marks vertex V as visited + + bool IsMarked(string v); + // IsMarked() + // Returns true if vertex V is marked, false otherwise + + void GetToVertices(string V, queue& q); + // GetToVertices() + // Returns queue Q of vertex names of those vertices adjacent to vertex V + // The queue here is from the Standard Template Library + + void DepthFirstSearch(string startVertex, string endVertex, queue& path); + // DepthFirstSearch() + // Uses the DFS algorithm from the CPE 212 textbook to determine a path from the + // startVertex to the endVertex. If a path is found, the path vertices should + // be in the path queue. If no path is found, the path queue should be emptied + // as a signal to the client code that no path exists between the start and + // end vertices. + // + // Notes: + // (1) This algorithm is flawed in that as it searches for a path, it may + // output some additional vertices that it visited but were not part + // of the actual path. Implement the algorithm just as it appears in the textbook. + // + // (2) This algorithm requires use of the stack and queue containers from the + // Standard Template Library. The STL stack and queue interfaces may require + // minor modifications to the DFS code from the textbook. + + + // Print -- write graph to stdout. DO NOT MODIFY THIS FUNCTION!!! + void Print() + { + EdgeNode* eptr; + VertexNode* vptr = vertices; + const int FIELDWIDTH = 6; + string STARS = "**********"; + STARS = STARS + STARS + STARS; + + cout << endl << STARS << endl; + + cout << setw(FIELDWIDTH) << "Vertex" << " : " << "Adjacent Vertices" << endl; + cout << "------------------------------" << endl; + + while(vptr != NULL) + { + cout << setw(FIELDWIDTH) << vptr->vname << " : "; + + eptr = vptr->edgePtr; + while (eptr != NULL) + { + cout << eptr->destination->vname << eptr->weight << " "; + eptr = eptr->nextPtr; + } + cout << endl; + vptr = vptr->nextVertex; + } + cout << STARS << endl << endl; + } // Graph::Print() +}; + +#endif + + diff --git a/CPE212/Project_06/graph.o b/CPE212/Project_06/graph.o new file mode 100644 index 0000000..eebb734 Binary files /dev/null and b/CPE212/Project_06/graph.o differ diff --git a/CPE212/Project_06/main.cpp b/CPE212/Project_06/main.cpp new file mode 100644 index 0000000..503fc94 --- /dev/null +++ b/CPE212/Project_06/main.cpp @@ -0,0 +1,165 @@ +// +// main.cpp 2010 Fall CPE 212 - Project06 - Graphs and STL +// +// Driver program for Graph class -- The text files (read by this code) contain a series +// of commands that will help you test your Graph ADT code by triggering various class methods. +// +// DO NOT MODIFY OR SUBMIT THIS FILE +// +#include +#include +#include "graph.h" +#include // For STL stack class +#include // For STL queue class + +using namespace std; + +int main(int argc, char* argv[]) +{ + ifstream inputs; // Input file for commands + char op, ch; // Hold operation and optional char input + Graph* gPtr = NULL; // Will point to Graph object + int num; // Holds number of graph nodes + string v1, v2; // Vertex names input from file + int w; // Edge weight input from file + queue path; // Computed path + string comment; // Comment input from file + + // Output usage message if one input file name is not provided + if (argc != 2) + { + cout << "Usage:\n project07 \n"; + return 1; + } + + // Attempt to open input file -- terminate if file does not open + inputs.open(argv[1]); + if (!inputs) + { + cout << "Error - unable to open input file" << endl; + return 1; + } + + cout << endl; + + // Process commands from input file + getline(inputs, comment); + cout << comment << endl; + + inputs >> op; // Attempt to input number of vertices + while (inputs) + { + switch (op) + { + case '#': // Comment + getline(inputs, comment); + cout << comment << endl; + break; + + case 'c': // Add vertex + cout << "Constructor()" << endl; + gPtr = new Graph(); + break; + + case 'v': // Add vertex + inputs >> v1; + cout << "AddVertex(" << v1 << ")" << endl; + gPtr->AddVertex(v1); + break; + + case 'd': // Add directed edge + inputs >> v1 >> v2 >> w; + cout << "AddEdge(" << v1 << ", " << v2 << ", " << w << ")" << endl; + gPtr->AddEdge(v1, v2, w); + break; + + case 'u': // Add undirected edge + inputs >> v1 >> v2 >> w; + cout << "AddEdge(" << v1 << ", " << v2 << ", " << w << ")" << endl; + gPtr->AddEdge(v1, v2, w); + cout << "AddEdge(" << v2 << ", " << v1 << ", " << w << ")" << endl; + gPtr->AddEdge(v2, v1, w); + break; + + case '?': // IsPresent() + inputs >> v1; + if (gPtr->IsPresent(v1)) + cout << "IsPresent(" << v1 << ") -- true" << endl; + else + cout << "IsPresent(" << v1 << ") -- false" << endl; + break; + + case 'w': // WeightIs() + inputs >> v1 >> v2; + try + { + cout << "WeightIs(" << v1 << ", " << v2 << ") -- "; + w = gPtr->WeightIs(v1, v2); + cout << w << endl; + } + catch ( GraphVertexNotFound ) + { + cout << "Error: vertex not found" << endl; + } + catch ( GraphEdgeNotFound ) + { + cout << "Error: edge not found" << endl; + } + break; + + case 's': // Perform Depth-First Search + inputs >> v1 >> v2; // Input v1-start and v2-end vertices + + cout << "DFS( " << v1 << ", " << v2 << " ) -- "; + try + { + gPtr->DepthFirstSearch(v1, v2, path); + + + if (path.empty()) + cout << "No path found" << endl; + else + { + cout << " { "; + while (!path.empty()) + { + cout << path.front() << " "; + path.pop(); + } + cout << "}" << endl; + } + } + catch ( GraphVertexNotFound ) + { + cout << "Error: vertex not found" << endl; + } + + while (!path.empty()) + path.pop(); + + break; + + case 'p': // Print Graph + gPtr->Print(); + break; + + case '~': // Destructor + delete gPtr; + gPtr = NULL; + cout << "Destructor()" << endl << endl; + break; + + default: // Error + cout << "Error - unrecognized operation '" << op << "'" << endl; + cout << "Terminating now..." << endl; + return 1; + break; + } + + inputs >> op; // Attempt to input next command + } + + + return 0; +} + diff --git a/CPE212/Project_06/main.o b/CPE212/Project_06/main.o new file mode 100644 index 0000000..85ef453 Binary files /dev/null and b/CPE212/Project_06/main.o differ diff --git a/CPE212/Project_06/makefile b/CPE212/Project_06/makefile new file mode 100644 index 0000000..d447192 --- /dev/null +++ b/CPE212/Project_06/makefile @@ -0,0 +1,15 @@ +# Project06 makefile + + +project06: graph.o main.o + g++ graph.o main.o -o project06 + +graph.o: graph.h graph.cpp + g++ -c graph.cpp + +main.o: graph.h main.cpp + g++ -c main.cpp + +clean: + rm *.o project06 + diff --git a/CPE212/Project_06/p06input1.txt b/CPE212/Project_06/p06input1.txt new file mode 100644 index 0000000..82c03bc --- /dev/null +++ b/CPE212/Project_06/p06input1.txt @@ -0,0 +1,41 @@ +# p06input1.txt - Test Graph(), ~Graph(), AddVertex(), AddEdge() with undirected graph + +c +v A +v B +v C +v D +u A B 5 +u A C 10 +u B C 15 +u B D 25 +u C D 20 +p +~ + + +c +v A +v B +v C +v D +v E +v F +v G +v H +u A B 25 +u A C 10 +u A E 60 +u B G 75 +u B H 15 +u C E 15 +u D F 25 +u D H 80 +u E G 35 +u E F 5 +u F H 40 +p +~ + + + diff --git a/CPE212/Project_06/p06input2.txt b/CPE212/Project_06/p06input2.txt new file mode 100644 index 0000000..9c99579 --- /dev/null +++ b/CPE212/Project_06/p06input2.txt @@ -0,0 +1,40 @@ +# p06input2.txt - Test Graph(), ~Graph(), AddVertex(), AddEdge() with directed graph +c +v A +v B +v C +v D +d A B 5 +d A C 10 +d B C 15 +d B D 25 +d C D 20 +p +~ + + +c +v A +v B +v C +v D +v E +v F +v G +v H +d A B 25 +d A C 10 +d A E 60 +d B G 75 +d B H 15 +d C E 15 +d D F 25 +d D H 80 +d E G 35 +d E F 5 +d F H 40 +p +~ + + + diff --git a/CPE212/Project_06/p06input3.txt b/CPE212/Project_06/p06input3.txt new file mode 100644 index 0000000..463a4da --- /dev/null +++ b/CPE212/Project_06/p06input3.txt @@ -0,0 +1,33 @@ +# p06input3.txt - Test IsPresent() + +c +v A +v B +v C +v D +v E +v F +v G +v H +u A B 25 +u A C 10 +u A E 60 +u B G 75 +u B H 15 +u C E 15 +u D F 25 +u D H 80 +u E G 35 +u E F 5 +u F H 40 +p +? A +? B +? G +? H +? K +? Z +~ + + + diff --git a/CPE212/Project_06/p06input4.txt b/CPE212/Project_06/p06input4.txt new file mode 100644 index 0000000..e8c7545 --- /dev/null +++ b/CPE212/Project_06/p06input4.txt @@ -0,0 +1,31 @@ +# p06input4.txt - Test WeightIs() and its error handling + +c +v A +v B +v C +v D +v E +v F +v G +v H +u A B 25 +u A C 10 +u A E 60 +u B G 75 +u B H 15 +u C E 15 +u D F 25 +u D H 80 +u E G 35 +u E F 5 +u F H 40 +p +w E F +w F H +w A K +w A H +~ + + + diff --git a/CPE212/Project_06/p06input5.txt b/CPE212/Project_06/p06input5.txt new file mode 100644 index 0000000..0ae9414 --- /dev/null +++ b/CPE212/Project_06/p06input5.txt @@ -0,0 +1,23 @@ +# p06input5.txt - Test DepthFirstSearch() and supporting functions + +c +v A +v B +v C +v D +u A B 5 +u A C 10 +u B C 15 +u B D 25 +u C D 20 +p +s A B +s A C +s A D +s A K +s D A +~ + + + + diff --git a/CPE212/Project_06/p06input6.txt b/CPE212/Project_06/p06input6.txt new file mode 100644 index 0000000..e4f3044 --- /dev/null +++ b/CPE212/Project_06/p06input6.txt @@ -0,0 +1,21 @@ +# p06input6.txt - Test DepthFirstSearch() and supporting functions + +c +v A +v B +v C +v D +d A B 5 +d A C 10 +d B C 15 +d D B 25 +d C D 20 +p +s A B +s A C +s A D +s A K +s D A +~ + + diff --git a/CPE212/Project_06/p06input7.txt b/CPE212/Project_06/p06input7.txt new file mode 100644 index 0000000..90e798e --- /dev/null +++ b/CPE212/Project_06/p06input7.txt @@ -0,0 +1,34 @@ +# p06input7.txt - Test DepthFirstSearch() and supporting functions + +c +v A +v B +v C +v D +v E +v F +v G +v H +u A B 25 +u A C 10 +u A E 60 +u B G 75 +u B H 15 +u C E 15 +u D F 25 +u D H 80 +u E G 35 +u E F 5 +u F H 40 +p +s A B +s A C +s A G +s A D +s A E +s A H +s A K +~ + + + diff --git a/CPE212/Project_06/p06input8.txt b/CPE212/Project_06/p06input8.txt new file mode 100644 index 0000000..aa95d34 --- /dev/null +++ b/CPE212/Project_06/p06input8.txt @@ -0,0 +1,36 @@ +# p06input8.txt - Test DepthFirstSearch() and supporting functions + +c +v A +v B +v C +v D +v E +v F +v G +v H +d A B 25 +d A C 10 +d A E 60 +d B G 75 +d B H 15 +d C E 15 +d D F 25 +d D H 80 +d E G 35 +d E F 5 +d F H 40 +p +s A B +s A C +s A G +s A D +s A E +s A H +s A K +s G A +s H E +~ + + + diff --git a/CPE212/Project_06/project06 b/CPE212/Project_06/project06 new file mode 100644 index 0000000..1d03a18 Binary files /dev/null and b/CPE212/Project_06/project06 differ diff --git a/CPE212/Project_06/project06_materials.zip b/CPE212/Project_06/project06_materials.zip new file mode 100644 index 0000000..9cb405f Binary files /dev/null and b/CPE212/Project_06/project06_materials.zip differ diff --git a/CPE212/Project_06/project_6.pdf b/CPE212/Project_06/project_6.pdf new file mode 100644 index 0000000..72969df Binary files /dev/null and b/CPE212/Project_06/project_6.pdf differ diff --git a/CPE212/project02_materials.zip b/CPE212/project02_materials.zip new file mode 100644 index 0000000..afd4483 Binary files /dev/null and b/CPE212/project02_materials.zip differ diff --git a/CPE221/CreateHeaders.bash b/CPE221/CreateHeaders.bash new file mode 100644 index 0000000..4526f23 --- /dev/null +++ b/CPE221/CreateHeaders.bash @@ -0,0 +1,39 @@ +#!/bin/bash +if [ -e Cpp_header.cpp ] +then + + if [ -e a.out ] + then + rm a.out + fi + OSNAME=`uname -s` + if [ $OSNAME == "SunOS" ] + then + CC Cpp_header.cpp + elif [ $OSNAME == "Linux" ] + then + g++ Cpp_header.cpp + else + echo "machine OS ($OSNAME) not recognized. contact TA" + exit + fi + if [ -e a.out ] + then + rm a.out + for x in `ls ` + do + if [ -d $x ] + then + echo "Copying Cpp_header.cpp to directory $x" + cp Cpp_header.cpp $x/$x.cpp + fi + done + else + echo "The File Cpp_header.cpp does not compile." + echo "Fix the problems and run this script again." + fi +else + echo "The file Cpp_header.cpp does not exist." + echo "Correct this problem and run the script again" +fi + diff --git a/CPE221/DataTypes1_01.cpp b/CPE221/DataTypes1_01.cpp new file mode 100644 index 0000000..54bfe85 --- /dev/null +++ b/CPE221/DataTypes1_01.cpp @@ -0,0 +1,54 @@ +// DataTypes 1, program 1: DataTypes1_01.cpp +// +#include +#include + +#include // required for chharacter functions + +using namespace std; + +// This program looks at char variables and how they correspond +// to integers. +// +int main() +{ + const float PI = 3.14159; + int count; // loop control variable + char letter; // holds character corresponding to count + string line; // used for program flow control + + // can you assign a character variable to a string + letter='j'; + line = letter; + cout << "Assigned character variable to a string variable: " << line << endl; + + // print out the corresponding character for an integer value + // The machine has the ascii character set, so only integers + // 0 to 127 have significance. However, there are other + // characters available for values 128 to 255. Note that since + // char variables are only one byte, the highest integer value + // that can be assigned to them is 255. A value of 256 results + // in a wrapping back to 0, 257 to 1, etc. + + for (count = 0 ; count < 260; count++) + { + letter = count; // use implicit coercion to assign an integer value + // to the char variable letter + cout << "Count: " << count; + cout << " integer(0-256): " << count%256 << " is: " << letter << endl; + + // put a pause in the printing of the values after every 20 values. + // Note testing for a vlue of 19 instead of 0 since count starts at 0 + // if I tested for equal to 0, I would get a pause after one value and then every + // twenty. by testing on 19, the first pause occurs after 20 values every time + + if (count%20 == 19) + { + cout << "press enter to continue:"; + getline(cin,line); + } + } + + + return 0; +} diff --git a/CPE221/DataTypes2_02.cpp b/CPE221/DataTypes2_02.cpp new file mode 100644 index 0000000..69b3686 --- /dev/null +++ b/CPE221/DataTypes2_02.cpp @@ -0,0 +1,58 @@ +// +// ***** Program Ch03_2.cpp *********** +// Example of arithmetic operations, increment and decrement +// operators +#include + +using namespace std; + +int main() +{ + // declare variables for use in the program and assign them an initial + // value. These variables are used in various expressions to illustrate + // mathematical computations in C++ + int num1 = 10, num2 = 20, num3 = 30; + float flt1 = 40, flt2 = 50.0, flt3 = 60.5; + int num; + float flt; + + + // Output the values of the variables used in the program. This information + // is then used to verify the results shown for the mathematical operations + + cout << "num1 = " << num1 << " : num2 = " << num2 << " : num3 = " << num3 << endl; + cout << "flt1 = " << flt1 << " : flt2 = " << flt2 << " : flt3 = " << flt3 << endl; + cout << "=================================================================\n"; + + // Addition and subtraction + // Perform integer and floating point addition and subtraction and output + // the results. + cout << "Addition and subtraction\n\n"; + num = num1 - num2 + num3 +5; + cout << "num1 - num2 + num3 +5 = " << num << endl; + flt = -flt1 + flt2 + flt3; + cout << "-flt1 + flt2 + flt3 = " << flt << endl; + cout << "=================================================================\n"; + + // Integer and Floating point multiplication examples + cout << "Multiplication\n\n"; + cout << "num1*num2 = " << num1*num2 << endl; + cout << "flt1*flt3 = " << flt1*flt3 << endl; + cout << "=================================================================\n"; + + + // Example of floating point division + cout << "floating point division\n"; + cout << "flt1/flt2 = " << flt1/flt2 << endl; + cout << "16.0000/5.0000 = " << 16.0000/5.0000 << endl; + cout << "16.0000/4.0000 = " << 16.0000/4.0000 << endl; + + // Example of integer division + cout << "\nInteger division: " << num1 << "/" << num2 << " = " + << num1/num2 << endl; + cout << "integer division2, 19/3 = " << 19/3 << endl; + cout << "integer division3, 17/9 = " << 17/9 << endl; + cout << "=================================================================\n"; + + return 0; +} diff --git a/CPE221/DataTypes2_02b.cpp b/CPE221/DataTypes2_02b.cpp new file mode 100644 index 0000000..d69143c --- /dev/null +++ b/CPE221/DataTypes2_02b.cpp @@ -0,0 +1,31 @@ +// +// ***** Program Ch03_2b.cpp *********** +// Example of arithmetic operations, increment and decrement +// operators +#include + +using namespace std; + +int main() +{ + + cout << "Integer division\n\n"; + cout << "10/2: " << 10/2 << endl; + cout << "10/3: " << 10/3 << endl; + cout << "10/4: " << 10/4 << endl; + cout << "10/6: " << 10/6 << endl; + + cout << "\nModulus operation\n"; + // Modulus operation examples. These examples show the + // result of the modulos operation on various integer division values. + + cout << "10 mod 2: " << 10%2 << endl; + cout << "10 mod 3: " << 10%3 << endl; + cout << "10 mod 4: " << 10%4 << endl; + cout << "10 mod 6: " << 10%6 << endl; + cout << "*******************************\n"; + //cout << "10.5 mod 6.5: " << 10.5%6.5 << endl; + + + return 0; +} diff --git a/CPE221/DataTypes2_02c.cpp b/CPE221/DataTypes2_02c.cpp new file mode 100644 index 0000000..9de711c --- /dev/null +++ b/CPE221/DataTypes2_02c.cpp @@ -0,0 +1,53 @@ +// +// ***** Program Ch03_2c.cpp *********** +// Example of arithmetic operations, increment and decrement +// operators +#include +#include +#include +#include + +using namespace std; + +int main() +{ + int num1 = 10; // variable used for increment and decrement operations + + // Perform prefix and postfix increment and decrement operations + // on the num1 variable. These operations are performed in an output + // statement to illustrate the difference between the two methods + + // increment and decrement operators - POSTFIX + cout << "POSTFIX incremennt and decrement operations\n"; + cout << "*******************************************\n"; + cout << "Perform Postfix increment:\n"; + cout << "\tnum1 before postfix ++ operation: " << num1 << endl; + cout << "\tnum1 during postfix ++ operation: " << num1++ < + +using namespace std; + +int main() +{ + int num1 = 50; // variable used in coercion equations + int num; // variable to hold coerced values + float flt1 = 3.14159; // variable used in coercion equations + float flt; // variable to hold coerced values + + // If you want to coerce a number from one data type + // to another, show it by using type casting. do not let + // the computer do it automatically by using implicit type coercion + + // implicit type coercion - conversion is done automatically + cout << "Implicit type coercion of integer to float and float to an int.i\n"; + num = flt1; + flt = num1; + cout << "int num contains the value for 3.14159: " << num << endl; + cout << "float flt contains the value for 50: " << flt << endl; + cout << "***********************************\n\n"; + + // explicit type coercion - type casting + // here num1 is converted to a float before the multiplication, + // then the overall result is converted to an integer. + cout << "Explicit type coercion of int to a float and a float to an int\n"; + num = int(flt1*float(num1)); + cout << "type cast value for num: " << num << endl; + cout << "calculated float value: " << flt1*num1 << endl; + cout << "***********************************\n\n"; + + // in this statement, flt1 is converted to an integer to + // perform integer division, and then the result is made a float + cout << "integer division result converted to a float\n"; + flt = float(num1/int(flt1)); + cout << "calculated integer value: " << num1/int(flt1) << endl; + cout << "type cast value for flt: " << flt << endl; + cout << "***********************************\n\n"; + + // mixed data type statements + // illustration of floating point arithmetic with implicit coercion from int to float + cout << "Mixed expressions output\n"; + cout << "Value of 3.0/2 + 0.75 = " << 3.0/2 + 0.75 << endl; + + // Illustration of integer division followed by implicit coercion to a float + flt1 = 100/40*1.0; + cout << "Value of 100/40*1.0 = " << flt1 << endl; + + flt1 = 1.0*100/40; + cout << "Value of 1.0*100/40 = " << flt1 << endl; + + flt1 = float(num1/13); // integer division typecast to float + cout << "float(num1/13) = " << flt1 << endl; + + flt1 = float(num1)/13; // integer division typecast to float + cout << "float(num1)/13 = " << flt1 << endl; + + return 0; +} diff --git a/CPE221/DataTypes2_05.cpp b/CPE221/DataTypes2_05.cpp new file mode 100644 index 0000000..44980ca --- /dev/null +++ b/CPE221/DataTypes2_05.cpp @@ -0,0 +1,59 @@ +// +// Chpater 03 program 5: Ch_03_05.cpp +#include +#include // for using setw and setprecision +#include // so that the string class can be used +using namespace std; +main() +{ + + string str1 = "This is a programming class"; + string str2 = "Instructor"; + string str3 = "cl"; + string::size_type length; // holds length of a string variable + string::size_type pos; // holds character position in a string + + // output values for string::npos under various conditions + cout << endl; + cout << "Value for string::npos: " << string::npos << endl; + + int number = string::npos; + cout << "string::npos assigned to an integer variable: " << number << endl; + + unsigned int number2 = string::npos; + cout << "string::npos assigned to an unsigned integer variable: " << number2 << endl; + + // output how much memory certain data types use + cout << "size of int: " << sizeof(int) << endl; + cout << "size of long: " << sizeof(long) << endl; + cout << "size of long long: " << sizeof(long long) << endl; + cout << "size of Ulong: " << sizeof(unsigned long) << endl; + cout << "size of string::size_type: " << sizeof(string::size_type) << endl; + cout << endl; + + + cout << "The following two strings will be manipulated " + << "in the program\n"; + cout << " 0123456789012345678901234567890\n"; + cout << "str1: " << str1 << endl; + cout << "str2: " << str2 << endl << endl; + + // show that length() and size() both perform the same function + cout << "Determine number of characters in str1 and str2 " + << "using length and size\n"; + length = str1.length(); + cout << "The length of str1 is: " << length << endl; + length = str2.size(); + cout << "The size of str2 is: " << length << endl << endl; + + cout << "Use the find function to find various sub strings in str1\n"; + pos = str1.find("gram"); + cout << "\"gram\" first occurs in str1 at position: " << pos << endl; + + pos = str1.find("GRAM"); + cout << "\"GRAM\" is not in str1, so string::npos is returned: " << pos << endl; + + pos = str1.find(str3+"as"); + cout << "\"" << str3 + "as" << "\" is found in str1 at position: " << pos << endl; + return 0; +} diff --git a/CPE221/DataTypes2_06.cpp b/CPE221/DataTypes2_06.cpp new file mode 100644 index 0000000..1289795 --- /dev/null +++ b/CPE221/DataTypes2_06.cpp @@ -0,0 +1,72 @@ +// +// Chpater 03 program 6: Ch_03_06.cpp +#include +#include // for using setw and setprecision +#include // so that the string class can be used +using namespace std; +main() +{ + string str1 = "This is a programming class"; + string str2 = ""; // str2 contains the substring, + + // output what is contained in string1, with a position indicator + cout << endl; + cout << "Substrings will be found in the following string:\n"; + cout << " 0123456789012345678901234567890\n"; + cout << "str1: " << str1 << endl << endl; + + // Look at various substring values + // the substrings are output between the arrow indicators + // of ==> and <== + + // Length of 0 attempt - null string + str2 = str1.substr(4,0); + cout << "str1.substr(4,0) should return null string\n"; + cout << "str2 contains the null ==>" << str2 << "<== string\n"; + + // two valid attempts - one with literals, one using find function + str2 = str1.substr(6,5); + cout << "\nstr1 substring (6,5) is ==>" << str2 << "<==" << endl; + + cout << endl << "substring of str1 starting with 'pro'\n" << "and containing 8 characters\n"; + str2 = str1.substr(str1.find("pro"),8); + cout << "str1 substring (str1.find(\"pro\"),8) is ==>" << str2 <<"<==" << endl; + + // substring going past end of string + cout << "\nExtracting beyond the end of the string is okay\n"; + str2 = str1.substr(20,20); + cout << "str1 substring(20,20) is ==>" << str2 << "<==" << endl; + + // substring starting at position 1 + str2 = str1.substr(1,5); + cout << "\nstr1 substring(1,5) is ==>" << str2 << "<==" << endl << endl; + + cout.flush(); // make sure the above is printed + + //cout << "Substring with a negative starting position: " << endl; + // this results in a runtime error with out of range substring error + //str2 = str1.substr(-40,3); + //cout << "str2:" << str2 << "<==\n"; + + // here length is -3, -3 will be converted to a large + // positive number due to the way unsigned integers are + // stored in the computer. therefore , the rest of the + // string from the starting position will be pulled out + // as the substring + str2 = str1.substr(4,-3); + cout << "Substring starting at position 4 with length -3\n"; + cout << "str2:" << str2 << "<==\n\n"; + + cout << "-3 assinged to unsigned integer data types becomes\n"; + cout << "a large positive number\n"; + cout << "-3 assigned to unsigned int: " << unsigned(-3) << endl; + cout << "-3 assigned to unsigned long: " << (unsigned long)(-3) << endl << endl; + + cout << "\nThe following causes an abort due to starting position\n"; + cout << "Attempting str1 substring (40,3):\n"; + str2 = str1.substr(40,3); + cout << str2; + // starting beyond the end of the string + + return 0; +} diff --git a/CPE221/Final Exam/in1.txt b/CPE221/Final Exam/in1.txt new file mode 100644 index 0000000..98fdba5 --- /dev/null +++ b/CPE221/Final Exam/in1.txt @@ -0,0 +1,11 @@ +1 +2 +3 +4 +5 6 7 8 +-9 +-8 +0 +0 +-7 + diff --git a/CPE221/Final Exam/in2.txt b/CPE221/Final Exam/in2.txt new file mode 100644 index 0000000..f032092 --- /dev/null +++ b/CPE221/Final Exam/in2.txt @@ -0,0 +1,12 @@ +0 1 -1 -5 +0 +-9 +7 +3 +0 7 123 -54 0 +0 +776 +-3432 +8 6 0 0 +45 + diff --git a/CPE221/Loops1_05.cpp b/CPE221/Loops1_05.cpp new file mode 100644 index 0000000..d613378 --- /dev/null +++ b/CPE221/Loops1_05.cpp @@ -0,0 +1,90 @@ +// Chpater 06 program 5: Ch_06_05.cpp +#include +#include +#include +using namespace std; + +// Event controlled loops +// 1) Sentinel loops - Loop is executed until a special value +// is used (typically read) indicating the termination of the loop +// 2) End-of-File controlled loops - Loop is executed until the +// End-of-File(EOF) is reached. +// 3) Flag-controlled loops - The loop is executed until a +// Boolean variable is changed (from true to false or false +// to true) such that the loop is exited. + +int main() +{ + bool finished; // flag used for loop control + int value; // number read from the input file + int sum; // sum of the numbers read from the file + int line_num; // number of lines read from the file + ifstream InData; // input file stream variable + + // Flag Controlled Loop - uses a flag which is a boolean variable. + // The flag records whether or not the event that controls + // the loop has occurred. + + // Flags can be initialized to true or false. The value + // used is usuall decided by the variable name so that + // reading the statement indicates the desired action. + + // Examples while (!negative), while (DataOk) + + // In this example, integers are read from a file until one + // of the following occurs: Either the end of the file is + // reached, or the sum of the integers exceeds 300. + + cout << "\n\nFlag controlled loop example. In this case, the\n"; + cout << "flag is changed when the sum of integers entered\n"; + cout << "exceeds 300. The loop terminates when the EOF is\n"; + cout << "reached or the sum exceeds 300\n\n"; + + cout << "File: data_file1.txt has integers that sum to > 300.\n\n"; + + line_num = 1; + sum = 0; + finished = false; // initialize this to false since we are not done + + cout << boolalpha; + + // open the input file stream + InData.open("data_file1.txt"); + + cout << left << setw(17) << "Line and Value" << + setw(20) << " sum" << right << setw(10)<< "finished" << setw(10) + << "InData" << endl; + cout << left << setw(17) << "--------------" << + setw(20) << "-------------" << right << setw(10)<< "--------" << setw(10) + << "------" << endl; + + InData >> value; // Priming read to read the first value + + // Loop executes As long as the input stream is valid and the sum is less than 300 + + while (InData && !finished ) + { + sum += value; + cout << "Line " << line_num << ": " << left << setw(9) << value; + cout << ":: sum is " << setw(10) << sum << right << setw(10)<< finished << setw(10) + << bool(InData) << endl; + + line_num++; + // test the sum to see if we have reached 301 or higher + // could use finished = sum > 300 this sets the value false + // to finished until sum exceeds 300 + if (sum > 300 ) + finished = true; //finished = sum > 300; + else + InData >> value; // Read the next value + } + + // print out the status of the input stream and finished + + cout << boolalpha; // prints out true or false for boolean variables. + cout << "finished is : " << finished << endl; + cout << "The status of the input stream is: " << bool(InData) << endl; + + InData.close(); // close the file used for the input stream + return 0; +} diff --git a/CPE325/FinalProject/Debug/FinalProject.d b/CPE325/FinalProject/Debug/FinalProject.d new file mode 100644 index 0000000..085249e --- /dev/null +++ b/CPE325/FinalProject/Debug/FinalProject.d @@ -0,0 +1,54 @@ +# FIXED + +FinalProject.obj: ../FinalProject.c +FinalProject.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +FinalProject.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h +FinalProject.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/string.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/xlocale/_string.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdlib.h +FinalProject.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdbool.h + +../FinalProject.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/string.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/xlocale/_string.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdlib.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdbool.h: + diff --git a/CPE325/FinalProject/Debug/FinalProject.map b/CPE325/FinalProject/Debug/FinalProject.map new file mode 100644 index 0000000..b009885 --- /dev/null +++ b/CPE325/FinalProject/Debug/FinalProject.map @@ -0,0 +1,1212 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Dec 3 14:41:32 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00003152 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOB 00001000 00000080 00000000 00000080 RWIX + INFOA 00001080 00000080 00000000 00000080 RWIX + RAM 00001100 00002000 000000a8 00001f58 RWIX + FLASH 00003100 0000cebe 0000060e 0000c8b0 RWIX + BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff + INT00 0000ffc0 00000002 00000000 00000002 RWIX + INT01 0000ffc2 00000002 00000000 00000002 RWIX + INT02 0000ffc4 00000002 00000000 00000002 RWIX + INT03 0000ffc6 00000002 00000000 00000002 RWIX + INT04 0000ffc8 00000002 00000000 00000002 RWIX + INT05 0000ffca 00000002 00000000 00000002 RWIX + INT06 0000ffcc 00000002 00000000 00000002 RWIX + INT07 0000ffce 00000002 00000000 00000002 RWIX + INT08 0000ffd0 00000002 00000000 00000002 RWIX + INT09 0000ffd2 00000002 00000000 00000002 RWIX + INT10 0000ffd4 00000002 00000000 00000002 RWIX + INT11 0000ffd6 00000002 00000000 00000002 RWIX + INT12 0000ffd8 00000002 00000000 00000002 RWIX + INT13 0000ffda 00000002 00000000 00000002 RWIX + INT14 0000ffdc 00000002 00000002 00000000 RWIX + INT15 0000ffde 00000002 00000002 00000000 RWIX + INT16 0000ffe0 00000002 00000002 00000000 RWIX + INT17 0000ffe2 00000002 00000002 00000000 RWIX + INT18 0000ffe4 00000002 00000002 00000000 RWIX + INT19 0000ffe6 00000002 00000002 00000000 RWIX + INT20 0000ffe8 00000002 00000002 00000000 RWIX + INT21 0000ffea 00000002 00000002 00000000 RWIX + INT22 0000ffec 00000002 00000002 00000000 RWIX + INT23 0000ffee 00000002 00000002 00000000 RWIX + INT24 0000fff0 00000002 00000002 00000000 RWIX + INT25 0000fff2 00000002 00000002 00000000 RWIX + INT26 0000fff4 00000002 00000002 00000000 RWIX + INT27 0000fff6 00000002 00000002 00000000 RWIX + INT28 0000fff8 00000002 00000002 00000000 RWIX + INT29 0000fffa 00000002 00000002 00000000 RWIX + INT30 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 00010000 00004208 0000bdf8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00001100 0000004e UNINITIALIZED + 00001100 00000024 FinalProject.obj (.data) + 00001124 0000000a FinalProject.obj (.data:andrew) + 0000112e 0000000a FinalProject.obj (.data:bill) + 00001138 0000000a FinalProject.obj (.data:jeff) + 00001142 0000000a FinalProject.obj (.data:joe) + 0000114c 00000002 rts430x_lc_rd_eabi.lib : errno.c.obj (.data) + +.bss 0 0000114e 0000000a UNINITIALIZED + 0000114e 00000002 (.common:SystemTime) + 00001150 00000002 (.common:command) + 00001152 00000002 (.common:cpu) + 00001154 00000002 (.common:password) + 00001156 00000002 (.common:user) + +.stack 0 000030b0 00000050 UNINITIALIZED + 000030b0 00000004 rts430x_lc_rd_eabi.lib : boot.c.obj (.stack) + 000030b4 0000004c --HOLE-- + +.text:_isr +* 0 00003100 00000076 + 00003100 00000032 FinalProject.obj (.text:_isr:watchdog_timer) + 00003132 00000020 FinalProject.obj (.text:_isr:Port1_ISR) + 00003152 0000001c rts430x_lc_rd_eabi.lib : boot.c.obj (.text:_isr:_c_int00_noargs) + 0000316e 00000008 : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 000036bc 00000052 + 000036bc 0000002f (.cinit..data.load) [load image, compression = lzss] + 000036eb 00000001 --HOLE-- [fill = 0] + 000036ec 0000000c (__TI_handler_table) + 000036f8 00000006 (.cinit..bss.load) [load image, compression = zero_init] + 000036fe 00000010 (__TI_cinit_table) + +.binit 0 00003100 00000000 + +.init_array +* 0 00003100 00000000 UNINITIALIZED + +.const 0 00003176 00000546 + 00003176 0000041e FinalProject.obj (.const:.string) + 00003594 00000101 rts430x_lc_rd_eabi.lib : ctype.c.obj (.const:.string:_ctypes_) + 00003695 00000001 --HOLE-- [fill = 0] + 00003696 00000026 : _printfi.c.obj (.const:.string) + +$fill000 0 0000ffbe 00000002 + 0000ffbe 00000002 --HOLE-- [fill = ffff] + +DAC12 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430x_lc_rd_eabi.lib : int14.asm.obj (.int14) + +DMA 0 0000ffde 00000002 + 0000ffde 00000002 rts430x_lc_rd_eabi.lib : int15.asm.obj (.int15) + +BASICTIMER +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430x_lc_rd_eabi.lib : int16.asm.obj (.int16) + +PORT2 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430x_lc_rd_eabi.lib : int17.asm.obj (.int17) + +USART1TX 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430x_lc_rd_eabi.lib : int18.asm.obj (.int18) + +USART1RX 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430x_lc_rd_eabi.lib : int19.asm.obj (.int19) + +PORT1 0 0000ffe8 00000002 + 0000ffe8 00000002 FinalProject.obj (.int20) + +TIMERA1 0 0000ffea 00000002 + 0000ffea 00000002 rts430x_lc_rd_eabi.lib : int21.asm.obj (.int21) + +TIMERA0 0 0000ffec 00000002 + 0000ffec 00000002 rts430x_lc_rd_eabi.lib : int22.asm.obj (.int22) + +ADC12 0 0000ffee 00000002 + 0000ffee 00000002 rts430x_lc_rd_eabi.lib : int23.asm.obj (.int23) + +USCIAB0TX +* 0 0000fff0 00000002 + 0000fff0 00000002 rts430x_lc_rd_eabi.lib : int24.asm.obj (.int24) + +USCIAB0RX +* 0 0000fff2 00000002 + 0000fff2 00000002 rts430x_lc_rd_eabi.lib : int25.asm.obj (.int25) + +WDT 0 0000fff4 00000002 + 0000fff4 00000002 FinalProject.obj (.int26) + +COMPARATORA +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430x_lc_rd_eabi.lib : int27.asm.obj (.int27) + +TIMERB1 0 0000fff8 00000002 + 0000fff8 00000002 rts430x_lc_rd_eabi.lib : int28.asm.obj (.int28) + +TIMERB0 0 0000fffa 00000002 + 0000fffa 00000002 rts430x_lc_rd_eabi.lib : int29.asm.obj (.int29) + +NMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430x_lc_rd_eabi.lib : int30.asm.obj (.int30) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430x_lc_rd_eabi.lib : boot.c.obj (.reset) + +.text 0 00010000 00004208 + 00010000 0000072a rts430x_lc_rd_eabi.lib : addd.c.obj (.text:__mspabi_addd) + 0001072a 00000466 : frcdivd.c.obj (.text:__TI_frcdivd) + 00010b90 000003f0 FinalProject.obj (.text:main) + 00010f80 0000034e rts430x_lc_rd_eabi.lib : div64u.c.obj (.text:__mspabi_divull) + 000112ce 000002a6 : _printfi.c.obj (.text:__TI_printfi) + 00011574 00000298 : mpyd.c.obj (.text:__mspabi_mpyd) + 0001180c 0000027a : _printfi.c.obj (.text:_setfield) + 00011a86 00000268 : _printfi.c.obj (.text:_pproc_fgea) + 00011cee 00000224 : _printfi.c.obj (.text:acvt) + 00011f12 00000222 : divd.c.obj (.text:__mspabi_divd) + 00012134 0000020c : _printfi.c.obj (.text:_getarg_diouxp) + 00012340 000001e6 : _printfi.c.obj (.text:ecvt) + 00012526 000001c8 : _printfi.c.obj (.text:fcvt) + 000126ee 000001a2 : _printfi.c.obj (.text:_pconv_e) + 00012890 00000170 : _printfi.c.obj (.text:_pconv_a) + 00012a00 00000164 : frcmpyd.c.obj (.text:__TI_frcmpyd) + 00012b64 0000015a : s_scalbn.c.obj (.text:scalbn) + 00012cbe 00000148 : _printfi.c.obj (.text:_pproc_diouxp) + 00012e06 00000128 : _printfi.c.obj (.text:_ltostr) + 00012f2e 000000fc : _printfi.c.obj (.text:_pconv_g) + 0001302a 000000ea : _printfi.c.obj (.text:_pproc_fwp) + 00013114 000000d8 : cmpd.c.obj (.text:__mspabi_cmpd) + 000131ec 000000c8 : _printfi.c.obj (.text:_pproc_wstr) + 000132b4 000000a6 : _printfi.c.obj (.text:_pproc_str) + 0001335a 000000a6 : s_frexp.c.obj (.text:frexp) + 00013400 0000009e : fltlid.c.obj (.text:__mspabi_fltlid) + 0001349e 00000096 : mult64_hw.asm.obj (.text:__mpyll) + 00013534 00000090 : _printfi.c.obj (.text:_ecpy) + 000135c4 00000090 : _printfi.c.obj (.text:_mcpy) + 00013654 00000088 FinalProject.obj (.text:stringCheck) + 000136dc 00000080 rts430x_lc_rd_eabi.lib : _ltoa.c.obj (.text:__TI_ltoa) + 0001375c 00000078 : _printfi.c.obj (.text:_pconv_f) + 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+GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a6 ADC12IE +000001a4 ADC12IFG +000001a8 ADC12IV +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +00000040 BTCTL +000141fc C$$EXIT +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +000001c0 DAC12_0CTL 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LCDM9 +00000134 MAC +00000136 MACS +00000005 ME2 +00000130 MPY +00000132 MPYS +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000138 OP2 +0000000d P10DIR +00000009 P10IN +0000000b P10OUT +0000000f P10SEL +00000022 P1DIR +00000025 P1IE +00000024 P1IES +00000023 P1IFG +00000020 P1IN +00000021 P1OUT +00000026 P1SEL +0000002a P2DIR +0000002d P2IE +0000002c P2IES +0000002b P2IFG +00000028 P2IN +00000029 P2OUT +0000002e P2SEL +0000001a P3DIR +00000018 P3IN +00000019 P3OUT +0000001b P3SEL +0000001e P4DIR +0000001c P4IN +0000001d P4OUT +0000001f P4SEL +00000032 P5DIR +00000030 P5IN +00000031 P5OUT +00000033 P5SEL +00000036 P6DIR +00000034 P6IN +00000035 P6OUT +00000037 P6SEL +0000003c P7DIR +00000038 P7IN +0000003a P7OUT +0000003e P7SEL +0000003d P8DIR +00000039 P8IN +0000003b P8OUT +0000003f P8SEL +0000000c P9DIR +00000008 P9IN +0000000a P9OUT +0000000e P9SEL +0000003c PADIR +00000038 PAIN +0000003a PAOUT +0000003e PASEL +0000000c PBDIR +00000008 PBIN +0000000a PBOUT +0000000e PBSEL +00003132 Port1_ISR +0000013c RESHI +0000013a RESLO +00000041 RTCCTL +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +00000042 RTCNT1 +00000043 RTCNT2 +00000044 RTCNT3 +00000045 RTCNT4 +00000042 RTCTIM0 +00000044 RTCTIM1 +00000040 RTCTL +0000004e RTCYEAR +0000004f RTCYEARH +0000004e RTCYEARL +00000050 SCFI0 +00000051 SCFI1 +00000052 SCFQCTL +0000013e SUMEXT +00000056 SVSCTL +0000114e SystemTime +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000160 TACTL +0000012e TAIV +00000170 TAR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000180 TBCTL +0000011e TBIV +00000190 TBR +0000007c U1BR0 +0000007d U1BR1 +00000078 U1CTL +0000007b U1MCTL +0000007a U1RCTL +0000007e U1RXBUF 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TBCCTL4 + 0x18a + + + TBCCTL5 + 0x18c + + + TBCCTL6 + 0x18e + + + TBR + 0x190 + + + TBCCR0 + 0x192 + + + TBCCR1 + 0x194 + + + TBCCR2 + 0x196 + + + TBCCR3 + 0x198 + + + TBCCR4 + 0x19a + + + TBCCR5 + 0x19c + + + TBCCR6 + 0x19e + + + UCA0CTL0 + 0x60 + + + UCA0CTL1 + 0x61 + + + UCA0BR0 + 0x62 + + + UCA0BR1 + 0x63 + + + UCA0MCTL + 0x64 + + + UCA0STAT + 0x65 + + + UCA0RXBUF + 0x66 + + + UCA0TXBUF + 0x67 + + + UCA0ABCTL + 0x5d + + + UCA0IRTCTL + 0x5e + + + UCA0IRRCTL + 0x5f + + + UCB0CTL0 + 0x68 + + + UCB0CTL1 + 0x69 + + + UCB0BR0 + 0x6a + + + UCB0BR1 + 0x6b + + + UCB0I2CIE + 0x6c + + + UCB0STAT + 0x6d + + + UCB0RXBUF + 0x6e + + + UCB0TXBUF + 0x6f + + + UCB0I2COA + 0x118 + + + UCB0I2CSA + 0x11a + + + U1CTL + 0x78 + + + U1TCTL + 0x79 + + + U1RCTL + 0x7a + + + U1MCTL + 0x7b + + + U1BR0 + 0x7c + + + U1BR1 + 0x7d + + + U1RXBUF + 0x7e + + + U1TXBUF + 0x7f + + + WDTCTL + 0x120 + + + __TI_CINIT_Base + 0x36fe + + + __TI_CINIT_Limit + 0x370e + + + __TI_Handler_Table_Base + 0x36ec + + + __TI_Handler_Table_Limit + 0x36f8 + + + __STACK_SIZE + 0x50 + + + __STACK_END + 0x3100 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + user + 0x1156 + + + cpu + 0x1152 + + + password + 0x1154 + + + command + 0x1150 + + + SystemTime + 0x114e + + + andrew + 0x1124 + + + + logout + 0x1114 + + + + jeff + 0x1138 + + + + resetBuzzer + 0x141b0 + + + + timerCheck + 0x1110 + + + + __TI_int26 + 0xfff4 + + + + __TI_int20 + 0xffe8 + + + + Up + 0x1104 + + + + bill + 0x112e + + + + Port1_ISR + 0x3132 + + + + promptOutput + 0x13acc + + + + stringCheck + 0x13654 + + + + clock + 0x110e + + + + clockFunc + 0x137d4 + + + + commandCheck + 0x13996 + + + + joe + 0x1142 + + + + timer + 0x1102 + + + + watchdog_timer + 0x3100 + + + + main + 0x10b90 + + + + upgradeFunc + 0x13f8c + + + + clockCheck + 0x1106 + + + + UART_setup + 0x13fb8 + + + + UART_Send_Character + 0x141da + + + + setTimer + 0x14168 + + + + updateFunc + 0x138c0 + + + + setBuzzer + 0x141be + + + + timeCheck + 0x110a + + + + stringLength + 0x140e6 + + + + setup + 0x139fe + + + + UARTsendString + 0x1402e + + + + upgrade + 0x110c + + + + UARTgetWord + 0x1392e + + + + data + 0x1112 + + + + update + 0x1108 + + + + timerCount + 0x1118 + + + + test + 0x1107 + + + + timeout + 0x1100 + + + + admin + 0x1116 + + + + nonadmin + 0x1117 + + + + sprintf + 0x13cda + + + + __TI_int14 + 0xffdc + + + + __TI_int15 + 0xffde + + + + __TI_int16 + 0xffe0 + + + + __TI_int17 + 0xffe2 + + + + __TI_int18 + 0xffe4 + + + + __TI_int19 + 0xffe6 + + + + __TI_int21 + 0xffea + + + + __TI_int22 + 0xffec + + + + __TI_int23 + 0xffee + + + + __TI_int24 + 0xfff0 + + + + __TI_int25 + 0xfff2 + + + + __TI_int27 + 0xfff6 + + + + __TI_int28 + 0xfff8 + + + + __TI_int29 + 0xfffa + + + + __TI_int30 + 0xfffc + + + + __TI_ISR_TRAP + 0x316e + + + + __mspabi_mpyi_hw + 0x140ce + + + + __mspabi_mpyl_hw + 0x13efe + + + + __mspabi_mpyull_hw + 0x13c3e + + + + __mspabi_mpyll_hw + 0x1349e + + + + _stack + 0x30b0 + + + + _c_int00_noargs + 0x3152 + + + + _reset_vector + 0xfffe + + + + __TI_auto_init_nobinit_nopinit_hold_wdt + 0x13bea + + + + __TI_zero_init_nomemset + 0x14052 + + + + _system_pre_init + 0x14202 + + + + _system_post_cinit + 0x14206 + + + + __TI_decompress_none + 0x1417c + + + + __TI_decompress_lzss + 0x1384a + + + + C$$EXIT + 0x141fc + + + + abort + 0x141fc + + + + memcpy + 0x14154 + + + + strcmp + 0x140b2 + + + + __TI_printfi + 0x112ce + + + + wcslen + 0x1412a + + + + frexpl + 0x1335a + + + + frexp + 0x1335a + + + + scalbn + 0x12b64 + + + + scalbnl + 0x12b64 + + + + ldexpl + 0x12b64 + + + + ldexp + 0x12b64 + + + + __mspabi_remu + 0x14114 + + + + __mspabi_divu + 0x14114 + + + + __mspabi_remul + 0x13b92 + + + + __mspabi_divul + 0x13b92 + + + + __mspabi_srlll + 0x13e92 + + + + __mspabi_divull + 0x10f80 + + + + __mspabi_addd + 0x10000 + + + + __mspabi_cmpd + 0x13114 + + + + __mspabi_divd + 0x11f12 + + + + __mspabi_fixdi + 0x13fe0 + + + + __mspabi_fixdli + 0x13a66 + + + + __mspabi_fltid + 0x141e6 + + + + __mspabi_fltlid + 0x13400 + + + + __TI_frcdivd + 0x1072a + + + + __mspabi_mpyd + 0x11574 + + + + __mspabi_negd + 0x13f30 + + + + __mspabi_subd + 0x13ecc + + + + __TI_ltoa + 0x136dc + + + + atoi + 0x13b30 + + + + _ctypes_ + 0x3594 + + + + memccpy + 0x14008 + + + + memset + 0x140fe + + + + strchr + 0x14096 + + + + strlen + 0x141cc + + + + toupper + 0x1418e + + + + abs + 0x141f2 + + + + errno + 0x114c + + + + copysign + 0x13f5e + + + + copysignl + 0x13f5e + + + + __mspabi_sral_15 + 0x13d9e + + + + __mspabi_sral_14 + 0x13da2 + + + + __mspabi_sral_13 + 0x13da6 + + + + __mspabi_sral_12 + 0x13daa + + + + __mspabi_sral_11 + 0x13dae + + + + __mspabi_sral_10 + 0x13db2 + + + + __mspabi_sral_8 + 0x13dba + + + + __mspabi_sral_9 + 0x13db6 + + + + __mspabi_sral_6 + 0x13dc2 + + + + __mspabi_sral_7 + 0x13dbe + + + + __mspabi_sral_4 + 0x13dca + + + + __mspabi_sral_5 + 0x13dc6 + + + + __mspabi_sral_2 + 0x13dd2 + + + + __mspabi_sral_3 + 0x13dce + + + + __mspabi_sral_1 + 0x13dd6 + + + + __mspabi_remli + 0x13d5e + + + + __mspabi_divli + 0x13d5e + + + + __mspabi_slll_9 + 0x13df4 + + + + __mspabi_slll_8 + 0x13df8 + + + + __mspabi_slll_7 + 0x13dfc + + + + __mspabi_slll_6 + 0x13e00 + + + + __mspabi_slll_5 + 0x13e04 + + + + __mspabi_slll_4 + 0x13e08 + + + + __mspabi_slll_3 + 0x13e0c + + + + __mspabi_slll_2 + 0x13e10 + + + + __mspabi_slll_1 + 0x13e14 + + + + __mspabi_slll_15 + 0x13ddc + + + + __mspabi_slll_14 + 0x13de0 + + + + __mspabi_slll_13 + 0x13de4 + + + + __mspabi_slll_12 + 0x13de8 + + + + __mspabi_slll_11 + 0x13dec + + + + __mspabi_slll_10 + 0x13df0 + + + + __mspabi_srll_8 + 0x13e36 + + + + __mspabi_srll_9 + 0x13e32 + + + + __mspabi_srll_6 + 0x13e3e + + + + __mspabi_srll_7 + 0x13e3a + + + + __mspabi_srll_4 + 0x13e46 + + + + __mspabi_srll_5 + 0x13e42 + + + + __mspabi_srll_2 + 0x13e4e + + + + __mspabi_srll_3 + 0x13e4a + + + + __mspabi_srll_1 + 0x13e52 + + + + __mspabi_srll_15 + 0x13e1a + + + + __mspabi_srll_14 + 0x13e1e + + + + __mspabi_srll_13 + 0x13e22 + + + + __mspabi_srll_12 + 0x13e26 + + + + __mspabi_srll_11 + 0x13e2a + + + + __mspabi_srll_10 + 0x13e2e + + + + __mspabi_srll + 0x141a0 + + + + __mspabi_srall + 0x13d1e + + + + __mspabi_sllll + 0x13e58 + + + + __TI_frcmpyd + 0x12a00 + + + + Link successful + diff --git a/CPE325/FinalProject/Debug/ccsObjs.opt b/CPE325/FinalProject/Debug/ccsObjs.opt new file mode 100644 index 0000000..2f110d3 --- /dev/null +++ b/CPE325/FinalProject/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./FinalProject.obj" "../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/FinalProject/Debug/makefile b/CPE325/FinalProject/Debug/makefile new file mode 100644 index 0000000..e525c88 --- /dev/null +++ b/CPE325/FinalProject/Debug/makefile @@ -0,0 +1,166 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./FinalProject.obj" \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +FinalProject.out \ + +EXE_OUTPUTS__QUOTED += \ +"FinalProject.out" \ + +BIN_OUTPUTS += \ +FinalProject.hex \ + +BIN_OUTPUTS__QUOTED += \ +"FinalProject.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "FinalProject.out" + +# Tool invocations +FinalProject.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"FinalProject.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="FinalProject_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "FinalProject.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +FinalProject.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "FinalProject.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "FinalProject.obj" + -$(RM) "FinalProject.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/FinalProject/Debug/objects.mk b/CPE325/FinalProject/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/FinalProject/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/FinalProject/Debug/sources.mk b/CPE325/FinalProject/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/FinalProject/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/FinalProject/Debug/subdir_rules.mk b/CPE325/FinalProject/Debug/subdir_rules.mk new file mode 100644 index 0000000..3ec9df2 --- /dev/null +++ b/CPE325/FinalProject/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/FinalProject" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --preproc_with_compile --preproc_dependency="$(basename $( +#include +#include +#include +#include + +#define SW1_PRESSED ((BIT0&P1IFG)==0) // SW1 Status +#define SW2_PRESSED ((BIT1&P1IFG)==0) // SW2 Status +#define checkTime() (clockCheck=true) +#define GREENLED() (P2OUT|=BIT2) +#define REDLED() (P5OUT|=BIT1) +#define GREENLEDOFF() (P2OUT&=~BIT2) +#define REDLEDOFF() (P5OUT&=~BIT1) + +// Struct used to define users +struct user +{ + char *name; + char *password; + int admin; +}; +struct user andrew; +struct user joe; +struct user bill; +struct user jeff; +struct user andrew = {.name = "Andrew", .admin = 1, .password = "an"}; +struct user joe = { .name = "Joe", .admin = 1, .password = "jo" }; +struct user bill = { .name = "Bill", .admin = 0, .password = "bi" }; +struct user jeff = { .name = "Jeff", .admin = 0, .password = "je" }; + +char user[]; +char cpu[]; +char askReset[]; +char password[]; +char command[]; +//int admin; +int timeout=0; +int timer=0; +int Up=1; +bool clockCheck = false; +char SystemTime[]; +//int diskspace = rand(); + +char time[]; + +bool test = false; +int update=0, timeCheck=0, upgrade=0, clock=0, timerCheck=0, data=0, logout=0; + +bool admin = false; +bool nonadmin = false; + +// Characters for clock +//#define RTC_STATE_SECONDS 0 +//#define RTC_STATE_MINUTES 1 +//#define RTC_STATE_HOURS 2 +// +//volatile uint8_t timerCount = 0; +//volatile uint8_t rtcState[3] = {0, 0, 0}; + +unsigned int s, m, h; +int timerCount =0; +int diskspace; + + +// user tries to update and gets a buzzer and light +void clockFunc(); + +//upgrade the packages +void upgradeFunc(); + +// set a timer +void setTimer(); + +//void buzzer(); +void resetBuzzer(); + +void setBuzzer(); + +void timerAInit(void){ + // Enable Timer Interrupts + TACCTL0 = CCIE; + + // SMCLK, Count to CCR0 Value, Divide by 8 + TA0CTL = TASSEL_2 + MC_1 + ID_3; + + // 1,000,000 / 8 / 25 = 5000 + TACCR0 = 5000; +} + +// checks string to see if correct, +// returns true if one of the users, false if not +bool stringCheck(char* string); +void updateFunc(); //update code when "update" is entered + +void setup(); + + +void promptOutput(); // Outputs prompt + +void commandCheck(char* command); + + +void UART_setup(); // Configures UCI to work in the UART mode + // at the baud rate of 115200. +void UART_Send_Character(char my_char); // Sends a character via UART + +void UARTsendString(char* string); // Sends a string via UART using + // send_Character(char c) + +void UARTgetWord(char* buffer, int limit); +/* Receives characters via UART until it finds +the new line character or until the limit of +characters is exceeded. Writes that string +(excluding the new line character) to the +buffer allocated outside of the function. +Terminates the string with the null +character */ + +int stringLength(char *str); // String length + +int main(void) +{ +// WDTCTL = WDT_ADLY_1000; // 1 s interval + WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer + UART_setup(); + setup(); + //timerAInit(); + UCA0TXBUF = 0x0D; // Carriage Return + clockFunc(); + while(1){ + //timeout =0; + UCA0TXBUF = 0x0D; // Carriage Return + UCA0TXBUF = 0x0D; // Carriage Return + clockFunc(); + UARTsendString("\nPlease enter a username: "); // Output + UCA0RXBUF = 0x0D; // Carriage Return + clockFunc(); + UARTgetWord(user, 30); + //clockFunc(); + bool usercheck = stringCheck(user); + clockFunc(); + UCA0TXBUF = 0x0D; // Carriage Return + clockFunc(); + UARTsendString("\nPlease enter the password: "); + clockFunc(); + //timeout = 1; + UARTgetWord(password, 30); + clockFunc(); + bool passcheck = stringCheck(password); + clockFunc(); + UCA0TXBUF = 0x0D; // Carriage Return + clockFunc(); + if(usercheck && passcheck && admin) // If user and password match + { + clockFunc(); + while(1){ + clockFunc(); + UCA0TXBUF = 0x0D; // Carriage Return + promptOutput(); + clockFunc(); + // char* commandEq; + UARTgetWord(command, 50); + //commandCheck(command); + //if(update==1) + if(strcmp(command, "update")==0) + { + GREENLED(); + __delay_cycles(500000); // second + GREENLEDOFF(); + clockFunc(); + updateFunc(); + //for(i=0; i ==stringLength(command); i++) command[i]=0x00; + } + else if(strcmp(command, "upgrade")==0) + { + GREENLED(); + __delay_cycles(500000); // second + GREENLEDOFF(); + clockFunc(); + upgradeFunc(); + } + else if(strcmp(command, "date")==0) + { + GREENLED(); + __delay_cycles(500000); // second + GREENLEDOFF(); + clockFunc(); + clockFunc(); + UARTsendString("The date is 1980, November 1. The time is "); + UARTsendString(SystemTime); + } + else if(strcmp(command, "timer")==0) // timer to reboot + { + GREENLED(); + __delay_cycles(500000); // half-second + GREENLEDOFF(); + clockFunc(); + setTimer(); + } + else if(strcmp(command, "data")==0) + { + GREENLED(); + __delay_cycles(500000); // half-second + GREENLEDOFF(); + clockFunc(); + clockFunc(); + setTimer(); + } + else if(strcmp(command, "logout")==0) + { + GREENLED(); + __delay_cycles(500000); // half-second + GREENLEDOFF(); + clockFunc(); + clockFunc(); + break; + } + else + { + clockFunc(); + REDLED(); + setBuzzer(); + __delay_cycles(500000); // half-second + resetBuzzer(); + REDLEDOFF(); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("Unknown command."); + } + } + } + else if(usercheck && passcheck && admin==false) + { + while(1){ + clockFunc(); + UCA0TXBUF = 0x0D; // Carriage Return + promptOutput(); + UARTgetWord(command, 50); + commandCheck(command); + if(strcmp(command, "upgrade")==0 || strcmp(command, "update")==0) + { + clockFunc(); + REDLED(); + setBuzzer(); + __delay_cycles(500000); // half-second + resetBuzzer(); + REDLEDOFF(); + clockFunc(); + } + else if(strcmp(command, "date")==0) + { + clockFunc(); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("The date is 1980, November 1. The time is "); + UARTsendString(SystemTime); + clockFunc(); + } + else if(strcmp(command, "timer")==0) + { + GREENLED(); + __delay_cycles(500000); // half-second + GREENLEDOFF(); + clockFunc(); + clockFunc(); + setTimer(); + } + else if(strcmp(command, "logout")==0) + { + GREENLED(); + __delay_cycles(500000); // half-second + GREENLEDOFF(); + clockFunc(); + clockFunc(); + break; + } + else + { + REDLED(); + setBuzzer(); + __delay_cycles(500000); // half-second + resetBuzzer(); + REDLEDOFF(); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("Unknown command."); + } + } + } + else { + clockFunc(); + UCA0TXBUF = '\n'; // Newline + UCA0TXBUF = 0x0D; // Carriage Return + REDLED(); + setBuzzer(); + __delay_cycles(500000); // half-second + resetBuzzer(); + REDLEDOFF(); + UARTsendString("\nInvalid username or password! Please try again."); + } + } +} + +void promptOutput() +{ + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\nWelcome!! Enter a command: \n"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\n1. Set timer: timer"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\n2. Check for system updates: update"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\n3. Update system: upgrade"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\n4. Check system time: date"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\n5. Logout: logout"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\nCommand: "); +} + +void UART_setup() +{ + P2SEL |= BIT4 + BIT5; // Set USCI_A0 RXD/TXD to receive/transmit data + UCA0CTL1 |= UCSWRST; // Set software reset during initialization + UCA0CTL0 = 0; // USCI_A0 control register + UCA0CTL1 |= UCSSEL_2; // Clock source SMCLK + UCA0BR0 = 0x09; // 1048576 Hz / 115200 lower byte + UCA0BR1 = 0x00; // upper byte + UCA0MCTL = 0x02; // Modulation (UCBRS0=0x01, UCOS16=0) + UCA0CTL1 &= ~UCSWRST; // Clear software reset to initialize USCI state machine +} + +void setBuzzer() +{ + TBCCR0 = 250; + TBCCR4 = 125; +} + +void resetBuzzer() +{ + TBCCR0 = 3500; + TBCCR4 = 3600; +} + + +void UART_Send_Character(char my_char) +{ + while (!(IFG2 & UCA0TXIFG)); // Wait for previous character to transmit + UCA0TXBUF = my_char; // Put character into tx buffer +} + +void UARTsendString(char* string) +{ + int i=0; + int len = stringLength(string); + for(i =0; i<=len; i++) //loops over word + { + UART_Send_Character(string[i]); + } +} + +void UARTgetWord(char* buffer, int limit) +{ + int i; + for(i =0; i < limit; i++){ + while(!(IFG2&UCA0RXIFG)); // Wait for a new character + buffer[i] = UCA0RXBUF; + if(buffer[i] == '\r' || buffer[i] == '\n' || buffer[i] == '\0'){ + buffer[i] = '\0'; // end is here in UCA0RXBUF + return; + } + while(!(IFG2&UCA0TXIFG)); // Wait until TXBUF is free + UCA0TXBUF = UCA0RXBUF; // TXBUF <= RXBUF (echo) + } +} + +int stringLength(char *str) // gets string length for word +{ + int i=0; + while(str[i] != '\0') i++; + return i; +} + + +// Port 1 interrupt service routine +#pragma vector = PORT1_VECTOR +__interrupt void Port1_ISR (void) { + if(SW1_PRESSED) + { + main(); + } + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared +} + +bool stringCheck(char* string) +{ + if(strcmp(string,andrew.name) == 0 + || strcmp(string,joe.name) == 0 + || strcmp(string,andrew.password)== 0 + || strcmp(string,joe.password)== 0) + { + admin = true; + return true; + } + else if(strcmp(string,bill.name) == 0 + || strcmp(string,jeff.password)== 0 + || strcmp(string,jeff.name) == 0 + || strcmp(string,bill.password)== 0) + { + admin = false; + return true; + } + + else + { + // UARTsendString("False "); + return false; + } +} + +void setTimer() +{ + UARTsendString("The system will reboot in 30 seconds."); + //UARTgetWord(time,5); + WDTCTL = WDT_ADLY_1000; + timerCheck=1; +} + +void commandCheck(char* command) +{ + if(strcmp(command, "update")==0) + { + update = 1; + return; + } + else if(strcmp(command, "upgrade")==0) + { + upgrade = 1; + return; + } + else if(strcmp(command, "time")==0) + { + timerCheck = 1; + return; + } + else if(strcmp(command, "clock")==0) + { + clock = 1; + return; + } + else if(strcmp(command, "logout")==0) + { + logout = 1; + return; + } +} + +// Timer Interrupt +//#pragma vector = TIMER0_A0_VECTOR +//__interrupt void Timer_A(void){ +// // static int timerCount =0; +// static int m =0; +// static int h =0; +// static int s =0; +// s++; +// if (s >= 60){ +// s = 0; +// m++; +// if (m >= 60){ +// m = 0; +// h++; +// if (h >= 24) { +// h = 0; +// } +// } +// } +// sprintf(cpu, "%d", s); +// sprintf(SystemTime, "%d%d%d",h,m,s); +// //TA0CCTL0 &=~ TAIFG; +//} + + +void setup() +{ + _EINT(); // Enable interrupts + IE1 |= WDTIE; // Enable WDT interrupt + P2DIR |= (BIT1 + BIT2); // P2.1 and P2.2 set up as output + P5DIR |= BIT1; // REDLED set up as output + P2OUT &= ~BIT1; // Turn on LED2 + P2OUT &= ~BIT2; // Turn Off LED1 + P1IE |= BIT0; // P1.0 interrupt enabled + P1IE |= BIT1; // P1.1 interrupt enabled + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared + P2OUT &= ~(BIT1+BIT2); // Turn Off LED1 + GREENLEDOFF(); + REDLEDOFF(); + TB0CTL = TBSSEL_2 + MC_1; // SMCLK Clock source Upmode + TB0CCR0 = 32765; // Set TB4 count value + TB0CCR4 = 32767; // Set TB4 count value + P3SEL |= 0x20; // P3.5 as special function + P3DIR |= 0x20; // P3.5 as digital output + TB0CCTL4 = OUTMOD_3; // Set/Rest mode +} + +void updateFunc() +{ + UCA0TXBUF = 0x0D; // Carriage Return + // P2OUT |= BIT2; + UARTsendString("\nUpdating packages."); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\nHit:1 https://brave-browser-apt-release.s3.brave.com trusty InRelease"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\nHit:2 https://deb.debian.org/debian bullseye InRelease"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\nHit:3 https://repo.steampowered.com/steam stable InRelease"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\nHit:4 https://typora.io/linux ./ InRelease [793 B]"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\nReading package lists... Done"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\n9 packages can be upgraded. Run 'apt list --upgradable' to see them."); + UCA0TXBUF = 0x0D; // Carriage Return + +} +void clockFunc() +{ + + static int timerCount =0; + static int h=0,m=0,s=0; + timerCount++; + timerCount = 0; + s++; + if (s >= 60){ + s = 0; + m++; + if (m >= 60){ + m = 0; + h++; + if (h >= 24) { + h = 0; + } + } + } + + sprintf(cpu, "%d", s); + sprintf(SystemTime, "%d%d%d",h,m,s); + +} + + +void upgradeFunc() +{ + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\nThe following packages will be upgraded: "); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\n brave-browser steam:i386 steam-launcher steam-libs-amd64 steam-libs-i386:i386 typora"); + UCA0TXBUF = 0x0D; // Carriage Return + UARTsendString("\n Preparing to unpack .../0-brave-browser_1.32.113_amd64.deb ..."); +} + + +// Watchdog Timer interrupt service routine +#pragma vector=WDT_VECTOR +__interrupt void watchdog_timer(void) +{ + static int i =0; + //static int c =0; + + i++; + if(i==30 && timerCheck==1){ + setBuzzer(); + UCA0TXBUF = 0x0D; // Carriage Return + timerCheck=0; + IFG2=1; + resetBuzzer(); + // systemTime(); + main(); + } + + + // systemTime(); + //IFG2=1; +} diff --git a/CPE325/FinalProject/lnk_msp430fg4618.cmd b/CPE325/FinalProject/lnk_msp430fg4618.cmd new file mode 100755 index 0000000..557b664 --- /dev/null +++ b/CPE325/FinalProject/lnk_msp430fg4618.cmd @@ -0,0 +1,184 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************************/ +/* lnk_msp430fg4618.cmd - LINKER COMMAND FILE FOR LINKING MSP430FG4618 PROGRAMS */ +/* */ +/* Usage: lnk430 -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/FinalProject/targetConfigs/MSP430FG4618.ccxml b/CPE325/FinalProject/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/FinalProject/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/FinalProject/targetConfigs/readme.txt b/CPE325/FinalProject/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/FinalProject/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/L1_P1_For/Debug/L1_P1_For.map b/CPE325/L1_P1_For/Debug/L1_P1_For.map new file mode 100644 index 0000000..a7c1803 --- /dev/null +++ b/CPE325/L1_P1_For/Debug/L1_P1_For.map @@ -0,0 +1,2437 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Wed Aug 25 17:47:57 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00008946 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 00000494 00001b6c RWIX + FLASH 00004400 0000bb80 0000486a 00007316 RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 0000264c 000000fe UNINITIALIZED + 0000264c 00000078 rts430_eabi.lib : defs.c.obj (.data:_ftable) + 000026c4 0000004e : host_device.c.obj (.data:_device) + 00002712 00000028 : host_device.c.obj (.data:_stream) + 0000273a 00000002 : exit_gvars.c.obj (.data:__TI_cleanup_ptr) + 0000273c 00000002 : exit_gvars.c.obj (.data:__TI_dtors_ptr) + 0000273e 00000002 : _lock.c.obj (.data:_lock) + 00002740 00000002 : _lock.c.obj (.data:_unlock) + 00002742 00000002 : defs.c.obj (.data) + 00002744 00000002 : errno.c.obj (.data) + 00002746 00000002 : exit.c.obj (.data) + 00002748 00000002 : memory.c.obj (.data) + +.bss 0 0000274a 000000aa UNINITIALIZED + 0000274a 000000a0 (.common:__TI_tmpnams) + 000027ea 00000008 (.common:parmbuf) + 000027f2 00000002 rts430_eabi.lib : memory.c.obj (.bss) + +.sysmem 0 00002400 0000012c UNINITIALIZED + 00002400 00000008 rts430_eabi.lib : memory.c.obj (.sysmem) + 00002408 00000124 --HOLE-- + +.cio 0 0000252c 00000120 UNINITIALIZED + 0000252c 00000120 rts430_eabi.lib : trgmsg.c.obj (.cio) + +.stack 0 00004360 000000a0 UNINITIALIZED + 00004360 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 00004362 0000009e --HOLE-- + +.text 0 00004400 000046d0 + 00004400 00000736 rts430_eabi.lib : addd.c.obj (.text:__mspabi_addd) + 00004b36 00000478 : frcdivd.c.obj (.text:__TI_frcdivd) + 00004fae 00000360 : div64u.c.obj (.text:__mspabi_divull) + 0000530e 000002c0 : mpyd.c.obj (.text:__mspabi_mpyd) + 000055ce 00000288 : _printfi.c.obj (.text:__TI_printfi) + 00005856 0000026e : _printfi.c.obj (.text:_pproc_fgea) + 00005ac4 00000252 : _printfi.c.obj (.text:_setfield) + 00005d16 00000244 : _printfi.c.obj (.text:acvt) + 00005f5a 00000238 : divd.c.obj (.text:__mspabi_divd) + 00006192 000001ec : _printfi.c.obj (.text:_getarg_diouxp) + 0000637e 000001de : _printfi.c.obj (.text:ecvt) + 0000655c 000001c4 : _printfi.c.obj (.text:fcvt) + 00006720 000001a6 : _printfi.c.obj (.text:_pconv_e) + 000068c6 00000174 : _printfi.c.obj (.text:_pconv_a) + 00006a3a 00000172 : frcmpyd.c.obj (.text:__TI_frcmpyd) + 00006bac 0000016a : s_scalbn.c.obj (.text:scalbn) + 00006d16 0000014c : _printfi.c.obj (.text:_pproc_diouxp) + 00006e62 0000012e : _printfi.c.obj (.text:_ltostr) + 00006f90 000000f8 : _printfi.c.obj (.text:_pconv_g) + 00007088 000000f6 : memory.c.obj (.text:aligned_alloc) + 0000717e 000000ea : fputs.c.obj (.text:fputs) + 00007268 000000e0 : _printfi.c.obj (.text:_pproc_fwp) + 00007348 000000dc : cmpd.c.obj (.text:__mspabi_cmpd) + 00007424 000000d2 : memory.c.obj (.text:free) + 000074f6 000000d0 : setvbuf.c.obj (.text:setvbuf) + 000075c6 000000c4 : _printfi.c.obj (.text:_pproc_wstr) + 0000768a 000000b0 : s_frexp.c.obj (.text:frexp) + 0000773a 000000ac : fltlid.c.obj (.text:__mspabi_fltlid) + 000077e6 000000ac : _printfi.c.obj (.text:_pproc_str) + 00007892 00000092 : _printfi.c.obj (.text:_mcpy) + 00007924 00000090 : fputc.c.obj (.text:fputc) + 000079b4 0000008e : _printfi.c.obj (.text:_ecpy) + 00007a42 00000088 : hostlseek.c.obj (.text:HOSTlseek) + 00007aca 00000084 : _ltoa.c.obj (.text:__TI_ltoa) + 00007b4e 0000007c : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00007bca 0000007a : _io_perm.c.obj (.text:__TI_wrt_ok) + 00007c44 0000007a : _printfi.c.obj (.text:_pconv_f) + 00007cbe 00000072 : fclose.c.obj (.text:__TI_closefile) + 00007d30 00000072 : fixdli.c.obj (.text:__mspabi_fixdli) + 00007da2 00000070 : fseek.c.obj (.text:fseek) + 00007e12 0000006a : hostrename.c.obj (.text:HOSTrename) + 00007e7c 00000068 : memory.c.obj (.text:split) + 00007ee4 00000066 : hostopen.c.obj (.text:HOSTopen) + 00007f4a 00000062 : hostwrite.c.obj (.text:HOSTwrite) + 00007fac 00000062 : fflush.c.obj (.text:__TI_doflush) + 0000800e 00000060 : hostread.c.obj (.text:HOSTread) + 0000806e 0000005e : mult64_f5hw.asm.obj (.text:__mpyll) + 000080cc 0000005c : lsr32.asm.obj (.text:l_lsr_const) + 00008128 00000058 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 00008180 00000058 : getdevice.c.obj (.text:getdevice) + 000081d8 00000058 : div32u.asm.obj (.text) + 00008230 00000054 for.obj (.text:main) + 00008284 00000052 rts430_eabi.lib : atoi.c.obj (.text:atoi) + 000082d6 0000004e : _printfi.c.obj (.text:_fcpy) + 00008324 0000004c : lsr16.asm.obj (.text) + 00008370 0000004a : asr64.c.obj (.text:__mspabi_srall) + 000083ba 0000004a : close.c.obj (.text:close) + 00008404 00000046 : lsr64.c.obj (.text:__mspabi_srlll) + 0000844a 00000044 : hostclose.c.obj (.text:HOSTclose) + 0000848e 00000044 : lsl64.c.obj (.text:__mspabi_sllll) + 000084d2 00000044 : exit.c.obj (.text:exit) + 00008516 00000040 : hostunlink.c.obj (.text:HOSTunlink) + 00008556 00000040 : div32s.asm.obj (.text) + 00008596 0000003e : asr32.asm.obj (.text:l_asr_const) + 000085d4 0000003e : lsl32.asm.obj (.text:l_lsl_const) + 00008612 0000003c : printf.c.obj (.text:printf) + 0000864e 00000034 : fopen.c.obj (.text:__TI_cleanup) + 00008682 00000034 : getdevice.c.obj (.text:finddevice) + 000086b6 0000002e : trgmsg.c.obj (.text:__TI_writemsg) + 000086e4 0000002e : subd.c.obj (.text:__mspabi_subd) + 00008712 0000002e : s_copysign.c.obj (.text:copysign) + 00008740 0000002c : trgmsg.c.obj (.text:__TI_readmsg) + 0000876c 0000002c : asr16.asm.obj (.text) + 00008798 0000002c : lsl16.asm.obj (.text) + 000087c4 0000002c : strncpy.c.obj (.text:strncpy) + 000087f0 0000002a : negd.c.obj (.text:__mspabi_negd) + 0000881a 00000028 : mult3264_f5hw.asm.obj (.text:__mpyull) + 00008842 00000028 : fixdi.c.obj (.text:__mspabi_fixdi) + 0000886a 00000028 : memory.c.obj (.text:free_list_insert) + 00008892 00000028 : unlink.c.obj (.text:unlink) + 000088ba 00000026 : lseek.c.obj (.text:lseek) + 000088e0 00000024 : write.c.obj (.text:write) + 00008904 00000022 : memccpy.c.obj (.text:memccpy) + 00008926 00000020 : mult32_f5hw.asm.obj (.text) + 00008946 0000001c : boot.c.obj (.text:_c_int00_noargs) + 00008962 0000001c : memory.c.obj (.text:free_list_remove) + 0000897e 0000001a : strchr.c.obj (.text:strchr) + 00008998 00000018 : strcmp.c.obj (.text:strcmp) + 000089b0 00000016 : div16u.asm.obj (.text) + 000089c6 00000014 : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset:__TI_zero_init_nomemset) + 000089da 00000014 : memchr.c.obj (.text:memchr) + 000089ee 00000014 : memset.c.obj (.text:memset) + 00008a02 00000014 : mult16_f5hw.asm.obj (.text) + 00008a16 00000014 : wcslen.c.obj (.text:wcslen) + 00008a2a 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00008a3c 00000012 : lsr32.asm.obj (.text:l_lsr) + 00008a4e 00000012 : memcpy.c.obj (.text:memcpy) + 00008a60 00000010 : epilog.asm.obj (.text) + 00008a70 00000010 : strcpy.c.obj (.text:strcpy) + 00008a80 0000000e : strlen.c.obj (.text:strlen) + 00008a8e 0000000c : fltid.c.obj (.text:__mspabi_fltid) + 00008a9a 0000000c : toupper.c.obj (.text:toupper) + 00008aa6 0000000a : abs.c.obj (.text:abs) + 00008ab0 00000008 : memory.c.obj (.text:malloc) + 00008ab8 00000006 : printf.c.obj (.text:_outc) + 00008abe 00000006 : exit.c.obj (.text:abort) + 00008ac4 00000004 : printf.c.obj (.text:_outs) + 00008ac8 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00008acc 00000002 : _lock.c.obj (.text:_nop) + 00008ace 00000002 : startup.c.obj (.text:_system_post_cinit) + +.const 0 00008ad0 0000013c + 00008ad0 00000101 rts430_eabi.lib : ctype.c.obj (.const:.string:_ctypes_) + 00008bd1 00000001 --HOLE-- [fill = 0] + 00008bd2 00000026 : _printfi.c.obj (.const:.string) + 00008bf8 00000014 for.obj (.const:.string) + +.text:_isr +* 0 00008c0c 00000008 + 00008c0c 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00008c14 00000056 + 00008c14 00000044 (.cinit..data.load) [load image, compression = lzss] + 00008c58 00000006 (__TI_handler_table) + 00008c5e 00000004 (.cinit..bss.load) [load image, compression = zero_init] + 00008c62 00000008 (__TI_cinit_table) + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + for.obj 84 20 0 + +--+----------------------------+-------+---------+---------+ + Total: 84 20 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + _printfi.c.obj 6622 38 0 + addd.c.obj 1846 0 0 + frcdivd.c.obj 1144 0 0 + div64u.c.obj 864 0 0 + mpyd.c.obj 704 0 0 + memory.c.obj 636 0 4 + divd.c.obj 568 0 0 + trgmsg.c.obj 90 0 288 + frcmpyd.c.obj 370 0 0 + s_scalbn.c.obj 362 0 0 + defs.c.obj 0 0 282 + ctype.c.obj 0 257 0 + fputs.c.obj 234 0 0 + cmpd.c.obj 220 0 0 + setvbuf.c.obj 208 0 0 + s_frexp.c.obj 176 0 0 + fltlid.c.obj 172 0 0 + fputc.c.obj 144 0 0 + getdevice.c.obj 140 0 0 + hostlseek.c.obj 136 0 0 + _ltoa.c.obj 132 0 0 + copy_decompress_lzss.c.obj 124 0 0 + _io_perm.c.obj 122 0 0 + host_device.c.obj 0 0 118 + fclose.c.obj 114 0 0 + fixdli.c.obj 114 0 0 + fseek.c.obj 112 0 0 + hostopen.c.obj 102 0 8 + lsr32.asm.obj 110 0 0 + hostrename.c.obj 106 0 0 + fflush.c.obj 98 0 0 + hostwrite.c.obj 98 0 0 + hostread.c.obj 96 0 0 + mult64_f5hw.asm.obj 94 0 0 + autoinit.c.obj 88 0 0 + div32u.asm.obj 88 0 0 + atoi.c.obj 82 0 0 + exit.c.obj 74 0 2 + lsr16.asm.obj 76 0 0 + asr64.c.obj 74 0 0 + close.c.obj 74 0 0 + lsr64.c.obj 70 0 0 + printf.c.obj 70 0 0 + hostclose.c.obj 68 0 0 + lsl64.c.obj 68 0 0 + div32s.asm.obj 64 0 0 + hostunlink.c.obj 64 0 0 + asr32.asm.obj 62 0 0 + lsl32.asm.obj 62 0 0 + fopen.c.obj 52 0 0 + s_copysign.c.obj 46 0 0 + subd.c.obj 46 0 0 + asr16.asm.obj 44 0 0 + lsl16.asm.obj 44 0 0 + strncpy.c.obj 44 0 0 + negd.c.obj 42 0 0 + fixdi.c.obj 40 0 0 + mult3264_f5hw.asm.obj 40 0 0 + unlink.c.obj 40 0 0 + lseek.c.obj 38 0 0 + write.c.obj 36 0 0 + memccpy.c.obj 34 0 0 + mult32_f5hw.asm.obj 32 0 0 + boot.c.obj 28 2 0 + strchr.c.obj 26 0 0 + strcmp.c.obj 24 0 0 + div16u.asm.obj 22 0 0 + copy_zero_init.c.obj 20 0 0 + memchr.c.obj 20 0 0 + memset.c.obj 20 0 0 + mult16_f5hw.asm.obj 20 0 0 + wcslen.c.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + memcpy.c.obj 18 0 0 + epilog.asm.obj 16 0 0 + strcpy.c.obj 16 0 0 + strlen.c.obj 14 0 0 + fltid.c.obj 12 0 0 + toupper.c.obj 12 0 0 + abs.c.obj 10 0 0 + isr_trap.asm.obj 8 0 0 + _lock.c.obj 2 0 4 + exit_gvars.c.obj 0 0 4 + pre_init.c.obj 4 0 0 + errno.c.obj 0 0 2 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 18052 341 712 + + Heap: 0 0 300 + Stack: 0 0 160 + Linker Generated: 0 86 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 18136 447 1172 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00008c62 records: 2, size/record: 4, table size: 8 + .data: load addr=00008c14, load size=00000044 bytes, run addr=0000264c, run size=000000fe bytes, compression=lzss + .bss: load addr=00008c5e, load size=00000004 bytes, run addr=0000274a, run size=000000aa bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 00008c58 records: 3, size/record: 2, table size: 6 + index: 0, handler: __TI_zero_init + index: 1, handler: __TI_decompress_lzss + index: 2, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +00008abe C$$EXIT +000086e0 C$$IO$$ +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +0000844a HOSTclose +00007a42 HOSTlseek +00007ee4 HOSTopen +0000800e HOSTread +00007e12 HOSTrename +00008516 HOSTunlink +00007f4a HOSTwrite +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +00000902 USBCNF +00000903 USBCNF_H +00000902 USBCNF_L +0000093c USBCTL +0000093a USBFN +0000093b USBFN_H +0000093a USBFN_L +0000093f USBFUNADR +0000093d USBIE +00002378 USBIEP0BUF +000023c9 USBIEPBBAX_1 +000023d1 USBIEPBBAX_2 +000023d9 USBIEPBBAX_3 +000023e1 USBIEPBBAX_4 +000023e9 USBIEPBBAX_5 +000023f1 USBIEPBBAX_6 +000023f9 USBIEPBBAX_7 +000023cd USBIEPBBAY_1 +000023d5 USBIEPBBAY_2 +000023dd USBIEPBBAY_3 +000023e5 USBIEPBBAY_4 +000023ed USBIEPBBAY_5 +000023f5 USBIEPBBAY_6 +000023fd USBIEPBBAY_7 +000023ca USBIEPBCTX_1 +000023d2 USBIEPBCTX_2 +000023da USBIEPBCTX_3 +000023e2 USBIEPBCTX_4 +000023ea USBIEPBCTX_5 +000023f2 USBIEPBCTX_6 +000023fa USBIEPBCTX_7 +000023ce USBIEPBCTY_1 +000023d6 USBIEPBCTY_2 +000023de USBIEPBCTY_3 +000023e6 USBIEPBCTY_4 +000023ee USBIEPBCTY_5 +000023f6 USBIEPBCTY_6 +000023fe USBIEPBCTY_7 +00000920 USBIEPCNF_0 +000023c8 USBIEPCNF_1 +000023d0 USBIEPCNF_2 +000023d8 USBIEPCNF_3 +000023e0 USBIEPCNF_4 +000023e8 USBIEPCNF_5 +000023f0 USBIEPCNF_6 +000023f8 USBIEPCNF_7 +00000921 USBIEPCNT_0 +0000092e USBIEPIE +00000930 USBIEPIFG +000023cf USBIEPSIZXY_1 +000023d7 USBIEPSIZXY_2 +000023df USBIEPSIZXY_3 +000023e7 USBIEPSIZXY_4 +000023ef USBIEPSIZXY_5 +000023f7 USBIEPSIZXY_6 +000023ff USBIEPSIZXY_7 +0000093e USBIFG +00000900 USBKEYID +00000901 USBKEYID_H +00000900 USBKEYID_L +00000936 USBMAINT +00000937 USBMAINT_H +00000936 USBMAINT_L +00002370 USBOEP0BUF +00002389 USBOEPBBAX_1 +00002391 USBOEPBBAX_2 +00002399 USBOEPBBAX_3 +000023a1 USBOEPBBAX_4 +000023a9 USBOEPBBAX_5 +000023b1 USBOEPBBAX_6 +000023b9 USBOEPBBAX_7 +0000238d USBOEPBBAY_1 +00002395 USBOEPBBAY_2 +0000239d USBOEPBBAY_3 +000023a5 USBOEPBBAY_4 +000023ad USBOEPBBAY_5 +000023b5 USBOEPBBAY_6 +000023bd USBOEPBBAY_7 +0000238a USBOEPBCTX_1 +00002392 USBOEPBCTX_2 +0000239a USBOEPBCTX_3 +000023a2 USBOEPBCTX_4 +000023aa USBOEPBCTX_5 +000023b2 USBOEPBCTX_6 +000023ba USBOEPBCTX_7 +0000238e USBOEPBCTY_1 +00002396 USBOEPBCTY_2 +0000239e USBOEPBCTY_3 +000023a6 USBOEPBCTY_4 +000023ae USBOEPBCTY_5 +000023b6 USBOEPBCTY_6 +000023be USBOEPBCTY_7 +00000922 USBOEPCNF_0 +00002388 USBOEPCNF_1 +00002390 USBOEPCNF_2 +00002398 USBOEPCNF_3 +000023a0 USBOEPCNF_4 +000023a8 USBOEPCNF_5 +000023b0 USBOEPCNF_6 +000023b8 USBOEPCNF_7 +00000923 USBOEPCNT_0 +0000092f USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +0000252c _CIOBUF_ +00004400 __STACK_END +000000a0 __STACK_SIZE +0000012c __SYSMEM_SIZE +00008c62 __TI_CINIT_Base +00008c6a __TI_CINIT_Limit +00008c58 __TI_Handler_Table_Base +00008c5e __TI_Handler_Table_Limit +00008c0c __TI_ISR_TRAP +00008128 __TI_auto_init_nobinit_nopinit_hold_wdt +0000864e __TI_cleanup +0000273a __TI_cleanup_ptr +00007cbe __TI_closefile +00007b4e __TI_decompress_lzss +00008a2a __TI_decompress_none +00007fac __TI_doflush +0000273c __TI_dtors_ptr +00002746 __TI_enable_exit_profile_output +00004b36 __TI_frcdivd +00006a3a __TI_frcmpyd +00002742 __TI_ft_end +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +00007aca __TI_ltoa +ffffffff __TI_pprof_out_hndl +000055ce __TI_printfi +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +00008740 __TI_readmsg +0000274a __TI_tmpnams +000086b6 __TI_writemsg +00007bca __TI_wrt_ok +000089c6 __TI_zero_init_nomemset +ffffffff __c_args__ +00004400 __mspabi_addd +00007348 __mspabi_cmpd +00005f5a __mspabi_divd +00008556 __mspabi_divli +000089b0 __mspabi_divu +000081d8 __mspabi_divul +00004fae __mspabi_divull +00008842 __mspabi_fixdi +00007d30 __mspabi_fixdli +00008a8e __mspabi_fltid +0000773a __mspabi_fltlid +00008a6c __mspabi_func_epilog_1 +00008a6a __mspabi_func_epilog_2 +00008a68 __mspabi_func_epilog_3 +00008a66 __mspabi_func_epilog_4 +00008a64 __mspabi_func_epilog_5 +00008a62 __mspabi_func_epilog_6 +00008a60 __mspabi_func_epilog_7 +0000530e __mspabi_mpyd +00008a02 __mspabi_mpyi_f5hw +00008926 __mspabi_mpyl_f5hw +0000806e __mspabi_mpyll_f5hw +0000881a __mspabi_mpyull_f5hw +000087f0 __mspabi_negd +00008556 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close +00008712 copysign +00008712 copysignl +00002744 errno +000084d2 exit +00008682 finddevice +00007924 fputc +0000717e fputs +00007424 free +0000768a frexp +0000768a frexpl +00007da2 fseek +00008180 getdevice +00006bac ldexp +00006bac ldexpl +000088ba lseek +00008230 main +00008ab0 malloc +00007088 memalign +00008904 memccpy +000089da memchr +00008a4e memcpy +000089ee memset +000027ea parmbuf +00008612 printf +00007924 putc +00008892 remove +00006bac scalbn +00006bac scalbnl +000074f6 setvbuf +0000897e strchr +00008998 strcmp +00008a70 strcpy +00008a80 strlen +000087c4 strncpy +00008a9a toupper +00008892 unlink +00008a16 wcslen +000088e0 write + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +000000a0 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012c __SYSMEM_SIZE +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H +00000726 ADC12MEM3 +00000726 ADC12MEM3_L +00000727 ADC12MEM3_H +00000728 ADC12MEM4 +00000728 ADC12MEM4_L +00000729 ADC12MEM4_H +0000072a ADC12MEM5 +0000072a ADC12MEM5_L +0000072b ADC12MEM5_H +0000072c ADC12MEM6 +0000072c ADC12MEM6_L +0000072d ADC12MEM6_H +0000072e ADC12MEM7 +0000072e ADC12MEM7_L +0000072f ADC12MEM7_H +00000730 ADC12MEM8 +00000730 ADC12MEM8_L +00000731 ADC12MEM8_H +00000732 ADC12MEM9 +00000732 ADC12MEM9_L +00000733 ADC12MEM9_H +00000734 ADC12MEM10 +00000734 ADC12MEM10_L +00000735 ADC12MEM10_H +00000736 ADC12MEM11 +00000736 ADC12MEM11_L +00000737 ADC12MEM11_H +00000738 ADC12MEM12 +00000738 ADC12MEM12_L +00000739 ADC12MEM12_H +0000073a ADC12MEM13 +0000073a ADC12MEM13_L +0000073b ADC12MEM13_H +0000073c ADC12MEM14 +0000073c ADC12MEM14_L +0000073d ADC12MEM14_H +0000073e ADC12MEM15 +0000073e ADC12MEM15_L +0000073f ADC12MEM15_H +000008c0 CBCTL0 +000008c0 CBCTL0_L +000008c1 CBCTL0_H +000008c2 CBCTL1 +000008c2 CBCTL1_L +000008c3 CBCTL1_H +000008c4 CBCTL2 +000008c4 CBCTL2_L +000008c5 CBCTL2_H +000008c6 CBCTL3 +000008c6 CBCTL3_L +000008c7 CBCTL3_H +000008cc CBINT +000008cc CBINT_L +000008cd CBINT_H +000008ce CBIV +00000900 USBKEYID +00000900 USBKEYID_L +00000901 USBKEYID_H +00000902 USBCNF +00000902 USBCNF_L +00000903 USBCNF_H +00000904 USBPHYCTL +00000904 USBPHYCTL_L +00000905 USBPHYCTL_H +00000908 USBPWRCTL +00000908 USBPWRCTL_L +00000909 USBPWRCTL_H +00000910 USBPLLCTL +00000910 USBPLLCTL_L +00000911 USBPLLCTL_H +00000912 USBPLLDIVB +00000912 USBPLLDIVB_L +00000913 USBPLLDIVB_H +00000914 USBPLLIR +00000914 USBPLLIR_L +00000915 USBPLLIR_H +00000920 USBIEPCNF_0 +00000921 USBIEPCNT_0 +00000922 USBOEPCNF_0 +00000923 USBOEPCNT_0 +0000092e USBIEPIE +0000092f USBOEPIE +00000930 USBIEPIFG +00000931 USBOEPIFG +00000932 USBVECINT +00000932 USBVECINT_L +00000933 USBVECINT_H +00000936 USBMAINT +00000936 USBMAINT_L +00000937 USBMAINT_H +00000938 USBTSREG +00000938 USBTSREG_L +00000939 USBTSREG_H +0000093a USBFN +0000093a USBFN_L +0000093b USBFN_H +0000093c USBCTL +0000093d USBIE +0000093e USBIFG +0000093f USBFUNADR +00001c00 USBSTABUFF +0000236f USBTOPBUFF +00002370 USBOEP0BUF +00002378 USBIEP0BUF +00002380 USBSUBLK +00002388 USBOEPCNF_1 +00002389 USBOEPBBAX_1 +0000238a USBOEPBCTX_1 +0000238d USBOEPBBAY_1 +0000238e USBOEPBCTY_1 +0000238f USBOEPSIZXY_1 +00002390 USBOEPCNF_2 +00002391 USBOEPBBAX_2 +00002392 USBOEPBCTX_2 +00002395 USBOEPBBAY_2 +00002396 USBOEPBCTY_2 +00002397 USBOEPSIZXY_2 +00002398 USBOEPCNF_3 +00002399 USBOEPBBAX_3 +0000239a USBOEPBCTX_3 +0000239d USBOEPBBAY_3 +0000239e USBOEPBCTY_3 +0000239f USBOEPSIZXY_3 +000023a0 USBOEPCNF_4 +000023a1 USBOEPBBAX_4 +000023a2 USBOEPBCTX_4 +000023a5 USBOEPBBAY_4 +000023a6 USBOEPBCTY_4 +000023a7 USBOEPSIZXY_4 +000023a8 USBOEPCNF_5 +000023a9 USBOEPBBAX_5 +000023aa USBOEPBCTX_5 +000023ad USBOEPBBAY_5 +000023ae USBOEPBCTY_5 +000023af USBOEPSIZXY_5 +000023b0 USBOEPCNF_6 +000023b1 USBOEPBBAX_6 +000023b2 USBOEPBCTX_6 +000023b5 USBOEPBBAY_6 +000023b6 USBOEPBCTY_6 +000023b7 USBOEPSIZXY_6 +000023b8 USBOEPCNF_7 +000023b9 USBOEPBBAX_7 +000023ba USBOEPBCTX_7 +000023bd USBOEPBBAY_7 +000023be USBOEPBCTY_7 +000023bf USBOEPSIZXY_7 +000023c8 USBIEPCNF_1 +000023c9 USBIEPBBAX_1 +000023ca USBIEPBCTX_1 +000023cd USBIEPBBAY_1 +000023ce USBIEPBCTY_1 +000023cf USBIEPSIZXY_1 +000023d0 USBIEPCNF_2 +000023d1 USBIEPBBAX_2 +000023d2 USBIEPBCTX_2 +000023d5 USBIEPBBAY_2 +000023d6 USBIEPBCTY_2 +000023d7 USBIEPSIZXY_2 +000023d8 USBIEPCNF_3 +000023d9 USBIEPBBAX_3 +000023da USBIEPBCTX_3 +000023dd USBIEPBBAY_3 +000023de USBIEPBCTY_3 +000023df USBIEPSIZXY_3 +000023e0 USBIEPCNF_4 +000023e1 USBIEPBBAX_4 +000023e2 USBIEPBCTX_4 +000023e5 USBIEPBBAY_4 +000023e6 USBIEPBCTY_4 +000023e7 USBIEPSIZXY_4 +000023e8 USBIEPCNF_5 +000023e9 USBIEPBBAX_5 +000023ea USBIEPBCTX_5 +000023ed USBIEPBBAY_5 +000023ee USBIEPBCTY_5 +000023ef USBIEPSIZXY_5 +000023f0 USBIEPCNF_6 +000023f1 USBIEPBBAX_6 +000023f2 USBIEPBCTX_6 +000023f5 USBIEPBBAY_6 +000023f6 USBIEPBCTY_6 +000023f7 USBIEPSIZXY_6 +000023f8 USBIEPCNF_7 +000023f9 USBIEPBBAX_7 +000023fa USBIEPBCTX_7 +000023fd USBIEPBBAY_7 +000023fe USBIEPBCTY_7 +000023ff USBIEPSIZXY_7 +00002400 _sys_memory +0000252c _CIOBUF_ +0000264c _ftable +000026c4 _device +00002712 _stream +0000273a __TI_cleanup_ptr +0000273c __TI_dtors_ptr +0000273e _lock +00002740 _unlock +00002742 __TI_ft_end +00002744 errno +00002746 __TI_enable_exit_profile_output +0000274a __TI_tmpnams +000027ea parmbuf +00004360 _stack +00004400 __STACK_END +00004400 __mspabi_addd +00004b36 __TI_frcdivd +00004fae __mspabi_divull +0000530e __mspabi_mpyd +000055ce __TI_printfi +00005f5a __mspabi_divd +00006a3a __TI_frcmpyd +00006bac ldexp +00006bac ldexpl +00006bac scalbn +00006bac scalbnl +00007088 aligned_alloc +00007088 memalign +0000717e fputs +00007348 __mspabi_cmpd +00007424 free +000074f6 setvbuf +0000768a frexp +0000768a frexpl +0000773a __mspabi_fltlid +00007924 fputc +00007924 putc +00007a42 HOSTlseek +00007aca __TI_ltoa +00007b4e __TI_decompress_lzss +00007bca __TI_wrt_ok +00007cbe __TI_closefile +00007d30 __mspabi_fixdli +00007da2 fseek +00007e12 HOSTrename +00007ee4 HOSTopen +00007f4a HOSTwrite +00007fac __TI_doflush +0000800e HOSTread +0000806e __mspabi_mpyll_f5hw +000080cc __mspabi_srll_15 +000080d2 __mspabi_srll_14 +000080d8 __mspabi_srll_13 +000080de __mspabi_srll_12 +000080e4 __mspabi_srll_11 +000080ea __mspabi_srll_10 +000080f0 __mspabi_srll_9 +000080f6 __mspabi_srll_8 +000080fc __mspabi_srll_7 +00008102 __mspabi_srll_6 +00008108 __mspabi_srll_5 +0000810e __mspabi_srll_4 +00008114 __mspabi_srll_3 +0000811a __mspabi_srll_2 +00008120 __mspabi_srll_1 +00008128 __TI_auto_init_nobinit_nopinit_hold_wdt +00008180 getdevice +000081d8 __mspabi_divul +000081d8 __mspabi_remul +00008230 main +00008284 atoi +00008324 __mspabi_srli +00008332 __mspabi_srli_15 +00008336 __mspabi_srli_14 +0000833a __mspabi_srli_13 +0000833e __mspabi_srli_12 +00008342 __mspabi_srli_11 +00008346 __mspabi_srli_10 +0000834a __mspabi_srli_9 +0000834e __mspabi_srli_8 +00008352 __mspabi_srli_7 +00008356 __mspabi_srli_6 +0000835a __mspabi_srli_5 +0000835e __mspabi_srli_4 +00008362 __mspabi_srli_3 +00008366 __mspabi_srli_2 +0000836a __mspabi_srli_1 +00008370 __mspabi_srall +000083ba close +00008404 __mspabi_srlll +0000844a HOSTclose +0000848e __mspabi_sllll +000084d2 exit +00008516 HOSTunlink +00008556 __mspabi_divli +00008556 __mspabi_remli +00008596 __mspabi_sral_15 +0000859a __mspabi_sral_14 +0000859e __mspabi_sral_13 +000085a2 __mspabi_sral_12 +000085a6 __mspabi_sral_11 +000085aa __mspabi_sral_10 +000085ae __mspabi_sral_9 +000085b2 __mspabi_sral_8 +000085b6 __mspabi_sral_7 +000085ba __mspabi_sral_6 +000085be __mspabi_sral_5 +000085c2 __mspabi_sral_4 +000085c6 __mspabi_sral_3 +000085ca __mspabi_sral_2 +000085ce __mspabi_sral_1 +000085d4 __mspabi_slll_15 +000085d8 __mspabi_slll_14 +000085dc __mspabi_slll_13 +000085e0 __mspabi_slll_12 +000085e4 __mspabi_slll_11 +000085e8 __mspabi_slll_10 +000085ec __mspabi_slll_9 +000085f0 __mspabi_slll_8 +000085f4 __mspabi_slll_7 +000085f8 __mspabi_slll_6 +000085fc __mspabi_slll_5 +00008600 __mspabi_slll_4 +00008604 __mspabi_slll_3 +00008608 __mspabi_slll_2 +0000860c __mspabi_slll_1 +00008612 printf +0000864e __TI_cleanup +00008682 finddevice +000086b6 __TI_writemsg +000086e0 C$$IO$$ +000086e4 __mspabi_subd +00008712 copysign +00008712 copysignl +00008740 __TI_readmsg +0000876c __mspabi_srai +00008778 __mspabi_srai_15 +0000877a __mspabi_srai_14 +0000877c __mspabi_srai_13 +0000877e __mspabi_srai_12 +00008780 __mspabi_srai_11 +00008782 __mspabi_srai_10 +00008784 __mspabi_srai_9 +00008786 __mspabi_srai_8 +00008788 __mspabi_srai_7 +0000878a __mspabi_srai_6 +0000878c __mspabi_srai_5 +0000878e __mspabi_srai_4 +00008790 __mspabi_srai_3 +00008792 __mspabi_srai_2 +00008794 __mspabi_srai_1 +00008798 __mspabi_slli +000087a4 __mspabi_slli_15 +000087a6 __mspabi_slli_14 +000087a8 __mspabi_slli_13 +000087aa __mspabi_slli_12 +000087ac __mspabi_slli_11 +000087ae __mspabi_slli_10 +000087b0 __mspabi_slli_9 +000087b2 __mspabi_slli_8 +000087b4 __mspabi_slli_7 +000087b6 __mspabi_slli_6 +000087b8 __mspabi_slli_5 +000087ba __mspabi_slli_4 +000087bc __mspabi_slli_3 +000087be __mspabi_slli_2 +000087c0 __mspabi_slli_1 +000087c4 strncpy +000087f0 __mspabi_negd +0000881a __mspabi_mpyull_f5hw +00008842 __mspabi_fixdi +00008892 remove +00008892 unlink +000088ba lseek +000088e0 write +00008904 memccpy +00008926 __mspabi_mpyl_f5hw +00008946 _c_int00_noargs +0000897e strchr +00008998 strcmp +000089b0 __mspabi_divu +000089b0 __mspabi_remu +000089c6 __TI_zero_init_nomemset +000089da memchr +000089ee memset +00008a02 __mspabi_mpyi_f5hw +00008a16 wcslen +00008a2a __TI_decompress_none +00008a3c __mspabi_srll +00008a4e memcpy +00008a60 __mspabi_func_epilog_7 +00008a62 __mspabi_func_epilog_6 +00008a64 __mspabi_func_epilog_5 +00008a66 __mspabi_func_epilog_4 +00008a68 __mspabi_func_epilog_3 +00008a6a __mspabi_func_epilog_2 +00008a6c __mspabi_func_epilog_1 +00008a70 strcpy +00008a80 strlen +00008a8e __mspabi_fltid +00008a9a toupper +00008aa6 abs +00008ab0 malloc +00008abe C$$EXIT +00008abe abort +00008ac8 _system_pre_init +00008acc _nop +00008ace _system_post_cinit +00008ad0 _ctypes_ +00008c0c __TI_ISR_TRAP +00008c58 __TI_Handler_Table_Base +00008c5e __TI_Handler_Table_Limit +00008c62 __TI_CINIT_Base +00008c6a __TI_CINIT_Limit +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +0000fffe _reset_vector +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[974 symbols] diff --git a/CPE325/L1_P1_For/Debug/L1_P1_For.out b/CPE325/L1_P1_For/Debug/L1_P1_For.out new file mode 100644 index 0000000..52fea87 Binary files /dev/null and b/CPE325/L1_P1_For/Debug/L1_P1_For.out differ diff --git a/CPE325/L1_P1_For/Debug/L1_P1_For_linkInfo.xml b/CPE325/L1_P1_For/Debug/L1_P1_For_linkInfo.xml new file mode 100644 index 0000000..b44a94f --- /dev/null +++ b/CPE325/L1_P1_For/Debug/L1_P1_For_linkInfo.xml @@ -0,0 +1,16322 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x6126c89d + 0x0 + L1_P1_For.out + + _c_int00_noargs +
0x8946
+ + + + .\ + object + for.obj + for.obj + + + object + <internal> + <internal> + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + printf.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + _printfi.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + fputc.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + fputs.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + _io_perm.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + setvbuf.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + wcslen.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + s_frexp.c.obj + + + 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+ UCSCTL4_L + 0x168 + + + UCSCTL4_H + 0x169 + + + UCSCTL5 + 0x16a + + + UCSCTL5_L + 0x16a + + + UCSCTL5_H + 0x16b + + + UCSCTL6 + 0x16c + + + UCSCTL6_L + 0x16c + + + UCSCTL6_H + 0x16d + + + UCSCTL7 + 0x16e + + + UCSCTL7_L + 0x16e + + + UCSCTL7_H + 0x16f + + + UCSCTL8 + 0x170 + + + UCSCTL8_L + 0x170 + + + UCSCTL8_H + 0x171 + + + UCA0CTLW0 + 0x5c0 + + + UCA0CTLW0_L + 0x5c0 + + + UCA0CTLW0_H + 0x5c1 + + + UCA0BRW + 0x5c6 + + + UCA0BRW_L + 0x5c6 + + + UCA0BRW_H + 0x5c7 + + + UCA0MCTL + 0x5c8 + + + UCA0STAT + 0x5ca + + + UCA0RXBUF + 0x5cc + + + UCA0TXBUF + 0x5ce + + + UCA0ABCTL + 0x5d0 + + + UCA0IRCTL + 0x5d2 + + + UCA0IRCTL_L + 0x5d2 + + + UCA0IRCTL_H + 0x5d3 + + + UCA0ICTL + 0x5dc + + + UCA0ICTL_L + 0x5dc + + + UCA0ICTL_H + 0x5dd + + + UCA0IV + 0x5de + + + UCB0CTLW0 + 0x5e0 + + + UCB0CTLW0_L + 0x5e0 + + + UCB0CTLW0_H + 0x5e1 + + + UCB0BRW + 0x5e6 + + + UCB0BRW_L + 0x5e6 + + + UCB0BRW_H + 0x5e7 + + + UCB0STAT + 0x5ea + + + UCB0RXBUF + 0x5ec + + + UCB0TXBUF + 0x5ee + + + UCB0I2COA + 0x5f0 + + + UCB0I2COA_L + 0x5f0 + + + UCB0I2COA_H + 0x5f1 + + + UCB0I2CSA + 0x5f2 + + + UCB0I2CSA_L + 0x5f2 + + + UCB0I2CSA_H + 0x5f3 + + + UCB0ICTL + 0x5fc + + + UCB0ICTL_L + 0x5fc + + + UCB0ICTL_H + 0x5fd + + + UCB0IV + 0x5fe + + + UCA1CTLW0 + 0x600 + + + UCA1CTLW0_L + 0x600 + + + UCA1CTLW0_H + 0x601 + + + UCA1BRW + 0x606 + + + UCA1BRW_L + 0x606 + + + UCA1BRW_H + 0x607 + + + UCA1MCTL + 0x608 + + + UCA1STAT + 0x60a + + + UCA1RXBUF + 0x60c + + + UCA1TXBUF + 0x60e + + + UCA1ABCTL + 0x610 + + + UCA1IRCTL + 0x612 + + + UCA1IRCTL_L + 0x612 + + + UCA1IRCTL_H + 0x613 + + + UCA1ICTL + 0x61c + + + UCA1ICTL_L + 0x61c + + + UCA1ICTL_H + 0x61d + + + UCA1IV + 0x61e + + + UCB1CTLW0 + 0x620 + + + UCB1CTLW0_L + 0x620 + + + UCB1CTLW0_H + 0x621 + + + UCB1BRW + 0x626 + + + UCB1BRW_L + 0x626 + + + UCB1BRW_H + 0x627 + + + UCB1STAT + 0x62a + + + UCB1RXBUF + 0x62c + + + UCB1TXBUF + 0x62e + + + UCB1I2COA + 0x630 + + + UCB1I2COA_L + 0x630 + + + UCB1I2COA_H + 0x631 + + + UCB1I2CSA + 0x632 + + + UCB1I2CSA_L + 0x632 + + + UCB1I2CSA_H + 0x633 + + + UCB1ICTL + 0x63c + + + UCB1ICTL_L + 0x63c + + + UCB1ICTL_H + 0x63d + + + UCB1IV + 0x63e + + + WDTCTL + 0x15c + + + WDTCTL_L + 0x15c + + + WDTCTL_H + 0x15d + + + __TI_CINIT_Base + 0x8c62 + + + __TI_CINIT_Limit + 0x8c6a + + + __TI_Handler_Table_Base + 0x8c58 + + + __TI_Handler_Table_Limit + 0x8c5e + + + __STACK_SIZE + 0xa0 + + + __STACK_END + 0x4400 + + + __SYSMEM_SIZE + 0x12c + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + main + 0x8230 + + + + printf + 0x8612 + + + + __TI_printfi + 0x55ce + + + + putc + 0x7924 + + + + fputc + 0x7924 + + + + fputs + 0x717e + + + + __TI_wrt_ok + 0x7bca + + + + setvbuf + 0x74f6 + + + + wcslen + 0x8a16 + + + + frexpl + 0x768a + + + + frexp + 0x768a + + + + scalbn + 0x6bac + + + + scalbnl + 0x6bac + + + + ldexpl + 0x6bac + + + + ldexp + 0x6bac + + + + __mspabi_srai + 0x876c + + + + __mspabi_srai_8 + 0x8786 + + + + __mspabi_srai_9 + 0x8784 + + + + __mspabi_srai_6 + 0x878a + + + + __mspabi_srai_7 + 0x8788 + + + + __mspabi_srai_4 + 0x878e + + + + __mspabi_srai_5 + 0x878c + + + + __mspabi_srai_2 + 0x8792 + + + + __mspabi_srai_3 + 0x8790 + + + + __mspabi_srai_1 + 0x8794 + + + + __mspabi_srai_15 + 0x8778 + + + + __mspabi_srai_14 + 0x877a + + + + __mspabi_srai_13 + 0x877c + + + + __mspabi_srai_12 + 0x877e + + + + __mspabi_srai_11 + 0x8780 + + + + __mspabi_srai_10 + 0x8782 + + + + __mspabi_remu + 0x89b0 + + + + __mspabi_divu + 0x89b0 + + + + __mspabi_remul + 0x81d8 + + + + __mspabi_divul + 0x81d8 + + + + __mspabi_func_epilog_2 + 0x8a6a + + + + __mspabi_func_epilog_3 + 0x8a68 + + + + __mspabi_func_epilog_1 + 0x8a6c + + + + __mspabi_func_epilog_6 + 0x8a62 + + + + __mspabi_func_epilog_7 + 0x8a60 + + + + __mspabi_func_epilog_4 + 0x8a66 + + + + __mspabi_func_epilog_5 + 0x8a64 + + + + __TI_int41 + 0xffd2 + + + + __TI_int42 + 0xffd4 + + + + __TI_int43 + 0xffd6 + + + + __TI_int44 + 0xffd8 + + + + __TI_int45 + 0xffda + + + + __TI_int46 + 0xffdc + + + + __TI_int47 + 0xffde + + + + __TI_int48 + 0xffe0 + + + + __TI_int49 + 0xffe2 + + + + __TI_int50 + 0xffe4 + + + + __TI_int51 + 0xffe6 + + + + __TI_int52 + 0xffe8 + + + + __TI_int53 + 0xffea + + + + __TI_int54 + 0xffec + + + + __TI_int55 + 0xffee + + + + __TI_int56 + 0xfff0 + + + + __TI_int57 + 0xfff2 + + + + __TI_int58 + 0xfff4 + + + + __TI_int59 + 0xfff6 + + + + __TI_int60 + 0xfff8 + + + + __TI_int61 + 0xfffa + + + + __TI_int62 + 0xfffc + + + + __TI_ISR_TRAP + 0x8c0c + + + + __mspabi_slli + 0x8798 + + + + __mspabi_slli_9 + 0x87b0 + + + + __mspabi_slli_8 + 0x87b2 + + + + __mspabi_slli_7 + 0x87b4 + + + + __mspabi_slli_6 + 0x87b6 + + + + __mspabi_slli_5 + 0x87b8 + + + + __mspabi_slli_4 + 0x87ba + + + + __mspabi_slli_3 + 0x87bc + + + + __mspabi_slli_2 + 0x87be + + + + __mspabi_slli_1 + 0x87c0 + + + + __mspabi_slli_15 + 0x87a4 + + + + __mspabi_slli_14 + 0x87a6 + + + + __mspabi_slli_13 + 0x87a8 + + + + __mspabi_slli_12 + 0x87aa + + + + __mspabi_slli_11 + 0x87ac + + + + __mspabi_slli_10 + 0x87ae + + + + __mspabi_srli_8 + 0x834e + + + + __mspabi_srli_9 + 0x834a + + + + __mspabi_srli_6 + 0x8356 + + + + __mspabi_srli_7 + 0x8352 + + + + __mspabi_srli_4 + 0x835e + + + + __mspabi_srli_5 + 0x835a + + + + __mspabi_srli_2 + 0x8366 + + + + __mspabi_srli_3 + 0x8362 + + + + __mspabi_srli_1 + 0x836a + + + + __mspabi_srli + 0x8324 + + + + __mspabi_srli_15 + 0x8332 + + + + __mspabi_srli_14 + 0x8336 + + + + __mspabi_srli_13 + 0x833a + + + + __mspabi_srli_12 + 0x833e + + + + __mspabi_srli_11 + 0x8342 + + + + __mspabi_srli_10 + 0x8346 + + + + __mspabi_mpyi_f5hw + 0x8a02 + + + + __mspabi_mpyl_f5hw + 0x8926 + + + + __mspabi_mpyull_f5hw + 0x881a + + + + __mspabi_mpyll_f5hw + 0x806e + + + + _stack + 0x4360 + + + + _c_int00_noargs + 0x8946 + + + + _reset_vector + 0xfffe + + + + __TI_auto_init_nobinit_nopinit_hold_wdt + 0x8128 + + + + __TI_zero_init_nomemset + 0x89c6 + + + + __TI_dtors_ptr + 0x273c + + + + __TI_cleanup_ptr + 0x273a + + + + __mspabi_srlll + 0x8404 + + + + __mspabi_divull + 0x4fae + + + + _system_pre_init + 0x8ac8 + + + + _system_post_cinit + 0x8ace + + + + __TI_decompress_none + 0x8a2a + + + + __TI_decompress_lzss + 0x7b4e + + + + __mspabi_addd + 0x4400 + + + + __mspabi_cmpd + 0x7348 + + + + __mspabi_divd + 0x5f5a + + + + __mspabi_fixdi + 0x8842 + + + + __mspabi_fixdli + 0x7d30 + + + + __mspabi_fltid + 0x8a8e + + + + __mspabi_fltlid + 0x773a + + + + __TI_frcdivd + 0x4b36 + + + + __mspabi_mpyd + 0x530e + + + + __mspabi_negd + 0x87f0 + + + + __mspabi_subd + 0x86e4 + + + + C$$EXIT + 0x8abe + + + + abort + 0x8abe + + + + __TI_enable_exit_profile_output + 0x2746 + + + + exit + 0x84d2 + + + + _nop + 0x8acc + + + + _lock + 0x273e + + + + _unlock + 0x2740 + + + + __TI_ltoa + 0x7aca + + + + atoi + 0x8284 + + + + _ctypes_ + 0x8ad0 + + + + __TI_tmpnams + 0x274a + + + _ftable + 0x264c + + + + __TI_ft_end + 0x2742 + + + + memccpy + 0x8904 + + + + memchr + 0x89da + + + + memcpy + 0x8a4e + + + + _sys_memory + 0x2400 + + + + free + 0x7424 + + + + memalign + 0x7088 + + + + malloc + 0x8ab0 + + + + aligned_alloc + 0x7088 + + + + memset + 0x89ee + + + + strchr + 0x897e + + + + strlen + 0x8a80 + + + + toupper + 0x8a9a + + + + write + 0x88e0 + + + + _stream + 0x2712 + + + + _device + 0x26c4 + + + + abs + 0x8aa6 + + + + errno + 0x2744 + + + + __TI_doflush + 0x7fac + + + + __TI_cleanup + 0x864e + + + + fseek + 0x7da2 + + + + copysign + 0x8712 + + + + copysignl + 0x8712 + + + + __mspabi_sral_15 + 0x8596 + + + + __mspabi_sral_14 + 0x859a + + + + __mspabi_sral_13 + 0x859e + + + + __mspabi_sral_12 + 0x85a2 + + + + __mspabi_sral_11 + 0x85a6 + + + + __mspabi_sral_10 + 0x85aa + + + + __mspabi_sral_8 + 0x85b2 + + + + __mspabi_sral_9 + 0x85ae + + + + __mspabi_sral_6 + 0x85ba + + + + __mspabi_sral_7 + 0x85b6 + + + + __mspabi_sral_4 + 0x85c2 + + + + __mspabi_sral_5 + 0x85be + + + + __mspabi_sral_2 + 0x85ca + + + + __mspabi_sral_3 + 0x85c6 + + + + __mspabi_sral_1 + 0x85ce + + + + __mspabi_remli + 0x8556 + + + + __mspabi_divli + 0x8556 + + + + __mspabi_slll_9 + 0x85ec + + + + __mspabi_slll_8 + 0x85f0 + + + + __mspabi_slll_7 + 0x85f4 + + + + __mspabi_slll_6 + 0x85f8 + + + + __mspabi_slll_5 + 0x85fc + + + + __mspabi_slll_4 + 0x8600 + + + + __mspabi_slll_3 + 0x8604 + + + + __mspabi_slll_2 + 0x8608 + + + + __mspabi_slll_1 + 0x860c + + + + __mspabi_slll_15 + 0x85d4 + + + + __mspabi_slll_14 + 0x85d8 + + + + __mspabi_slll_13 + 0x85dc + + + + __mspabi_slll_12 + 0x85e0 + + + + __mspabi_slll_11 + 0x85e4 + + + + __mspabi_slll_10 + 0x85e8 + + + + __mspabi_srll_8 + 0x80f6 + + + + __mspabi_srll_9 + 0x80f0 + + + + __mspabi_srll_6 + 0x8102 + + + + __mspabi_srll_7 + 0x80fc + + + + __mspabi_srll_4 + 0x810e + + + + __mspabi_srll_5 + 0x8108 + + + + __mspabi_srll_2 + 0x811a + + + + __mspabi_srll_3 + 0x8114 + + + + __mspabi_srll_1 + 0x8120 + + + + __mspabi_srll_15 + 0x80cc + + + + __mspabi_srll_14 + 0x80d2 + + + + __mspabi_srll_13 + 0x80d8 + + + + __mspabi_srll_12 + 0x80de + + + + __mspabi_srll_11 + 0x80e4 + + + + __mspabi_srll_10 + 0x80ea + + + + __mspabi_srll + 0x8a3c + + + + __mspabi_srall + 0x8370 + + + + __mspabi_sllll + 0x848e + + + + __TI_frcmpyd + 0x6a3a + + + + HOSTclose + 0x844a + + + + HOSTlseek + 0x7a42 + + + + parmbuf + 0x27ea + + + HOSTopen + 0x7ee4 + + + + HOSTread + 0x800e + + + + HOSTrename + 0x7e12 + + + + HOSTunlink + 0x8516 + + + + HOSTwrite + 0x7f4a + + + + __TI_readmsg + 0x8740 + + + + C$$IO$$ + 0x86e0 + + + + _CIOBUF_ + 0x252c + + + + __TI_writemsg + 0x86b6 + + + + lseek + 0x88ba + + + + __TI_closefile + 0x7cbe + + + + finddevice + 0x8682 + + + + getdevice + 0x8180 + + + + strcmp + 0x8998 + + + + strcpy + 0x8a70 + + + + strncpy + 0x87c4 + + + + close + 0x83ba + + + + unlink + 0x8892 + + + + remove + 0x8892 + + + Link successful + diff --git a/CPE325/L1_P1_For/Debug/ccsObjs.opt b/CPE325/L1_P1_For/Debug/ccsObjs.opt new file mode 100644 index 0000000..7cccc09 --- /dev/null +++ b/CPE325/L1_P1_For/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./for.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/L1_P1_For/Debug/for.d b/CPE325/L1_P1_For/Debug/for.d new file mode 100644 index 0000000..b1b7ec2 --- /dev/null +++ b/CPE325/L1_P1_For/Debug/for.d @@ -0,0 +1,42 @@ +# FIXED + +for.obj: ../for.c +for.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +for.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h +for.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +for.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h + +../for.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + diff --git a/CPE325/L1_P1_For/Debug/for.lst b/CPE325/L1_P1_For/Debug/for.lst new file mode 100644 index 0000000..a46498d --- /dev/null +++ b/CPE325/L1_P1_For/Debug/for.lst @@ -0,0 +1,1395 @@ +MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 1 + + 1 ;****************************************************************************** + 2 ;* MSP430 G3 C/C++ Codegen PC v20.2.5.LTS * + 3 ;* Date/Time created: Wed Aug 25 17:47:57 2021 * + 4 ;****************************************************************************** + 5 .compiler_opts --abi=eabi --diag_wrap=off --hll_source=on --mem_model:code=small --mem_model:d + 6 + 7 $C$DW$CU .dwtag DW_TAG_compile_unit + 8 .dwattr $C$DW$CU, DW_AT_name("../for.c") + 9 .dwattr $C$DW$CU, DW_AT_producer("TI MSP430 G3 C/C++ Codegen PC v20.2.5.LTS Copyright (c) 2003 + 10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + 11 .dwattr $C$DW$CU, DW_AT_comp_dir("C:\CPE325_Workspace\L1_P1_For\Debug") + 12 + 13 $C$DW$1 .dwtag DW_TAG_subprogram + 14 .dwattr $C$DW$1, DW_AT_name("printf") + 15 .dwattr $C$DW$1, DW_AT_TI_symbol_name("printf") + 16 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$10) + 17 .dwattr $C$DW$1, DW_AT_declaration + 18 .dwattr $C$DW$1, DW_AT_external + 19 .dwattr $C$DW$1, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/in + 20 .dwattr $C$DW$1, DW_AT_decl_line(0xf6) + 21 .dwattr $C$DW$1, DW_AT_decl_column(0x19) + 22 $C$DW$2 .dwtag DW_TAG_formal_parameter + 23 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$39) + 24 + 25 $C$DW$3 .dwtag DW_TAG_unspecified_parameters + 26 + 27 .dwendtag $C$DW$1 + 28 + 29 ; C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\bin\acpia430.exe -@C:\\Users\\LIBRAR + 30 000000 .sect ".text:main" + 31 .clink + 32 .global main + 33 + 34 $C$DW$4 .dwtag DW_TAG_subprogram + 35 .dwattr $C$DW$4, DW_AT_name("main") + 36 .dwattr $C$DW$4, DW_AT_low_pc(main) + 37 .dwattr $C$DW$4, DW_AT_high_pc(0x00) + 38 .dwattr $C$DW$4, DW_AT_TI_symbol_name("main") + 39 .dwattr $C$DW$4, DW_AT_external + 40 .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$10) + 41 .dwattr $C$DW$4, DW_AT_TI_begin_file("../for.c") + 42 .dwattr $C$DW$4, DW_AT_TI_begin_line(0x0e) + 43 .dwattr $C$DW$4, DW_AT_TI_begin_column(0x05) + 44 .dwattr $C$DW$4, DW_AT_decl_file("../for.c") + 45 .dwattr $C$DW$4, DW_AT_decl_line(0x0e) + 46 .dwattr $C$DW$4, DW_AT_decl_column(0x05) + 47 .dwattr $C$DW$4, DW_AT_TI_max_frame_size(0x12) + 48 .dwpsn file "../for.c",line 14,column 11,is_stmt,address main,isa 0 + 49 + 50 .dwfde $C$DW$CIE, main + 51 + 52 ;***************************************************************************** + 53 ;* FUNCTION NAME: main * + 54 ;* * + 55 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 2 + + 56 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 57 ;* Local Frame Size : 8 Args + 8 Auto + 0 Save = 16 byte * + 58 ;***************************************************************************** + 59 000000 main: + 60 ;* --------------------------------------------------------------------------* + 61 .dwcfi cfa_offset, 2 + 62 .dwcfi save_reg_to_mem, 16, -2 + 63 000000 8031 SUB.W #16,SP ; [] + 000002 0010 + 64 .dwcfi cfa_offset, 18 + 65 $C$DW$5 .dwtag DW_TAG_variable + 66 .dwattr $C$DW$5, DW_AT_name("i") + 67 .dwattr $C$DW$5, DW_AT_TI_symbol_name("i") + 68 .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$10) + 69 .dwattr $C$DW$5, DW_AT_location[DW_OP_breg1 8] + 70 + 71 $C$DW$6 .dwtag DW_TAG_variable + 72 .dwattr $C$DW$6, DW_AT_name("p") + 73 .dwattr $C$DW$6, DW_AT_TI_symbol_name("p") + 74 .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$10) + 75 .dwattr $C$DW$6, DW_AT_location[DW_OP_breg1 10] + 76 + 77 $C$DW$7 .dwtag DW_TAG_variable + 78 .dwattr $C$DW$7, DW_AT_name("second") + 79 .dwattr $C$DW$7, DW_AT_TI_symbol_name("second") + 80 .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$10) + 81 .dwattr $C$DW$7, DW_AT_location[DW_OP_breg1 12] + 82 + 83 $C$DW$8 .dwtag DW_TAG_variable + 84 .dwattr $C$DW$8, DW_AT_name("first") + 85 .dwattr $C$DW$8, DW_AT_TI_symbol_name("first") + 86 .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$10) + 87 .dwattr $C$DW$8, DW_AT_location[DW_OP_breg1 14] + 88 + 89 .dwpsn file "../for.c",line 15,column 13,is_stmt,isa 0 + 90 000004 4381 MOV.W #0,10(SP) ; [] |15| + 000006 000A + 91 .dwpsn file "../for.c",line 16,column 16,is_stmt,isa 0 + 92 000008 40B1 MOV.W #6,12(SP) ; [] |16| + 00000a 0006 + 00000c 000C + 93 .dwpsn file "../for.c",line 17,column 15,is_stmt,isa 0 + 94 00000e 42A1 MOV.W #4,14(SP) ; [] |17| + 000010 000E + 95 .dwpsn file "../for.c",line 18,column 9,is_stmt,isa 0 + 96 000012 4381 MOV.W #0,8(SP) ; [] |18| + 000014 0008 + 97 .dwpsn file "../for.c",line 18,column 13,is_stmt,isa 0 + 98 000016 9191 CMP.W 12(SP),8(SP) ; [] |18| + 000018 000C + 00001a 0008 + 99 00001c 3409 JGE $C$L2 ; [] |18| + 100 ; [] |18| + 101 ;* --------------------------------------------------------------------------* + 102 ;* BEGIN LOOP $C$L1 + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 3 + + 103 ;* + 104 ;* Loop source line : 18 + 105 ;* Loop closing brace source line : 20 + 106 ;* Known Minimum Trip Count : 1 + 107 ;* Known Maximum Trip Count : 4294967295 + 108 ;* Known Max Trip Count Factor : 1 + 109 ;* --------------------------------------------------------------------------* + 110 00001e $C$L1: + 111 .dwpsn file "../for.c",line 19,column 12,is_stmt,isa 0 + 112 00001e 5191 ADD.W 14(SP),10(SP) ; [] |19| + 000020 000E + 000022 000A + 113 .dwpsn file "../for.c",line 18,column 23,is_stmt,isa 0 + 114 000024 5391 ADD.W #1,8(SP) ; [] |18| + 000026 0008 + 115 .dwpsn file "../for.c",line 18,column 13,is_stmt,isa 0 + 116 000028 9191 CMP.W 12(SP),8(SP) ; [] |18| + 00002a 000C + 00002c 0008 + 117 00002e 3BF7 JL $C$L1 ; [] |18| + 118 ; [] |18| + 119 ;* --------------------------------------------------------------------------* + 120 000030 $C$L2: + 121 .dwpsn file "../for.c",line 21,column 5,is_stmt,isa 0 + 122 000030 40B1 MOV.W #$C$SL1+0,0(SP) ; [] |21| + 000032 0000! + 000034 0000 + 123 000036 4191 MOV.W 14(SP),2(SP) ; [] |21| + 000038 000E + 00003a 0002 + 124 00003c 4191 MOV.W 12(SP),4(SP) ; [] |21| + 00003e 000C + 000040 0004 + 125 000042 4191 MOV.W 10(SP),6(SP) ; [] |21| + 000044 000A + 000046 0006 + 126 $C$DW$9 .dwtag DW_TAG_TI_branch + 127 .dwattr $C$DW$9, DW_AT_low_pc(0x00) + 128 .dwattr $C$DW$9, DW_AT_name("printf") + 129 .dwattr $C$DW$9, DW_AT_TI_call + 130 + 131 000048 12B0 CALL #printf ; [] |21| + 00004a 0000! + 132 ; [] |21| + 133 .dwpsn file "../for.c",line 22,column 1,is_stmt,isa 0 + 134 00004c 430C MOV.W #0,r12 ; [] |22| + 135 00004e 5031 ADD.W #16,SP ; [] + 000050 0010 + 136 .dwcfi cfa_offset, 2 + 137 $C$DW$10 .dwtag DW_TAG_TI_branch + 138 .dwattr $C$DW$10, DW_AT_low_pc(0x00) + 139 .dwattr $C$DW$10, DW_AT_TI_return + 140 + 141 000052 4130 RET ; [] + 142 ; [] + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 4 + + 143 .dwattr $C$DW$4, DW_AT_TI_end_file("../for.c") + 144 .dwattr $C$DW$4, DW_AT_TI_end_line(0x16) + 145 .dwattr $C$DW$4, DW_AT_TI_end_column(0x01) + 146 .dwendentry + 147 .dwendtag $C$DW$4 + 148 + 149 ;****************************************************************************** + 150 ;* STRINGS * + 151 ;****************************************************************************** + 152 000000 .sect ".const:.string" + 153 .align 2 + 154 000000 0025 $C$SL1: .string "%d times %d is %d",10,0 + 000001 0064 + 000002 0020 + 000003 0074 + 000004 0069 + 000005 006D + 000006 0065 + 000007 0073 + 000008 0020 + 000009 0025 + 00000a 0064 + 00000b 0020 + 00000c 0069 + 00000d 0073 + 00000e 0020 + 00000f 0025 + 000010 0064 + 000011 000A + 000012 0000 + 155 ;***************************************************************************** + 156 ;* UNDEFINED EXTERNAL REFERENCES * + 157 ;***************************************************************************** + 158 .global printf + 159 + 160 ;****************************************************************************** + 161 ;* BUILD ATTRIBUTES * + 162 ;****************************************************************************** + 163 .battr "TI", Tag_File, 1, Tag_LPM_INFO(1) + 164 .battr "TI", Tag_File, 1, Tag_PORTS_INIT_INFO("012345678901ABCDEFGHIJ0000000000001111000000000 + 165 .battr "TI", Tag_File, 1, Tag_LEA_INFO(1) + 166 .battr "TI", Tag_File, 1, Tag_HW_MPY32_INFO(2) + 167 .battr "TI", Tag_File, 1, Tag_HW_MPY_ISR_INFO(1) + 168 .battr "TI", Tag_File, 1, Tag_HW_MPY_INLINE_INFO(1) + 169 .battr "mspabi", Tag_File, 1, Tag_enum_size(3) + 170 + 171 ;****************************************************************************** + 172 ;* TYPE INFORMATION * + 173 ;****************************************************************************** + 174 + 175 $C$DW$T$21 .dwtag DW_TAG_structure_type + 176 .dwattr $C$DW$T$21, DW_AT_byte_size(0x10) + 177 $C$DW$11 .dwtag DW_TAG_member + 178 .dwattr $C$DW$11, DW_AT_type(*$C$DW$T$14) + 179 .dwattr $C$DW$11, DW_AT_name("__max_align1") + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 5 + + 180 .dwattr $C$DW$11, DW_AT_TI_symbol_name("__max_align1") + 181 .dwattr $C$DW$11, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 182 .dwattr $C$DW$11, DW_AT_accessibility(DW_ACCESS_public) + 183 .dwattr $C$DW$11, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 184 .dwattr $C$DW$11, DW_AT_decl_line(0x7b) + 185 .dwattr $C$DW$11, DW_AT_decl_column(0x0c) + 186 + 187 $C$DW$12 .dwtag DW_TAG_member + 188 .dwattr $C$DW$12, DW_AT_type(*$C$DW$T$18) + 189 .dwattr $C$DW$12, DW_AT_name("__max_align2") + 190 .dwattr $C$DW$12, DW_AT_TI_symbol_name("__max_align2") + 191 .dwattr $C$DW$12, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 192 .dwattr $C$DW$12, DW_AT_accessibility(DW_ACCESS_public) + 193 .dwattr $C$DW$12, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 194 .dwattr $C$DW$12, DW_AT_decl_line(0x7c) + 195 .dwattr $C$DW$12, DW_AT_decl_column(0x0e) + 196 + 197 .dwattr $C$DW$T$21, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 198 .dwattr $C$DW$T$21, DW_AT_decl_line(0x7a) + 199 .dwattr $C$DW$T$21, DW_AT_decl_column(0x10) + 200 .dwendtag $C$DW$T$21 + 201 + 202 $C$DW$T$24 .dwtag DW_TAG_typedef + 203 .dwattr $C$DW$T$24, DW_AT_name("__max_align_t") + 204 .dwattr $C$DW$T$24, DW_AT_type(*$C$DW$T$21) + 205 .dwattr $C$DW$T$24, DW_AT_language(DW_LANG_C) + 206 .dwattr $C$DW$T$24, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 207 .dwattr $C$DW$T$24, DW_AT_decl_line(0x7d) + 208 .dwattr $C$DW$T$24, DW_AT_decl_column(0x03) + 209 + 210 $C$DW$T$2 .dwtag DW_TAG_unspecified_type + 211 .dwattr $C$DW$T$2, DW_AT_name("void") + 212 + 213 + 214 $C$DW$T$25 .dwtag DW_TAG_subroutine_type + 215 .dwattr $C$DW$T$25, DW_AT_language(DW_LANG_C) + 216 .dwendtag $C$DW$T$25 + 217 + 218 $C$DW$T$26 .dwtag DW_TAG_pointer_type + 219 .dwattr $C$DW$T$26, DW_AT_type(*$C$DW$T$25) + 220 .dwattr $C$DW$T$26, DW_AT_address_class(0x10) + 221 + 222 $C$DW$T$27 .dwtag DW_TAG_typedef + 223 .dwattr $C$DW$T$27, DW_AT_name("__SFR_FARPTR") + 224 .dwattr $C$DW$T$27, DW_AT_type(*$C$DW$T$26) + 225 .dwattr $C$DW$T$27, DW_AT_language(DW_LANG_C) + 226 .dwattr $C$DW$T$27, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430f5529.h") + 227 .dwattr $C$DW$T$27, DW_AT_decl_line(0x4a) + 228 .dwattr $C$DW$T$27, DW_AT_decl_column(0x11) + 229 + 230 $C$DW$T$4 .dwtag DW_TAG_base_type + 231 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + 232 .dwattr $C$DW$T$4, DW_AT_name("bool") + 233 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01) + 234 + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 6 + + 235 $C$DW$T$5 .dwtag DW_TAG_base_type + 236 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char) + 237 .dwattr $C$DW$T$5, DW_AT_name("signed char") + 238 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01) + 239 + 240 $C$DW$T$28 .dwtag DW_TAG_typedef + 241 .dwattr $C$DW$T$28, DW_AT_name("__int8_t") + 242 .dwattr $C$DW$T$28, DW_AT_type(*$C$DW$T$5) + 243 .dwattr $C$DW$T$28, DW_AT_language(DW_LANG_C) + 244 .dwattr $C$DW$T$28, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 245 .dwattr $C$DW$T$28, DW_AT_decl_line(0x36) + 246 .dwattr $C$DW$T$28, DW_AT_decl_column(0x16) + 247 + 248 $C$DW$T$29 .dwtag DW_TAG_typedef + 249 .dwattr $C$DW$T$29, DW_AT_name("__int_least8_t") + 250 .dwattr $C$DW$T$29, DW_AT_type(*$C$DW$T$28) + 251 .dwattr $C$DW$T$29, DW_AT_language(DW_LANG_C) + 252 .dwattr $C$DW$T$29, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 253 .dwattr $C$DW$T$29, DW_AT_decl_line(0x5a) + 254 .dwattr $C$DW$T$29, DW_AT_decl_column(0x12) + 255 + 256 $C$DW$T$6 .dwtag DW_TAG_base_type + 257 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char) + 258 .dwattr $C$DW$T$6, DW_AT_name("unsigned char") + 259 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01) + 260 + 261 $C$DW$T$22 .dwtag DW_TAG_pointer_type + 262 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$6) + 263 .dwattr $C$DW$T$22, DW_AT_address_class(0x10) + 264 + 265 $C$DW$T$30 .dwtag DW_TAG_typedef + 266 .dwattr $C$DW$T$30, DW_AT_name("__uint8_t") + 267 .dwattr $C$DW$T$30, DW_AT_type(*$C$DW$T$6) + 268 .dwattr $C$DW$T$30, DW_AT_language(DW_LANG_C) + 269 .dwattr $C$DW$T$30, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 270 .dwattr $C$DW$T$30, DW_AT_decl_line(0x37) + 271 .dwattr $C$DW$T$30, DW_AT_decl_column(0x18) + 272 + 273 $C$DW$T$31 .dwtag DW_TAG_typedef + 274 .dwattr $C$DW$T$31, DW_AT_name("__sa_family_t") + 275 .dwattr $C$DW$T$31, DW_AT_type(*$C$DW$T$30) + 276 .dwattr $C$DW$T$31, DW_AT_language(DW_LANG_C) + 277 .dwattr $C$DW$T$31, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 278 .dwattr $C$DW$T$31, DW_AT_decl_line(0x47) + 279 .dwattr $C$DW$T$31, DW_AT_decl_column(0x13) + 280 + 281 $C$DW$T$32 .dwtag DW_TAG_typedef + 282 .dwattr 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DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1037 .dwattr $C$DW$T$124, DW_AT_decl_line(0x4c) + 1038 .dwattr $C$DW$T$124, DW_AT_decl_column(0x16) + 1039 + 1040 + 1041 $C$DW$T$23 .dwtag DW_TAG_structure_type + 1042 .dwattr $C$DW$T$23, DW_AT_name("__sFILE") + 1043 .dwattr $C$DW$T$23, DW_AT_byte_size(0x0c) + 1044 $C$DW$13 .dwtag DW_TAG_member + 1045 .dwattr $C$DW$13, DW_AT_type(*$C$DW$T$10) + 1046 .dwattr $C$DW$13, DW_AT_name("fd") + 1047 .dwattr $C$DW$13, DW_AT_TI_symbol_name("fd") + 1048 .dwattr $C$DW$13, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 1049 .dwattr $C$DW$13, DW_AT_accessibility(DW_ACCESS_public) + 1050 .dwattr $C$DW$13, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1051 .dwattr $C$DW$13, DW_AT_decl_line(0x52) + 1052 .dwattr $C$DW$13, DW_AT_decl_column(0x0b) + 1053 + 1054 $C$DW$14 .dwtag DW_TAG_member + 1055 .dwattr $C$DW$14, DW_AT_type(*$C$DW$T$22) + 1056 .dwattr $C$DW$14, DW_AT_name("buf") + 1057 .dwattr $C$DW$14, DW_AT_TI_symbol_name("buf") + 1058 .dwattr $C$DW$14, DW_AT_data_member_location[DW_OP_plus_uconst 0x2] + 1059 .dwattr $C$DW$14, DW_AT_accessibility(DW_ACCESS_public) + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 21 + + 1060 .dwattr $C$DW$14, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1061 .dwattr $C$DW$14, DW_AT_decl_line(0x53) + 1062 .dwattr $C$DW$14, DW_AT_decl_column(0x16) + 1063 + 1064 $C$DW$15 .dwtag DW_TAG_member + 1065 .dwattr $C$DW$15, DW_AT_type(*$C$DW$T$22) + 1066 .dwattr $C$DW$15, DW_AT_name("pos") + 1067 .dwattr $C$DW$15, DW_AT_TI_symbol_name("pos") + 1068 .dwattr $C$DW$15, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + 1069 .dwattr $C$DW$15, DW_AT_accessibility(DW_ACCESS_public) + 1070 .dwattr $C$DW$15, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1071 .dwattr $C$DW$15, DW_AT_decl_line(0x54) + 1072 .dwattr $C$DW$15, DW_AT_decl_column(0x16) + 1073 + 1074 $C$DW$16 .dwtag DW_TAG_member + 1075 .dwattr $C$DW$16, DW_AT_type(*$C$DW$T$22) + 1076 .dwattr $C$DW$16, DW_AT_name("bufend") + 1077 .dwattr $C$DW$16, DW_AT_TI_symbol_name("bufend") + 1078 .dwattr $C$DW$16, DW_AT_data_member_location[DW_OP_plus_uconst 0x6] + 1079 .dwattr $C$DW$16, DW_AT_accessibility(DW_ACCESS_public) + 1080 .dwattr $C$DW$16, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1081 .dwattr $C$DW$16, DW_AT_decl_line(0x55) + 1082 .dwattr $C$DW$16, DW_AT_decl_column(0x16) + 1083 + 1084 $C$DW$17 .dwtag DW_TAG_member + 1085 .dwattr $C$DW$17, DW_AT_type(*$C$DW$T$22) + 1086 .dwattr $C$DW$17, DW_AT_name("buff_stop") + 1087 .dwattr $C$DW$17, DW_AT_TI_symbol_name("buff_stop") + 1088 .dwattr $C$DW$17, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 1089 .dwattr $C$DW$17, DW_AT_accessibility(DW_ACCESS_public) + 1090 .dwattr $C$DW$17, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1091 .dwattr $C$DW$17, DW_AT_decl_line(0x56) + 1092 .dwattr $C$DW$17, DW_AT_decl_column(0x16) + 1093 + 1094 $C$DW$18 .dwtag DW_TAG_member + 1095 .dwattr $C$DW$18, DW_AT_type(*$C$DW$T$11) + 1096 .dwattr $C$DW$18, DW_AT_name("flags") + 1097 .dwattr $C$DW$18, DW_AT_TI_symbol_name("flags") + 1098 .dwattr $C$DW$18, DW_AT_data_member_location[DW_OP_plus_uconst 0xa] + 1099 .dwattr $C$DW$18, DW_AT_accessibility(DW_ACCESS_public) + 1100 .dwattr $C$DW$18, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1101 .dwattr $C$DW$18, DW_AT_decl_line(0x57) + 1102 .dwattr $C$DW$18, DW_AT_decl_column(0x16) + 1103 + 1104 .dwattr $C$DW$T$23, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1105 .dwattr $C$DW$T$23, DW_AT_decl_line(0x51) + 1106 .dwattr $C$DW$T$23, DW_AT_decl_column(0x08) + 1107 .dwendtag $C$DW$T$23 + 1108 + 1109 $C$DW$T$125 .dwtag DW_TAG_typedef + 1110 .dwattr $C$DW$T$125, DW_AT_name("FILE") + 1111 .dwattr $C$DW$T$125, DW_AT_type(*$C$DW$T$23) + 1112 .dwattr $C$DW$T$125, DW_AT_language(DW_LANG_C) + 1113 .dwattr $C$DW$T$125, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1114 .dwattr $C$DW$T$125, DW_AT_decl_line(0x5c) + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 22 + + 1115 .dwattr $C$DW$T$125, DW_AT_decl_column(0x18) + 1116 + 1117 + 1118 $C$DW$T$20 .dwtag DW_TAG_structure_type + 1119 .dwattr $C$DW$T$20, DW_AT_name("__timer") + 1120 .dwattr $C$DW$T$20, DW_AT_declaration + 1121 .dwattr $C$DW$T$20, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1122 .dwattr $C$DW$T$20, DW_AT_decl_line(0x4b) + 1123 .dwattr $C$DW$T$20, DW_AT_decl_column(0x10) + 1124 .dwendtag $C$DW$T$20 + 1125 + 1126 $C$DW$T$126 .dwtag DW_TAG_pointer_type + 1127 .dwattr $C$DW$T$126, DW_AT_type(*$C$DW$T$20) + 1128 .dwattr $C$DW$T$126, DW_AT_address_class(0x10) + 1129 + 1130 $C$DW$T$127 .dwtag DW_TAG_typedef + 1131 .dwattr $C$DW$T$127, DW_AT_name("__timer_t") + 1132 .dwattr $C$DW$T$127, DW_AT_type(*$C$DW$T$126) + 1133 .dwattr $C$DW$T$127, DW_AT_language(DW_LANG_C) + 1134 .dwattr $C$DW$T$127, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1135 .dwattr $C$DW$T$127, DW_AT_decl_line(0x4b) + 1136 .dwattr $C$DW$T$127, DW_AT_decl_column(0x19) + 1137 + 1138 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C) + 1139 + 1140 ;*************************************************************** + 1141 ;* DWARF CIE ENTRIES * + 1142 ;*************************************************************** + 1143 + 1144 $C$DW$CIE .dwcie 16 + 1145 .dwcfi cfa_register, 1 + 1146 .dwcfi cfa_offset, 0 + 1147 .dwcfi same_value, 0 + 1148 .dwcfi same_value, 1 + 1149 .dwcfi same_value, 3 + 1150 .dwcfi same_value, 4 + 1151 .dwcfi same_value, 5 + 1152 .dwcfi same_value, 6 + 1153 .dwcfi same_value, 7 + 1154 .dwcfi same_value, 8 + 1155 .dwcfi same_value, 9 + 1156 .dwcfi same_value, 10 + 1157 .dwendentry + 1158 + 1159 ;*************************************************************** + 1160 ;* DWARF REGISTER MAP * + 1161 ;*************************************************************** + 1162 + 1163 $C$DW$19 .dwtag DW_TAG_TI_assign_register + 1164 .dwattr $C$DW$19, DW_AT_name("PC") + 1165 .dwattr $C$DW$19, DW_AT_location[DW_OP_reg0] + 1166 + 1167 $C$DW$20 .dwtag DW_TAG_TI_assign_register + 1168 .dwattr $C$DW$20, DW_AT_name("SP") + 1169 .dwattr $C$DW$20, DW_AT_location[DW_OP_reg1] + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 23 + + 1170 + 1171 $C$DW$21 .dwtag DW_TAG_TI_assign_register + 1172 .dwattr $C$DW$21, DW_AT_name("SR") + 1173 .dwattr $C$DW$21, DW_AT_location[DW_OP_reg2] + 1174 + 1175 $C$DW$22 .dwtag DW_TAG_TI_assign_register + 1176 .dwattr $C$DW$22, DW_AT_name("CG") + 1177 .dwattr $C$DW$22, DW_AT_location[DW_OP_reg3] + 1178 + 1179 $C$DW$23 .dwtag DW_TAG_TI_assign_register + 1180 .dwattr $C$DW$23, DW_AT_name("r4") + 1181 .dwattr $C$DW$23, DW_AT_location[DW_OP_reg4] + 1182 + 1183 $C$DW$24 .dwtag DW_TAG_TI_assign_register + 1184 .dwattr $C$DW$24, DW_AT_name("r5") + 1185 .dwattr $C$DW$24, DW_AT_location[DW_OP_reg5] + 1186 + 1187 $C$DW$25 .dwtag DW_TAG_TI_assign_register + 1188 .dwattr $C$DW$25, DW_AT_name("r6") + 1189 .dwattr $C$DW$25, DW_AT_location[DW_OP_reg6] + 1190 + 1191 $C$DW$26 .dwtag DW_TAG_TI_assign_register + 1192 .dwattr $C$DW$26, DW_AT_name("r7") + 1193 .dwattr $C$DW$26, DW_AT_location[DW_OP_reg7] + 1194 + 1195 $C$DW$27 .dwtag DW_TAG_TI_assign_register + 1196 .dwattr $C$DW$27, DW_AT_name("r8") + 1197 .dwattr $C$DW$27, DW_AT_location[DW_OP_reg8] + 1198 + 1199 $C$DW$28 .dwtag DW_TAG_TI_assign_register + 1200 .dwattr $C$DW$28, DW_AT_name("r9") + 1201 .dwattr $C$DW$28, DW_AT_location[DW_OP_reg9] + 1202 + 1203 $C$DW$29 .dwtag DW_TAG_TI_assign_register + 1204 .dwattr $C$DW$29, DW_AT_name("r10") + 1205 .dwattr $C$DW$29, DW_AT_location[DW_OP_reg10] + 1206 + 1207 $C$DW$30 .dwtag DW_TAG_TI_assign_register + 1208 .dwattr $C$DW$30, DW_AT_name("r11") + 1209 .dwattr $C$DW$30, DW_AT_location[DW_OP_reg11] + 1210 + 1211 $C$DW$31 .dwtag DW_TAG_TI_assign_register + 1212 .dwattr $C$DW$31, DW_AT_name("r12") + 1213 .dwattr $C$DW$31, DW_AT_location[DW_OP_reg12] + 1214 + 1215 $C$DW$32 .dwtag DW_TAG_TI_assign_register + 1216 .dwattr $C$DW$32, DW_AT_name("r13") + 1217 .dwattr $C$DW$32, DW_AT_location[DW_OP_reg13] + 1218 + 1219 $C$DW$33 .dwtag DW_TAG_TI_assign_register + 1220 .dwattr $C$DW$33, DW_AT_name("r14") + 1221 .dwattr $C$DW$33, DW_AT_location[DW_OP_reg14] + 1222 + 1223 $C$DW$34 .dwtag DW_TAG_TI_assign_register + 1224 .dwattr $C$DW$34, DW_AT_name("r15") + MSP430 Assembler PC v20.2.5 Wed Aug 25 17:47:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{31B3A224-AF6E-494B-92E4-D86D7D19292E} PAGE 24 + + 1225 .dwattr $C$DW$34, DW_AT_location[DW_OP_reg15] + 1226 + 1227 $C$DW$35 .dwtag DW_TAG_TI_assign_register + 1228 .dwattr $C$DW$35, DW_AT_name("CIE_RETA") + 1229 .dwattr $C$DW$35, DW_AT_location[DW_OP_reg16] + 1230 + 1231 .dwendtag $C$DW$CU + 1232 + +No Assembly Errors, No Assembly Warnings diff --git a/CPE325/L1_P1_For/Debug/for.obj b/CPE325/L1_P1_For/Debug/for.obj new file mode 100644 index 0000000..0188396 Binary files /dev/null and b/CPE325/L1_P1_For/Debug/for.obj differ diff --git a/CPE325/L1_P1_For/Debug/makefile b/CPE325/L1_P1_For/Debug/makefile new file mode 100644 index 0000000..9c983b8 --- /dev/null +++ b/CPE325/L1_P1_For/Debug/makefile @@ -0,0 +1,168 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./for.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +L1_P1_For.out \ + +EXE_OUTPUTS__QUOTED += \ +"L1_P1_For.out" \ + +BIN_OUTPUTS += \ +L1_P1_For.hex \ + +BIN_OUTPUTS__QUOTED += \ +"L1_P1_For.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "L1_P1_For.out" + +# Tool invocations +L1_P1_For.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --advice:power=all --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing -z -m"L1_P1_For.map" --heap_size=300 --stack_size=160 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="L1_P1_For_linkInfo.xml" --use_hw_mpy=F5 --rom_model -o "L1_P1_For.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +L1_P1_For.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "L1_P1_For.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "for.lst" + -$(RM) "for.obj" + -$(RM) "for.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/L1_P1_For/Debug/objects.mk b/CPE325/L1_P1_For/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/L1_P1_For/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/L1_P1_For/Debug/sources.mk b/CPE325/L1_P1_For/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/L1_P1_For/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/L1_P1_For/Debug/subdir_rules.mk b/CPE325/L1_P1_For/Debug/subdir_rules.mk new file mode 100644 index 0000000..2c6a2a5 --- /dev/null +++ b/CPE325/L1_P1_For/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/L1_P1_For" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing --preproc_with_compile --preproc_dependency="$(basename $( +#include + +int main(){ + int i, p=0; + int second = 6; + int first = 4; + for(i=0;i -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/L1_P1_For/targetConfigs/MSP430F5529.ccxml b/CPE325/L1_P1_For/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/L1_P1_For/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/L1_P1_For/targetConfigs/readme.txt b/CPE325/L1_P1_For/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/L1_P1_For/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/L1_Problem2/Debug/L1_Problem2.map b/CPE325/L1_Problem2/Debug/L1_Problem2.map new file mode 100644 index 0000000..964c514 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/L1_Problem2.map @@ -0,0 +1,2443 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Aug 27 14:36:09 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00008982 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 000005c0 00001a40 RWIX + FLASH 00004400 0000bb80 000048c0 000072c0 RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00002778 000000fe UNINITIALIZED + 00002778 00000078 rts430_eabi.lib : defs.c.obj (.data:_ftable) + 000027f0 0000004e : host_device.c.obj (.data:_device) + 0000283e 00000028 : host_device.c.obj (.data:_stream) + 00002866 00000002 : exit_gvars.c.obj (.data:__TI_cleanup_ptr) + 00002868 00000002 : exit_gvars.c.obj (.data:__TI_dtors_ptr) + 0000286a 00000002 : _lock.c.obj (.data:_lock) + 0000286c 00000002 : _lock.c.obj (.data:_unlock) + 0000286e 00000002 : defs.c.obj (.data) + 00002870 00000002 : errno.c.obj (.data) + 00002872 00000002 : exit.c.obj (.data) + 00002874 00000002 : memory.c.obj (.data) + +.bss 0 00002876 000000aa UNINITIALIZED + 00002876 000000a0 (.common:__TI_tmpnams) + 00002916 00000008 (.common:parmbuf) + 0000291e 00000002 rts430_eabi.lib : memory.c.obj (.bss) + +.sysmem 0 00002400 00000258 UNINITIALIZED + 00002400 00000008 rts430_eabi.lib : memory.c.obj (.sysmem) + 00002408 00000250 --HOLE-- + +.cio 0 00002658 00000120 UNINITIALIZED + 00002658 00000120 rts430_eabi.lib : trgmsg.c.obj (.cio) + +.stack 0 00004360 000000a0 UNINITIALIZED + 00004360 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 00004362 0000009e --HOLE-- + +.text 0 00004400 00004714 + 00004400 00000736 rts430_eabi.lib : addd.c.obj (.text:__mspabi_addd) + 00004b36 00000478 : frcdivd.c.obj (.text:__TI_frcdivd) + 00004fae 00000360 : div64u.c.obj (.text:__mspabi_divull) + 0000530e 000002c0 : mpyd.c.obj (.text:__mspabi_mpyd) + 000055ce 00000288 : _printfi.c.obj (.text:__TI_printfi) + 00005856 0000026e : _printfi.c.obj (.text:_pproc_fgea) + 00005ac4 00000252 : _printfi.c.obj (.text:_setfield) + 00005d16 00000244 : _printfi.c.obj (.text:acvt) + 00005f5a 00000238 : divd.c.obj (.text:__mspabi_divd) + 00006192 000001ec : _printfi.c.obj (.text:_getarg_diouxp) + 0000637e 000001de : _printfi.c.obj (.text:ecvt) + 0000655c 000001c4 : _printfi.c.obj (.text:fcvt) + 00006720 000001a6 : _printfi.c.obj (.text:_pconv_e) + 000068c6 00000174 : _printfi.c.obj (.text:_pconv_a) + 00006a3a 00000172 : frcmpyd.c.obj (.text:__TI_frcmpyd) + 00006bac 0000016a : s_scalbn.c.obj (.text:scalbn) + 00006d16 0000014c : _printfi.c.obj (.text:_pproc_diouxp) + 00006e62 0000012e : _printfi.c.obj (.text:_ltostr) + 00006f90 000000f8 : _printfi.c.obj (.text:_pconv_g) + 00007088 000000f6 : memory.c.obj (.text:aligned_alloc) + 0000717e 000000ea : fputs.c.obj (.text:fputs) + 00007268 000000e0 : _printfi.c.obj (.text:_pproc_fwp) + 00007348 000000dc : cmpd.c.obj (.text:__mspabi_cmpd) + 00007424 000000d2 : memory.c.obj (.text:free) + 000074f6 000000d0 : setvbuf.c.obj (.text:setvbuf) + 000075c6 000000c4 : _printfi.c.obj (.text:_pproc_wstr) + 0000768a 000000b0 : s_frexp.c.obj (.text:frexp) + 0000773a 000000ac : fltlid.c.obj (.text:__mspabi_fltlid) + 000077e6 000000ac : _printfi.c.obj (.text:_pproc_str) + 00007892 00000092 : _printfi.c.obj (.text:_mcpy) + 00007924 00000090 : fputc.c.obj (.text:fputc) + 000079b4 00000090 problem2.obj (.text:main) + 00007a44 0000008e rts430_eabi.lib : _printfi.c.obj (.text:_ecpy) + 00007ad2 00000088 : hostlseek.c.obj (.text:HOSTlseek) + 00007b5a 00000084 : _ltoa.c.obj (.text:__TI_ltoa) + 00007bde 0000007c : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00007c5a 0000007a : _io_perm.c.obj (.text:__TI_wrt_ok) + 00007cd4 0000007a : _printfi.c.obj (.text:_pconv_f) + 00007d4e 00000072 : fclose.c.obj (.text:__TI_closefile) + 00007dc0 00000072 : fixdli.c.obj (.text:__mspabi_fixdli) + 00007e32 00000070 : fseek.c.obj (.text:fseek) + 00007ea2 0000006a : hostrename.c.obj (.text:HOSTrename) + 00007f0c 00000068 : memory.c.obj (.text:split) + 00007f74 00000066 : hostopen.c.obj (.text:HOSTopen) + 00007fda 00000062 : hostwrite.c.obj (.text:HOSTwrite) + 0000803c 00000062 : fflush.c.obj (.text:__TI_doflush) + 0000809e 00000060 : hostread.c.obj (.text:HOSTread) + 000080fe 0000005e : mult64_f5hw.asm.obj (.text:__mpyll) + 0000815c 0000005c : lsr32.asm.obj (.text:l_lsr_const) + 000081b8 00000058 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 00008210 00000058 : getdevice.c.obj (.text:getdevice) + 00008268 00000058 : div32u.asm.obj (.text) + 000082c0 00000052 : atoi.c.obj (.text:atoi) + 00008312 0000004e : _printfi.c.obj (.text:_fcpy) + 00008360 0000004c : lsr16.asm.obj (.text) + 000083ac 0000004a : asr64.c.obj (.text:__mspabi_srall) + 000083f6 0000004a : close.c.obj (.text:close) + 00008440 00000046 : lsr64.c.obj (.text:__mspabi_srlll) + 00008486 00000044 : hostclose.c.obj (.text:HOSTclose) + 000084ca 00000044 : lsl64.c.obj (.text:__mspabi_sllll) + 0000850e 00000044 : exit.c.obj (.text:exit) + 00008552 00000040 : hostunlink.c.obj (.text:HOSTunlink) + 00008592 00000040 : div32s.asm.obj (.text) + 000085d2 0000003e : asr32.asm.obj (.text:l_asr_const) + 00008610 0000003e : lsl32.asm.obj (.text:l_lsl_const) + 0000864e 0000003c : printf.c.obj (.text:printf) + 0000868a 00000034 : fopen.c.obj (.text:__TI_cleanup) + 000086be 00000034 : getdevice.c.obj (.text:finddevice) + 000086f2 0000002e : trgmsg.c.obj (.text:__TI_writemsg) + 00008720 0000002e : subd.c.obj (.text:__mspabi_subd) + 0000874e 0000002e : s_copysign.c.obj (.text:copysign) + 0000877c 0000002c : trgmsg.c.obj (.text:__TI_readmsg) + 000087a8 0000002c : asr16.asm.obj (.text) + 000087d4 0000002c : lsl16.asm.obj (.text) + 00008800 0000002c : strncpy.c.obj (.text:strncpy) + 0000882c 0000002a : negd.c.obj (.text:__mspabi_negd) + 00008856 00000028 : mult3264_f5hw.asm.obj (.text:__mpyull) + 0000887e 00000028 : fixdi.c.obj (.text:__mspabi_fixdi) + 000088a6 00000028 : memory.c.obj (.text:free_list_insert) + 000088ce 00000028 : unlink.c.obj (.text:unlink) + 000088f6 00000026 : lseek.c.obj (.text:lseek) + 0000891c 00000024 : write.c.obj (.text:write) + 00008940 00000022 : memccpy.c.obj (.text:memccpy) + 00008962 00000020 : mult32_f5hw.asm.obj (.text) + 00008982 0000001c : boot.c.obj (.text:_c_int00_noargs) + 0000899e 0000001c : memory.c.obj (.text:free_list_remove) + 000089ba 0000001a : strchr.c.obj (.text:strchr) + 000089d4 00000018 : strcmp.c.obj (.text:strcmp) + 000089ec 00000016 : div16u.asm.obj (.text) + 00008a02 00000014 : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset:__TI_zero_init_nomemset) + 00008a16 00000014 : memchr.c.obj (.text:memchr) + 00008a2a 00000014 : memset.c.obj (.text:memset) + 00008a3e 00000014 : mult16_f5hw.asm.obj (.text) + 00008a52 00000014 : wcslen.c.obj (.text:wcslen) + 00008a66 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00008a78 00000012 : lsr32.asm.obj (.text:l_lsr) + 00008a8a 00000012 : memcpy.c.obj (.text:memcpy) + 00008a9c 00000010 : epilog.asm.obj (.text) + 00008aac 00000010 : strcpy.c.obj (.text:strcpy) + 00008abc 0000000e : strlen.c.obj (.text:strlen) + 00008aca 0000000c : fltid.c.obj (.text:__mspabi_fltid) + 00008ad6 0000000c : toupper.c.obj (.text:toupper) + 00008ae2 0000000a : abs.c.obj (.text:abs) + 00008aec 00000008 : islower.c.obj (.text:islower) + 00008af4 00000008 : memory.c.obj (.text:malloc) + 00008afc 00000006 : printf.c.obj (.text:_outc) + 00008b02 00000006 : exit.c.obj (.text:abort) + 00008b08 00000004 : printf.c.obj (.text:_outs) + 00008b0c 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00008b10 00000002 : _lock.c.obj (.text:_nop) + 00008b12 00000002 : startup.c.obj (.text:_system_post_cinit) + +.const 0 00008b14 0000014e + 00008b14 00000101 rts430_eabi.lib : ctype.c.obj (.const:.string:_ctypes_) + 00008c15 00000001 --HOLE-- [fill = 0] + 00008c16 00000026 : _printfi.c.obj (.const:.string) + 00008c3c 00000021 problem2.obj (.const:.string:$P$T0$1) + 00008c5d 00000001 --HOLE-- [fill = 0] + 00008c5e 00000004 problem2.obj (.const:.string) + +.text:_isr +* 0 00008c62 00000008 + 00008c62 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00008c6a 00000056 + 00008c6a 00000044 (.cinit..data.load) [load image, compression = lzss] + 00008cae 00000006 (__TI_handler_table) + 00008cb4 00000004 (.cinit..bss.load) [load image, compression = zero_init] + 00008cb8 00000008 (__TI_cinit_table) + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + problem2.obj 144 37 0 + +--+----------------------------+-------+---------+---------+ + Total: 144 37 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + _printfi.c.obj 6622 38 0 + addd.c.obj 1846 0 0 + frcdivd.c.obj 1144 0 0 + div64u.c.obj 864 0 0 + mpyd.c.obj 704 0 0 + memory.c.obj 636 0 4 + divd.c.obj 568 0 0 + trgmsg.c.obj 90 0 288 + frcmpyd.c.obj 370 0 0 + s_scalbn.c.obj 362 0 0 + defs.c.obj 0 0 282 + ctype.c.obj 0 257 0 + fputs.c.obj 234 0 0 + cmpd.c.obj 220 0 0 + setvbuf.c.obj 208 0 0 + s_frexp.c.obj 176 0 0 + fltlid.c.obj 172 0 0 + fputc.c.obj 144 0 0 + getdevice.c.obj 140 0 0 + hostlseek.c.obj 136 0 0 + _ltoa.c.obj 132 0 0 + copy_decompress_lzss.c.obj 124 0 0 + _io_perm.c.obj 122 0 0 + host_device.c.obj 0 0 118 + fclose.c.obj 114 0 0 + fixdli.c.obj 114 0 0 + fseek.c.obj 112 0 0 + hostopen.c.obj 102 0 8 + lsr32.asm.obj 110 0 0 + hostrename.c.obj 106 0 0 + fflush.c.obj 98 0 0 + hostwrite.c.obj 98 0 0 + hostread.c.obj 96 0 0 + mult64_f5hw.asm.obj 94 0 0 + autoinit.c.obj 88 0 0 + div32u.asm.obj 88 0 0 + atoi.c.obj 82 0 0 + exit.c.obj 74 0 2 + lsr16.asm.obj 76 0 0 + asr64.c.obj 74 0 0 + close.c.obj 74 0 0 + lsr64.c.obj 70 0 0 + printf.c.obj 70 0 0 + hostclose.c.obj 68 0 0 + lsl64.c.obj 68 0 0 + div32s.asm.obj 64 0 0 + hostunlink.c.obj 64 0 0 + asr32.asm.obj 62 0 0 + lsl32.asm.obj 62 0 0 + fopen.c.obj 52 0 0 + s_copysign.c.obj 46 0 0 + subd.c.obj 46 0 0 + asr16.asm.obj 44 0 0 + lsl16.asm.obj 44 0 0 + strncpy.c.obj 44 0 0 + negd.c.obj 42 0 0 + fixdi.c.obj 40 0 0 + mult3264_f5hw.asm.obj 40 0 0 + unlink.c.obj 40 0 0 + lseek.c.obj 38 0 0 + write.c.obj 36 0 0 + memccpy.c.obj 34 0 0 + mult32_f5hw.asm.obj 32 0 0 + boot.c.obj 28 2 0 + strchr.c.obj 26 0 0 + strcmp.c.obj 24 0 0 + div16u.asm.obj 22 0 0 + copy_zero_init.c.obj 20 0 0 + memchr.c.obj 20 0 0 + memset.c.obj 20 0 0 + mult16_f5hw.asm.obj 20 0 0 + wcslen.c.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + memcpy.c.obj 18 0 0 + epilog.asm.obj 16 0 0 + strcpy.c.obj 16 0 0 + strlen.c.obj 14 0 0 + fltid.c.obj 12 0 0 + toupper.c.obj 12 0 0 + abs.c.obj 10 0 0 + islower.c.obj 8 0 0 + isr_trap.asm.obj 8 0 0 + _lock.c.obj 2 0 4 + exit_gvars.c.obj 0 0 4 + pre_init.c.obj 4 0 0 + errno.c.obj 0 0 2 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 18060 341 712 + + Heap: 0 0 600 + Stack: 0 0 160 + Linker Generated: 0 86 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 18204 464 1472 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00008cb8 records: 2, size/record: 4, table size: 8 + .data: load addr=00008c6a, load size=00000044 bytes, run addr=00002778, run size=000000fe bytes, compression=lzss + .bss: load addr=00008cb4, load size=00000004 bytes, run addr=00002876, run size=000000aa bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 00008cae records: 3, size/record: 2, table size: 6 + index: 0, handler: __TI_zero_init + index: 1, handler: __TI_decompress_lzss + index: 2, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +00008b02 C$$EXIT +0000871c C$$IO$$ +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +00008486 HOSTclose +00007ad2 HOSTlseek +00007f74 HOSTopen +0000809e HOSTread +00007ea2 HOSTrename +00008552 HOSTunlink +00007fda HOSTwrite +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L 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_stack +0000283e _stream +00002400 _sys_memory +00008b12 _system_post_cinit +00008b0c _system_pre_init +0000286c _unlock +00008b02 abort +00008ae2 abs +00007088 aligned_alloc +000082c0 atoi +000083f6 close +0000874e copysign +0000874e copysignl +00002870 errno +0000850e exit +000086be finddevice +00007924 fputc +0000717e fputs +00007424 free +0000768a frexp +0000768a frexpl +00007e32 fseek +00008210 getdevice +00008aec islower +00006bac ldexp +00006bac ldexpl +000088f6 lseek +000079b4 main +00008af4 malloc +00007088 memalign +00008940 memccpy +00008a16 memchr +00008a8a memcpy +00008a2a memset +00002916 parmbuf +0000864e printf +00007924 putc +000088ce remove +00006bac scalbn +00006bac scalbnl +000074f6 setvbuf +000089ba strchr +000089d4 strcmp +00008aac strcpy +00008abc strlen +00008800 strncpy +00008ad6 toupper +000088ce unlink +00008a52 wcslen +0000891c write + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +000000a0 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000258 __SYSMEM_SIZE +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H +00000726 ADC12MEM3 +00000726 ADC12MEM3_L +00000727 ADC12MEM3_H +00000728 ADC12MEM4 +00000728 ADC12MEM4_L +00000729 ADC12MEM4_H +0000072a ADC12MEM5 +0000072a ADC12MEM5_L +0000072b ADC12MEM5_H +0000072c ADC12MEM6 +0000072c ADC12MEM6_L +0000072d ADC12MEM6_H +0000072e ADC12MEM7 +0000072e ADC12MEM7_L +0000072f ADC12MEM7_H +00000730 ADC12MEM8 +00000730 ADC12MEM8_L +00000731 ADC12MEM8_H +00000732 ADC12MEM9 +00000732 ADC12MEM9_L +00000733 ADC12MEM9_H +00000734 ADC12MEM10 +00000734 ADC12MEM10_L +00000735 ADC12MEM10_H +00000736 ADC12MEM11 +00000736 ADC12MEM11_L +00000737 ADC12MEM11_H +00000738 ADC12MEM12 +00000738 ADC12MEM12_L +00000739 ADC12MEM12_H +0000073a ADC12MEM13 +0000073a ADC12MEM13_L +0000073b ADC12MEM13_H +0000073c ADC12MEM14 +0000073c ADC12MEM14_L +0000073d ADC12MEM14_H +0000073e ADC12MEM15 +0000073e ADC12MEM15_L +0000073f ADC12MEM15_H +000008c0 CBCTL0 +000008c0 CBCTL0_L +000008c1 CBCTL0_H +000008c2 CBCTL1 +000008c2 CBCTL1_L +000008c3 CBCTL1_H +000008c4 CBCTL2 +000008c4 CBCTL2_L +000008c5 CBCTL2_H +000008c6 CBCTL3 +000008c6 CBCTL3_L +000008c7 CBCTL3_H +000008cc CBINT +000008cc CBINT_L +000008cd CBINT_H +000008ce CBIV +00000900 USBKEYID +00000900 USBKEYID_L +00000901 USBKEYID_H +00000902 USBCNF +00000902 USBCNF_L +00000903 USBCNF_H +00000904 USBPHYCTL +00000904 USBPHYCTL_L +00000905 USBPHYCTL_H +00000908 USBPWRCTL +00000908 USBPWRCTL_L +00000909 USBPWRCTL_H +00000910 USBPLLCTL +00000910 USBPLLCTL_L +00000911 USBPLLCTL_H +00000912 USBPLLDIVB +00000912 USBPLLDIVB_L +00000913 USBPLLDIVB_H +00000914 USBPLLIR +00000914 USBPLLIR_L +00000915 USBPLLIR_H +00000920 USBIEPCNF_0 +00000921 USBIEPCNT_0 +00000922 USBOEPCNF_0 +00000923 USBOEPCNT_0 +0000092e USBIEPIE +0000092f USBOEPIE +00000930 USBIEPIFG +00000931 USBOEPIFG +00000932 USBVECINT +00000932 USBVECINT_L +00000933 USBVECINT_H +00000936 USBMAINT +00000936 USBMAINT_L +00000937 USBMAINT_H +00000938 USBTSREG +00000938 USBTSREG_L +00000939 USBTSREG_H +0000093a USBFN +0000093a USBFN_L +0000093b USBFN_H +0000093c USBCTL +0000093d USBIE +0000093e USBIFG +0000093f USBFUNADR +00001c00 USBSTABUFF +0000236f USBTOPBUFF +00002370 USBOEP0BUF +00002378 USBIEP0BUF +00002380 USBSUBLK +00002388 USBOEPCNF_1 +00002389 USBOEPBBAX_1 +0000238a USBOEPBCTX_1 +0000238d USBOEPBBAY_1 +0000238e USBOEPBCTY_1 +0000238f USBOEPSIZXY_1 +00002390 USBOEPCNF_2 +00002391 USBOEPBBAX_2 +00002392 USBOEPBCTX_2 +00002395 USBOEPBBAY_2 +00002396 USBOEPBCTY_2 +00002397 USBOEPSIZXY_2 +00002398 USBOEPCNF_3 +00002399 USBOEPBBAX_3 +0000239a USBOEPBCTX_3 +0000239d USBOEPBBAY_3 +0000239e USBOEPBCTY_3 +0000239f USBOEPSIZXY_3 +000023a0 USBOEPCNF_4 +000023a1 USBOEPBBAX_4 +000023a2 USBOEPBCTX_4 +000023a5 USBOEPBBAY_4 +000023a6 USBOEPBCTY_4 +000023a7 USBOEPSIZXY_4 +000023a8 USBOEPCNF_5 +000023a9 USBOEPBBAX_5 +000023aa USBOEPBCTX_5 +000023ad USBOEPBBAY_5 +000023ae USBOEPBCTY_5 +000023af USBOEPSIZXY_5 +000023b0 USBOEPCNF_6 +000023b1 USBOEPBBAX_6 +000023b2 USBOEPBCTX_6 +000023b5 USBOEPBBAY_6 +000023b6 USBOEPBCTY_6 +000023b7 USBOEPSIZXY_6 +000023b8 USBOEPCNF_7 +000023b9 USBOEPBBAX_7 +000023ba USBOEPBCTX_7 +000023bd USBOEPBBAY_7 +000023be USBOEPBCTY_7 +000023bf USBOEPSIZXY_7 +000023c8 USBIEPCNF_1 +000023c9 USBIEPBBAX_1 +000023ca USBIEPBCTX_1 +000023cd USBIEPBBAY_1 +000023ce USBIEPBCTY_1 +000023cf USBIEPSIZXY_1 +000023d0 USBIEPCNF_2 +000023d1 USBIEPBBAX_2 +000023d2 USBIEPBCTX_2 +000023d5 USBIEPBBAY_2 +000023d6 USBIEPBCTY_2 +000023d7 USBIEPSIZXY_2 +000023d8 USBIEPCNF_3 +000023d9 USBIEPBBAX_3 +000023da USBIEPBCTX_3 +000023dd USBIEPBBAY_3 +000023de USBIEPBCTY_3 +000023df USBIEPSIZXY_3 +000023e0 USBIEPCNF_4 +000023e1 USBIEPBBAX_4 +000023e2 USBIEPBCTX_4 +000023e5 USBIEPBBAY_4 +000023e6 USBIEPBCTY_4 +000023e7 USBIEPSIZXY_4 +000023e8 USBIEPCNF_5 +000023e9 USBIEPBBAX_5 +000023ea USBIEPBCTX_5 +000023ed USBIEPBBAY_5 +000023ee USBIEPBCTY_5 +000023ef USBIEPSIZXY_5 +000023f0 USBIEPCNF_6 +000023f1 USBIEPBBAX_6 +000023f2 USBIEPBCTX_6 +000023f5 USBIEPBBAY_6 +000023f6 USBIEPBCTY_6 +000023f7 USBIEPSIZXY_6 +000023f8 USBIEPCNF_7 +000023f9 USBIEPBBAX_7 +000023fa USBIEPBCTX_7 +000023fd USBIEPBBAY_7 +000023fe USBIEPBCTY_7 +000023ff USBIEPSIZXY_7 +00002400 _sys_memory +00002658 _CIOBUF_ +00002778 _ftable +000027f0 _device +0000283e _stream +00002866 __TI_cleanup_ptr +00002868 __TI_dtors_ptr +0000286a _lock +0000286c _unlock +0000286e __TI_ft_end +00002870 errno +00002872 __TI_enable_exit_profile_output +00002876 __TI_tmpnams +00002916 parmbuf +00004360 _stack +00004400 __STACK_END +00004400 __mspabi_addd +00004b36 __TI_frcdivd +00004fae __mspabi_divull +0000530e __mspabi_mpyd +000055ce __TI_printfi +00005f5a __mspabi_divd +00006a3a __TI_frcmpyd +00006bac ldexp +00006bac ldexpl +00006bac scalbn +00006bac scalbnl +00007088 aligned_alloc +00007088 memalign +0000717e fputs +00007348 __mspabi_cmpd +00007424 free +000074f6 setvbuf +0000768a frexp +0000768a frexpl +0000773a __mspabi_fltlid +00007924 fputc +00007924 putc +000079b4 main +00007ad2 HOSTlseek +00007b5a __TI_ltoa +00007bde __TI_decompress_lzss +00007c5a __TI_wrt_ok +00007d4e __TI_closefile +00007dc0 __mspabi_fixdli +00007e32 fseek +00007ea2 HOSTrename +00007f74 HOSTopen +00007fda HOSTwrite +0000803c __TI_doflush +0000809e HOSTread +000080fe __mspabi_mpyll_f5hw +0000815c __mspabi_srll_15 +00008162 __mspabi_srll_14 +00008168 __mspabi_srll_13 +0000816e __mspabi_srll_12 +00008174 __mspabi_srll_11 +0000817a __mspabi_srll_10 +00008180 __mspabi_srll_9 +00008186 __mspabi_srll_8 +0000818c __mspabi_srll_7 +00008192 __mspabi_srll_6 +00008198 __mspabi_srll_5 +0000819e __mspabi_srll_4 +000081a4 __mspabi_srll_3 +000081aa __mspabi_srll_2 +000081b0 __mspabi_srll_1 +000081b8 __TI_auto_init_nobinit_nopinit_hold_wdt +00008210 getdevice +00008268 __mspabi_divul +00008268 __mspabi_remul +000082c0 atoi +00008360 __mspabi_srli +0000836e __mspabi_srli_15 +00008372 __mspabi_srli_14 +00008376 __mspabi_srli_13 +0000837a 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+ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[975 symbols] diff --git a/CPE325/L1_Problem2/Debug/L1_Problem2.out b/CPE325/L1_Problem2/Debug/L1_Problem2.out new file mode 100644 index 0000000..2bfa7ff Binary files /dev/null and b/CPE325/L1_Problem2/Debug/L1_Problem2.out differ diff --git a/CPE325/L1_Problem2/Debug/L1_Problem2_linkInfo.xml b/CPE325/L1_Problem2/Debug/L1_Problem2_linkInfo.xml new file mode 100644 index 0000000..04e1b19 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/L1_Problem2_linkInfo.xml @@ -0,0 +1,16493 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x61293ea9 + 0x0 + L1_Problem2.out + + _c_int00_noargs +
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_sys_memory + 0x2400 + + + + free + 0x7424 + + + + memalign + 0x7088 + + + + malloc + 0x8af4 + + + + aligned_alloc + 0x7088 + + + + memset + 0x8a2a + + + + strchr + 0x89ba + + + + strlen + 0x8abc + + + + toupper + 0x8ad6 + + + + write + 0x891c + + + + _stream + 0x283e + + + + _device + 0x27f0 + + + + abs + 0x8ae2 + + + + errno + 0x2870 + + + + __TI_doflush + 0x803c + + + + __TI_cleanup + 0x868a + + + + fseek + 0x7e32 + + + + copysign + 0x874e + + + + copysignl + 0x874e + + + + __mspabi_sral_15 + 0x85d2 + + + + __mspabi_sral_14 + 0x85d6 + + + + __mspabi_sral_13 + 0x85da + + + + __mspabi_sral_12 + 0x85de + + + + __mspabi_sral_11 + 0x85e2 + + + + __mspabi_sral_10 + 0x85e6 + + + + __mspabi_sral_8 + 0x85ee + + + + __mspabi_sral_9 + 0x85ea + + + + __mspabi_sral_6 + 0x85f6 + + + + __mspabi_sral_7 + 0x85f2 + + + + __mspabi_sral_4 + 0x85fe + + + + __mspabi_sral_5 + 0x85fa + + + + __mspabi_sral_2 + 0x8606 + + + + __mspabi_sral_3 + 0x8602 + + + + __mspabi_sral_1 + 0x860a + + + + __mspabi_remli + 0x8592 + + + + __mspabi_divli + 0x8592 + + + + __mspabi_slll_9 + 0x8628 + + + + __mspabi_slll_8 + 0x862c + + + + __mspabi_slll_7 + 0x8630 + + + + __mspabi_slll_6 + 0x8634 + + + + __mspabi_slll_5 + 0x8638 + + + + __mspabi_slll_4 + 0x863c + + + + __mspabi_slll_3 + 0x8640 + + + + __mspabi_slll_2 + 0x8644 + + + + __mspabi_slll_1 + 0x8648 + + + + __mspabi_slll_15 + 0x8610 + + + + __mspabi_slll_14 + 0x8614 + + + + __mspabi_slll_13 + 0x8618 + + + + __mspabi_slll_12 + 0x861c + + + + __mspabi_slll_11 + 0x8620 + + + + __mspabi_slll_10 + 0x8624 + + + + __mspabi_srll_8 + 0x8186 + + + + __mspabi_srll_9 + 0x8180 + + + + __mspabi_srll_6 + 0x8192 + + + + __mspabi_srll_7 + 0x818c + + + + __mspabi_srll_4 + 0x819e + + + + __mspabi_srll_5 + 0x8198 + + + + __mspabi_srll_2 + 0x81aa + + + + __mspabi_srll_3 + 0x81a4 + + + + __mspabi_srll_1 + 0x81b0 + + + + __mspabi_srll_15 + 0x815c + + + + __mspabi_srll_14 + 0x8162 + + + + __mspabi_srll_13 + 0x8168 + + + + __mspabi_srll_12 + 0x816e + + + + __mspabi_srll_11 + 0x8174 + + + + __mspabi_srll_10 + 0x817a + + + + __mspabi_srll + 0x8a78 + + + + __mspabi_srall + 0x83ac + + + + __mspabi_sllll + 0x84ca + + + + __TI_frcmpyd + 0x6a3a + + + + HOSTclose + 0x8486 + + + + HOSTlseek + 0x7ad2 + + + + parmbuf + 0x2916 + + + HOSTopen + 0x7f74 + + + + HOSTread + 0x809e + + + + HOSTrename + 0x7ea2 + + + + HOSTunlink + 0x8552 + + + + HOSTwrite + 0x7fda + + + + __TI_readmsg + 0x877c + + + + C$$IO$$ + 0x871c + + + + _CIOBUF_ + 0x2658 + + + + __TI_writemsg + 0x86f2 + + + + lseek + 0x88f6 + + + + __TI_closefile + 0x7d4e + + + + finddevice + 0x86be + + + + getdevice + 0x8210 + + + + strcmp + 0x89d4 + + + + strcpy + 0x8aac + + + + strncpy + 0x8800 + + + + close + 0x83f6 + + + + unlink + 0x88ce + + + + remove + 0x88ce + + + Link successful + diff --git a/CPE325/L1_Problem2/Debug/L2_Problem2.map b/CPE325/L1_Problem2/Debug/L2_Problem2.map new file mode 100644 index 0000000..a50a57e --- /dev/null +++ b/CPE325/L1_Problem2/Debug/L2_Problem2.map @@ -0,0 +1,2443 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Aug 27 13:49:19 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00008982 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 000005c0 00001a40 RWIX + FLASH 00004400 0000bb80 000048c0 000072c0 RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00002778 000000fe UNINITIALIZED + 00002778 00000078 rts430_eabi.lib : defs.c.obj (.data:_ftable) + 000027f0 0000004e : host_device.c.obj (.data:_device) + 0000283e 00000028 : host_device.c.obj (.data:_stream) + 00002866 00000002 : exit_gvars.c.obj (.data:__TI_cleanup_ptr) + 00002868 00000002 : exit_gvars.c.obj (.data:__TI_dtors_ptr) + 0000286a 00000002 : _lock.c.obj (.data:_lock) + 0000286c 00000002 : _lock.c.obj (.data:_unlock) + 0000286e 00000002 : defs.c.obj (.data) + 00002870 00000002 : errno.c.obj (.data) + 00002872 00000002 : exit.c.obj (.data) + 00002874 00000002 : memory.c.obj (.data) + +.bss 0 00002876 000000aa UNINITIALIZED + 00002876 000000a0 (.common:__TI_tmpnams) + 00002916 00000008 (.common:parmbuf) + 0000291e 00000002 rts430_eabi.lib : memory.c.obj (.bss) + +.sysmem 0 00002400 00000258 UNINITIALIZED + 00002400 00000008 rts430_eabi.lib : memory.c.obj (.sysmem) + 00002408 00000250 --HOLE-- + +.cio 0 00002658 00000120 UNINITIALIZED + 00002658 00000120 rts430_eabi.lib : trgmsg.c.obj (.cio) + +.stack 0 00004360 000000a0 UNINITIALIZED + 00004360 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 00004362 0000009e --HOLE-- + +.text 0 00004400 00004714 + 00004400 00000736 rts430_eabi.lib : addd.c.obj (.text:__mspabi_addd) + 00004b36 00000478 : frcdivd.c.obj (.text:__TI_frcdivd) + 00004fae 00000360 : div64u.c.obj (.text:__mspabi_divull) + 0000530e 000002c0 : mpyd.c.obj (.text:__mspabi_mpyd) + 000055ce 00000288 : _printfi.c.obj (.text:__TI_printfi) + 00005856 0000026e : _printfi.c.obj (.text:_pproc_fgea) + 00005ac4 00000252 : _printfi.c.obj (.text:_setfield) + 00005d16 00000244 : _printfi.c.obj (.text:acvt) + 00005f5a 00000238 : divd.c.obj (.text:__mspabi_divd) + 00006192 000001ec : _printfi.c.obj (.text:_getarg_diouxp) + 0000637e 000001de : _printfi.c.obj (.text:ecvt) + 0000655c 000001c4 : _printfi.c.obj (.text:fcvt) + 00006720 000001a6 : _printfi.c.obj (.text:_pconv_e) + 000068c6 00000174 : _printfi.c.obj (.text:_pconv_a) + 00006a3a 00000172 : frcmpyd.c.obj (.text:__TI_frcmpyd) + 00006bac 0000016a : s_scalbn.c.obj (.text:scalbn) + 00006d16 0000014c : _printfi.c.obj (.text:_pproc_diouxp) + 00006e62 0000012e : _printfi.c.obj (.text:_ltostr) + 00006f90 000000f8 : _printfi.c.obj (.text:_pconv_g) + 00007088 000000f6 : memory.c.obj (.text:aligned_alloc) + 0000717e 000000ea : fputs.c.obj (.text:fputs) + 00007268 000000e0 : _printfi.c.obj (.text:_pproc_fwp) + 00007348 000000dc : cmpd.c.obj (.text:__mspabi_cmpd) + 00007424 000000d2 : memory.c.obj (.text:free) + 000074f6 000000d0 : setvbuf.c.obj (.text:setvbuf) + 000075c6 000000c4 : _printfi.c.obj (.text:_pproc_wstr) + 0000768a 000000b0 : s_frexp.c.obj (.text:frexp) + 0000773a 000000ac : fltlid.c.obj (.text:__mspabi_fltlid) + 000077e6 000000ac : _printfi.c.obj (.text:_pproc_str) + 00007892 00000092 : _printfi.c.obj (.text:_mcpy) + 00007924 00000090 : fputc.c.obj (.text:fputc) + 000079b4 00000090 problem2.obj (.text:main) + 00007a44 0000008e rts430_eabi.lib : _printfi.c.obj (.text:_ecpy) + 00007ad2 00000088 : hostlseek.c.obj (.text:HOSTlseek) + 00007b5a 00000084 : _ltoa.c.obj (.text:__TI_ltoa) + 00007bde 0000007c : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00007c5a 0000007a : _io_perm.c.obj (.text:__TI_wrt_ok) + 00007cd4 0000007a : _printfi.c.obj (.text:_pconv_f) + 00007d4e 00000072 : fclose.c.obj (.text:__TI_closefile) + 00007dc0 00000072 : fixdli.c.obj (.text:__mspabi_fixdli) + 00007e32 00000070 : fseek.c.obj (.text:fseek) + 00007ea2 0000006a : hostrename.c.obj (.text:HOSTrename) + 00007f0c 00000068 : memory.c.obj (.text:split) + 00007f74 00000066 : hostopen.c.obj (.text:HOSTopen) + 00007fda 00000062 : hostwrite.c.obj (.text:HOSTwrite) + 0000803c 00000062 : fflush.c.obj (.text:__TI_doflush) + 0000809e 00000060 : hostread.c.obj (.text:HOSTread) + 000080fe 0000005e : mult64_f5hw.asm.obj (.text:__mpyll) + 0000815c 0000005c : lsr32.asm.obj (.text:l_lsr_const) + 000081b8 00000058 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 00008210 00000058 : getdevice.c.obj (.text:getdevice) + 00008268 00000058 : div32u.asm.obj (.text) + 000082c0 00000052 : atoi.c.obj (.text:atoi) + 00008312 0000004e : _printfi.c.obj (.text:_fcpy) + 00008360 0000004c : lsr16.asm.obj (.text) + 000083ac 0000004a : asr64.c.obj (.text:__mspabi_srall) + 000083f6 0000004a : close.c.obj (.text:close) + 00008440 00000046 : lsr64.c.obj (.text:__mspabi_srlll) + 00008486 00000044 : hostclose.c.obj (.text:HOSTclose) + 000084ca 00000044 : lsl64.c.obj (.text:__mspabi_sllll) + 0000850e 00000044 : exit.c.obj (.text:exit) + 00008552 00000040 : hostunlink.c.obj (.text:HOSTunlink) + 00008592 00000040 : div32s.asm.obj (.text) + 000085d2 0000003e : asr32.asm.obj (.text:l_asr_const) + 00008610 0000003e : lsl32.asm.obj (.text:l_lsl_const) + 0000864e 0000003c : printf.c.obj (.text:printf) + 0000868a 00000034 : fopen.c.obj (.text:__TI_cleanup) + 000086be 00000034 : getdevice.c.obj (.text:finddevice) + 000086f2 0000002e : trgmsg.c.obj (.text:__TI_writemsg) + 00008720 0000002e : subd.c.obj (.text:__mspabi_subd) + 0000874e 0000002e : s_copysign.c.obj (.text:copysign) + 0000877c 0000002c : trgmsg.c.obj (.text:__TI_readmsg) + 000087a8 0000002c : asr16.asm.obj (.text) + 000087d4 0000002c : lsl16.asm.obj (.text) + 00008800 0000002c : strncpy.c.obj (.text:strncpy) + 0000882c 0000002a : negd.c.obj (.text:__mspabi_negd) + 00008856 00000028 : mult3264_f5hw.asm.obj (.text:__mpyull) + 0000887e 00000028 : fixdi.c.obj (.text:__mspabi_fixdi) + 000088a6 00000028 : memory.c.obj (.text:free_list_insert) + 000088ce 00000028 : unlink.c.obj (.text:unlink) + 000088f6 00000026 : lseek.c.obj (.text:lseek) + 0000891c 00000024 : write.c.obj (.text:write) + 00008940 00000022 : memccpy.c.obj (.text:memccpy) + 00008962 00000020 : mult32_f5hw.asm.obj (.text) + 00008982 0000001c : boot.c.obj (.text:_c_int00_noargs) + 0000899e 0000001c : memory.c.obj (.text:free_list_remove) + 000089ba 0000001a : strchr.c.obj (.text:strchr) + 000089d4 00000018 : strcmp.c.obj (.text:strcmp) + 000089ec 00000016 : div16u.asm.obj (.text) + 00008a02 00000014 : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset:__TI_zero_init_nomemset) + 00008a16 00000014 : memchr.c.obj (.text:memchr) + 00008a2a 00000014 : memset.c.obj (.text:memset) + 00008a3e 00000014 : mult16_f5hw.asm.obj (.text) + 00008a52 00000014 : wcslen.c.obj (.text:wcslen) + 00008a66 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00008a78 00000012 : lsr32.asm.obj (.text:l_lsr) + 00008a8a 00000012 : memcpy.c.obj (.text:memcpy) + 00008a9c 00000010 : epilog.asm.obj (.text) + 00008aac 00000010 : strcpy.c.obj (.text:strcpy) + 00008abc 0000000e : strlen.c.obj (.text:strlen) + 00008aca 0000000c : fltid.c.obj (.text:__mspabi_fltid) + 00008ad6 0000000c : toupper.c.obj (.text:toupper) + 00008ae2 0000000a : abs.c.obj (.text:abs) + 00008aec 00000008 : islower.c.obj (.text:islower) + 00008af4 00000008 : memory.c.obj (.text:malloc) + 00008afc 00000006 : printf.c.obj (.text:_outc) + 00008b02 00000006 : exit.c.obj (.text:abort) + 00008b08 00000004 : printf.c.obj (.text:_outs) + 00008b0c 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00008b10 00000002 : _lock.c.obj (.text:_nop) + 00008b12 00000002 : startup.c.obj (.text:_system_post_cinit) + +.const 0 00008b14 0000014e + 00008b14 00000101 rts430_eabi.lib : ctype.c.obj (.const:.string:_ctypes_) + 00008c15 00000001 --HOLE-- [fill = 0] + 00008c16 00000026 : _printfi.c.obj (.const:.string) + 00008c3c 00000021 problem2.obj (.const:.string:$P$T0$1) + 00008c5d 00000001 --HOLE-- [fill = 0] + 00008c5e 00000004 problem2.obj (.const:.string) + +.text:_isr +* 0 00008c62 00000008 + 00008c62 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00008c6a 00000056 + 00008c6a 00000044 (.cinit..data.load) [load image, compression = lzss] + 00008cae 00000006 (__TI_handler_table) + 00008cb4 00000004 (.cinit..bss.load) [load image, compression = zero_init] + 00008cb8 00000008 (__TI_cinit_table) + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + problem2.obj 144 37 0 + +--+----------------------------+-------+---------+---------+ + Total: 144 37 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + _printfi.c.obj 6622 38 0 + addd.c.obj 1846 0 0 + frcdivd.c.obj 1144 0 0 + div64u.c.obj 864 0 0 + mpyd.c.obj 704 0 0 + memory.c.obj 636 0 4 + divd.c.obj 568 0 0 + trgmsg.c.obj 90 0 288 + frcmpyd.c.obj 370 0 0 + s_scalbn.c.obj 362 0 0 + defs.c.obj 0 0 282 + ctype.c.obj 0 257 0 + fputs.c.obj 234 0 0 + cmpd.c.obj 220 0 0 + setvbuf.c.obj 208 0 0 + s_frexp.c.obj 176 0 0 + fltlid.c.obj 172 0 0 + fputc.c.obj 144 0 0 + getdevice.c.obj 140 0 0 + hostlseek.c.obj 136 0 0 + _ltoa.c.obj 132 0 0 + copy_decompress_lzss.c.obj 124 0 0 + _io_perm.c.obj 122 0 0 + host_device.c.obj 0 0 118 + fclose.c.obj 114 0 0 + fixdli.c.obj 114 0 0 + fseek.c.obj 112 0 0 + hostopen.c.obj 102 0 8 + lsr32.asm.obj 110 0 0 + hostrename.c.obj 106 0 0 + fflush.c.obj 98 0 0 + hostwrite.c.obj 98 0 0 + hostread.c.obj 96 0 0 + mult64_f5hw.asm.obj 94 0 0 + autoinit.c.obj 88 0 0 + div32u.asm.obj 88 0 0 + atoi.c.obj 82 0 0 + exit.c.obj 74 0 2 + lsr16.asm.obj 76 0 0 + asr64.c.obj 74 0 0 + close.c.obj 74 0 0 + lsr64.c.obj 70 0 0 + printf.c.obj 70 0 0 + hostclose.c.obj 68 0 0 + lsl64.c.obj 68 0 0 + div32s.asm.obj 64 0 0 + hostunlink.c.obj 64 0 0 + asr32.asm.obj 62 0 0 + lsl32.asm.obj 62 0 0 + fopen.c.obj 52 0 0 + s_copysign.c.obj 46 0 0 + subd.c.obj 46 0 0 + asr16.asm.obj 44 0 0 + lsl16.asm.obj 44 0 0 + strncpy.c.obj 44 0 0 + negd.c.obj 42 0 0 + fixdi.c.obj 40 0 0 + mult3264_f5hw.asm.obj 40 0 0 + unlink.c.obj 40 0 0 + lseek.c.obj 38 0 0 + write.c.obj 36 0 0 + memccpy.c.obj 34 0 0 + mult32_f5hw.asm.obj 32 0 0 + boot.c.obj 28 2 0 + strchr.c.obj 26 0 0 + strcmp.c.obj 24 0 0 + div16u.asm.obj 22 0 0 + copy_zero_init.c.obj 20 0 0 + memchr.c.obj 20 0 0 + memset.c.obj 20 0 0 + mult16_f5hw.asm.obj 20 0 0 + wcslen.c.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + memcpy.c.obj 18 0 0 + epilog.asm.obj 16 0 0 + strcpy.c.obj 16 0 0 + strlen.c.obj 14 0 0 + fltid.c.obj 12 0 0 + toupper.c.obj 12 0 0 + abs.c.obj 10 0 0 + islower.c.obj 8 0 0 + isr_trap.asm.obj 8 0 0 + _lock.c.obj 2 0 4 + exit_gvars.c.obj 0 0 4 + pre_init.c.obj 4 0 0 + errno.c.obj 0 0 2 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 18060 341 712 + + Heap: 0 0 600 + Stack: 0 0 160 + Linker Generated: 0 86 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 18204 464 1472 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00008cb8 records: 2, size/record: 4, table size: 8 + .data: load addr=00008c6a, load size=00000044 bytes, run addr=00002778, run size=000000fe bytes, compression=lzss + .bss: load addr=00008cb4, load size=00000004 bytes, run addr=00002876, run size=000000aa bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 00008cae records: 3, size/record: 2, table size: 6 + index: 0, handler: __TI_zero_init + index: 1, handler: __TI_decompress_lzss + index: 2, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +00008b02 C$$EXIT +0000871c C$$IO$$ +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +00008486 HOSTclose +00007ad2 HOSTlseek +00007f74 HOSTopen +0000809e HOSTread +00007ea2 HOSTrename +00008552 HOSTunlink +00007fda HOSTwrite +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H 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USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +00002658 _CIOBUF_ +00004400 __STACK_END +000000a0 __STACK_SIZE +00000258 __SYSMEM_SIZE +00008cb8 __TI_CINIT_Base +00008cc0 __TI_CINIT_Limit +00008cae __TI_Handler_Table_Base +00008cb4 __TI_Handler_Table_Limit +00008c62 __TI_ISR_TRAP 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SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000258 __SYSMEM_SIZE +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H +00000726 ADC12MEM3 +00000726 ADC12MEM3_L +00000727 ADC12MEM3_H +00000728 ADC12MEM4 +00000728 ADC12MEM4_L +00000729 ADC12MEM4_H +0000072a ADC12MEM5 +0000072a ADC12MEM5_L +0000072b ADC12MEM5_H +0000072c ADC12MEM6 +0000072c ADC12MEM6_L +0000072d ADC12MEM6_H +0000072e ADC12MEM7 +0000072e ADC12MEM7_L +0000072f ADC12MEM7_H +00000730 ADC12MEM8 +00000730 ADC12MEM8_L +00000731 ADC12MEM8_H +00000732 ADC12MEM9 +00000732 ADC12MEM9_L +00000733 ADC12MEM9_H +00000734 ADC12MEM10 +00000734 ADC12MEM10_L +00000735 ADC12MEM10_H +00000736 ADC12MEM11 +00000736 ADC12MEM11_L +00000737 ADC12MEM11_H +00000738 ADC12MEM12 +00000738 ADC12MEM12_L +00000739 ADC12MEM12_H +0000073a ADC12MEM13 +0000073a ADC12MEM13_L +0000073b ADC12MEM13_H +0000073c ADC12MEM14 +0000073c ADC12MEM14_L +0000073d ADC12MEM14_H +0000073e ADC12MEM15 +0000073e ADC12MEM15_L +0000073f ADC12MEM15_H +000008c0 CBCTL0 +000008c0 CBCTL0_L +000008c1 CBCTL0_H +000008c2 CBCTL1 +000008c2 CBCTL1_L +000008c3 CBCTL1_H +000008c4 CBCTL2 +000008c4 CBCTL2_L +000008c5 CBCTL2_H +000008c6 CBCTL3 +000008c6 CBCTL3_L +000008c7 CBCTL3_H +000008cc CBINT +000008cc CBINT_L +000008cd CBINT_H +000008ce CBIV +00000900 USBKEYID +00000900 USBKEYID_L +00000901 USBKEYID_H +00000902 USBCNF +00000902 USBCNF_L +00000903 USBCNF_H +00000904 USBPHYCTL +00000904 USBPHYCTL_L +00000905 USBPHYCTL_H +00000908 USBPWRCTL +00000908 USBPWRCTL_L +00000909 USBPWRCTL_H +00000910 USBPLLCTL +00000910 USBPLLCTL_L +00000911 USBPLLCTL_H +00000912 USBPLLDIVB +00000912 USBPLLDIVB_L +00000913 USBPLLDIVB_H +00000914 USBPLLIR +00000914 USBPLLIR_L +00000915 USBPLLIR_H +00000920 USBIEPCNF_0 +00000921 USBIEPCNT_0 +00000922 USBOEPCNF_0 +00000923 USBOEPCNT_0 +0000092e USBIEPIE +0000092f USBOEPIE +00000930 USBIEPIFG +00000931 USBOEPIFG +00000932 USBVECINT +00000932 USBVECINT_L +00000933 USBVECINT_H +00000936 USBMAINT +00000936 USBMAINT_L +00000937 USBMAINT_H +00000938 USBTSREG +00000938 USBTSREG_L +00000939 USBTSREG_H +0000093a USBFN +0000093a USBFN_L +0000093b USBFN_H +0000093c USBCTL +0000093d USBIE +0000093e USBIFG +0000093f USBFUNADR +00001c00 USBSTABUFF +0000236f USBTOPBUFF +00002370 USBOEP0BUF +00002378 USBIEP0BUF +00002380 USBSUBLK +00002388 USBOEPCNF_1 +00002389 USBOEPBBAX_1 +0000238a USBOEPBCTX_1 +0000238d USBOEPBBAY_1 +0000238e USBOEPBCTY_1 +0000238f USBOEPSIZXY_1 +00002390 USBOEPCNF_2 +00002391 USBOEPBBAX_2 +00002392 USBOEPBCTX_2 +00002395 USBOEPBBAY_2 +00002396 USBOEPBCTY_2 +00002397 USBOEPSIZXY_2 +00002398 USBOEPCNF_3 +00002399 USBOEPBBAX_3 +0000239a USBOEPBCTX_3 +0000239d USBOEPBBAY_3 +0000239e USBOEPBCTY_3 +0000239f USBOEPSIZXY_3 +000023a0 USBOEPCNF_4 +000023a1 USBOEPBBAX_4 +000023a2 USBOEPBCTX_4 +000023a5 USBOEPBBAY_4 +000023a6 USBOEPBCTY_4 +000023a7 USBOEPSIZXY_4 +000023a8 USBOEPCNF_5 +000023a9 USBOEPBBAX_5 +000023aa USBOEPBCTX_5 +000023ad USBOEPBBAY_5 +000023ae USBOEPBCTY_5 +000023af USBOEPSIZXY_5 +000023b0 USBOEPCNF_6 +000023b1 USBOEPBBAX_6 +000023b2 USBOEPBCTX_6 +000023b5 USBOEPBBAY_6 +000023b6 USBOEPBCTY_6 +000023b7 USBOEPSIZXY_6 +000023b8 USBOEPCNF_7 +000023b9 USBOEPBBAX_7 +000023ba USBOEPBCTX_7 +000023bd USBOEPBBAY_7 +000023be USBOEPBCTY_7 +000023bf USBOEPSIZXY_7 +000023c8 USBIEPCNF_1 +000023c9 USBIEPBBAX_1 +000023ca USBIEPBCTX_1 +000023cd USBIEPBBAY_1 +000023ce USBIEPBCTY_1 +000023cf USBIEPSIZXY_1 +000023d0 USBIEPCNF_2 +000023d1 USBIEPBBAX_2 +000023d2 USBIEPBCTX_2 +000023d5 USBIEPBBAY_2 +000023d6 USBIEPBCTY_2 +000023d7 USBIEPSIZXY_2 +000023d8 USBIEPCNF_3 +000023d9 USBIEPBBAX_3 +000023da USBIEPBCTX_3 +000023dd USBIEPBBAY_3 +000023de USBIEPBCTY_3 +000023df USBIEPSIZXY_3 +000023e0 USBIEPCNF_4 +000023e1 USBIEPBBAX_4 +000023e2 USBIEPBCTX_4 +000023e5 USBIEPBBAY_4 +000023e6 USBIEPBCTY_4 +000023e7 USBIEPSIZXY_4 +000023e8 USBIEPCNF_5 +000023e9 USBIEPBBAX_5 +000023ea USBIEPBCTX_5 +000023ed USBIEPBBAY_5 +000023ee USBIEPBCTY_5 +000023ef USBIEPSIZXY_5 +000023f0 USBIEPCNF_6 +000023f1 USBIEPBBAX_6 +000023f2 USBIEPBCTX_6 +000023f5 USBIEPBBAY_6 +000023f6 USBIEPBCTY_6 +000023f7 USBIEPSIZXY_6 +000023f8 USBIEPCNF_7 +000023f9 USBIEPBBAX_7 +000023fa USBIEPBCTX_7 +000023fd USBIEPBBAY_7 +000023fe USBIEPBCTY_7 +000023ff USBIEPSIZXY_7 +00002400 _sys_memory +00002658 _CIOBUF_ +00002778 _ftable +000027f0 _device +0000283e _stream +00002866 __TI_cleanup_ptr +00002868 __TI_dtors_ptr +0000286a _lock +0000286c _unlock +0000286e __TI_ft_end +00002870 errno +00002872 __TI_enable_exit_profile_output +00002876 __TI_tmpnams +00002916 parmbuf +00004360 _stack +00004400 __STACK_END +00004400 __mspabi_addd +00004b36 __TI_frcdivd +00004fae __mspabi_divull +0000530e __mspabi_mpyd +000055ce __TI_printfi +00005f5a __mspabi_divd +00006a3a __TI_frcmpyd +00006bac ldexp +00006bac ldexpl +00006bac scalbn +00006bac scalbnl +00007088 aligned_alloc +00007088 memalign +0000717e fputs +00007348 __mspabi_cmpd +00007424 free +000074f6 setvbuf +0000768a frexp +0000768a frexpl +0000773a __mspabi_fltlid +00007924 fputc +00007924 putc +000079b4 main +00007ad2 HOSTlseek +00007b5a __TI_ltoa +00007bde __TI_decompress_lzss +00007c5a __TI_wrt_ok +00007d4e __TI_closefile +00007dc0 __mspabi_fixdli +00007e32 fseek +00007ea2 HOSTrename +00007f74 HOSTopen +00007fda HOSTwrite +0000803c __TI_doflush +0000809e HOSTread +000080fe __mspabi_mpyll_f5hw +0000815c __mspabi_srll_15 +00008162 __mspabi_srll_14 +00008168 __mspabi_srll_13 +0000816e __mspabi_srll_12 +00008174 __mspabi_srll_11 +0000817a __mspabi_srll_10 +00008180 __mspabi_srll_9 +00008186 __mspabi_srll_8 +0000818c __mspabi_srll_7 +00008192 __mspabi_srll_6 +00008198 __mspabi_srll_5 +0000819e __mspabi_srll_4 +000081a4 __mspabi_srll_3 +000081aa __mspabi_srll_2 +000081b0 __mspabi_srll_1 +000081b8 __TI_auto_init_nobinit_nopinit_hold_wdt +00008210 getdevice +00008268 __mspabi_divul +00008268 __mspabi_remul +000082c0 atoi +00008360 __mspabi_srli +0000836e __mspabi_srli_15 +00008372 __mspabi_srli_14 +00008376 __mspabi_srli_13 +0000837a __mspabi_srli_12 +0000837e __mspabi_srli_11 +00008382 __mspabi_srli_10 +00008386 __mspabi_srli_9 +0000838a __mspabi_srli_8 +0000838e __mspabi_srli_7 +00008392 __mspabi_srli_6 +00008396 __mspabi_srli_5 +0000839a __mspabi_srli_4 +0000839e __mspabi_srli_3 +000083a2 __mspabi_srli_2 +000083a6 __mspabi_srli_1 +000083ac __mspabi_srall +000083f6 close +00008440 __mspabi_srlll +00008486 HOSTclose +000084ca __mspabi_sllll +0000850e exit +00008552 HOSTunlink +00008592 __mspabi_divli +00008592 __mspabi_remli +000085d2 __mspabi_sral_15 +000085d6 __mspabi_sral_14 +000085da __mspabi_sral_13 +000085de __mspabi_sral_12 +000085e2 __mspabi_sral_11 +000085e6 __mspabi_sral_10 +000085ea __mspabi_sral_9 +000085ee __mspabi_sral_8 +000085f2 __mspabi_sral_7 +000085f6 __mspabi_sral_6 +000085fa __mspabi_sral_5 +000085fe __mspabi_sral_4 +00008602 __mspabi_sral_3 +00008606 __mspabi_sral_2 +0000860a __mspabi_sral_1 +00008610 __mspabi_slll_15 +00008614 __mspabi_slll_14 +00008618 __mspabi_slll_13 +0000861c __mspabi_slll_12 +00008620 __mspabi_slll_11 +00008624 __mspabi_slll_10 +00008628 __mspabi_slll_9 +0000862c __mspabi_slll_8 +00008630 __mspabi_slll_7 +00008634 __mspabi_slll_6 +00008638 __mspabi_slll_5 +0000863c __mspabi_slll_4 +00008640 __mspabi_slll_3 +00008644 __mspabi_slll_2 +00008648 __mspabi_slll_1 +0000864e printf +0000868a __TI_cleanup +000086be finddevice +000086f2 __TI_writemsg +0000871c C$$IO$$ +00008720 __mspabi_subd +0000874e copysign +0000874e copysignl +0000877c __TI_readmsg +000087a8 __mspabi_srai +000087b4 __mspabi_srai_15 +000087b6 __mspabi_srai_14 +000087b8 __mspabi_srai_13 +000087ba __mspabi_srai_12 +000087bc __mspabi_srai_11 +000087be __mspabi_srai_10 +000087c0 __mspabi_srai_9 +000087c2 __mspabi_srai_8 +000087c4 __mspabi_srai_7 +000087c6 __mspabi_srai_6 +000087c8 __mspabi_srai_5 +000087ca __mspabi_srai_4 +000087cc __mspabi_srai_3 +000087ce __mspabi_srai_2 +000087d0 __mspabi_srai_1 +000087d4 __mspabi_slli +000087e0 __mspabi_slli_15 +000087e2 __mspabi_slli_14 +000087e4 __mspabi_slli_13 +000087e6 __mspabi_slli_12 +000087e8 __mspabi_slli_11 +000087ea __mspabi_slli_10 +000087ec __mspabi_slli_9 +000087ee __mspabi_slli_8 +000087f0 __mspabi_slli_7 +000087f2 __mspabi_slli_6 +000087f4 __mspabi_slli_5 +000087f6 __mspabi_slli_4 +000087f8 __mspabi_slli_3 +000087fa __mspabi_slli_2 +000087fc __mspabi_slli_1 +00008800 strncpy +0000882c __mspabi_negd +00008856 __mspabi_mpyull_f5hw +0000887e __mspabi_fixdi +000088ce remove +000088ce unlink +000088f6 lseek +0000891c write +00008940 memccpy +00008962 __mspabi_mpyl_f5hw +00008982 _c_int00_noargs +000089ba strchr +000089d4 strcmp +000089ec __mspabi_divu +000089ec __mspabi_remu +00008a02 __TI_zero_init_nomemset +00008a16 memchr +00008a2a memset +00008a3e __mspabi_mpyi_f5hw +00008a52 wcslen +00008a66 __TI_decompress_none +00008a78 __mspabi_srll +00008a8a memcpy +00008a9c __mspabi_func_epilog_7 +00008a9e __mspabi_func_epilog_6 +00008aa0 __mspabi_func_epilog_5 +00008aa2 __mspabi_func_epilog_4 +00008aa4 __mspabi_func_epilog_3 +00008aa6 __mspabi_func_epilog_2 +00008aa8 __mspabi_func_epilog_1 +00008aac strcpy +00008abc strlen +00008aca __mspabi_fltid +00008ad6 toupper +00008ae2 abs +00008aec islower +00008af4 malloc +00008b02 C$$EXIT +00008b02 abort +00008b0c _system_pre_init +00008b10 _nop +00008b12 _system_post_cinit +00008b14 _ctypes_ +00008c62 __TI_ISR_TRAP +00008cae __TI_Handler_Table_Base +00008cb4 __TI_Handler_Table_Limit +00008cb8 __TI_CINIT_Base +00008cc0 __TI_CINIT_Limit +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +0000fffe _reset_vector +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[975 symbols] diff --git a/CPE325/L1_Problem2/Debug/L2_Problem2_linkInfo.xml b/CPE325/L1_Problem2/Debug/L2_Problem2_linkInfo.xml new file mode 100644 index 0000000..e85871e --- /dev/null +++ b/CPE325/L1_Problem2/Debug/L2_Problem2_linkInfo.xml @@ -0,0 +1,16493 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x612933af + 0x0 + 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0x8174 + + + + __mspabi_srll_10 + 0x817a + + + + __mspabi_srll + 0x8a78 + + + + __mspabi_srall + 0x83ac + + + + __mspabi_sllll + 0x84ca + + + + __TI_frcmpyd + 0x6a3a + + + + HOSTclose + 0x8486 + + + + HOSTlseek + 0x7ad2 + + + + parmbuf + 0x2916 + + + HOSTopen + 0x7f74 + + + + HOSTread + 0x809e + + + + HOSTrename + 0x7ea2 + + + + HOSTunlink + 0x8552 + + + + HOSTwrite + 0x7fda + + + + __TI_readmsg + 0x877c + + + + C$$IO$$ + 0x871c + + + + _CIOBUF_ + 0x2658 + + + + __TI_writemsg + 0x86f2 + + + + lseek + 0x88f6 + + + + __TI_closefile + 0x7d4e + + + + finddevice + 0x86be + + + + getdevice + 0x8210 + + + + strcmp + 0x89d4 + + + + strcpy + 0x8aac + + + + strncpy + 0x8800 + + + + close + 0x83f6 + + + + unlink + 0x88ce + + + + remove + 0x88ce + + + Link successful + diff --git a/CPE325/L1_Problem2/Debug/Problem2.map b/CPE325/L1_Problem2/Debug/Problem2.map new file mode 100644 index 0000000..c110814 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/Problem2.map @@ -0,0 +1,2443 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Thu Aug 26 23:08:44 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00008982 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 000005c0 00001a40 RWIX + FLASH 00004400 0000bb80 000048c0 000072c0 RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00002778 000000fe UNINITIALIZED + 00002778 00000078 rts430_eabi.lib : defs.c.obj (.data:_ftable) + 000027f0 0000004e : host_device.c.obj (.data:_device) + 0000283e 00000028 : host_device.c.obj (.data:_stream) + 00002866 00000002 : exit_gvars.c.obj (.data:__TI_cleanup_ptr) + 00002868 00000002 : exit_gvars.c.obj (.data:__TI_dtors_ptr) + 0000286a 00000002 : _lock.c.obj (.data:_lock) + 0000286c 00000002 : _lock.c.obj (.data:_unlock) + 0000286e 00000002 : defs.c.obj (.data) + 00002870 00000002 : errno.c.obj (.data) + 00002872 00000002 : exit.c.obj (.data) + 00002874 00000002 : memory.c.obj (.data) + +.bss 0 00002876 000000aa UNINITIALIZED + 00002876 000000a0 (.common:__TI_tmpnams) + 00002916 00000008 (.common:parmbuf) + 0000291e 00000002 rts430_eabi.lib : memory.c.obj (.bss) + +.sysmem 0 00002400 00000258 UNINITIALIZED + 00002400 00000008 rts430_eabi.lib : memory.c.obj (.sysmem) + 00002408 00000250 --HOLE-- + +.cio 0 00002658 00000120 UNINITIALIZED + 00002658 00000120 rts430_eabi.lib : trgmsg.c.obj (.cio) + +.stack 0 00004360 000000a0 UNINITIALIZED + 00004360 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 00004362 0000009e --HOLE-- + +.text 0 00004400 00004714 + 00004400 00000736 rts430_eabi.lib : addd.c.obj (.text:__mspabi_addd) + 00004b36 00000478 : frcdivd.c.obj (.text:__TI_frcdivd) + 00004fae 00000360 : div64u.c.obj (.text:__mspabi_divull) + 0000530e 000002c0 : mpyd.c.obj (.text:__mspabi_mpyd) + 000055ce 00000288 : _printfi.c.obj (.text:__TI_printfi) + 00005856 0000026e : _printfi.c.obj (.text:_pproc_fgea) + 00005ac4 00000252 : _printfi.c.obj (.text:_setfield) + 00005d16 00000244 : _printfi.c.obj (.text:acvt) + 00005f5a 00000238 : divd.c.obj (.text:__mspabi_divd) + 00006192 000001ec : _printfi.c.obj (.text:_getarg_diouxp) + 0000637e 000001de : _printfi.c.obj (.text:ecvt) + 0000655c 000001c4 : _printfi.c.obj (.text:fcvt) + 00006720 000001a6 : _printfi.c.obj (.text:_pconv_e) + 000068c6 00000174 : _printfi.c.obj (.text:_pconv_a) + 00006a3a 00000172 : frcmpyd.c.obj (.text:__TI_frcmpyd) + 00006bac 0000016a : s_scalbn.c.obj (.text:scalbn) + 00006d16 0000014c : _printfi.c.obj (.text:_pproc_diouxp) + 00006e62 0000012e : _printfi.c.obj (.text:_ltostr) + 00006f90 000000f8 : _printfi.c.obj (.text:_pconv_g) + 00007088 000000f6 : memory.c.obj (.text:aligned_alloc) + 0000717e 000000ea : fputs.c.obj (.text:fputs) + 00007268 000000e0 : _printfi.c.obj (.text:_pproc_fwp) + 00007348 000000dc : cmpd.c.obj (.text:__mspabi_cmpd) + 00007424 000000d2 : memory.c.obj (.text:free) + 000074f6 000000d0 : setvbuf.c.obj (.text:setvbuf) + 000075c6 000000c4 : _printfi.c.obj (.text:_pproc_wstr) + 0000768a 000000b0 : s_frexp.c.obj (.text:frexp) + 0000773a 000000ac : fltlid.c.obj (.text:__mspabi_fltlid) + 000077e6 000000ac : _printfi.c.obj (.text:_pproc_str) + 00007892 00000092 : _printfi.c.obj (.text:_mcpy) + 00007924 00000090 : fputc.c.obj (.text:fputc) + 000079b4 00000090 problem2.obj (.text:main) + 00007a44 0000008e rts430_eabi.lib : _printfi.c.obj (.text:_ecpy) + 00007ad2 00000088 : hostlseek.c.obj (.text:HOSTlseek) + 00007b5a 00000084 : _ltoa.c.obj (.text:__TI_ltoa) + 00007bde 0000007c : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00007c5a 0000007a : _io_perm.c.obj (.text:__TI_wrt_ok) + 00007cd4 0000007a : _printfi.c.obj (.text:_pconv_f) + 00007d4e 00000072 : fclose.c.obj (.text:__TI_closefile) + 00007dc0 00000072 : fixdli.c.obj (.text:__mspabi_fixdli) + 00007e32 00000070 : fseek.c.obj (.text:fseek) + 00007ea2 0000006a : hostrename.c.obj (.text:HOSTrename) + 00007f0c 00000068 : memory.c.obj (.text:split) + 00007f74 00000066 : hostopen.c.obj (.text:HOSTopen) + 00007fda 00000062 : hostwrite.c.obj (.text:HOSTwrite) + 0000803c 00000062 : fflush.c.obj (.text:__TI_doflush) + 0000809e 00000060 : hostread.c.obj (.text:HOSTread) + 000080fe 0000005e : mult64_f5hw.asm.obj (.text:__mpyll) + 0000815c 0000005c : lsr32.asm.obj (.text:l_lsr_const) + 000081b8 00000058 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 00008210 00000058 : getdevice.c.obj (.text:getdevice) + 00008268 00000058 : div32u.asm.obj (.text) + 000082c0 00000052 : atoi.c.obj (.text:atoi) + 00008312 0000004e : _printfi.c.obj (.text:_fcpy) + 00008360 0000004c : lsr16.asm.obj (.text) + 000083ac 0000004a : asr64.c.obj (.text:__mspabi_srall) + 000083f6 0000004a : close.c.obj (.text:close) + 00008440 00000046 : lsr64.c.obj (.text:__mspabi_srlll) + 00008486 00000044 : hostclose.c.obj (.text:HOSTclose) + 000084ca 00000044 : lsl64.c.obj (.text:__mspabi_sllll) + 0000850e 00000044 : exit.c.obj (.text:exit) + 00008552 00000040 : hostunlink.c.obj (.text:HOSTunlink) + 00008592 00000040 : div32s.asm.obj (.text) + 000085d2 0000003e : asr32.asm.obj (.text:l_asr_const) + 00008610 0000003e : lsl32.asm.obj (.text:l_lsl_const) + 0000864e 0000003c : printf.c.obj (.text:printf) + 0000868a 00000034 : fopen.c.obj (.text:__TI_cleanup) + 000086be 00000034 : getdevice.c.obj (.text:finddevice) + 000086f2 0000002e : trgmsg.c.obj (.text:__TI_writemsg) + 00008720 0000002e : subd.c.obj (.text:__mspabi_subd) + 0000874e 0000002e : s_copysign.c.obj (.text:copysign) + 0000877c 0000002c : trgmsg.c.obj (.text:__TI_readmsg) + 000087a8 0000002c : asr16.asm.obj (.text) + 000087d4 0000002c : lsl16.asm.obj (.text) + 00008800 0000002c : strncpy.c.obj (.text:strncpy) + 0000882c 0000002a : negd.c.obj (.text:__mspabi_negd) + 00008856 00000028 : mult3264_f5hw.asm.obj (.text:__mpyull) + 0000887e 00000028 : fixdi.c.obj (.text:__mspabi_fixdi) + 000088a6 00000028 : memory.c.obj (.text:free_list_insert) + 000088ce 00000028 : unlink.c.obj (.text:unlink) + 000088f6 00000026 : lseek.c.obj (.text:lseek) + 0000891c 00000024 : write.c.obj (.text:write) + 00008940 00000022 : memccpy.c.obj (.text:memccpy) + 00008962 00000020 : mult32_f5hw.asm.obj (.text) + 00008982 0000001c : boot.c.obj (.text:_c_int00_noargs) + 0000899e 0000001c : memory.c.obj (.text:free_list_remove) + 000089ba 0000001a : strchr.c.obj (.text:strchr) + 000089d4 00000018 : strcmp.c.obj (.text:strcmp) + 000089ec 00000016 : div16u.asm.obj (.text) + 00008a02 00000014 : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset:__TI_zero_init_nomemset) + 00008a16 00000014 : memchr.c.obj (.text:memchr) + 00008a2a 00000014 : memset.c.obj (.text:memset) + 00008a3e 00000014 : mult16_f5hw.asm.obj (.text) + 00008a52 00000014 : wcslen.c.obj (.text:wcslen) + 00008a66 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00008a78 00000012 : lsr32.asm.obj (.text:l_lsr) + 00008a8a 00000012 : memcpy.c.obj (.text:memcpy) + 00008a9c 00000010 : epilog.asm.obj (.text) + 00008aac 00000010 : strcpy.c.obj (.text:strcpy) + 00008abc 0000000e : strlen.c.obj (.text:strlen) + 00008aca 0000000c : fltid.c.obj (.text:__mspabi_fltid) + 00008ad6 0000000c : toupper.c.obj (.text:toupper) + 00008ae2 0000000a : abs.c.obj (.text:abs) + 00008aec 00000008 : islower.c.obj (.text:islower) + 00008af4 00000008 : memory.c.obj (.text:malloc) + 00008afc 00000006 : printf.c.obj (.text:_outc) + 00008b02 00000006 : exit.c.obj (.text:abort) + 00008b08 00000004 : printf.c.obj (.text:_outs) + 00008b0c 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00008b10 00000002 : _lock.c.obj (.text:_nop) + 00008b12 00000002 : startup.c.obj (.text:_system_post_cinit) + +.const 0 00008b14 0000014e + 00008b14 00000101 rts430_eabi.lib : ctype.c.obj (.const:.string:_ctypes_) + 00008c15 00000001 --HOLE-- [fill = 0] + 00008c16 00000026 : _printfi.c.obj (.const:.string) + 00008c3c 00000021 problem2.obj (.const:.string:$P$T0$1) + 00008c5d 00000001 --HOLE-- [fill = 0] + 00008c5e 00000004 problem2.obj (.const:.string) + +.text:_isr +* 0 00008c62 00000008 + 00008c62 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00008c6a 00000056 + 00008c6a 00000044 (.cinit..data.load) [load image, compression = lzss] + 00008cae 00000006 (__TI_handler_table) + 00008cb4 00000004 (.cinit..bss.load) [load image, compression = zero_init] + 00008cb8 00000008 (__TI_cinit_table) + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + problem2.obj 144 37 0 + +--+----------------------------+-------+---------+---------+ + Total: 144 37 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + _printfi.c.obj 6622 38 0 + addd.c.obj 1846 0 0 + frcdivd.c.obj 1144 0 0 + div64u.c.obj 864 0 0 + mpyd.c.obj 704 0 0 + memory.c.obj 636 0 4 + divd.c.obj 568 0 0 + trgmsg.c.obj 90 0 288 + frcmpyd.c.obj 370 0 0 + s_scalbn.c.obj 362 0 0 + defs.c.obj 0 0 282 + ctype.c.obj 0 257 0 + fputs.c.obj 234 0 0 + cmpd.c.obj 220 0 0 + setvbuf.c.obj 208 0 0 + s_frexp.c.obj 176 0 0 + fltlid.c.obj 172 0 0 + fputc.c.obj 144 0 0 + getdevice.c.obj 140 0 0 + hostlseek.c.obj 136 0 0 + _ltoa.c.obj 132 0 0 + copy_decompress_lzss.c.obj 124 0 0 + _io_perm.c.obj 122 0 0 + host_device.c.obj 0 0 118 + fclose.c.obj 114 0 0 + fixdli.c.obj 114 0 0 + fseek.c.obj 112 0 0 + hostopen.c.obj 102 0 8 + lsr32.asm.obj 110 0 0 + hostrename.c.obj 106 0 0 + fflush.c.obj 98 0 0 + hostwrite.c.obj 98 0 0 + hostread.c.obj 96 0 0 + mult64_f5hw.asm.obj 94 0 0 + autoinit.c.obj 88 0 0 + div32u.asm.obj 88 0 0 + atoi.c.obj 82 0 0 + exit.c.obj 74 0 2 + lsr16.asm.obj 76 0 0 + asr64.c.obj 74 0 0 + close.c.obj 74 0 0 + lsr64.c.obj 70 0 0 + printf.c.obj 70 0 0 + hostclose.c.obj 68 0 0 + lsl64.c.obj 68 0 0 + div32s.asm.obj 64 0 0 + hostunlink.c.obj 64 0 0 + asr32.asm.obj 62 0 0 + lsl32.asm.obj 62 0 0 + fopen.c.obj 52 0 0 + s_copysign.c.obj 46 0 0 + subd.c.obj 46 0 0 + asr16.asm.obj 44 0 0 + lsl16.asm.obj 44 0 0 + strncpy.c.obj 44 0 0 + negd.c.obj 42 0 0 + fixdi.c.obj 40 0 0 + mult3264_f5hw.asm.obj 40 0 0 + unlink.c.obj 40 0 0 + lseek.c.obj 38 0 0 + write.c.obj 36 0 0 + memccpy.c.obj 34 0 0 + mult32_f5hw.asm.obj 32 0 0 + boot.c.obj 28 2 0 + strchr.c.obj 26 0 0 + strcmp.c.obj 24 0 0 + div16u.asm.obj 22 0 0 + copy_zero_init.c.obj 20 0 0 + memchr.c.obj 20 0 0 + memset.c.obj 20 0 0 + mult16_f5hw.asm.obj 20 0 0 + wcslen.c.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + memcpy.c.obj 18 0 0 + epilog.asm.obj 16 0 0 + strcpy.c.obj 16 0 0 + strlen.c.obj 14 0 0 + fltid.c.obj 12 0 0 + toupper.c.obj 12 0 0 + abs.c.obj 10 0 0 + islower.c.obj 8 0 0 + isr_trap.asm.obj 8 0 0 + _lock.c.obj 2 0 4 + exit_gvars.c.obj 0 0 4 + pre_init.c.obj 4 0 0 + errno.c.obj 0 0 2 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 18060 341 712 + + Heap: 0 0 600 + Stack: 0 0 160 + Linker Generated: 0 86 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 18204 464 1472 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00008cb8 records: 2, size/record: 4, table size: 8 + .data: load addr=00008c6a, load size=00000044 bytes, run addr=00002778, run size=000000fe bytes, compression=lzss + .bss: load addr=00008cb4, load size=00000004 bytes, run addr=00002876, run size=000000aa bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 00008cae records: 3, size/record: 2, table size: 6 + index: 0, handler: __TI_zero_init + index: 1, handler: __TI_decompress_lzss + index: 2, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +00008b02 C$$EXIT +0000871c C$$IO$$ +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +00008486 HOSTclose +00007ad2 HOSTlseek +00007f74 HOSTopen +0000809e HOSTread +00007ea2 HOSTrename +00008552 HOSTunlink +00007fda HOSTwrite +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +00000902 USBCNF +00000903 USBCNF_H +00000902 USBCNF_L +0000093c USBCTL +0000093a USBFN +0000093b USBFN_H +0000093a USBFN_L +0000093f USBFUNADR +0000093d USBIE +00002378 USBIEP0BUF +000023c9 USBIEPBBAX_1 +000023d1 USBIEPBBAX_2 +000023d9 USBIEPBBAX_3 +000023e1 USBIEPBBAX_4 +000023e9 USBIEPBBAX_5 +000023f1 USBIEPBBAX_6 +000023f9 USBIEPBBAX_7 +000023cd USBIEPBBAY_1 +000023d5 USBIEPBBAY_2 +000023dd USBIEPBBAY_3 +000023e5 USBIEPBBAY_4 +000023ed USBIEPBBAY_5 +000023f5 USBIEPBBAY_6 +000023fd USBIEPBBAY_7 +000023ca USBIEPBCTX_1 +000023d2 USBIEPBCTX_2 +000023da USBIEPBCTX_3 +000023e2 USBIEPBCTX_4 +000023ea USBIEPBCTX_5 +000023f2 USBIEPBCTX_6 +000023fa USBIEPBCTX_7 +000023ce USBIEPBCTY_1 +000023d6 USBIEPBCTY_2 +000023de USBIEPBCTY_3 +000023e6 USBIEPBCTY_4 +000023ee USBIEPBCTY_5 +000023f6 USBIEPBCTY_6 +000023fe USBIEPBCTY_7 +00000920 USBIEPCNF_0 +000023c8 USBIEPCNF_1 +000023d0 USBIEPCNF_2 +000023d8 USBIEPCNF_3 +000023e0 USBIEPCNF_4 +000023e8 USBIEPCNF_5 +000023f0 USBIEPCNF_6 +000023f8 USBIEPCNF_7 +00000921 USBIEPCNT_0 +0000092e USBIEPIE +00000930 USBIEPIFG +000023cf USBIEPSIZXY_1 +000023d7 USBIEPSIZXY_2 +000023df USBIEPSIZXY_3 +000023e7 USBIEPSIZXY_4 +000023ef USBIEPSIZXY_5 +000023f7 USBIEPSIZXY_6 +000023ff USBIEPSIZXY_7 +0000093e USBIFG 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USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +00002658 _CIOBUF_ +00004400 __STACK_END +000000a0 __STACK_SIZE +00000258 __SYSMEM_SIZE +00008cb8 __TI_CINIT_Base +00008cc0 __TI_CINIT_Limit +00008cae __TI_Handler_Table_Base +00008cb4 __TI_Handler_Table_Limit +00008c62 __TI_ISR_TRAP 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__TI_writemsg +00007c5a __TI_wrt_ok +00008a02 __TI_zero_init_nomemset +ffffffff __c_args__ +00004400 __mspabi_addd +00007348 __mspabi_cmpd +00005f5a __mspabi_divd +00008592 __mspabi_divli +000089ec __mspabi_divu +00008268 __mspabi_divul +00004fae __mspabi_divull +0000887e __mspabi_fixdi +00007dc0 __mspabi_fixdli +00008aca __mspabi_fltid +0000773a __mspabi_fltlid +00008aa8 __mspabi_func_epilog_1 +00008aa6 __mspabi_func_epilog_2 +00008aa4 __mspabi_func_epilog_3 +00008aa2 __mspabi_func_epilog_4 +00008aa0 __mspabi_func_epilog_5 +00008a9e __mspabi_func_epilog_6 +00008a9c __mspabi_func_epilog_7 +0000530e __mspabi_mpyd +00008a3e __mspabi_mpyi_f5hw +00008962 __mspabi_mpyl_f5hw +000080fe __mspabi_mpyll_f5hw +00008856 __mspabi_mpyull_f5hw +0000882c __mspabi_negd +00008592 __mspabi_remli +000089ec __mspabi_remu +00008268 __mspabi_remul +000087d4 __mspabi_slli +000087fc __mspabi_slli_1 +000087ea __mspabi_slli_10 +000087e8 __mspabi_slli_11 +000087e6 __mspabi_slli_12 +000087e4 __mspabi_slli_13 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+0000817a __mspabi_srll_10 +00008174 __mspabi_srll_11 +0000816e __mspabi_srll_12 +00008168 __mspabi_srll_13 +00008162 __mspabi_srll_14 +0000815c __mspabi_srll_15 +000081aa __mspabi_srll_2 +000081a4 __mspabi_srll_3 +0000819e __mspabi_srll_4 +00008198 __mspabi_srll_5 +00008192 __mspabi_srll_6 +0000818c __mspabi_srll_7 +00008186 __mspabi_srll_8 +00008180 __mspabi_srll_9 +00008440 __mspabi_srlll +00008720 __mspabi_subd +00008982 _c_int00_noargs +00008b14 _ctypes_ +000027f0 _device +00002778 _ftable +0000286a _lock +00008b10 _nop +0000fffe _reset_vector +00004360 _stack +0000283e _stream +00002400 _sys_memory +00008b12 _system_post_cinit +00008b0c _system_pre_init +0000286c _unlock +00008b02 abort +00008ae2 abs +00007088 aligned_alloc +000082c0 atoi +000083f6 close +0000874e copysign +0000874e copysignl +00002870 errno +0000850e exit +000086be finddevice +00007924 fputc +0000717e fputs +00007424 free +0000768a frexp +0000768a frexpl +00007e32 fseek +00008210 getdevice +00008aec islower +00006bac ldexp +00006bac ldexpl +000088f6 lseek +000079b4 main +00008af4 malloc +00007088 memalign +00008940 memccpy +00008a16 memchr +00008a8a memcpy +00008a2a memset +00002916 parmbuf +0000864e printf +00007924 putc +000088ce remove +00006bac scalbn +00006bac scalbnl +000074f6 setvbuf +000089ba strchr +000089d4 strcmp +00008aac strcpy +00008abc strlen +00008800 strncpy +00008ad6 toupper +000088ce unlink +00008a52 wcslen +0000891c write + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +000000a0 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000258 __SYSMEM_SIZE +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H +00000726 ADC12MEM3 +00000726 ADC12MEM3_L +00000727 ADC12MEM3_H +00000728 ADC12MEM4 +00000728 ADC12MEM4_L +00000729 ADC12MEM4_H +0000072a ADC12MEM5 +0000072a ADC12MEM5_L +0000072b ADC12MEM5_H +0000072c ADC12MEM6 +0000072c ADC12MEM6_L +0000072d ADC12MEM6_H +0000072e ADC12MEM7 +0000072e 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USBPHYCTL_L +00000905 USBPHYCTL_H +00000908 USBPWRCTL +00000908 USBPWRCTL_L +00000909 USBPWRCTL_H +00000910 USBPLLCTL +00000910 USBPLLCTL_L +00000911 USBPLLCTL_H +00000912 USBPLLDIVB +00000912 USBPLLDIVB_L +00000913 USBPLLDIVB_H +00000914 USBPLLIR +00000914 USBPLLIR_L +00000915 USBPLLIR_H +00000920 USBIEPCNF_0 +00000921 USBIEPCNT_0 +00000922 USBOEPCNF_0 +00000923 USBOEPCNT_0 +0000092e USBIEPIE +0000092f USBOEPIE +00000930 USBIEPIFG +00000931 USBOEPIFG +00000932 USBVECINT +00000932 USBVECINT_L +00000933 USBVECINT_H +00000936 USBMAINT +00000936 USBMAINT_L +00000937 USBMAINT_H +00000938 USBTSREG +00000938 USBTSREG_L +00000939 USBTSREG_H +0000093a USBFN +0000093a USBFN_L +0000093b USBFN_H +0000093c USBCTL +0000093d USBIE +0000093e USBIFG +0000093f USBFUNADR +00001c00 USBSTABUFF +0000236f USBTOPBUFF +00002370 USBOEP0BUF +00002378 USBIEP0BUF +00002380 USBSUBLK +00002388 USBOEPCNF_1 +00002389 USBOEPBBAX_1 +0000238a USBOEPBCTX_1 +0000238d USBOEPBBAY_1 +0000238e USBOEPBCTY_1 +0000238f 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__TI_CINIT_Limit +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +0000fffe _reset_vector +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[975 symbols] diff --git a/CPE325/L1_Problem2/Debug/Problem2_linkInfo.xml b/CPE325/L1_Problem2/Debug/Problem2_linkInfo.xml new file mode 100644 index 0000000..d332a5a --- /dev/null +++ b/CPE325/L1_Problem2/Debug/Problem2_linkInfo.xml @@ -0,0 +1,16493 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x6128654c + 0x0 + Problem2.out + + _c_int00_noargs +
0x8982
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UCB1I2CSA_L + 0x632 + + + UCB1I2CSA_H + 0x633 + + + UCB1ICTL + 0x63c + + + UCB1ICTL_L + 0x63c + + + UCB1ICTL_H + 0x63d + + + UCB1IV + 0x63e + + + WDTCTL + 0x15c + + + WDTCTL_L + 0x15c + + + WDTCTL_H + 0x15d + + + __TI_CINIT_Base + 0x8cb8 + + + __TI_CINIT_Limit + 0x8cc0 + + + __TI_Handler_Table_Base + 0x8cae + + + __TI_Handler_Table_Limit + 0x8cb4 + + + __STACK_SIZE + 0xa0 + + + __STACK_END + 0x4400 + + + __SYSMEM_SIZE + 0x258 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + main + 0x79b4 + + + + printf + 0x864e + + + + __TI_printfi + 0x55ce + + + + putc + 0x7924 + + + + fputc + 0x7924 + + + + fputs + 0x717e + + + + __TI_wrt_ok + 0x7c5a + + + + setvbuf + 0x74f6 + + + + wcslen + 0x8a52 + + + + frexpl + 0x768a + + + + frexp + 0x768a + + + + scalbn + 0x6bac + + + + scalbnl + 0x6bac + + + + ldexpl + 0x6bac + + + + ldexp + 0x6bac + + + + __mspabi_srai + 0x87a8 + + + + __mspabi_srai_8 + 0x87c2 + + + + __mspabi_srai_9 + 0x87c0 + + + + __mspabi_srai_6 + 0x87c6 + + + + __mspabi_srai_7 + 0x87c4 + + + + __mspabi_srai_4 + 0x87ca + + + + __mspabi_srai_5 + 0x87c8 + + + + __mspabi_srai_2 + 0x87ce + + + + __mspabi_srai_3 + 0x87cc + + + + __mspabi_srai_1 + 0x87d0 + + + + __mspabi_srai_15 + 0x87b4 + + + + __mspabi_srai_14 + 0x87b6 + + + + __mspabi_srai_13 + 0x87b8 + + + + __mspabi_srai_12 + 0x87ba + + + + __mspabi_srai_11 + 0x87bc + + + + __mspabi_srai_10 + 0x87be + + + + __mspabi_remu + 0x89ec + + + + __mspabi_divu + 0x89ec + + + + __mspabi_remul + 0x8268 + + + + __mspabi_divul + 0x8268 + + + + __mspabi_func_epilog_2 + 0x8aa6 + + + + __mspabi_func_epilog_3 + 0x8aa4 + + + + __mspabi_func_epilog_1 + 0x8aa8 + + + + __mspabi_func_epilog_6 + 0x8a9e + + + + __mspabi_func_epilog_7 + 0x8a9c + + + + __mspabi_func_epilog_4 + 0x8aa2 + + + + __mspabi_func_epilog_5 + 0x8aa0 + + + + __TI_int41 + 0xffd2 + + + + __TI_int42 + 0xffd4 + + + + __TI_int43 + 0xffd6 + + + + __TI_int44 + 0xffd8 + + + + __TI_int45 + 0xffda + + + + __TI_int46 + 0xffdc + + + + __TI_int47 + 0xffde + + + + __TI_int48 + 0xffe0 + + + + __TI_int49 + 0xffe2 + + + + __TI_int50 + 0xffe4 + + + + __TI_int51 + 0xffe6 + + + + __TI_int52 + 0xffe8 + + + + __TI_int53 + 0xffea + + + + __TI_int54 + 0xffec + + + + __TI_int55 + 0xffee + + + + __TI_int56 + 0xfff0 + + + + __TI_int57 + 0xfff2 + + + + __TI_int58 + 0xfff4 + + + + __TI_int59 + 0xfff6 + + + + __TI_int60 + 0xfff8 + + + + __TI_int61 + 0xfffa + + + + __TI_int62 + 0xfffc + + + + __TI_ISR_TRAP + 0x8c62 + + + + __mspabi_slli + 0x87d4 + + + + __mspabi_slli_9 + 0x87ec + + + + __mspabi_slli_8 + 0x87ee + + + + __mspabi_slli_7 + 0x87f0 + + + + __mspabi_slli_6 + 0x87f2 + + + + __mspabi_slli_5 + 0x87f4 + + + + __mspabi_slli_4 + 0x87f6 + + + + __mspabi_slli_3 + 0x87f8 + + + + __mspabi_slli_2 + 0x87fa + + + + __mspabi_slli_1 + 0x87fc + + + + __mspabi_slli_15 + 0x87e0 + + + + __mspabi_slli_14 + 0x87e2 + + + + __mspabi_slli_13 + 0x87e4 + + + + __mspabi_slli_12 + 0x87e6 + + + + __mspabi_slli_11 + 0x87e8 + + + + __mspabi_slli_10 + 0x87ea + + + + __mspabi_srli_8 + 0x838a + + + + __mspabi_srli_9 + 0x8386 + + + + __mspabi_srli_6 + 0x8392 + + + + __mspabi_srli_7 + 0x838e + + + + __mspabi_srli_4 + 0x839a + + + + __mspabi_srli_5 + 0x8396 + + + + __mspabi_srli_2 + 0x83a2 + + + + __mspabi_srli_3 + 0x839e + + + + __mspabi_srli_1 + 0x83a6 + + + + __mspabi_srli + 0x8360 + + + + __mspabi_srli_15 + 0x836e + + + + __mspabi_srli_14 + 0x8372 + + + + __mspabi_srli_13 + 0x8376 + + + + __mspabi_srli_12 + 0x837a + + + + __mspabi_srli_11 + 0x837e + + + + __mspabi_srli_10 + 0x8382 + + + + __mspabi_mpyi_f5hw + 0x8a3e + + + + __mspabi_mpyl_f5hw + 0x8962 + + + + __mspabi_mpyull_f5hw + 0x8856 + + + + __mspabi_mpyll_f5hw + 0x80fe + + + + _stack + 0x4360 + + + + _c_int00_noargs + 0x8982 + + + + _reset_vector + 0xfffe + + + + __TI_auto_init_nobinit_nopinit_hold_wdt + 0x81b8 + + + + __TI_zero_init_nomemset + 0x8a02 + + + + __TI_dtors_ptr + 0x2868 + + + + __TI_cleanup_ptr + 0x2866 + + + + __mspabi_srlll + 0x8440 + + + + __mspabi_divull + 0x4fae + + + + _system_pre_init + 0x8b0c + + + + _system_post_cinit + 0x8b12 + + + + __TI_decompress_none + 0x8a66 + + + + __TI_decompress_lzss + 0x7bde + + + + __mspabi_addd + 0x4400 + + + + __mspabi_cmpd + 0x7348 + + + + __mspabi_divd + 0x5f5a + + + + __mspabi_fixdi + 0x887e + + + + __mspabi_fixdli + 0x7dc0 + + + + __mspabi_fltid + 0x8aca + + + + __mspabi_fltlid + 0x773a + + + + __TI_frcdivd + 0x4b36 + + + + __mspabi_mpyd + 0x530e + + + + __mspabi_negd + 0x882c + + + + __mspabi_subd + 0x8720 + + + + C$$EXIT + 0x8b02 + + + + abort + 0x8b02 + + + + __TI_enable_exit_profile_output + 0x2872 + + + + exit + 0x850e + + + + _nop + 0x8b10 + + + + _lock + 0x286a + + + + _unlock + 0x286c + + + + __TI_ltoa + 0x7b5a + + + + atoi + 0x82c0 + + + + _ctypes_ + 0x8b14 + + + + __TI_tmpnams + 0x2876 + + + _ftable + 0x2778 + + + + __TI_ft_end + 0x286e + + + + islower + 0x8aec + + + + memccpy + 0x8940 + + + + memchr + 0x8a16 + + + + memcpy + 0x8a8a + + + + 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0x8592 + + + + __mspabi_divli + 0x8592 + + + + __mspabi_slll_9 + 0x8628 + + + + __mspabi_slll_8 + 0x862c + + + + __mspabi_slll_7 + 0x8630 + + + + __mspabi_slll_6 + 0x8634 + + + + __mspabi_slll_5 + 0x8638 + + + + __mspabi_slll_4 + 0x863c + + + + __mspabi_slll_3 + 0x8640 + + + + __mspabi_slll_2 + 0x8644 + + + + __mspabi_slll_1 + 0x8648 + + + + __mspabi_slll_15 + 0x8610 + + + + __mspabi_slll_14 + 0x8614 + + + + __mspabi_slll_13 + 0x8618 + + + + __mspabi_slll_12 + 0x861c + + + + __mspabi_slll_11 + 0x8620 + + + + __mspabi_slll_10 + 0x8624 + + + + __mspabi_srll_8 + 0x8186 + + + + __mspabi_srll_9 + 0x8180 + + + + __mspabi_srll_6 + 0x8192 + + + + __mspabi_srll_7 + 0x818c + + + + __mspabi_srll_4 + 0x819e + + + + __mspabi_srll_5 + 0x8198 + + + + __mspabi_srll_2 + 0x81aa + + + + __mspabi_srll_3 + 0x81a4 + + + + __mspabi_srll_1 + 0x81b0 + + + + __mspabi_srll_15 + 0x815c + + + + __mspabi_srll_14 + 0x8162 + + + + __mspabi_srll_13 + 0x8168 + + + + __mspabi_srll_12 + 0x816e + + + + __mspabi_srll_11 + 0x8174 + + + + __mspabi_srll_10 + 0x817a + + + + __mspabi_srll + 0x8a78 + + + + __mspabi_srall + 0x83ac + + + + __mspabi_sllll + 0x84ca + + + + __TI_frcmpyd + 0x6a3a + + + + HOSTclose + 0x8486 + + + + HOSTlseek + 0x7ad2 + + + + parmbuf + 0x2916 + + + HOSTopen + 0x7f74 + + + + HOSTread + 0x809e + + + + HOSTrename + 0x7ea2 + + + + HOSTunlink + 0x8552 + + + + HOSTwrite + 0x7fda + + + + __TI_readmsg + 0x877c + + + + C$$IO$$ + 0x871c + + + + _CIOBUF_ + 0x2658 + + + + __TI_writemsg + 0x86f2 + + + + lseek + 0x88f6 + + + + __TI_closefile + 0x7d4e + + + + finddevice + 0x86be + + + + getdevice + 0x8210 + + + + strcmp + 0x89d4 + + + + strcpy + 0x8aac + + + + strncpy + 0x8800 + + + + close + 0x83f6 + + + + unlink + 0x88ce + + + + remove + 0x88ce + + + Link successful + diff --git a/CPE325/L1_Problem2/Debug/ccsObjs.opt b/CPE325/L1_Problem2/Debug/ccsObjs.opt new file mode 100644 index 0000000..7bc0d60 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./problem2.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/L1_Problem2/Debug/makefile b/CPE325/L1_Problem2/Debug/makefile new file mode 100644 index 0000000..cb903c6 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/makefile @@ -0,0 +1,168 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./problem2.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +L1_Problem2.out \ + +EXE_OUTPUTS__QUOTED += \ +"L1_Problem2.out" \ + +BIN_OUTPUTS += \ +L1_Problem2.hex \ + +BIN_OUTPUTS__QUOTED += \ +"L1_Problem2.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "L1_Problem2.out" + +# Tool invocations +L1_Problem2.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --advice:power=all --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing -z -m"L1_Problem2.map" --heap_size=600 --stack_size=160 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="L1_Problem2_linkInfo.xml" --use_hw_mpy=F5 --rom_model -o "L1_Problem2.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +L1_Problem2.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "L1_Problem2.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "problem2.lst" + -$(RM) "problem2.obj" + -$(RM) "problem2.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/L1_Problem2/Debug/objects.mk b/CPE325/L1_Problem2/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/L1_Problem2/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/L1_Problem2/Debug/problem2.d b/CPE325/L1_Problem2/Debug/problem2.d new file mode 100644 index 0000000..3a8ae07 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/problem2.d @@ -0,0 +1,48 @@ +# FIXED + +problem2.obj: ../problem2.c +problem2.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +problem2.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h +problem2.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/ctype.h +problem2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_isfuncdcl.h + +../problem2.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/ctype.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_isfuncdcl.h: + diff --git a/CPE325/L1_Problem2/Debug/problem2.lst b/CPE325/L1_Problem2/Debug/problem2.lst new file mode 100644 index 0000000..3aab8b2 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/problem2.lst @@ -0,0 +1,1576 @@ +MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 1 + + 1 ;****************************************************************************** + 2 ;* MSP430 G3 C/C++ Codegen PC v20.2.5.LTS * + 3 ;* Date/Time created: Fri Aug 27 14:36:08 2021 * + 4 ;****************************************************************************** + 5 .compiler_opts --abi=eabi --diag_wrap=off --hll_source=on --mem_model:code=small --mem_model:d + 6 + 7 $C$DW$CU .dwtag DW_TAG_compile_unit + 8 .dwattr $C$DW$CU, DW_AT_name("../problem2.c") + 9 .dwattr $C$DW$CU, DW_AT_producer("TI MSP430 G3 C/C++ Codegen PC v20.2.5.LTS Copyright (c) 2003 + 10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + 11 .dwattr $C$DW$CU, DW_AT_comp_dir("C:\CPE325_Workspace\L1_Problem2\Debug") + 12 000000 .sect ".const:.string:$P$T0$1" + 13 .align 2 + 14 .elfsym $P$T0$1,SYM_SIZE(34) + 15 000000 $P$T0$1: + 16 000000 0057 .bits 0x57,8 + 17 ; $P$T0$1[0] @ 0 + 18 000000 6557 .bits 0x65,8 + 19 ; $P$T0$1[1] @ 8 + 20 000002 006C .bits 0x6c,8 + 21 ; $P$T0$1[2] @ 16 + 22 000002 636C .bits 0x63,8 + 23 ; $P$T0$1[3] @ 24 + 24 000004 006F .bits 0x6f,8 + 25 ; $P$T0$1[4] @ 32 + 26 000004 6D6F .bits 0x6d,8 + 27 ; $P$T0$1[5] @ 40 + 28 000006 0065 .bits 0x65,8 + 29 ; $P$T0$1[6] @ 48 + 30 000006 2065 .bits 0x20,8 + 31 ; $P$T0$1[7] @ 56 + 32 000008 0074 .bits 0x74,8 + 33 ; $P$T0$1[8] @ 64 + 34 000008 6F74 .bits 0x6f,8 + 35 ; $P$T0$1[9] @ 72 + 36 00000a 0020 .bits 0x20,8 + 37 ; $P$T0$1[10] @ 80 + 38 00000a 4320 .bits 0x43,8 + 39 ; $P$T0$1[11] @ 88 + 40 00000c 0050 .bits 0x50,8 + 41 ; $P$T0$1[12] @ 96 + 42 00000c 4550 .bits 0x45,8 + 43 ; $P$T0$1[13] @ 104 + 44 00000e 0020 .bits 0x20,8 + 45 ; $P$T0$1[14] @ 112 + 46 00000e 3320 .bits 0x33,8 + 47 ; $P$T0$1[15] @ 120 + 48 000010 0032 .bits 0x32,8 + 49 ; $P$T0$1[16] @ 128 + 50 000010 3532 .bits 0x35,8 + 51 ; $P$T0$1[17] @ 136 + 52 000012 0020 .bits 0x20,8 + 53 ; $P$T0$1[18] @ 144 + 54 000012 6920 .bits 0x69,8 + 55 ; $P$T0$1[19] @ 152 + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 2 + + 56 000014 006E .bits 0x6e,8 + 57 ; $P$T0$1[20] @ 160 + 58 000014 206E .bits 0x20,8 + 59 ; $P$T0$1[21] @ 168 + 60 000016 0046 .bits 0x46,8 + 61 ; $P$T0$1[22] @ 176 + 62 000016 6146 .bits 0x61,8 + 63 ; $P$T0$1[23] @ 184 + 64 000018 006C .bits 0x6c,8 + 65 ; $P$T0$1[24] @ 192 + 66 000018 6C6C .bits 0x6c,8 + 67 ; $P$T0$1[25] @ 200 + 68 00001a 0020 .bits 0x20,8 + 69 ; $P$T0$1[26] @ 208 + 70 00001a 3220 .bits 0x32,8 + 71 ; $P$T0$1[27] @ 216 + 72 00001c 0030 .bits 0x30,8 + 73 ; $P$T0$1[28] @ 224 + 74 00001c 3230 .bits 0x32,8 + 75 ; $P$T0$1[29] @ 232 + 76 00001e 0031 .bits 0x31,8 + 77 ; $P$T0$1[30] @ 240 + 78 00001e 2131 .bits 0x21,8 + 79 ; $P$T0$1[31] @ 248 + 80 000020 0000 .bits 0,8 + 81 ; $P$T0$1[32] @ 256 + 82 + 83 $C$DW$1 .dwtag DW_TAG_variable + 84 .dwattr $C$DW$1, DW_AT_name("$P$T0$1") + 85 .dwattr $C$DW$1, DW_AT_TI_symbol_name("$P$T0$1") + 86 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$122) + 87 .dwattr $C$DW$1, DW_AT_location[DW_OP_addr $P$T0$1] + 88 .dwattr $C$DW$1, DW_AT_decl_file("../problem2.c") + 89 .dwattr $C$DW$1, DW_AT_decl_line(0x14) + 90 .dwattr $C$DW$1, DW_AT_decl_column(0x0a) + 91 + 92 + 93 $C$DW$2 .dwtag DW_TAG_subprogram + 94 .dwattr $C$DW$2, DW_AT_name("islower") + 95 .dwattr $C$DW$2, DW_AT_TI_symbol_name("islower") + 96 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$10) + 97 .dwattr $C$DW$2, DW_AT_declaration + 98 .dwattr $C$DW$2, DW_AT_external + 99 .dwattr $C$DW$2, DW_AT_decl_file("C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\in + 100 .dwattr $C$DW$2, DW_AT_decl_line(0x31) + 101 .dwattr $C$DW$2, DW_AT_decl_column(0x0c) + 102 $C$DW$3 .dwtag DW_TAG_formal_parameter + 103 .dwattr $C$DW$3, DW_AT_type(*$C$DW$T$10) + 104 + 105 .dwendtag $C$DW$2 + 106 + 107 + 108 $C$DW$4 .dwtag DW_TAG_subprogram + 109 .dwattr $C$DW$4, DW_AT_name("printf") + 110 .dwattr $C$DW$4, DW_AT_TI_symbol_name("printf") + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 3 + + 111 .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$10) + 112 .dwattr $C$DW$4, DW_AT_declaration + 113 .dwattr $C$DW$4, DW_AT_external + 114 .dwattr $C$DW$4, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/in + 115 .dwattr $C$DW$4, DW_AT_decl_line(0xf6) + 116 .dwattr $C$DW$4, DW_AT_decl_column(0x19) + 117 $C$DW$5 .dwtag DW_TAG_formal_parameter + 118 .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$39) + 119 + 120 $C$DW$6 .dwtag DW_TAG_unspecified_parameters + 121 + 122 .dwendtag $C$DW$4 + 123 + 124 ; C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\bin\acpia430.exe -@C:\\Users\\LIBRAR + 125 000000 .sect ".text:main" + 126 .clink + 127 .global main + 128 + 129 $C$DW$7 .dwtag DW_TAG_subprogram + 130 .dwattr $C$DW$7, DW_AT_name("main") + 131 .dwattr $C$DW$7, DW_AT_low_pc(main) + 132 .dwattr $C$DW$7, DW_AT_high_pc(0x00) + 133 .dwattr $C$DW$7, DW_AT_TI_symbol_name("main") + 134 .dwattr $C$DW$7, DW_AT_external + 135 .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$10) + 136 .dwattr $C$DW$7, DW_AT_TI_begin_file("../problem2.c") + 137 .dwattr $C$DW$7, DW_AT_TI_begin_line(0x12) + 138 .dwattr $C$DW$7, DW_AT_TI_begin_column(0x05) + 139 .dwattr $C$DW$7, DW_AT_decl_file("../problem2.c") + 140 .dwattr $C$DW$7, DW_AT_decl_line(0x12) + 141 .dwattr $C$DW$7, DW_AT_decl_column(0x05) + 142 .dwattr $C$DW$7, DW_AT_TI_max_frame_size(0x30) + 143 .dwpsn file "../problem2.c",line 18,column 11,is_stmt,address main,isa 0 + 144 + 145 .dwfde $C$DW$CIE, main + 146 + 147 ;***************************************************************************** + 148 ;* FUNCTION NAME: main * + 149 ;* * + 150 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + 151 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 152 ;* Local Frame Size : 4 Args + 42 Auto + 0 Save = 46 byte * + 153 ;***************************************************************************** + 154 000000 main: + 155 ;* --------------------------------------------------------------------------* + 156 .dwcfi cfa_offset, 2 + 157 .dwcfi save_reg_to_mem, 16, -2 + 158 000000 8031 SUB.W #46,SP ; [] + 000002 002E + 159 .dwcfi cfa_offset, 48 + 160 $C$DW$8 .dwtag DW_TAG_variable + 161 .dwattr $C$DW$8, DW_AT_name("msg") + 162 .dwattr $C$DW$8, DW_AT_TI_symbol_name("msg") + 163 .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$123) + 164 .dwattr $C$DW$8, DW_AT_location[DW_OP_breg1 4] + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 4 + + 165 + 166 $C$DW$9 .dwtag DW_TAG_variable + 167 .dwattr $C$DW$9, DW_AT_name("i") + 168 .dwattr $C$DW$9, DW_AT_TI_symbol_name("i") + 169 .dwattr $C$DW$9, DW_AT_type(*$C$DW$T$10) + 170 .dwattr $C$DW$9, DW_AT_location[DW_OP_breg1 38] + 171 + 172 $C$DW$10 .dwtag DW_TAG_variable + 173 .dwattr $C$DW$10, DW_AT_name("size") + 174 .dwattr $C$DW$10, DW_AT_TI_symbol_name("size") + 175 .dwattr $C$DW$10, DW_AT_type(*$C$DW$T$70) + 176 .dwattr $C$DW$10, DW_AT_location[DW_OP_breg1 40] + 177 + 178 .dwpsn file "../problem2.c",line 20,column 10,is_stmt,isa 0 + 179 000004 410C MOV.W SP,r12 ; [] |20| + 180 000006 522C ADD.W #4,r12 ; [] |20| + 181 000008 403D MOV.W #$P$T0$1+0,r13 ; [] |20| + 00000a 0000! + 182 00000c 403E MOV.W #33,r14 ; [] |20| + 00000e 0021 + 183 $C$DW$11 .dwtag DW_TAG_TI_branch + 184 .dwattr $C$DW$11, DW_AT_low_pc(0x00) + 185 .dwattr $C$DW$11, DW_AT_name("memcpy") + 186 .dwattr $C$DW$11, DW_AT_TI_call + 187 + 188 000010 12B0 CALL #memcpy ; [] |20| + 000012 0000! + 189 ; [] |20| + 190 .dwpsn file "../problem2.c",line 21,column 17,is_stmt,isa 0 + 191 000014 40B1 MOV.W #33,40(SP) ; [] |21| + 000016 0021 + 000018 0028 + 192 .dwpsn file "../problem2.c",line 22,column 10,is_stmt,isa 0 + 193 00001a 4381 MOV.W #0,38(SP) ; [] |22| + 00001c 0026 + 194 .dwpsn file "../problem2.c",line 22,column 15,is_stmt,isa 0 + 195 00001e 9191 CMP.W 40(SP),38(SP) ; [] |22| + 000020 0028 + 000022 0026 + 196 000024 2C28 JHS $C$L4 ; [] |22| + 197 ; [] |22| + 198 ;* --------------------------------------------------------------------------* + 199 ;* BEGIN LOOP $C$L1 + 200 ;* + 201 ;* Loop source line : 22 + 202 ;* Loop closing brace source line : 30 + 203 ;* Known Minimum Trip Count : 1 + 204 ;* Known Maximum Trip Count : 4294967295 + 205 ;* Known Max Trip Count Factor : 1 + 206 ;* --------------------------------------------------------------------------* + 207 $C$L1: + 208 + 209 $C$DW$12 .dwtag DW_TAG_lexical_block + 210 .dwattr $C$DW$12, DW_AT_low_pc(0x00) + 211 .dwattr $C$DW$12, DW_AT_high_pc(0x00) + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 5 + + 212 $C$DW$13 .dwtag DW_TAG_variable + 213 .dwattr $C$DW$13, DW_AT_name("str_as_int") + 214 .dwattr $C$DW$13, DW_AT_TI_symbol_name("str_as_int") + 215 .dwattr $C$DW$13, DW_AT_type(*$C$DW$T$10) + 216 .dwattr $C$DW$13, DW_AT_location[DW_OP_breg1 42] + 217 + 218 $C$DW$14 .dwtag DW_TAG_variable + 219 .dwattr $C$DW$14, DW_AT_name("str") + 220 .dwattr $C$DW$14, DW_AT_TI_symbol_name("str") + 221 .dwattr $C$DW$14, DW_AT_type(*$C$DW$T$6) + 222 .dwattr $C$DW$14, DW_AT_location[DW_OP_breg1 44] + 223 + 224 .dwpsn file "../problem2.c",line 23,column 18,is_stmt,isa 0 + 225 000026 410F MOV.W SP,r15 ; [] |23| + 226 000028 522F ADD.W #4,r15 ; [] |23| + 227 00002a 511F ADD.W 38(SP),r15 ; [] |23| + 00002c 0026 + 228 00002e 4FE1 MOV.B @r15,44(SP) ; [] |23| + 000030 002C + 229 .dwpsn file "../problem2.c",line 24,column 23,is_stmt,isa 0 + 230 000032 415F MOV.B 44(SP),r15 ; [] |24| + 000034 002C + 231 000036 4F81 MOV.W r15,42(SP) ; [] |24| + 000038 002A + 232 .dwpsn file "../problem2.c",line 26,column 9,is_stmt,isa 0 + 233 00003a 415C MOV.B 44(SP),r12 ; [] |26| + 00003c 002C + 234 $C$DW$15 .dwtag DW_TAG_TI_branch + 235 .dwattr $C$DW$15, DW_AT_low_pc(0x00) + 236 .dwattr $C$DW$15, DW_AT_name("islower") + 237 .dwattr $C$DW$15, DW_AT_TI_call + 238 + 239 00003e 12B0 CALL #islower ; [] |26| + 000040 0000! + 240 ; [] |26| + 241 000042 930C TST.W r12 ; [] |26| + 242 000044 240B JEQ $C$L2 ; [] |26| + 243 ; [] |26| + 244 ;* --------------------------------------------------------------------------* + 245 .dwpsn file "../problem2.c",line 27,column 13,is_stmt,isa 0 + 246 000046 415E MOV.B 42(SP),r14 ; [] |27| + 000048 002A + 247 00004a 807E SUB.B #32,r14 ; [] |27| + 00004c 0020 + 248 00004e 410F MOV.W SP,r15 ; [] |27| + 249 000050 522F ADD.W #4,r15 ; [] |27| + 250 000052 511F ADD.W 38(SP),r15 ; [] |27| + 000054 0026 + 251 000056 4ECF MOV.B r14,0(r15) ; [] |27| + 000058 0000 + 252 00005a 3C07 JMP $C$L3 ; [] + 253 ; [] + 254 ;* --------------------------------------------------------------------------* + 255 00005c $C$L2: + 256 .dwpsn file "../problem2.c",line 29,column 14,is_stmt,isa 0 + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 6 + + 257 00005c 410F MOV.W SP,r15 ; [] |29| + 258 00005e 522F ADD.W #4,r15 ; [] |29| + 259 000060 511F ADD.W 38(SP),r15 ; [] |29| + 000062 0026 + 260 000064 41DF MOV.B 42(SP),0(r15) ; [] |29| + 000066 002A + 000068 0000 + 261 ;* --------------------------------------------------------------------------* + 262 $C$L3: + 263 .dwendtag $C$DW$12 + 264 + 265 .dwpsn file "../problem2.c",line 22,column 24,is_stmt,isa 0 + 266 00006a 5391 ADD.W #1,38(SP) ; [] |22| + 00006c 0026 + 267 .dwpsn file "../problem2.c",line 22,column 15,is_stmt,isa 0 + 268 00006e 9191 CMP.W 40(SP),38(SP) ; [] |22| + 000070 0028 + 000072 0026 + 269 000074 2BD8 JLO $C$L1 ; [] |22| + 270 ; [] |22| + 271 ;* --------------------------------------------------------------------------* + 272 000076 $C$L4: + 273 .dwpsn file "../problem2.c",line 31,column 5,is_stmt,isa 0 + 274 000076 40B1 MOV.W #$C$SL1+0,0(SP) ; [] |31| + 000078 0000! + 00007a 0000 + 275 00007c 410F MOV.W SP,r15 ; [] |31| + 276 00007e 522F ADD.W #4,r15 ; [] |31| + 277 000080 4F81 MOV.W r15,2(SP) ; [] |31| + 000082 0002 + 278 $C$DW$16 .dwtag DW_TAG_TI_branch + 279 .dwattr $C$DW$16, DW_AT_low_pc(0x00) + 280 .dwattr $C$DW$16, DW_AT_name("printf") + 281 .dwattr $C$DW$16, DW_AT_TI_call + 282 + 283 000084 12B0 CALL #printf ; [] |31| + 000086 0000! + 284 ; [] |31| + 285 .dwpsn file "../problem2.c",line 32,column 1,is_stmt,isa 0 + 286 000088 430C MOV.W #0,r12 ; [] |32| + 287 00008a 5031 ADD.W #46,SP ; [] + 00008c 002E + 288 .dwcfi cfa_offset, 2 + 289 $C$DW$17 .dwtag DW_TAG_TI_branch + 290 .dwattr $C$DW$17, DW_AT_low_pc(0x00) + 291 .dwattr $C$DW$17, DW_AT_TI_return + 292 + 293 00008e 4130 RET ; [] + 294 ; [] + 295 .dwattr $C$DW$7, DW_AT_TI_end_file("../problem2.c") + 296 .dwattr $C$DW$7, DW_AT_TI_end_line(0x20) + 297 .dwattr $C$DW$7, DW_AT_TI_end_column(0x01) + 298 .dwendentry + 299 .dwendtag $C$DW$7 + 300 + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 7 + + 301 ;****************************************************************************** + 302 ;* STRINGS * + 303 ;****************************************************************************** + 304 000000 .sect ".const:.string" + 305 .align 2 + 306 000000 0025 $C$SL1: .string "%s",10,0 + 000001 0073 + 000002 000A + 000003 0000 + 307 ;***************************************************************************** + 308 ;* UNDEFINED EXTERNAL REFERENCES * + 309 ;***************************************************************************** + 310 .global islower + 311 .global printf + 312 .global memcpy + 313 + 314 ;****************************************************************************** + 315 ;* BUILD ATTRIBUTES * + 316 ;****************************************************************************** + 317 .battr "TI", Tag_File, 1, Tag_LPM_INFO(1) + 318 .battr "TI", Tag_File, 1, Tag_PORTS_INIT_INFO("012345678901ABCDEFGHIJ0000000000001111000000000 + 319 .battr "TI", Tag_File, 1, Tag_LEA_INFO(1) + 320 .battr "TI", Tag_File, 1, Tag_HW_MPY32_INFO(2) + 321 .battr "TI", Tag_File, 1, Tag_HW_MPY_ISR_INFO(1) + 322 .battr "TI", Tag_File, 1, Tag_HW_MPY_INLINE_INFO(1) + 323 .battr "mspabi", Tag_File, 1, Tag_enum_size(3) + 324 + 325 ;****************************************************************************** + 326 ;* TYPE INFORMATION * + 327 ;****************************************************************************** + 328 + 329 $C$DW$T$21 .dwtag DW_TAG_structure_type + 330 .dwattr $C$DW$T$21, DW_AT_byte_size(0x10) + 331 $C$DW$18 .dwtag DW_TAG_member + 332 .dwattr $C$DW$18, DW_AT_type(*$C$DW$T$14) + 333 .dwattr $C$DW$18, DW_AT_name("__max_align1") + 334 .dwattr $C$DW$18, DW_AT_TI_symbol_name("__max_align1") + 335 .dwattr $C$DW$18, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 336 .dwattr $C$DW$18, DW_AT_accessibility(DW_ACCESS_public) + 337 .dwattr $C$DW$18, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 338 .dwattr $C$DW$18, DW_AT_decl_line(0x7b) + 339 .dwattr $C$DW$18, DW_AT_decl_column(0x0c) + 340 + 341 $C$DW$19 .dwtag DW_TAG_member + 342 .dwattr $C$DW$19, DW_AT_type(*$C$DW$T$18) + 343 .dwattr $C$DW$19, DW_AT_name("__max_align2") + 344 .dwattr $C$DW$19, DW_AT_TI_symbol_name("__max_align2") + 345 .dwattr $C$DW$19, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 346 .dwattr $C$DW$19, DW_AT_accessibility(DW_ACCESS_public) + 347 .dwattr $C$DW$19, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 348 .dwattr $C$DW$19, DW_AT_decl_line(0x7c) + 349 .dwattr $C$DW$19, DW_AT_decl_column(0x0e) + 350 + 351 .dwattr $C$DW$T$21, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 352 .dwattr $C$DW$T$21, DW_AT_decl_line(0x7a) + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 8 + + 353 .dwattr $C$DW$T$21, DW_AT_decl_column(0x10) + 354 .dwendtag $C$DW$T$21 + 355 + 356 $C$DW$T$24 .dwtag DW_TAG_typedef + 357 .dwattr $C$DW$T$24, DW_AT_name("__max_align_t") + 358 .dwattr $C$DW$T$24, DW_AT_type(*$C$DW$T$21) + 359 .dwattr $C$DW$T$24, DW_AT_language(DW_LANG_C) + 360 .dwattr $C$DW$T$24, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 361 .dwattr $C$DW$T$24, DW_AT_decl_line(0x7d) + 362 .dwattr $C$DW$T$24, DW_AT_decl_column(0x03) + 363 + 364 $C$DW$T$2 .dwtag DW_TAG_unspecified_type + 365 .dwattr $C$DW$T$2, DW_AT_name("void") + 366 + 367 + 368 $C$DW$T$25 .dwtag DW_TAG_subroutine_type + 369 .dwattr $C$DW$T$25, DW_AT_language(DW_LANG_C) + 370 .dwendtag $C$DW$T$25 + 371 + 372 $C$DW$T$26 .dwtag DW_TAG_pointer_type + 373 .dwattr $C$DW$T$26, DW_AT_type(*$C$DW$T$25) + 374 .dwattr $C$DW$T$26, DW_AT_address_class(0x10) + 375 + 376 $C$DW$T$27 .dwtag DW_TAG_typedef + 377 .dwattr $C$DW$T$27, DW_AT_name("__SFR_FARPTR") + 378 .dwattr $C$DW$T$27, DW_AT_type(*$C$DW$T$26) + 379 .dwattr $C$DW$T$27, DW_AT_language(DW_LANG_C) + 380 .dwattr $C$DW$T$27, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430f5529.h") + 381 .dwattr $C$DW$T$27, DW_AT_decl_line(0x4a) + 382 .dwattr $C$DW$T$27, DW_AT_decl_column(0x11) + 383 + 384 $C$DW$T$4 .dwtag DW_TAG_base_type + 385 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + 386 .dwattr $C$DW$T$4, DW_AT_name("bool") + 387 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01) + 388 + 389 $C$DW$T$5 .dwtag DW_TAG_base_type + 390 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char) + 391 .dwattr $C$DW$T$5, DW_AT_name("signed char") + 392 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01) + 393 + 394 $C$DW$T$28 .dwtag DW_TAG_typedef + 395 .dwattr $C$DW$T$28, DW_AT_name("__int8_t") + 396 .dwattr $C$DW$T$28, DW_AT_type(*$C$DW$T$5) + 397 .dwattr $C$DW$T$28, DW_AT_language(DW_LANG_C) + 398 .dwattr $C$DW$T$28, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 399 .dwattr $C$DW$T$28, DW_AT_decl_line(0x36) + 400 .dwattr $C$DW$T$28, DW_AT_decl_column(0x16) + 401 + 402 $C$DW$T$29 .dwtag DW_TAG_typedef + 403 .dwattr $C$DW$T$29, DW_AT_name("__int_least8_t") + 404 .dwattr $C$DW$T$29, DW_AT_type(*$C$DW$T$28) + 405 .dwattr $C$DW$T$29, DW_AT_language(DW_LANG_C) + 406 .dwattr $C$DW$T$29, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 407 .dwattr $C$DW$T$29, DW_AT_decl_line(0x5a) + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 9 + + 408 .dwattr $C$DW$T$29, DW_AT_decl_column(0x12) + 409 + 410 $C$DW$T$6 .dwtag DW_TAG_base_type + 411 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char) + 412 .dwattr $C$DW$T$6, DW_AT_name("unsigned char") + 413 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01) + 414 + 415 $C$DW$T$22 .dwtag DW_TAG_pointer_type + 416 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$6) + 417 .dwattr $C$DW$T$22, DW_AT_address_class(0x10) + 418 + 419 $C$DW$T$30 .dwtag DW_TAG_typedef + 420 .dwattr $C$DW$T$30, DW_AT_name("__uint8_t") + 421 .dwattr $C$DW$T$30, DW_AT_type(*$C$DW$T$6) + 422 .dwattr $C$DW$T$30, DW_AT_language(DW_LANG_C) + 423 .dwattr $C$DW$T$30, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 424 .dwattr $C$DW$T$30, DW_AT_decl_line(0x37) + 425 .dwattr $C$DW$T$30, DW_AT_decl_column(0x18) + 426 + 427 $C$DW$T$31 .dwtag DW_TAG_typedef + 428 .dwattr $C$DW$T$31, DW_AT_name("__sa_family_t") + 429 .dwattr $C$DW$T$31, DW_AT_type(*$C$DW$T$30) + 430 .dwattr $C$DW$T$31, DW_AT_language(DW_LANG_C) + 431 .dwattr $C$DW$T$31, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 432 .dwattr $C$DW$T$31, DW_AT_decl_line(0x47) + 433 .dwattr $C$DW$T$31, DW_AT_decl_column(0x13) + 434 + 435 $C$DW$T$32 .dwtag DW_TAG_typedef + 436 .dwattr $C$DW$T$32, DW_AT_name("__uint_least8_t") + 437 .dwattr $C$DW$T$32, DW_AT_type(*$C$DW$T$30) + 438 .dwattr $C$DW$T$32, DW_AT_language(DW_LANG_C) + 439 .dwattr $C$DW$T$32, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 440 .dwattr $C$DW$T$32, DW_AT_decl_line(0x74) + 441 .dwattr $C$DW$T$32, DW_AT_decl_column(0x13) + 442 + 443 $C$DW$T$7 .dwtag DW_TAG_base_type + 444 .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char) + 445 .dwattr $C$DW$T$7, DW_AT_name("wchar_t") + 446 .dwattr $C$DW$T$7, DW_AT_byte_size(0x02) + 447 + 448 $C$DW$T$8 .dwtag DW_TAG_base_type + 449 .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed) + 450 .dwattr $C$DW$T$8, DW_AT_name("short") + 451 .dwattr $C$DW$T$8, DW_AT_byte_size(0x02) + 452 + 453 $C$DW$T$9 .dwtag DW_TAG_base_type + 454 .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned) + 455 .dwattr $C$DW$T$9, DW_AT_name("unsigned short") + 456 .dwattr $C$DW$T$9, DW_AT_byte_size(0x02) + 457 + 458 $C$DW$T$10 .dwtag DW_TAG_base_type + 459 .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed) + 460 .dwattr $C$DW$T$10, DW_AT_name("int") + 461 .dwattr $C$DW$T$10, DW_AT_byte_size(0x02) + 462 + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 10 + + 463 $C$DW$T$33 .dwtag DW_TAG_typedef + 464 .dwattr $C$DW$T$33, DW_AT_name("_Mbstatet") + 465 .dwattr $C$DW$T$33, DW_AT_type(*$C$DW$T$10) + 466 .dwattr $C$DW$T$33, DW_AT_language(DW_LANG_C) + 467 .dwattr $C$DW$T$33, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 468 .dwattr $C$DW$T$33, DW_AT_decl_line(0x8f) + 469 .dwattr $C$DW$T$33, DW_AT_decl_column(0x0d) + 470 + 471 $C$DW$T$34 .dwtag DW_TAG_typedef + 472 .dwattr $C$DW$T$34, DW_AT_name("__mbstate_t") + 473 .dwattr $C$DW$T$34, DW_AT_type(*$C$DW$T$33) + 474 .dwattr $C$DW$T$34, DW_AT_language(DW_LANG_C) + 475 .dwattr $C$DW$T$34, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 476 .dwattr $C$DW$T$34, DW_AT_decl_line(0x92) + 477 .dwattr $C$DW$T$34, DW_AT_decl_column(0x13) + 478 + 479 $C$DW$T$35 .dwtag DW_TAG_typedef + 480 .dwattr $C$DW$T$35, DW_AT_name("__accmode_t") + 481 .dwattr $C$DW$T$35, DW_AT_type(*$C$DW$T$10) + 482 .dwattr $C$DW$T$35, DW_AT_language(DW_LANG_C) + 483 .dwattr $C$DW$T$35, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 484 .dwattr $C$DW$T$35, DW_AT_decl_line(0x3b) + 485 .dwattr $C$DW$T$35, DW_AT_decl_column(0x0e) + 486 + 487 $C$DW$T$45 .dwtag DW_TAG_typedef + 488 .dwattr $C$DW$T$45, DW_AT_name("__cpulevel_t") + 489 .dwattr $C$DW$T$45, DW_AT_type(*$C$DW$T$10) + 490 .dwattr $C$DW$T$45, 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.dwendtag $C$DW$T$23 + 1282 + 1283 $C$DW$T$129 .dwtag DW_TAG_typedef + 1284 .dwattr $C$DW$T$129, DW_AT_name("FILE") + 1285 .dwattr $C$DW$T$129, DW_AT_type(*$C$DW$T$23) + 1286 .dwattr $C$DW$T$129, DW_AT_language(DW_LANG_C) + 1287 .dwattr $C$DW$T$129, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 25 + + 1288 .dwattr $C$DW$T$129, DW_AT_decl_line(0x5c) + 1289 .dwattr $C$DW$T$129, DW_AT_decl_column(0x18) + 1290 + 1291 + 1292 $C$DW$T$20 .dwtag DW_TAG_structure_type + 1293 .dwattr $C$DW$T$20, DW_AT_name("__timer") + 1294 .dwattr $C$DW$T$20, DW_AT_declaration + 1295 .dwattr $C$DW$T$20, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1296 .dwattr $C$DW$T$20, DW_AT_decl_line(0x4b) + 1297 .dwattr $C$DW$T$20, DW_AT_decl_column(0x10) + 1298 .dwendtag $C$DW$T$20 + 1299 + 1300 $C$DW$T$130 .dwtag DW_TAG_pointer_type + 1301 .dwattr $C$DW$T$130, DW_AT_type(*$C$DW$T$20) + 1302 .dwattr $C$DW$T$130, DW_AT_address_class(0x10) + 1303 + 1304 $C$DW$T$131 .dwtag DW_TAG_typedef + 1305 .dwattr $C$DW$T$131, DW_AT_name("__timer_t") + 1306 .dwattr $C$DW$T$131, DW_AT_type(*$C$DW$T$130) + 1307 .dwattr $C$DW$T$131, DW_AT_language(DW_LANG_C) + 1308 .dwattr $C$DW$T$131, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1309 .dwattr $C$DW$T$131, DW_AT_decl_line(0x4b) + 1310 .dwattr $C$DW$T$131, DW_AT_decl_column(0x19) + 1311 + 1312 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C) + 1313 + 1314 ;*************************************************************** + 1315 ;* DWARF CIE ENTRIES * + 1316 ;*************************************************************** + 1317 + 1318 $C$DW$CIE .dwcie 16 + 1319 .dwcfi cfa_register, 1 + 1320 .dwcfi cfa_offset, 0 + 1321 .dwcfi same_value, 0 + 1322 .dwcfi same_value, 1 + 1323 .dwcfi same_value, 3 + 1324 .dwcfi same_value, 4 + 1325 .dwcfi same_value, 5 + 1326 .dwcfi same_value, 6 + 1327 .dwcfi same_value, 7 + 1328 .dwcfi same_value, 8 + 1329 .dwcfi same_value, 9 + 1330 .dwcfi same_value, 10 + 1331 .dwendentry + 1332 + 1333 ;*************************************************************** + 1334 ;* DWARF REGISTER MAP * + 1335 ;*************************************************************** + 1336 + 1337 $C$DW$28 .dwtag DW_TAG_TI_assign_register + 1338 .dwattr $C$DW$28, DW_AT_name("PC") + 1339 .dwattr $C$DW$28, DW_AT_location[DW_OP_reg0] + 1340 + 1341 $C$DW$29 .dwtag DW_TAG_TI_assign_register + 1342 .dwattr $C$DW$29, DW_AT_name("SP") + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 26 + + 1343 .dwattr $C$DW$29, DW_AT_location[DW_OP_reg1] + 1344 + 1345 $C$DW$30 .dwtag DW_TAG_TI_assign_register + 1346 .dwattr $C$DW$30, DW_AT_name("SR") + 1347 .dwattr $C$DW$30, DW_AT_location[DW_OP_reg2] + 1348 + 1349 $C$DW$31 .dwtag DW_TAG_TI_assign_register + 1350 .dwattr $C$DW$31, DW_AT_name("CG") + 1351 .dwattr $C$DW$31, DW_AT_location[DW_OP_reg3] + 1352 + 1353 $C$DW$32 .dwtag DW_TAG_TI_assign_register + 1354 .dwattr $C$DW$32, DW_AT_name("r4") + 1355 .dwattr $C$DW$32, DW_AT_location[DW_OP_reg4] + 1356 + 1357 $C$DW$33 .dwtag DW_TAG_TI_assign_register + 1358 .dwattr $C$DW$33, DW_AT_name("r5") + 1359 .dwattr $C$DW$33, DW_AT_location[DW_OP_reg5] + 1360 + 1361 $C$DW$34 .dwtag DW_TAG_TI_assign_register + 1362 .dwattr $C$DW$34, DW_AT_name("r6") + 1363 .dwattr $C$DW$34, DW_AT_location[DW_OP_reg6] + 1364 + 1365 $C$DW$35 .dwtag DW_TAG_TI_assign_register + 1366 .dwattr $C$DW$35, DW_AT_name("r7") + 1367 .dwattr $C$DW$35, DW_AT_location[DW_OP_reg7] + 1368 + 1369 $C$DW$36 .dwtag DW_TAG_TI_assign_register + 1370 .dwattr $C$DW$36, DW_AT_name("r8") + 1371 .dwattr $C$DW$36, DW_AT_location[DW_OP_reg8] + 1372 + 1373 $C$DW$37 .dwtag DW_TAG_TI_assign_register + 1374 .dwattr $C$DW$37, DW_AT_name("r9") + 1375 .dwattr $C$DW$37, DW_AT_location[DW_OP_reg9] + 1376 + 1377 $C$DW$38 .dwtag DW_TAG_TI_assign_register + 1378 .dwattr $C$DW$38, DW_AT_name("r10") + 1379 .dwattr $C$DW$38, DW_AT_location[DW_OP_reg10] + 1380 + 1381 $C$DW$39 .dwtag DW_TAG_TI_assign_register + 1382 .dwattr $C$DW$39, DW_AT_name("r11") + 1383 .dwattr $C$DW$39, DW_AT_location[DW_OP_reg11] + 1384 + 1385 $C$DW$40 .dwtag DW_TAG_TI_assign_register + 1386 .dwattr $C$DW$40, DW_AT_name("r12") + 1387 .dwattr $C$DW$40, DW_AT_location[DW_OP_reg12] + 1388 + 1389 $C$DW$41 .dwtag DW_TAG_TI_assign_register + 1390 .dwattr $C$DW$41, DW_AT_name("r13") + 1391 .dwattr $C$DW$41, DW_AT_location[DW_OP_reg13] + 1392 + 1393 $C$DW$42 .dwtag DW_TAG_TI_assign_register + 1394 .dwattr $C$DW$42, DW_AT_name("r14") + 1395 .dwattr $C$DW$42, DW_AT_location[DW_OP_reg14] + 1396 + 1397 $C$DW$43 .dwtag DW_TAG_TI_assign_register + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:36:09 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{758C701A-39DA-4049-A45A-556A10E78F50} PAGE 27 + + 1398 .dwattr $C$DW$43, DW_AT_name("r15") + 1399 .dwattr $C$DW$43, DW_AT_location[DW_OP_reg15] + 1400 + 1401 $C$DW$44 .dwtag DW_TAG_TI_assign_register + 1402 .dwattr $C$DW$44, DW_AT_name("CIE_RETA") + 1403 .dwattr $C$DW$44, DW_AT_location[DW_OP_reg16] + 1404 + 1405 .dwendtag $C$DW$CU + 1406 + +No Assembly Errors, No Assembly Warnings diff --git a/CPE325/L1_Problem2/Debug/problem2.obj b/CPE325/L1_Problem2/Debug/problem2.obj new file mode 100644 index 0000000..e11cab2 Binary files /dev/null and b/CPE325/L1_Problem2/Debug/problem2.obj differ diff --git a/CPE325/L1_Problem2/Debug/sources.mk b/CPE325/L1_Problem2/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/L1_Problem2/Debug/subdir_rules.mk b/CPE325/L1_Problem2/Debug/subdir_rules.mk new file mode 100644 index 0000000..107ac90 --- /dev/null +++ b/CPE325/L1_Problem2/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/L1_Problem2" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/L1_Problem2/problem2.c b/CPE325/L1_Problem2/problem2.c new file mode 100644 index 0000000..f421e85 --- /dev/null +++ b/CPE325/L1_Problem2/problem2.c @@ -0,0 +1,32 @@ +/*------------------------------------------------------------------------------ + * File: problem2.c + * Function: Change lowercase letters to uppercase letters + * Description: This C program changes the message “Welcome to CPE 325 in Fall 2021!” to + * "WELCOME TO CPE 325 IN FALL 2021!" + * Input: None + * Output: "WELCOME TO CPE 325 IN FALL 2021!" + * Author(s): Noah Woodlee + * Lab Section: 09 + * Date: Aug 20, 2021 + *----------------------------------------------------------------------------*/ +#include +#include +#include + + + +int main(){ + int i; + char msg[] ="Welcome to CPE 325 in Fall 2021!"; + size_t size = sizeof(msg)/sizeof(msg[0]); // size of msg[] + for (i=0; i < size;i++){ // loop over the array + char str = msg[i]; // store the character in msg[i] as a char in str + int str_as_int=(int)str; // covert string to an integer + // check if str is lower-case + if (islower(str)){ + msg[i]=str_as_int-32; // if it is, subtract 32 from the character value + } + else msg[i]=str_as_int; //else keep the string the same + } + printf("%s\n",msg); // print output +} diff --git a/CPE325/L1_Problem2/targetConfigs/MSP430F5529.ccxml b/CPE325/L1_Problem2/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/L1_Problem2/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/L1_Problem2/targetConfigs/readme.txt b/CPE325/L1_Problem2/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/L1_Problem2/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/L2_P1/Debug/L2_P1.map b/CPE325/L2_P1/Debug/L2_P1.map new file mode 100644 index 0000000..82516c1 --- /dev/null +++ b/CPE325/L2_P1/Debug/L2_P1.map @@ -0,0 +1,2441 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Sep 3 14:07:12 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00008bee + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 00000494 00001b6c RWIX + FLASH 00004400 0000bb80 00005198 000069e8 RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 0000264c 000000fe UNINITIALIZED + 0000264c 00000078 rts430_eabi.lib : defs.c.obj (.data:_ftable) + 000026c4 0000004e : host_device.c.obj (.data:_device) + 00002712 00000028 : host_device.c.obj (.data:_stream) + 0000273a 00000002 : exit_gvars.c.obj (.data:__TI_cleanup_ptr) + 0000273c 00000002 : exit_gvars.c.obj (.data:__TI_dtors_ptr) + 0000273e 00000002 : _lock.c.obj (.data:_lock) + 00002740 00000002 : _lock.c.obj (.data:_unlock) + 00002742 00000002 : defs.c.obj (.data) + 00002744 00000002 : errno.c.obj (.data) + 00002746 00000002 : exit.c.obj (.data) + 00002748 00000002 : memory.c.obj (.data) + +.bss 0 0000274a 000000aa UNINITIALIZED + 0000274a 000000a0 (.common:__TI_tmpnams) + 000027ea 00000008 (.common:parmbuf) + 000027f2 00000002 rts430_eabi.lib : memory.c.obj (.bss) + +.sysmem 0 00002400 0000012c UNINITIALIZED + 00002400 00000008 rts430_eabi.lib : memory.c.obj (.sysmem) + 00002408 00000124 --HOLE-- + +.cio 0 0000252c 00000120 UNINITIALIZED + 0000252c 00000120 rts430_eabi.lib : trgmsg.c.obj (.cio) + +.stack 0 00004360 000000a0 UNINITIALIZED + 00004360 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 00004362 0000009e --HOLE-- + +.text 0 00004400 00004978 + 00004400 00000736 rts430_eabi.lib : addd.c.obj (.text:__mspabi_addd) + 00004b36 00000478 : frcdivd.c.obj (.text:__TI_frcdivd) + 00004fae 00000360 : div64u.c.obj (.text:__mspabi_divull) + 0000530e 000002c0 : mpyd.c.obj (.text:__mspabi_mpyd) + 000055ce 0000028c p1.obj (.text:main) + 0000585a 00000288 rts430_eabi.lib : _printfi.c.obj (.text:__TI_printfi) + 00005ae2 0000026e : _printfi.c.obj (.text:_pproc_fgea) + 00005d50 00000252 : _printfi.c.obj (.text:_setfield) + 00005fa2 00000244 : _printfi.c.obj (.text:acvt) + 000061e6 00000238 : divd.c.obj (.text:__mspabi_divd) + 0000641e 000001ec : _printfi.c.obj (.text:_getarg_diouxp) + 0000660a 000001de : _printfi.c.obj (.text:ecvt) + 000067e8 000001c4 : _printfi.c.obj (.text:fcvt) + 000069ac 000001a6 : _printfi.c.obj (.text:_pconv_e) + 00006b52 00000174 : _printfi.c.obj (.text:_pconv_a) + 00006cc6 00000172 : frcmpyd.c.obj (.text:__TI_frcmpyd) + 00006e38 0000016a : s_scalbn.c.obj (.text:scalbn) + 00006fa2 0000014c : _printfi.c.obj (.text:_pproc_diouxp) + 000070ee 0000012e : _printfi.c.obj (.text:_ltostr) + 0000721c 000000f8 : _printfi.c.obj (.text:_pconv_g) + 00007314 000000f6 : memory.c.obj (.text:aligned_alloc) + 0000740a 000000ea : fputs.c.obj (.text:fputs) + 000074f4 000000e0 : _printfi.c.obj (.text:_pproc_fwp) + 000075d4 000000dc : cmpd.c.obj (.text:__mspabi_cmpd) + 000076b0 000000d2 : memory.c.obj (.text:free) + 00007782 000000d0 : setvbuf.c.obj (.text:setvbuf) + 00007852 000000c4 : _printfi.c.obj (.text:_pproc_wstr) + 00007916 000000b0 : s_frexp.c.obj (.text:frexp) + 000079c6 000000ac : fltlid.c.obj (.text:__mspabi_fltlid) + 00007a72 000000ac : _printfi.c.obj (.text:_pproc_str) + 00007b1e 00000092 : _printfi.c.obj (.text:_mcpy) + 00007bb0 00000090 : fputc.c.obj (.text:fputc) + 00007c40 0000008e : _printfi.c.obj (.text:_ecpy) + 00007cce 00000088 : hostlseek.c.obj (.text:HOSTlseek) + 00007d56 00000084 : _ltoa.c.obj (.text:__TI_ltoa) + 00007dda 0000007c : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00007e56 0000007a : _io_perm.c.obj (.text:__TI_wrt_ok) + 00007ed0 0000007a : _printfi.c.obj (.text:_pconv_f) + 00007f4a 00000072 : fclose.c.obj (.text:__TI_closefile) + 00007fbc 00000072 : fixdli.c.obj (.text:__mspabi_fixdli) + 0000802e 00000070 : cvtfd.c.obj (.text:__mspabi_cvtfd) + 0000809e 00000070 : fseek.c.obj (.text:fseek) + 0000810e 0000006a : hostrename.c.obj (.text:HOSTrename) + 00008178 00000068 : memory.c.obj (.text:split) + 000081e0 00000066 : hostopen.c.obj (.text:HOSTopen) + 00008246 00000062 : hostwrite.c.obj (.text:HOSTwrite) + 000082a8 00000062 : fflush.c.obj (.text:__TI_doflush) + 0000830a 00000060 : hostread.c.obj (.text:HOSTread) + 0000836a 0000005e : mult64_f5hw.asm.obj (.text:__mpyll) + 000083c8 0000005c : lsr32.asm.obj (.text:l_lsr_const) + 00008424 00000058 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 0000847c 00000058 : getdevice.c.obj (.text:getdevice) + 000084d4 00000058 : div32u.asm.obj (.text) + 0000852c 00000052 : atoi.c.obj (.text:atoi) + 0000857e 0000004e : _printfi.c.obj (.text:_fcpy) + 000085cc 0000004c : lsr16.asm.obj (.text) + 00008618 0000004a : asr64.c.obj (.text:__mspabi_srall) + 00008662 0000004a : close.c.obj (.text:close) + 000086ac 00000046 : lsr64.c.obj (.text:__mspabi_srlll) + 000086f2 00000044 : hostclose.c.obj (.text:HOSTclose) + 00008736 00000044 : lsl64.c.obj (.text:__mspabi_sllll) + 0000877a 00000044 : exit.c.obj (.text:exit) + 000087be 00000040 : hostunlink.c.obj (.text:HOSTunlink) + 000087fe 00000040 : div32s.asm.obj (.text) + 0000883e 0000003e : asr32.asm.obj (.text:l_asr_const) + 0000887c 0000003e : lsl32.asm.obj (.text:l_lsl_const) + 000088ba 0000003c : printf.c.obj (.text:printf) + 000088f6 00000034 : fopen.c.obj (.text:__TI_cleanup) + 0000892a 00000034 : getdevice.c.obj (.text:finddevice) + 0000895e 0000002e : trgmsg.c.obj (.text:__TI_writemsg) + 0000898c 0000002e : subd.c.obj (.text:__mspabi_subd) + 000089ba 0000002e : s_copysign.c.obj (.text:copysign) + 000089e8 0000002c : trgmsg.c.obj (.text:__TI_readmsg) + 00008a14 0000002c : asr16.asm.obj (.text) + 00008a40 0000002c : lsl16.asm.obj (.text) + 00008a6c 0000002c : strncpy.c.obj (.text:strncpy) + 00008a98 0000002a : negd.c.obj (.text:__mspabi_negd) + 00008ac2 00000028 : mult3264_f5hw.asm.obj (.text:__mpyull) + 00008aea 00000028 : fixdi.c.obj (.text:__mspabi_fixdi) + 00008b12 00000028 : memory.c.obj (.text:free_list_insert) + 00008b3a 00000028 : unlink.c.obj (.text:unlink) + 00008b62 00000026 : lseek.c.obj (.text:lseek) + 00008b88 00000024 : write.c.obj (.text:write) + 00008bac 00000022 : memccpy.c.obj (.text:memccpy) + 00008bce 00000020 : mult32_f5hw.asm.obj (.text) + 00008bee 0000001c : boot.c.obj (.text:_c_int00_noargs) + 00008c0a 0000001c : memory.c.obj (.text:free_list_remove) + 00008c26 0000001a : strchr.c.obj (.text:strchr) + 00008c40 00000018 : strcmp.c.obj (.text:strcmp) + 00008c58 00000016 : div16u.asm.obj (.text) + 00008c6e 00000014 : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset:__TI_zero_init_nomemset) + 00008c82 00000014 : memchr.c.obj (.text:memchr) + 00008c96 00000014 : memset.c.obj (.text:memset) + 00008caa 00000014 : mult16_f5hw.asm.obj (.text) + 00008cbe 00000014 : wcslen.c.obj (.text:wcslen) + 00008cd2 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00008ce4 00000012 : lsr32.asm.obj (.text:l_lsr) + 00008cf6 00000012 : memcpy.c.obj (.text:memcpy) + 00008d08 00000010 : epilog.asm.obj (.text) + 00008d18 00000010 : strcpy.c.obj (.text:strcpy) + 00008d28 0000000e : strlen.c.obj (.text:strlen) + 00008d36 0000000c : fltid.c.obj (.text:__mspabi_fltid) + 00008d42 0000000c : toupper.c.obj (.text:toupper) + 00008d4e 0000000a : abs.c.obj (.text:abs) + 00008d58 00000008 : memory.c.obj (.text:malloc) + 00008d60 00000006 : printf.c.obj (.text:_outc) + 00008d66 00000006 : exit.c.obj (.text:abort) + 00008d6c 00000004 : printf.c.obj (.text:_outs) + 00008d70 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00008d74 00000002 : _lock.c.obj (.text:_nop) + 00008d76 00000002 : startup.c.obj (.text:_system_post_cinit) + +.const 0 00008d78 000007c2 + 00008d78 0000069a p1.obj (.const:.string) + 00009412 00000101 rts430_eabi.lib : ctype.c.obj (.const:.string:_ctypes_) + 00009513 00000001 --HOLE-- [fill = 0] + 00009514 00000026 : _printfi.c.obj (.const:.string) + +.text:_isr +* 0 0000953a 00000008 + 0000953a 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00009542 00000056 + 00009542 00000044 (.cinit..data.load) [load image, compression = lzss] + 00009586 00000006 (__TI_handler_table) + 0000958c 00000004 (.cinit..bss.load) [load image, compression = zero_init] + 00009590 00000008 (__TI_cinit_table) + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + p1.obj 652 1690 0 + +--+----------------------------+-------+---------+---------+ + Total: 652 1690 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + _printfi.c.obj 6622 38 0 + addd.c.obj 1846 0 0 + frcdivd.c.obj 1144 0 0 + div64u.c.obj 864 0 0 + mpyd.c.obj 704 0 0 + memory.c.obj 636 0 4 + divd.c.obj 568 0 0 + trgmsg.c.obj 90 0 288 + frcmpyd.c.obj 370 0 0 + s_scalbn.c.obj 362 0 0 + defs.c.obj 0 0 282 + ctype.c.obj 0 257 0 + fputs.c.obj 234 0 0 + cmpd.c.obj 220 0 0 + setvbuf.c.obj 208 0 0 + s_frexp.c.obj 176 0 0 + fltlid.c.obj 172 0 0 + fputc.c.obj 144 0 0 + getdevice.c.obj 140 0 0 + hostlseek.c.obj 136 0 0 + _ltoa.c.obj 132 0 0 + copy_decompress_lzss.c.obj 124 0 0 + _io_perm.c.obj 122 0 0 + host_device.c.obj 0 0 118 + fclose.c.obj 114 0 0 + fixdli.c.obj 114 0 0 + cvtfd.c.obj 112 0 0 + fseek.c.obj 112 0 0 + hostopen.c.obj 102 0 8 + lsr32.asm.obj 110 0 0 + hostrename.c.obj 106 0 0 + fflush.c.obj 98 0 0 + hostwrite.c.obj 98 0 0 + hostread.c.obj 96 0 0 + mult64_f5hw.asm.obj 94 0 0 + autoinit.c.obj 88 0 0 + div32u.asm.obj 88 0 0 + atoi.c.obj 82 0 0 + exit.c.obj 74 0 2 + lsr16.asm.obj 76 0 0 + asr64.c.obj 74 0 0 + close.c.obj 74 0 0 + lsr64.c.obj 70 0 0 + printf.c.obj 70 0 0 + hostclose.c.obj 68 0 0 + lsl64.c.obj 68 0 0 + div32s.asm.obj 64 0 0 + hostunlink.c.obj 64 0 0 + asr32.asm.obj 62 0 0 + lsl32.asm.obj 62 0 0 + fopen.c.obj 52 0 0 + s_copysign.c.obj 46 0 0 + subd.c.obj 46 0 0 + asr16.asm.obj 44 0 0 + lsl16.asm.obj 44 0 0 + strncpy.c.obj 44 0 0 + negd.c.obj 42 0 0 + fixdi.c.obj 40 0 0 + mult3264_f5hw.asm.obj 40 0 0 + unlink.c.obj 40 0 0 + lseek.c.obj 38 0 0 + write.c.obj 36 0 0 + memccpy.c.obj 34 0 0 + mult32_f5hw.asm.obj 32 0 0 + boot.c.obj 28 2 0 + strchr.c.obj 26 0 0 + strcmp.c.obj 24 0 0 + div16u.asm.obj 22 0 0 + copy_zero_init.c.obj 20 0 0 + memchr.c.obj 20 0 0 + memset.c.obj 20 0 0 + mult16_f5hw.asm.obj 20 0 0 + wcslen.c.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + memcpy.c.obj 18 0 0 + epilog.asm.obj 16 0 0 + strcpy.c.obj 16 0 0 + strlen.c.obj 14 0 0 + fltid.c.obj 12 0 0 + toupper.c.obj 12 0 0 + abs.c.obj 10 0 0 + isr_trap.asm.obj 8 0 0 + _lock.c.obj 2 0 4 + exit_gvars.c.obj 0 0 4 + pre_init.c.obj 4 0 0 + errno.c.obj 0 0 2 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 18164 341 712 + + Heap: 0 0 300 + Stack: 0 0 160 + Linker Generated: 0 86 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 18816 2117 1172 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00009590 records: 2, size/record: 4, table size: 8 + .data: load addr=00009542, load size=00000044 bytes, run addr=0000264c, run size=000000fe bytes, compression=lzss + .bss: load addr=0000958c, load size=00000004 bytes, run addr=0000274a, run size=000000aa bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 00009586 records: 3, size/record: 2, table size: 6 + index: 0, handler: __TI_zero_init + index: 1, handler: __TI_decompress_lzss + index: 2, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +00008d66 C$$EXIT +00008988 C$$IO$$ +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +000086f2 HOSTclose +00007cce HOSTlseek +000081e0 HOSTopen +0000830a HOSTread +0000810e HOSTrename +000087be HOSTunlink +00008246 HOSTwrite +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +00000902 USBCNF +00000903 USBCNF_H +00000902 USBCNF_L +0000093c USBCTL +0000093a USBFN +0000093b USBFN_H +0000093a USBFN_L +0000093f USBFUNADR +0000093d USBIE +00002378 USBIEP0BUF +000023c9 USBIEPBBAX_1 +000023d1 USBIEPBBAX_2 +000023d9 USBIEPBBAX_3 +000023e1 USBIEPBBAX_4 +000023e9 USBIEPBBAX_5 +000023f1 USBIEPBBAX_6 +000023f9 USBIEPBBAX_7 +000023cd USBIEPBBAY_1 +000023d5 USBIEPBBAY_2 +000023dd USBIEPBBAY_3 +000023e5 USBIEPBBAY_4 +000023ed USBIEPBBAY_5 +000023f5 USBIEPBBAY_6 +000023fd USBIEPBBAY_7 +000023ca USBIEPBCTX_1 +000023d2 USBIEPBCTX_2 +000023da USBIEPBCTX_3 +000023e2 USBIEPBCTX_4 +000023ea USBIEPBCTX_5 +000023f2 USBIEPBCTX_6 +000023fa USBIEPBCTX_7 +000023ce USBIEPBCTY_1 +000023d6 USBIEPBCTY_2 +000023de USBIEPBCTY_3 +000023e6 USBIEPBCTY_4 +000023ee USBIEPBCTY_5 +000023f6 USBIEPBCTY_6 +000023fe USBIEPBCTY_7 +00000920 USBIEPCNF_0 +000023c8 USBIEPCNF_1 +000023d0 USBIEPCNF_2 +000023d8 USBIEPCNF_3 +000023e0 USBIEPCNF_4 +000023e8 USBIEPCNF_5 +000023f0 USBIEPCNF_6 +000023f8 USBIEPCNF_7 +00000921 USBIEPCNT_0 +0000092e USBIEPIE +00000930 USBIEPIFG +000023cf USBIEPSIZXY_1 +000023d7 USBIEPSIZXY_2 +000023df USBIEPSIZXY_3 +000023e7 USBIEPSIZXY_4 +000023ef USBIEPSIZXY_5 +000023f7 USBIEPSIZXY_6 +000023ff USBIEPSIZXY_7 +0000093e USBIFG +00000900 USBKEYID +00000901 USBKEYID_H +00000900 USBKEYID_L +00000936 USBMAINT +00000937 USBMAINT_H +00000936 USBMAINT_L +00002370 USBOEP0BUF +00002389 USBOEPBBAX_1 +00002391 USBOEPBBAX_2 +00002399 USBOEPBBAX_3 +000023a1 USBOEPBBAX_4 +000023a9 USBOEPBBAX_5 +000023b1 USBOEPBBAX_6 +000023b9 USBOEPBBAX_7 +0000238d USBOEPBBAY_1 +00002395 USBOEPBBAY_2 +0000239d USBOEPBBAY_3 +000023a5 USBOEPBBAY_4 +000023ad USBOEPBBAY_5 +000023b5 USBOEPBBAY_6 +000023bd USBOEPBBAY_7 +0000238a USBOEPBCTX_1 +00002392 USBOEPBCTX_2 +0000239a USBOEPBCTX_3 +000023a2 USBOEPBCTX_4 +000023aa USBOEPBCTX_5 +000023b2 USBOEPBCTX_6 +000023ba USBOEPBCTX_7 +0000238e USBOEPBCTY_1 +00002396 USBOEPBCTY_2 +0000239e USBOEPBCTY_3 +000023a6 USBOEPBCTY_4 +000023ae USBOEPBCTY_5 +000023b6 USBOEPBCTY_6 +000023be USBOEPBCTY_7 +00000922 USBOEPCNF_0 +00002388 USBOEPCNF_1 +00002390 USBOEPCNF_2 +00002398 USBOEPCNF_3 +000023a0 USBOEPCNF_4 +000023a8 USBOEPCNF_5 +000023b0 USBOEPCNF_6 +000023b8 USBOEPCNF_7 +00000923 USBOEPCNT_0 +0000092f USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +0000252c _CIOBUF_ +00004400 __STACK_END +000000a0 __STACK_SIZE +0000012c __SYSMEM_SIZE +00009590 __TI_CINIT_Base +00009598 __TI_CINIT_Limit +00009586 __TI_Handler_Table_Base +0000958c __TI_Handler_Table_Limit +0000953a __TI_ISR_TRAP +00008424 __TI_auto_init_nobinit_nopinit_hold_wdt +000088f6 __TI_cleanup +0000273a __TI_cleanup_ptr +00007f4a __TI_closefile +00007dda __TI_decompress_lzss +00008cd2 __TI_decompress_none +000082a8 __TI_doflush +0000273c __TI_dtors_ptr +00002746 __TI_enable_exit_profile_output +00004b36 __TI_frcdivd +00006cc6 __TI_frcmpyd +00002742 __TI_ft_end +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +00007d56 __TI_ltoa +ffffffff __TI_pprof_out_hndl +0000585a __TI_printfi +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +000089e8 __TI_readmsg +0000274a __TI_tmpnams +0000895e __TI_writemsg +00007e56 __TI_wrt_ok +00008c6e __TI_zero_init_nomemset +ffffffff __c_args__ +00004400 __mspabi_addd +000075d4 __mspabi_cmpd +0000802e __mspabi_cvtfd +000061e6 __mspabi_divd +000087fe __mspabi_divli +00008c58 __mspabi_divu +000084d4 __mspabi_divul +00004fae __mspabi_divull +00008aea __mspabi_fixdi +00007fbc __mspabi_fixdli +00008d36 __mspabi_fltid +000079c6 __mspabi_fltlid +00008d14 __mspabi_func_epilog_1 +00008d12 __mspabi_func_epilog_2 +00008d10 __mspabi_func_epilog_3 +00008d0e __mspabi_func_epilog_4 +00008d0c __mspabi_func_epilog_5 +00008d0a __mspabi_func_epilog_6 +00008d08 __mspabi_func_epilog_7 +0000530e __mspabi_mpyd +00008caa __mspabi_mpyi_f5hw +00008bce __mspabi_mpyl_f5hw +0000836a __mspabi_mpyll_f5hw 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abort +00008d4e abs +00007314 aligned_alloc +0000852c atoi +00008662 close +000089ba copysign +000089ba copysignl +00002744 errno +0000877a exit +0000892a finddevice +00007bb0 fputc +0000740a fputs +000076b0 free +00007916 frexp +00007916 frexpl +0000809e fseek +0000847c getdevice +00006e38 ldexp +00006e38 ldexpl +00008b62 lseek +000055ce main +00008d58 malloc +00007314 memalign +00008bac memccpy +00008c82 memchr +00008cf6 memcpy +00008c96 memset +000027ea parmbuf +000088ba printf +00007bb0 putc +00008b3a remove +00006e38 scalbn +00006e38 scalbnl +00007782 setvbuf +00008c26 strchr +00008c40 strcmp +00008d18 strcpy +00008d28 strlen +00008a6c strncpy +00008d42 toupper +00008b3a unlink +00008cbe wcslen +00008b88 write + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +000000a0 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012c __SYSMEM_SIZE +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H 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__TI_closefile +00007fbc __mspabi_fixdli +0000802e __mspabi_cvtfd +0000809e fseek +0000810e HOSTrename +000081e0 HOSTopen +00008246 HOSTwrite +000082a8 __TI_doflush +0000830a HOSTread +0000836a __mspabi_mpyll_f5hw +000083c8 __mspabi_srll_15 +000083ce __mspabi_srll_14 +000083d4 __mspabi_srll_13 +000083da __mspabi_srll_12 +000083e0 __mspabi_srll_11 +000083e6 __mspabi_srll_10 +000083ec __mspabi_srll_9 +000083f2 __mspabi_srll_8 +000083f8 __mspabi_srll_7 +000083fe __mspabi_srll_6 +00008404 __mspabi_srll_5 +0000840a __mspabi_srll_4 +00008410 __mspabi_srll_3 +00008416 __mspabi_srll_2 +0000841c __mspabi_srll_1 +00008424 __TI_auto_init_nobinit_nopinit_hold_wdt +0000847c getdevice +000084d4 __mspabi_divul +000084d4 __mspabi_remul +0000852c atoi +000085cc __mspabi_srli +000085da __mspabi_srli_15 +000085de __mspabi_srli_14 +000085e2 __mspabi_srli_13 +000085e6 __mspabi_srli_12 +000085ea __mspabi_srli_11 +000085ee __mspabi_srli_10 +000085f2 __mspabi_srli_9 +000085f6 __mspabi_srli_8 +000085fa __mspabi_srli_7 +000085fe __mspabi_srli_6 +00008602 __mspabi_srli_5 +00008606 __mspabi_srli_4 +0000860a __mspabi_srli_3 +0000860e __mspabi_srli_2 +00008612 __mspabi_srli_1 +00008618 __mspabi_srall +00008662 close +000086ac __mspabi_srlll +000086f2 HOSTclose +00008736 __mspabi_sllll +0000877a exit +000087be HOSTunlink +000087fe __mspabi_divli +000087fe __mspabi_remli +0000883e __mspabi_sral_15 +00008842 __mspabi_sral_14 +00008846 __mspabi_sral_13 +0000884a __mspabi_sral_12 +0000884e __mspabi_sral_11 +00008852 __mspabi_sral_10 +00008856 __mspabi_sral_9 +0000885a __mspabi_sral_8 +0000885e __mspabi_sral_7 +00008862 __mspabi_sral_6 +00008866 __mspabi_sral_5 +0000886a __mspabi_sral_4 +0000886e __mspabi_sral_3 +00008872 __mspabi_sral_2 +00008876 __mspabi_sral_1 +0000887c __mspabi_slll_15 +00008880 __mspabi_slll_14 +00008884 __mspabi_slll_13 +00008888 __mspabi_slll_12 +0000888c __mspabi_slll_11 +00008890 __mspabi_slll_10 +00008894 __mspabi_slll_9 +00008898 __mspabi_slll_8 +0000889c __mspabi_slll_7 +000088a0 __mspabi_slll_6 +000088a4 __mspabi_slll_5 +000088a8 __mspabi_slll_4 +000088ac __mspabi_slll_3 +000088b0 __mspabi_slll_2 +000088b4 __mspabi_slll_1 +000088ba printf +000088f6 __TI_cleanup +0000892a finddevice +0000895e __TI_writemsg +00008988 C$$IO$$ +0000898c __mspabi_subd +000089ba copysign +000089ba copysignl +000089e8 __TI_readmsg +00008a14 __mspabi_srai +00008a20 __mspabi_srai_15 +00008a22 __mspabi_srai_14 +00008a24 __mspabi_srai_13 +00008a26 __mspabi_srai_12 +00008a28 __mspabi_srai_11 +00008a2a __mspabi_srai_10 +00008a2c __mspabi_srai_9 +00008a2e __mspabi_srai_8 +00008a30 __mspabi_srai_7 +00008a32 __mspabi_srai_6 +00008a34 __mspabi_srai_5 +00008a36 __mspabi_srai_4 +00008a38 __mspabi_srai_3 +00008a3a __mspabi_srai_2 +00008a3c __mspabi_srai_1 +00008a40 __mspabi_slli +00008a4c __mspabi_slli_15 +00008a4e __mspabi_slli_14 +00008a50 __mspabi_slli_13 +00008a52 __mspabi_slli_12 +00008a54 __mspabi_slli_11 +00008a56 __mspabi_slli_10 +00008a58 __mspabi_slli_9 +00008a5a __mspabi_slli_8 +00008a5c __mspabi_slli_7 +00008a5e __mspabi_slli_6 +00008a60 __mspabi_slli_5 +00008a62 __mspabi_slli_4 +00008a64 __mspabi_slli_3 +00008a66 __mspabi_slli_2 +00008a68 __mspabi_slli_1 +00008a6c strncpy +00008a98 __mspabi_negd +00008ac2 __mspabi_mpyull_f5hw +00008aea __mspabi_fixdi +00008b3a remove +00008b3a unlink +00008b62 lseek +00008b88 write +00008bac memccpy +00008bce __mspabi_mpyl_f5hw +00008bee _c_int00_noargs +00008c26 strchr +00008c40 strcmp +00008c58 __mspabi_divu +00008c58 __mspabi_remu +00008c6e __TI_zero_init_nomemset +00008c82 memchr +00008c96 memset +00008caa __mspabi_mpyi_f5hw +00008cbe wcslen +00008cd2 __TI_decompress_none +00008ce4 __mspabi_srll +00008cf6 memcpy +00008d08 __mspabi_func_epilog_7 +00008d0a __mspabi_func_epilog_6 +00008d0c __mspabi_func_epilog_5 +00008d0e __mspabi_func_epilog_4 +00008d10 __mspabi_func_epilog_3 +00008d12 __mspabi_func_epilog_2 +00008d14 __mspabi_func_epilog_1 +00008d18 strcpy +00008d28 strlen +00008d36 __mspabi_fltid +00008d42 toupper +00008d4e abs +00008d58 malloc +00008d66 C$$EXIT +00008d66 abort +00008d70 _system_pre_init +00008d74 _nop +00008d76 _system_post_cinit +00009412 _ctypes_ +0000953a __TI_ISR_TRAP +00009586 __TI_Handler_Table_Base +0000958c __TI_Handler_Table_Limit +00009590 __TI_CINIT_Base +00009598 __TI_CINIT_Limit +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +0000fffe _reset_vector +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[975 symbols] diff --git a/CPE325/L2_P1/Debug/L2_P1.out b/CPE325/L2_P1/Debug/L2_P1.out new file mode 100644 index 0000000..875215e Binary files /dev/null and b/CPE325/L2_P1/Debug/L2_P1.out differ diff --git a/CPE325/L2_P1/Debug/L2_P1_linkInfo.xml b/CPE325/L2_P1/Debug/L2_P1_linkInfo.xml new file mode 100644 index 0000000..80f51db --- /dev/null +++ b/CPE325/L2_P1/Debug/L2_P1_linkInfo.xml @@ -0,0 +1,16453 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x61327260 + 0x0 + L2_P1.out + + _c_int00_noargs +
0x8bee
+ + + + .\ + object + p1.obj + p1.obj + + + object + <internal> + <internal> + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + printf.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + _printfi.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + fputc.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + fputs.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + _io_perm.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + setvbuf.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + wcslen.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + s_frexp.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + s_scalbn.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + asr16.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + div16u.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + div32u.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + epilog.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int41.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int42.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int43.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + 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UCSCTL8_H + 0x171 + + + UCA0CTLW0 + 0x5c0 + + + UCA0CTLW0_L + 0x5c0 + + + UCA0CTLW0_H + 0x5c1 + + + UCA0BRW + 0x5c6 + + + UCA0BRW_L + 0x5c6 + + + UCA0BRW_H + 0x5c7 + + + UCA0MCTL + 0x5c8 + + + UCA0STAT + 0x5ca + + + UCA0RXBUF + 0x5cc + + + UCA0TXBUF + 0x5ce + + + UCA0ABCTL + 0x5d0 + + + UCA0IRCTL + 0x5d2 + + + UCA0IRCTL_L + 0x5d2 + + + UCA0IRCTL_H + 0x5d3 + + + UCA0ICTL + 0x5dc + + + UCA0ICTL_L + 0x5dc + + + UCA0ICTL_H + 0x5dd + + + UCA0IV + 0x5de + + + UCB0CTLW0 + 0x5e0 + + + UCB0CTLW0_L + 0x5e0 + + + UCB0CTLW0_H + 0x5e1 + + + UCB0BRW + 0x5e6 + + + UCB0BRW_L + 0x5e6 + + + UCB0BRW_H + 0x5e7 + + + UCB0STAT + 0x5ea + + + UCB0RXBUF + 0x5ec + + + UCB0TXBUF + 0x5ee + + + UCB0I2COA + 0x5f0 + + + UCB0I2COA_L + 0x5f0 + + + UCB0I2COA_H + 0x5f1 + + + UCB0I2CSA + 0x5f2 + + + UCB0I2CSA_L + 0x5f2 + + + UCB0I2CSA_H + 0x5f3 + + + UCB0ICTL + 0x5fc + + + UCB0ICTL_L + 0x5fc + + + UCB0ICTL_H + 0x5fd + + + UCB0IV + 0x5fe + + + UCA1CTLW0 + 0x600 + + + UCA1CTLW0_L + 0x600 + + + UCA1CTLW0_H + 0x601 + + + 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__TI_Handler_Table_Limit + 0x958c + + + __STACK_SIZE + 0xa0 + + + __STACK_END + 0x4400 + + + __SYSMEM_SIZE + 0x12c + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + main + 0x55ce + + + + printf + 0x88ba + + + + __TI_printfi + 0x585a + + + + putc + 0x7bb0 + + + + fputc + 0x7bb0 + + + + fputs + 0x740a + + + + __TI_wrt_ok + 0x7e56 + + + + setvbuf + 0x7782 + + + + wcslen + 0x8cbe + + + + frexpl + 0x7916 + + + + frexp + 0x7916 + + + + scalbn + 0x6e38 + + + + scalbnl + 0x6e38 + + + + ldexpl + 0x6e38 + + + + ldexp + 0x6e38 + + + + __mspabi_srai + 0x8a14 + + + + __mspabi_srai_8 + 0x8a2e + + + + __mspabi_srai_9 + 0x8a2c + + + + __mspabi_srai_6 + 0x8a32 + + + + __mspabi_srai_7 + 0x8a30 + + + + __mspabi_srai_4 + 0x8a36 + + + + __mspabi_srai_5 + 0x8a34 + + + + __mspabi_srai_2 + 0x8a3a + + + + __mspabi_srai_3 + 0x8a38 + + + + __mspabi_srai_1 + 0x8a3c + + + + __mspabi_srai_15 + 0x8a20 + + + + __mspabi_srai_14 + 0x8a22 + + + + __mspabi_srai_13 + 0x8a24 + + + + __mspabi_srai_12 + 0x8a26 + + + + __mspabi_srai_11 + 0x8a28 + + + + __mspabi_srai_10 + 0x8a2a + + + + __mspabi_remu + 0x8c58 + + + + __mspabi_divu + 0x8c58 + + + + __mspabi_remul + 0x84d4 + + + + __mspabi_divul + 0x84d4 + + + + __mspabi_func_epilog_2 + 0x8d12 + + + + __mspabi_func_epilog_3 + 0x8d10 + + + + __mspabi_func_epilog_1 + 0x8d14 + + + + __mspabi_func_epilog_6 + 0x8d0a + + + + __mspabi_func_epilog_7 + 0x8d08 + + + + __mspabi_func_epilog_4 + 0x8d0e + + + + __mspabi_func_epilog_5 + 0x8d0c + + + + __TI_int41 + 0xffd2 + + + + __TI_int42 + 0xffd4 + + + + __TI_int43 + 0xffd6 + + + + __TI_int44 + 0xffd8 + + + + __TI_int45 + 0xffda + + + + __TI_int46 + 0xffdc + + + + __TI_int47 + 0xffde + + + + __TI_int48 + 0xffe0 + + + + __TI_int49 + 0xffe2 + + + + __TI_int50 + 0xffe4 + + + + __TI_int51 + 0xffe6 + + + + __TI_int52 + 0xffe8 + + + + __TI_int53 + 0xffea + + + + __TI_int54 + 0xffec + + + + __TI_int55 + 0xffee + + + + __TI_int56 + 0xfff0 + + + + __TI_int57 + 0xfff2 + + + + __TI_int58 + 0xfff4 + + + + __TI_int59 + 0xfff6 + + + + __TI_int60 + 0xfff8 + + + + __TI_int61 + 0xfffa + + + + __TI_int62 + 0xfffc + + + + __TI_ISR_TRAP + 0x953a + + + + __mspabi_slli + 0x8a40 + + + + __mspabi_slli_9 + 0x8a58 + + + + __mspabi_slli_8 + 0x8a5a + + + + __mspabi_slli_7 + 0x8a5c + + + + __mspabi_slli_6 + 0x8a5e + + + + __mspabi_slli_5 + 0x8a60 + + + + __mspabi_slli_4 + 0x8a62 + + + + __mspabi_slli_3 + 0x8a64 + + + + __mspabi_slli_2 + 0x8a66 + + + + __mspabi_slli_1 + 0x8a68 + + + + __mspabi_slli_15 + 0x8a4c + + + + __mspabi_slli_14 + 0x8a4e + + + + __mspabi_slli_13 + 0x8a50 + + + + __mspabi_slli_12 + 0x8a52 + + + + __mspabi_slli_11 + 0x8a54 + + + + __mspabi_slli_10 + 0x8a56 + + + + __mspabi_srli_8 + 0x85f6 + + + + __mspabi_srli_9 + 0x85f2 + + + + __mspabi_srli_6 + 0x85fe + + + + __mspabi_srli_7 + 0x85fa + + + + __mspabi_srli_4 + 0x8606 + + + + __mspabi_srli_5 + 0x8602 + + + + __mspabi_srli_2 + 0x860e + + + + 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+ + + + HOSTrename + 0x810e + + + + HOSTunlink + 0x87be + + + + HOSTwrite + 0x8246 + + + + __TI_readmsg + 0x89e8 + + + + C$$IO$$ + 0x8988 + + + + _CIOBUF_ + 0x252c + + + + __TI_writemsg + 0x895e + + + + lseek + 0x8b62 + + + + __TI_closefile + 0x7f4a + + + + finddevice + 0x892a + + + + getdevice + 0x847c + + + + strcmp + 0x8c40 + + + + strcpy + 0x8d18 + + + + strncpy + 0x8a6c + + + + close + 0x8662 + + + + unlink + 0x8b3a + + + + remove + 0x8b3a + + + Link successful + diff --git a/CPE325/L2_P1/Debug/ccsObjs.opt b/CPE325/L2_P1/Debug/ccsObjs.opt new file mode 100644 index 0000000..2d7b23a --- /dev/null +++ b/CPE325/L2_P1/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./p1.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/L2_P1/Debug/makefile b/CPE325/L2_P1/Debug/makefile new file mode 100644 index 0000000..da3d97a --- /dev/null +++ b/CPE325/L2_P1/Debug/makefile @@ -0,0 +1,168 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./p1.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +L2_P1.out \ + +EXE_OUTPUTS__QUOTED += \ +"L2_P1.out" \ + +BIN_OUTPUTS += \ +L2_P1.hex \ + +BIN_OUTPUTS__QUOTED += \ +"L2_P1.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "L2_P1.out" + +# Tool invocations +L2_P1.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --advice:power="all" --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing -z -m"L2_P1.map" --heap_size=300 --stack_size=160 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="L2_P1_linkInfo.xml" --use_hw_mpy=F5 --rom_model -o "L2_P1.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +L2_P1.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "L2_P1.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "p1.lst" + -$(RM) "p1.obj" + -$(RM) "p1.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/L2_P1/Debug/objects.mk b/CPE325/L2_P1/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/L2_P1/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/L2_P1/Debug/p1.d b/CPE325/L2_P1/Debug/p1.d new file mode 100644 index 0000000..d2c64d9 --- /dev/null +++ b/CPE325/L2_P1/Debug/p1.d @@ -0,0 +1,48 @@ +# FIXED + +p1.obj: ../p1.c +p1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +p1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h +p1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/limits.h +p1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/float.h + +../p1.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/limits.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/float.h: + diff --git a/CPE325/L2_P1/Debug/p1.lst b/CPE325/L2_P1/Debug/p1.lst new file mode 100644 index 0000000..ada0f0a --- /dev/null +++ b/CPE325/L2_P1/Debug/p1.lst @@ -0,0 +1,3703 @@ +MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 1 + + 1 ;****************************************************************************** + 2 ;* MSP430 G3 C/C++ Codegen PC v20.2.5.LTS * + 3 ;* Date/Time created: Fri Sep 3 14:07:10 2021 * + 4 ;****************************************************************************** + 5 .compiler_opts --abi=eabi --diag_wrap=off --hll_source=on --mem_model:code=small --mem_model:d + 6 + 7 $C$DW$CU .dwtag DW_TAG_compile_unit + 8 .dwattr $C$DW$CU, DW_AT_name("../p1.c") + 9 .dwattr $C$DW$CU, DW_AT_producer("TI MSP430 G3 C/C++ Codegen PC v20.2.5.LTS Copyright (c) 2003 + 10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + 11 .dwattr $C$DW$CU, DW_AT_comp_dir("C:\CPE325_Workspace\L2_P1\Debug") + 12 $C$DW$1 .dwtag DW_TAG_variable + 13 .dwattr $C$DW$1, DW_AT_name("WDTCTL") + 14 .dwattr $C$DW$1, DW_AT_TI_symbol_name("WDTCTL") + 15 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$58) + 16 .dwattr $C$DW$1, DW_AT_declaration + 17 .dwattr $C$DW$1, DW_AT_external + 18 .dwattr $C$DW$1, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430f5529.h") + 19 .dwattr $C$DW$1, DW_AT_decl_line(0x1232) + 20 .dwattr $C$DW$1, DW_AT_decl_column(0x01) + 21 + 22 + 23 $C$DW$2 .dwtag DW_TAG_subprogram + 24 .dwattr $C$DW$2, DW_AT_name("printf") + 25 .dwattr $C$DW$2, DW_AT_TI_symbol_name("printf") + 26 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$10) + 27 .dwattr $C$DW$2, DW_AT_declaration + 28 .dwattr $C$DW$2, DW_AT_external + 29 .dwattr $C$DW$2, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/in + 30 .dwattr $C$DW$2, DW_AT_decl_line(0xf6) + 31 .dwattr $C$DW$2, DW_AT_decl_column(0x19) + 32 $C$DW$3 .dwtag DW_TAG_formal_parameter + 33 .dwattr $C$DW$3, DW_AT_type(*$C$DW$T$39) + 34 + 35 $C$DW$4 .dwtag DW_TAG_unspecified_parameters + 36 + 37 .dwendtag $C$DW$2 + 38 + 39 ; C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\bin\acpia430.exe -@C:\\Users\\LIBRAR + 40 000000 .sect ".text:main" + 41 .clink + 42 .global main + 43 + 44 $C$DW$5 .dwtag DW_TAG_subprogram + 45 .dwattr $C$DW$5, DW_AT_name("main") + 46 .dwattr $C$DW$5, DW_AT_low_pc(main) + 47 .dwattr $C$DW$5, DW_AT_high_pc(0x00) + 48 .dwattr $C$DW$5, DW_AT_TI_symbol_name("main") + 49 .dwattr $C$DW$5, DW_AT_external + 50 .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$10) + 51 .dwattr $C$DW$5, DW_AT_TI_begin_file("../p1.c") + 52 .dwattr $C$DW$5, DW_AT_TI_begin_line(0x10) + 53 .dwattr $C$DW$5, DW_AT_TI_begin_column(0x05) + 54 .dwattr $C$DW$5, DW_AT_decl_file("../p1.c") + 55 .dwattr $C$DW$5, DW_AT_decl_line(0x10) + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 2 + + 56 .dwattr $C$DW$5, DW_AT_decl_column(0x05) + 57 .dwattr $C$DW$5, DW_AT_TI_max_frame_size(0x3c) + 58 .dwpsn file "../p1.c",line 17,column 1,is_stmt,address main,isa 0 + 59 + 60 .dwfde $C$DW$CIE, main + 61 + 62 ;***************************************************************************** + 63 ;* FUNCTION NAME: main * + 64 ;* * + 65 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + 66 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 67 ;* Local Frame Size : 28 Args + 30 Auto + 0 Save = 58 byte * + 68 ;***************************************************************************** + 69 000000 main: + 70 ;* --------------------------------------------------------------------------* + 71 .dwcfi cfa_offset, 2 + 72 .dwcfi save_reg_to_mem, 16, -2 + 73 000000 8031 SUB.W #58,SP ; [] + 000002 003A + 74 .dwcfi cfa_offset, 60 + 75 $C$DW$6 .dwtag DW_TAG_variable + 76 .dwattr $C$DW$6, DW_AT_name("dou") + 77 .dwattr $C$DW$6, DW_AT_TI_symbol_name("dou") + 78 .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$17) + 79 .dwattr $C$DW$6, DW_AT_location[DW_OP_breg1 28] + 80 + 81 $C$DW$7 .dwtag DW_TAG_variable + 82 .dwattr $C$DW$7, DW_AT_name("flo") + 83 .dwattr $C$DW$7, DW_AT_TI_symbol_name("flo") + 84 .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$16) + 85 .dwattr $C$DW$7, DW_AT_location[DW_OP_breg1 36] + 86 + 87 $C$DW$8 .dwtag DW_TAG_variable + 88 .dwattr $C$DW$8, DW_AT_name("shortInt") + 89 .dwattr $C$DW$8, DW_AT_TI_symbol_name("shortInt") + 90 .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$10) + 91 .dwattr $C$DW$8, DW_AT_location[DW_OP_breg1 40] + 92 + 93 $C$DW$9 .dwtag DW_TAG_variable + 94 .dwattr $C$DW$9, DW_AT_name("integer") + 95 .dwattr $C$DW$9, DW_AT_TI_symbol_name("integer") + 96 .dwattr $C$DW$9, DW_AT_type(*$C$DW$T$10) + 97 .dwattr $C$DW$9, DW_AT_location[DW_OP_breg1 42] + 98 + 99 $C$DW$10 .dwtag DW_TAG_variable + 100 .dwattr $C$DW$10, DW_AT_name("longInt") + 101 .dwattr $C$DW$10, DW_AT_TI_symbol_name("longInt") + 102 .dwattr $C$DW$10, DW_AT_type(*$C$DW$T$10) + 103 .dwattr $C$DW$10, DW_AT_location[DW_OP_breg1 44] + 104 + 105 $C$DW$11 .dwtag DW_TAG_variable + 106 .dwattr $C$DW$11, DW_AT_name("longlongInt") + 107 .dwattr $C$DW$11, DW_AT_TI_symbol_name("longlongInt") + 108 .dwattr $C$DW$11, DW_AT_type(*$C$DW$T$10) + 109 .dwattr $C$DW$11, DW_AT_location[DW_OP_breg1 46] + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 3 + + 110 + 111 $C$DW$12 .dwtag DW_TAG_variable + 112 .dwattr $C$DW$12, DW_AT_name("unsignedshortInt") + 113 .dwattr $C$DW$12, DW_AT_TI_symbol_name("unsignedshortInt") + 114 .dwattr $C$DW$12, DW_AT_type(*$C$DW$T$10) + 115 .dwattr $C$DW$12, DW_AT_location[DW_OP_breg1 48] + 116 + 117 $C$DW$13 .dwtag DW_TAG_variable + 118 .dwattr $C$DW$13, DW_AT_name("unsignedInt") + 119 .dwattr $C$DW$13, DW_AT_TI_symbol_name("unsignedInt") + 120 .dwattr $C$DW$13, DW_AT_type(*$C$DW$T$10) + 121 .dwattr $C$DW$13, DW_AT_location[DW_OP_breg1 50] + 122 + 123 $C$DW$14 .dwtag DW_TAG_variable + 124 .dwattr $C$DW$14, DW_AT_name("unsignedlongInt") + 125 .dwattr $C$DW$14, DW_AT_TI_symbol_name("unsignedlongInt") + 126 .dwattr $C$DW$14, DW_AT_type(*$C$DW$T$10) + 127 .dwattr $C$DW$14, DW_AT_location[DW_OP_breg1 52] + 128 + 129 $C$DW$15 .dwtag DW_TAG_variable + 130 .dwattr $C$DW$15, DW_AT_name("unsignedlonglongInt") + 131 .dwattr $C$DW$15, DW_AT_TI_symbol_name("unsignedlonglongInt") + 132 .dwattr $C$DW$15, DW_AT_type(*$C$DW$T$10) + 133 .dwattr $C$DW$15, DW_AT_location[DW_OP_breg1 54] + 134 + 135 $C$DW$16 .dwtag DW_TAG_variable + 136 .dwattr $C$DW$16, DW_AT_name("signedChar") + 137 .dwattr $C$DW$16, DW_AT_TI_symbol_name("signedChar") + 138 .dwattr $C$DW$16, DW_AT_type(*$C$DW$T$6) + 139 .dwattr $C$DW$16, DW_AT_location[DW_OP_breg1 56] + 140 + 141 $C$DW$17 .dwtag DW_TAG_variable + 142 .dwattr $C$DW$17, DW_AT_name("unsignedChar") + 143 .dwattr $C$DW$17, DW_AT_TI_symbol_name("unsignedChar") + 144 .dwattr $C$DW$17, DW_AT_type(*$C$DW$T$6) + 145 .dwattr $C$DW$17, DW_AT_location[DW_OP_breg1 57] + 146 + 147 .dwpsn file "../p1.c",line 18,column 5,is_stmt,isa 0 + 148 000004 40B2 MOV.W #23168,&WDTCTL+0 ; [] |18| + 000006 5A80 + 000008 0000! + 149 .dwpsn file "../p1.c",line 21,column 5,is_stmt,isa 0 + 150 00000a 40B1 MOV.W #$C$SL1+0,0(SP) ; [] |21| + 00000c 0000! + 00000e 0000 + 151 $C$DW$18 .dwtag DW_TAG_TI_branch + 152 .dwattr $C$DW$18, DW_AT_low_pc(0x00) + 153 .dwattr $C$DW$18, DW_AT_name("printf") + 154 .dwattr $C$DW$18, DW_AT_TI_call + 155 + 156 000010 12B0 CALL #printf ; [] |21| + 000012 0000! + 157 ; [] |21| + 158 .dwpsn file "../p1.c",line 22,column 5,is_stmt,isa 0 + 159 000014 40B1 MOV.W #$C$SL2+0,0(SP) ; [] |22| + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 4 + + 000016 0000! + 000018 0000 + 160 $C$DW$19 .dwtag DW_TAG_TI_branch + 161 .dwattr $C$DW$19, DW_AT_low_pc(0x00) + 162 .dwattr $C$DW$19, DW_AT_name("printf") + 163 .dwattr $C$DW$19, DW_AT_TI_call + 164 + 165 00001a 12B0 CALL #printf ; [] |22| + 00001c 0000! + 166 ; [] |22| + 167 .dwpsn file "../p1.c",line 23,column 5,is_stmt,isa 0 + 168 00001e 40B1 MOV.W #$C$SL1+0,0(SP) ; [] |23| + 000020 0000! + 000022 0000 + 169 $C$DW$20 .dwtag DW_TAG_TI_branch + 170 .dwattr $C$DW$20, DW_AT_low_pc(0x00) + 171 .dwattr $C$DW$20, DW_AT_name("printf") + 172 .dwattr $C$DW$20, DW_AT_TI_call + 173 + 174 000024 12B0 CALL #printf ; [] |23| + 000026 0000! + 175 ; [] |23| + 176 .dwpsn file "../p1.c",line 25,column 21,is_stmt,isa 0 + 177 000028 40F1 MOV.B #97,56(SP) ; [] |25| + 00002a 0061 + 00002c 0038 + 178 .dwpsn file "../p1.c",line 26,column 5,is_stmt,isa 0 + 179 00002e 40B1 MOV.W #$C$SL3+0,0(SP) ; [] |26| + 000030 0000! + 000032 0000 + 180 000034 415F MOV.B 56(SP),r15 ; [] |26| + 000036 0038 + 181 000038 4F81 MOV.W r15,2(SP) ; [] |26| + 00003a 0002 + 182 00003c 4391 MOV.W #1,4(SP) ; [] |26| + 00003e 0004 + 183 000040 40B1 MOV.W #65408,6(SP) ; [] |26| + 000042 FF80 + 000044 0006 + 184 000046 40B1 MOV.W #127,8(SP) ; [] |26| + 000048 007F + 00004a 0008 + 185 $C$DW$21 .dwtag DW_TAG_TI_branch + 186 .dwattr $C$DW$21, DW_AT_low_pc(0x00) + 187 .dwattr $C$DW$21, DW_AT_name("printf") + 188 .dwattr $C$DW$21, DW_AT_TI_call + 189 + 190 00004c 12B0 CALL #printf ; [] |26| + 00004e 0000! + 191 ; [] |26| + 192 .dwpsn file "../p1.c",line 28,column 18,is_stmt,isa 0 + 193 000050 40B1 MOV.W #12,40(SP) ; [] |28| + 000052 000C + 000054 0028 + 194 .dwpsn file "../p1.c",line 29,column 5,is_stmt,isa 0 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 5 + + 195 000056 40B1 MOV.W #$C$SL4+0,0(SP) ; [] |29| + 000058 0000! + 00005a 0000 + 196 00005c 4191 MOV.W 40(SP),2(SP) ; [] |29| + 00005e 0028 + 000060 0002 + 197 000062 43A1 MOV.W #2,4(SP) ; [] |29| + 000064 0004 + 198 000066 40B1 MOV.W #32768,6(SP) ; [] |29| + 000068 8000 + 00006a 0006 + 199 00006c 40B1 MOV.W #32767,8(SP) ; [] |29| + 00006e 7FFF + 000070 0008 + 200 $C$DW$22 .dwtag DW_TAG_TI_branch + 201 .dwattr $C$DW$22, DW_AT_low_pc(0x00) + 202 .dwattr $C$DW$22, DW_AT_name("printf") + 203 .dwattr $C$DW$22, DW_AT_TI_call + 204 + 205 000072 12B0 CALL #printf ; [] |29| + 000074 0000! + 206 ; [] |29| + 207 .dwpsn file "../p1.c",line 31,column 17,is_stmt,isa 0 + 208 000076 40B1 MOV.W #900,42(SP) ; [] |31| + 000078 0384 + 00007a 002A + 209 .dwpsn file "../p1.c",line 32,column 5,is_stmt,isa 0 + 210 00007c 40B1 MOV.W #$C$SL5+0,0(SP) ; [] |32| + 00007e 0000! + 000080 0000 + 211 000082 4191 MOV.W 42(SP),2(SP) ; [] |32| + 000084 002A + 000086 0002 + 212 000088 43A1 MOV.W #2,4(SP) ; [] |32| + 00008a 0004 + 213 00008c 40B1 MOV.W #32768,6(SP) ; [] |32| + 00008e 8000 + 000090 0006 + 214 000092 40B1 MOV.W #32767,8(SP) ; [] |32| + 000094 7FFF + 000096 0008 + 215 $C$DW$23 .dwtag DW_TAG_TI_branch + 216 .dwattr $C$DW$23, DW_AT_low_pc(0x00) + 217 .dwattr $C$DW$23, DW_AT_name("printf") + 218 .dwattr $C$DW$23, DW_AT_TI_call + 219 + 220 000098 12B0 CALL #printf ; [] |32| + 00009a 0000! + 221 ; [] |32| + 222 .dwpsn file "../p1.c",line 34,column 17,is_stmt,isa 0 + 223 00009c 40B1 MOV.W #200,44(SP) ; [] |34| + 00009e 00C8 + 0000a0 002C + 224 .dwpsn file "../p1.c",line 35,column 5,is_stmt,isa 0 + 225 0000a2 40B1 MOV.W #$C$SL6+0,0(SP) ; [] |35| + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 6 + + 0000a4 0000! + 0000a6 0000 + 226 0000a8 4191 MOV.W 44(SP),2(SP) ; [] |35| + 0000aa 002C + 0000ac 0002 + 227 0000ae 43A1 MOV.W #2,4(SP) ; [] |35| + 0000b0 0004 + 228 0000b2 4381 MOV.W #0,6(SP) ; [] |35| + 0000b4 0006 + 229 0000b6 40B1 MOV.W #32768,8(SP) ; [] |35| + 0000b8 8000 + 0000ba 0008 + 230 0000bc 43B1 MOV.W #65535,10(SP) ; [] |35| + 0000be 000A + 231 0000c0 40B1 MOV.W #32767,12(SP) ; [] |35| + 0000c2 7FFF + 0000c4 000C + 232 $C$DW$24 .dwtag DW_TAG_TI_branch + 233 .dwattr $C$DW$24, DW_AT_low_pc(0x00) + 234 .dwattr $C$DW$24, DW_AT_name("printf") + 235 .dwattr $C$DW$24, DW_AT_TI_call + 236 + 237 0000c6 12B0 CALL #printf ; [] |35| + 0000c8 0000! + 238 ; [] |35| + 239 .dwpsn file "../p1.c",line 37,column 21,is_stmt,isa 0 + 240 0000ca 40B1 MOV.W #65136,46(SP) ; [] |37| + 0000cc FE70 + 0000ce 002E + 241 .dwpsn file "../p1.c",line 38,column 5,is_stmt,isa 0 + 242 0000d0 40B1 MOV.W #$C$SL7+0,0(SP) ; [] |38| + 0000d2 0000! + 0000d4 0000 + 243 0000d6 4191 MOV.W 46(SP),2(SP) ; [] |38| + 0000d8 002E + 0000da 0002 + 244 0000dc 43A1 MOV.W #2,4(SP) ; [] |38| + 0000de 0004 + 245 0000e0 4381 MOV.W #0,6(SP) ; [] |38| + 0000e2 0006 + 246 0000e4 4381 MOV.W #0,8(SP) ; [] |38| + 0000e6 0008 + 247 0000e8 4381 MOV.W #0,10(SP) ; [] |38| + 0000ea 000A + 248 0000ec 40B1 MOV.W #32768,12(SP) ; [] |38| + 0000ee 8000 + 0000f0 000C + 249 0000f2 43B1 MOV.W #65535,14(SP) ; [] |38| + 0000f4 000E + 250 0000f6 43B1 MOV.W #65535,16(SP) ; [] |38| + 0000f8 0010 + 251 0000fa 43B1 MOV.W #65535,18(SP) ; [] |38| + 0000fc 0012 + 252 0000fe 40B1 MOV.W #32767,20(SP) ; [] |38| + 000100 7FFF + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 7 + + 000102 0014 + 253 $C$DW$25 .dwtag DW_TAG_TI_branch + 254 .dwattr $C$DW$25, DW_AT_low_pc(0x00) + 255 .dwattr $C$DW$25, DW_AT_name("printf") + 256 .dwattr $C$DW$25, DW_AT_TI_call + 257 + 258 000104 12B0 CALL #printf ; [] |38| + 000106 0000! + 259 ; [] |38| + 260 ;* --------------------------------------------------------------------------* + 261 .dwpsn file "../p1.c",line 40,column 23,is_stmt,isa 0 + 262 000108 40F1 MOV.B #111,57(SP) ; [] |40| + 00010a 006F + 00010c 0039 + 263 .dwpsn file "../p1.c",line 41,column 5,is_stmt,isa 0 + 264 00010e 40B1 MOV.W #$C$SL8+0,0(SP) ; [] |41| + 000110 0000! + 000112 0000 + 265 000114 415F MOV.B 57(SP),r15 ; [] |41| + 000116 0039 + 266 000118 4F81 MOV.W r15,2(SP) ; [] |41| + 00011a 0002 + 267 00011c 4391 MOV.W #1,4(SP) ; [] |41| + 00011e 0004 + 268 000120 4381 MOV.W #0,6(SP) ; [] |41| + 000122 0006 + 269 000124 40B1 MOV.W #255,8(SP) ; [] |41| + 000126 00FF + 000128 0008 + 270 $C$DW$26 .dwtag DW_TAG_TI_branch + 271 .dwattr $C$DW$26, DW_AT_low_pc(0x00) + 272 .dwattr $C$DW$26, DW_AT_name("printf") + 273 .dwattr $C$DW$26, DW_AT_TI_call + 274 + 275 00012a 12B0 CALL #printf ; [] |41| + 00012c 0000! + 276 ; [] |41| + 277 .dwpsn file "../p1.c",line 43,column 26,is_stmt,isa 0 + 278 00012e 40B1 MOV.W #500,48(SP) ; [] |43| + 000130 01F4 + 000132 0030 + 279 .dwpsn file "../p1.c",line 44,column 5,is_stmt,isa 0 + 280 000134 40B1 MOV.W #$C$SL9+0,0(SP) ; [] |44| + 000136 0000! + 000138 0000 + 281 00013a 4191 MOV.W 48(SP),2(SP) ; [] |44| + 00013c 0030 + 00013e 0002 + 282 000140 43A1 MOV.W #2,4(SP) ; [] |44| + 000142 0004 + 283 000144 4381 MOV.W #0,6(SP) ; [] |44| + 000146 0006 + 284 000148 43B1 MOV.W #65535,8(SP) ; [] |44| + 00014a 0008 + 285 00014c 40B1 MOV.W #32767,10(SP) ; [] |44| + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 8 + + 00014e 7FFF + 000150 000A + 286 $C$DW$27 .dwtag DW_TAG_TI_branch + 287 .dwattr $C$DW$27, DW_AT_low_pc(0x00) + 288 .dwattr $C$DW$27, DW_AT_name("printf") + 289 .dwattr $C$DW$27, DW_AT_TI_call + 290 + 291 000152 12B0 CALL #printf ; [] |44| + 000154 0000! + 292 ; [] |44| + 293 .dwpsn file "../p1.c",line 46,column 21,is_stmt,isa 0 + 294 000156 40B1 MOV.W #500,50(SP) ; [] |46| + 000158 01F4 + 00015a 0032 + 295 .dwpsn file "../p1.c",line 47,column 5,is_stmt,isa 0 + 296 00015c 40B1 MOV.W #$C$SL10+0,0(SP) ; [] |47| + 00015e 0000! + 000160 0000 + 297 000162 4191 MOV.W 50(SP),2(SP) ; [] |47| + 000164 0032 + 000166 0002 + 298 000168 43A1 MOV.W #2,4(SP) ; [] |47| + 00016a 0004 + 299 00016c 4381 MOV.W #0,6(SP) ; [] |47| + 00016e 0006 + 300 000170 43B1 MOV.W #65535,8(SP) ; [] |47| + 000172 0008 + 301 000174 40B1 MOV.W #32767,10(SP) ; [] |47| + 000176 7FFF + 000178 000A + 302 $C$DW$28 .dwtag DW_TAG_TI_branch + 303 .dwattr $C$DW$28, DW_AT_low_pc(0x00) + 304 .dwattr $C$DW$28, DW_AT_name("printf") + 305 .dwattr $C$DW$28, DW_AT_TI_call + 306 + 307 00017a 12B0 CALL #printf ; [] |47| + 00017c 0000! + 308 ; [] |47| + 309 .dwpsn file "../p1.c",line 49,column 25,is_stmt,isa 0 + 310 00017e 40B1 MOV.W #800,52(SP) ; [] |49| + 000180 0320 + 000182 0034 + 311 .dwpsn file "../p1.c",line 50,column 5,is_stmt,isa 0 + 312 000184 40B1 MOV.W #$C$SL11+0,0(SP) ; [] |50| + 000186 0000! + 000188 0000 + 313 00018a 4191 MOV.W 52(SP),2(SP) ; [] |50| + 00018c 0034 + 00018e 0002 + 314 000190 43A1 MOV.W #2,4(SP) ; [] |50| + 000192 0004 + 315 000194 4381 MOV.W #0,6(SP) ; [] |50| + 000196 0006 + 316 000198 43B1 MOV.W #65535,8(SP) ; [] |50| + 00019a 0008 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 9 + + 317 00019c 43B1 MOV.W #65535,10(SP) ; [] |50| + 00019e 000A + 318 $C$DW$29 .dwtag DW_TAG_TI_branch + 319 .dwattr $C$DW$29, DW_AT_low_pc(0x00) + 320 .dwattr $C$DW$29, DW_AT_name("printf") + 321 .dwattr $C$DW$29, DW_AT_TI_call + 322 + 323 0001a0 12B0 CALL #printf ; [] |50| + 0001a2 0000! + 324 ; [] |50| + 325 .dwpsn file "../p1.c",line 52,column 29,is_stmt,isa 0 + 326 0001a4 40B1 MOV.W #5000,54(SP) ; [] |52| + 0001a6 1388 + 0001a8 0036 + 327 .dwpsn file "../p1.c",line 53,column 5,is_stmt,isa 0 + 328 0001aa 40B1 MOV.W #$C$SL12+0,0(SP) ; [] |53| + 0001ac 0000! + 0001ae 0000 + 329 0001b0 4191 MOV.W 54(SP),2(SP) ; [] |53| + 0001b2 0036 + 0001b4 0002 + 330 0001b6 43A1 MOV.W #2,4(SP) ; [] |53| + 0001b8 0004 + 331 0001ba 4381 MOV.W #0,6(SP) ; [] |53| + 0001bc 0006 + 332 0001be 43B1 MOV.W #-1,8(SP) ; [] |53| + 0001c0 0008 + 333 0001c2 43B1 MOV.W #-1,10(SP) ; [] |53| + 0001c4 000A + 334 0001c6 43B1 MOV.W #-1,12(SP) ; [] |53| + 0001c8 000C + 335 0001ca 43B1 MOV.W #-1,14(SP) ; [] |53| + 0001cc 000E + 336 $C$DW$30 .dwtag DW_TAG_TI_branch + 337 .dwattr $C$DW$30, DW_AT_low_pc(0x00) + 338 .dwattr $C$DW$30, DW_AT_name("printf") + 339 .dwattr $C$DW$30, DW_AT_TI_call + 340 + 341 0001ce 12B0 CALL #printf ; [] |53| + 0001d0 0000! + 342 ; [] |53| + 343 .dwpsn file "../p1.c",line 55,column 15,is_stmt,isa 0 + 344 0001d2 40B1 MOV.W #5767,36(SP) ; [] |55| + 0001d4 1687 + 0001d6 0024 + 345 0001d8 40B1 MOV.W #16968,38(SP) ; [] |55| + 0001da 4248 + 0001dc 0026 + 346 .dwpsn file "../p1.c",line 56,column 5,is_stmt,isa 0 + 347 0001de 411C MOV.W 36(SP),r12 ; [] |56| + 0001e0 0024 + 348 0001e2 411D MOV.W 38(SP),r13 ; [] |56| + 0001e4 0026 + 349 $C$DW$31 .dwtag DW_TAG_TI_branch + 350 .dwattr $C$DW$31, DW_AT_low_pc(0x00) + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 10 + + 351 .dwattr $C$DW$31, DW_AT_name("__mspabi_cvtfd") + 352 .dwattr $C$DW$31, DW_AT_TI_call + 353 + 354 0001e6 12B0 CALL #__mspabi_cvtfd ; [] |56| + 0001e8 0000! + 355 ; [] |56| + 356 0001ea 40B1 MOV.W #$C$SL13+0,0(SP) ; [] |56| + 0001ec 0000! + 0001ee 0000 + 357 0001f0 4C81 MOV.W r12,2(SP) ; [] |56| + 0001f2 0002 + 358 0001f4 4D81 MOV.W r13,4(SP) ; [] |56| + 0001f6 0004 + 359 0001f8 4E81 MOV.W r14,6(SP) ; [] |56| + 0001fa 0006 + 360 0001fc 4F81 MOV.W r15,8(SP) ; [] |56| + 0001fe 0008 + 361 000200 42A1 MOV.W #4,10(SP) ; [] |56| + 000202 000A + 362 000204 43B1 MOV.W #65535,12(SP) ; [] |56| + 000206 000C + 363 000208 40B1 MOV.W #255,14(SP) ; [] |56| + 00020a 00FF + 00020c 000E + 364 00020e 4381 MOV.W #0,16(SP) ; [] |56| + 000210 0010 + 365 000212 40B1 MOV.W #57344,18(SP) ; [] |56| + 000214 E000 + 000216 0012 + 366 000218 43B1 MOV.W #65535,20(SP) ; [] |56| + 00021a 0014 + 367 00021c 40B1 MOV.W #18415,22(SP) ; [] |56| + 00021e 47EF + 000220 0016 + 368 $C$DW$32 .dwtag DW_TAG_TI_branch + 369 .dwattr $C$DW$32, DW_AT_low_pc(0x00) + 370 .dwattr $C$DW$32, DW_AT_name("printf") + 371 .dwattr $C$DW$32, DW_AT_TI_call + 372 + 373 000222 12B0 CALL #printf ; [] |56| + 000224 0000! + 374 ; [] |56| + 375 .dwpsn file "../p1.c",line 58,column 16,is_stmt,isa 0 + 376 000226 4381 MOV.W #0,28(SP) ; [] |58| + 000228 001C + 377 00022a 4381 MOV.W #0,30(SP) ; [] |58| + 00022c 001E + 378 00022e 40B1 MOV.W #33280,32(SP) ; [] |58| + 000230 8200 + 000232 0020 + 379 000234 40B1 MOV.W #16565,34(SP) ; [] |58| + 000236 40B5 + 000238 0022 + 380 .dwpsn file "../p1.c",line 59,column 5,is_stmt,isa 0 + 381 00023a 40B1 MOV.W #$C$SL14+0,0(SP) ; [] |59| + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 11 + + 00023c 0000! + 00023e 0000 + 382 000240 4191 MOV.W 28(SP),2(SP) ; [] |59| + 000242 001C + 000244 0002 + 383 000246 4191 MOV.W 30(SP),4(SP) ; [] |59| + 000248 001E + 00024a 0004 + 384 00024c 4191 MOV.W 32(SP),6(SP) ; [] |59| + 00024e 0020 + 000250 0006 + 385 000252 4191 MOV.W 34(SP),8(SP) ; [] |59| + 000254 0022 + 000256 0008 + 386 000258 42B1 MOV.W #8,10(SP) ; [] |59| + 00025a 000A + 387 00025c 4381 MOV.W #0,12(SP) ; [] |59| + 00025e 000C + 388 000260 4381 MOV.W #0,14(SP) ; [] |59| + 000262 000E + 389 000264 4381 MOV.W #0,16(SP) ; [] |59| + 000266 0010 + 390 000268 40B1 MOV.W #16,18(SP) ; [] |59| + 00026a 0010 + 00026c 0012 + 391 00026e 43B1 MOV.W #65535,20(SP) ; [] |59| + 000270 0014 + 392 000272 43B1 MOV.W #65535,22(SP) ; [] |59| + 000274 0016 + 393 000276 43B1 MOV.W #65535,24(SP) ; [] |59| + 000278 0018 + 394 00027a 40B1 MOV.W #32751,26(SP) ; [] |59| + 00027c 7FEF + 00027e 001A + 395 $C$DW$33 .dwtag DW_TAG_TI_branch + 396 .dwattr $C$DW$33, DW_AT_low_pc(0x00) + 397 .dwattr $C$DW$33, DW_AT_name("printf") + 398 .dwattr $C$DW$33, DW_AT_TI_call + 399 + 400 000280 12B0 CALL #printf ; [] |59| + 000282 0000! + 401 ; [] |59| + 402 .dwpsn file "../p1.c",line 60,column 1,is_stmt,isa 0 + 403 000284 430C MOV.W #0,r12 ; [] |60| + 404 000286 5031 ADD.W #58,SP ; [] + 000288 003A + 405 .dwcfi cfa_offset, 2 + 406 $C$DW$34 .dwtag DW_TAG_TI_branch + 407 .dwattr $C$DW$34, DW_AT_low_pc(0x00) + 408 .dwattr $C$DW$34, DW_AT_TI_return + 409 + 410 00028a 4130 RET ; [] + 411 ; [] + 412 .dwattr $C$DW$5, DW_AT_TI_end_file("../p1.c") + 413 .dwattr $C$DW$5, DW_AT_TI_end_line(0x3c) + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 12 + + 414 .dwattr $C$DW$5, DW_AT_TI_end_column(0x01) + 415 .dwendentry + 416 .dwendtag $C$DW$5 + 417 + 418 ;****************************************************************************** + 419 ;* STRINGS * + 420 ;****************************************************************************** + 421 000000 .sect ".const:.string" + 422 .align 2 + 423 000000 002D $C$SL1: .string "-----------------------------------------------------------" + 000001 002D + 000002 002D + 000003 002D + 000004 002D + 000005 002D + 000006 002D + 000007 002D + 000008 002D + 000009 002D + 00000a 002D + 00000b 002D + 00000c 002D + 00000d 002D + 00000e 002D + 00000f 002D + 000010 002D + 000011 002D + 000012 002D + 000013 002D + 000014 002D + 000015 002D + 000016 002D + 000017 002D + 000018 002D + 000019 002D + 00001a 002D + 00001b 002D + 00001c 002D + 00001d 002D + 00001e 002D + 00001f 002D + 000020 002D + 000021 002D + 000022 002D + 000023 002D + 000024 002D + 000025 002D + 000026 002D + 000027 002D + 000028 002D + 000029 002D + 00002a 002D + 00002b 002D + 00002c 002D + 00002d 002D + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 13 + + 00002e 002D + 00002f 002D + 000030 002D + 000031 002D + 000032 002D + 000033 002D + 000034 002D + 000035 002D + 000036 002D + 000037 002D + 000038 002D + 000039 002D + 00003a 002D + 424 00003b 002D .string "--------------------------------------------------------",10 + 00003c 002D + 00003d 002D + 00003e 002D + 00003f 002D + 000040 002D + 000041 002D + 000042 002D + 000043 002D + 000044 002D + 000045 002D + 000046 002D + 000047 002D + 000048 002D + 000049 002D + 00004a 002D + 00004b 002D + 00004c 002D + 00004d 002D + 00004e 002D + 00004f 002D + 000050 002D + 000051 002D + 000052 002D + 000053 002D + 000054 002D + 000055 002D + 000056 002D + 000057 002D + 000058 002D + 000059 002D + 00005a 002D + 00005b 002D + 00005c 002D + 00005d 002D + 00005e 002D + 00005f 002D + 000060 002D + 000061 002D + 000062 002D + 000063 002D + 000064 002D + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 14 + + 000065 002D + 000066 002D + 000067 002D + 000068 002D + 000069 002D + 00006a 002D + 00006b 002D + 00006c 002D + 00006d 002D + 00006e 002D + 00006f 002D + 000070 002D + 000071 002D + 000072 002D + 000073 000A + 425 000074 0000 .string 0 + 426 .align 2 + 427 000076 007C $C$SL2: .string "| Data Type | Value | Size " + 000077 0020 + 000078 0044 + 000079 0061 + 00007a 0074 + 00007b 0061 + 00007c 0020 + 00007d 0054 + 00007e 0079 + 00007f 0070 + 000080 0065 + 000081 0020 + 000082 0020 + 000083 0020 + 000084 0020 + 000085 0020 + 000086 0020 + 000087 0020 + 000088 0020 + 000089 0020 + 00008a 0020 + 00008b 0020 + 00008c 0020 + 00008d 0020 + 00008e 0020 + 00008f 0020 + 000090 0020 + 000091 007C + 000092 0020 + 000093 0056 + 000094 0061 + 000095 006C + 000096 0075 + 000097 0065 + 000098 0020 + 000099 0020 + 00009a 0020 + 00009b 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 15 + + 00009c 0020 + 00009d 0020 + 00009e 0020 + 00009f 0020 + 0000a0 0020 + 0000a1 0020 + 0000a2 0020 + 0000a3 0020 + 0000a4 0020 + 0000a5 0020 + 0000a6 0020 + 0000a7 0020 + 0000a8 0020 + 0000a9 007C + 0000aa 0020 + 0000ab 0020 + 0000ac 0053 + 0000ad 0069 + 0000ae 007A + 0000af 0065 + 0000b0 0020 + 428 0000b1 0028 .string "(in bytes) | Min | Max |",10,0 + 0000b2 0069 + 0000b3 006E + 0000b4 0020 + 0000b5 0062 + 0000b6 0079 + 0000b7 0074 + 0000b8 0065 + 0000b9 0073 + 0000ba 0029 + 0000bb 0020 + 0000bc 0020 + 0000bd 0020 + 0000be 0020 + 0000bf 0020 + 0000c0 007C + 0000c1 0020 + 0000c2 004D + 0000c3 0069 + 0000c4 006E + 0000c5 0020 + 0000c6 0020 + 0000c7 0020 + 0000c8 0020 + 0000c9 0020 + 0000ca 0020 + 0000cb 0020 + 0000cc 0020 + 0000cd 0020 + 0000ce 0020 + 0000cf 0020 + 0000d0 0020 + 0000d1 0020 + 0000d2 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 16 + + 0000d3 007C + 0000d4 0020 + 0000d5 0020 + 0000d6 004D + 0000d7 0061 + 0000d8 0078 + 0000d9 0020 + 0000da 0020 + 0000db 0020 + 0000dc 0020 + 0000dd 0020 + 0000de 0020 + 0000df 0020 + 0000e0 0020 + 0000e1 0020 + 0000e2 0020 + 0000e3 0020 + 0000e4 0020 + 0000e5 007C + 0000e6 000A + 0000e7 0000 + 429 .align 2 + 430 0000e8 007C $C$SL3: .string "| signed char | '%c' | %d " + 0000e9 0020 + 0000ea 0073 + 0000eb 0069 + 0000ec 0067 + 0000ed 006E + 0000ee 0065 + 0000ef 0064 + 0000f0 0020 + 0000f1 0063 + 0000f2 0068 + 0000f3 0061 + 0000f4 0072 + 0000f5 0020 + 0000f6 0020 + 0000f7 0020 + 0000f8 0020 + 0000f9 0020 + 0000fa 0020 + 0000fb 0020 + 0000fc 0020 + 0000fd 0020 + 0000fe 0020 + 0000ff 0020 + 000100 0020 + 000101 0020 + 000102 0020 + 000103 007C + 000104 0020 + 000105 0027 + 000106 0025 + 000107 0063 + 000108 0027 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 17 + + 000109 0020 + 00010a 0020 + 00010b 0020 + 00010c 0020 + 00010d 0020 + 00010e 0020 + 00010f 0020 + 000110 0020 + 000111 0020 + 000112 0020 + 000113 0020 + 000114 0020 + 000115 0020 + 000116 0020 + 000117 0020 + 000118 0020 + 000119 0020 + 00011a 0020 + 00011b 007C + 00011c 0020 + 00011d 0025 + 00011e 0064 + 00011f 0020 + 000120 0020 + 000121 0020 + 000122 0020 + 431 000123 0020 .string " | %d | %d |",10,0 + 000124 0020 + 000125 0020 + 000126 0020 + 000127 0020 + 000128 0020 + 000129 0020 + 00012a 0020 + 00012b 0020 + 00012c 0020 + 00012d 0020 + 00012e 0020 + 00012f 0020 + 000130 0020 + 000131 0020 + 000132 0020 + 000133 007C + 000134 0020 + 000135 0025 + 000136 0064 + 000137 0020 + 000138 0020 + 000139 0020 + 00013a 0020 + 00013b 0020 + 00013c 0020 + 00013d 0020 + 00013e 0020 + 00013f 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 18 + + 000140 0020 + 000141 0020 + 000142 0020 + 000143 0020 + 000144 0020 + 000145 0020 + 000146 0020 + 000147 0020 + 000148 007C + 000149 0020 + 00014a 0025 + 00014b 0064 + 00014c 0020 + 00014d 0020 + 00014e 0020 + 00014f 0020 + 000150 0020 + 000151 0020 + 000152 0020 + 000153 0020 + 000154 0020 + 000155 0020 + 000156 0020 + 000157 0020 + 000158 007C + 000159 000A + 00015a 0000 + 432 .align 2 + 433 00015c 007C $C$SL4: .string "| short int | %hd | %d " + 00015d 0020 + 00015e 0073 + 00015f 0068 + 000160 006F + 000161 0072 + 000162 0074 + 000163 0020 + 000164 0069 + 000165 006E + 000166 0074 + 000167 0020 + 000168 0020 + 000169 0020 + 00016a 0020 + 00016b 0020 + 00016c 0020 + 00016d 0020 + 00016e 0020 + 00016f 0020 + 000170 0020 + 000171 0020 + 000172 0020 + 000173 0020 + 000174 0020 + 000175 0020 + 000176 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 19 + + 000177 007C + 000178 0020 + 000179 0025 + 00017a 0068 + 00017b 0064 + 00017c 0020 + 00017d 0020 + 00017e 0020 + 00017f 0020 + 000180 0020 + 000181 0020 + 000182 0020 + 000183 0020 + 000184 0020 + 000185 0020 + 000186 0020 + 000187 0020 + 000188 0020 + 000189 0020 + 00018a 0020 + 00018b 0020 + 00018c 0020 + 00018d 0020 + 00018e 0020 + 00018f 007C + 000190 0020 + 000191 0025 + 000192 0064 + 000193 0020 + 000194 0020 + 000195 0020 + 000196 0020 + 434 000197 0020 .string " | %d | %d |",10 + 000198 0020 + 000199 0020 + 00019a 0020 + 00019b 0020 + 00019c 0020 + 00019d 0020 + 00019e 0020 + 00019f 0020 + 0001a0 0020 + 0001a1 0020 + 0001a2 0020 + 0001a3 0020 + 0001a4 0020 + 0001a5 0020 + 0001a6 0020 + 0001a7 007C + 0001a8 0020 + 0001a9 0025 + 0001aa 0064 + 0001ab 0020 + 0001ac 0020 + 0001ad 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 20 + + 0001ae 0020 + 0001af 0020 + 0001b0 0020 + 0001b1 0020 + 0001b2 0020 + 0001b3 0020 + 0001b4 0020 + 0001b5 0020 + 0001b6 0020 + 0001b7 0020 + 0001b8 0020 + 0001b9 0020 + 0001ba 0020 + 0001bb 0020 + 0001bc 007C + 0001bd 0020 + 0001be 0025 + 0001bf 0064 + 0001c0 0020 + 0001c1 0020 + 0001c2 0020 + 0001c3 0020 + 0001c4 0020 + 0001c5 0020 + 0001c6 0020 + 0001c7 0020 + 0001c8 0020 + 0001c9 0020 + 0001ca 0020 + 0001cb 0020 + 0001cc 0020 + 0001cd 007C + 0001ce 000A + 435 0001cf 0000 .string 0 + 436 .align 2 + 437 0001d0 007C $C$SL5: .string "| int | %d | %d " + 0001d1 0020 + 0001d2 0069 + 0001d3 006E + 0001d4 0074 + 0001d5 0020 + 0001d6 0020 + 0001d7 0020 + 0001d8 0020 + 0001d9 0020 + 0001da 0020 + 0001db 0020 + 0001dc 0020 + 0001dd 0020 + 0001de 0020 + 0001df 0020 + 0001e0 0020 + 0001e1 0020 + 0001e2 0020 + 0001e3 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 21 + + 0001e4 0020 + 0001e5 0020 + 0001e6 0020 + 0001e7 0020 + 0001e8 0020 + 0001e9 0020 + 0001ea 0020 + 0001eb 007C + 0001ec 0020 + 0001ed 0025 + 0001ee 0064 + 0001ef 0020 + 0001f0 0020 + 0001f1 0020 + 0001f2 0020 + 0001f3 0020 + 0001f4 0020 + 0001f5 0020 + 0001f6 0020 + 0001f7 0020 + 0001f8 0020 + 0001f9 0020 + 0001fa 0020 + 0001fb 0020 + 0001fc 0020 + 0001fd 0020 + 0001fe 0020 + 0001ff 0020 + 000200 0020 + 000201 0020 + 000202 0020 + 000203 007C + 000204 0020 + 000205 0025 + 000206 0064 + 000207 0020 + 000208 0020 + 000209 0020 + 00020a 0020 + 438 00020b 0020 .string " | %d | %d |",10 + 00020c 0020 + 00020d 0020 + 00020e 0020 + 00020f 0020 + 000210 0020 + 000211 0020 + 000212 0020 + 000213 0020 + 000214 0020 + 000215 0020 + 000216 0020 + 000217 0020 + 000218 0020 + 000219 0020 + 00021a 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 22 + + 00021b 007C + 00021c 0020 + 00021d 0025 + 00021e 0064 + 00021f 0020 + 000220 0020 + 000221 0020 + 000222 0020 + 000223 0020 + 000224 0020 + 000225 0020 + 000226 0020 + 000227 0020 + 000228 0020 + 000229 0020 + 00022a 0020 + 00022b 0020 + 00022c 0020 + 00022d 0020 + 00022e 0020 + 00022f 0020 + 000230 007C + 000231 0020 + 000232 0025 + 000233 0064 + 000234 0020 + 000235 0020 + 000236 0020 + 000237 0020 + 000238 0020 + 000239 0020 + 00023a 0020 + 00023b 0020 + 00023c 0020 + 00023d 0020 + 00023e 0020 + 00023f 0020 + 000240 0020 + 000241 0020 + 000242 007C + 000243 000A + 439 000244 0000 .string 0 + 440 .align 2 + 441 000246 007C $C$SL6: .string "| long int | %hi | %i " + 000247 0020 + 000248 006C + 000249 006F + 00024a 006E + 00024b 0067 + 00024c 0020 + 00024d 0069 + 00024e 006E + 00024f 0074 + 000250 0020 + 000251 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 23 + + 000252 0020 + 000253 0020 + 000254 0020 + 000255 0020 + 000256 0020 + 000257 0020 + 000258 0020 + 000259 0020 + 00025a 0020 + 00025b 0020 + 00025c 0020 + 00025d 0020 + 00025e 0020 + 00025f 0020 + 000260 0020 + 000261 007C + 000262 0020 + 000263 0025 + 000264 0068 + 000265 0069 + 000266 0020 + 000267 0020 + 000268 0020 + 000269 0020 + 00026a 0020 + 00026b 0020 + 00026c 0020 + 00026d 0020 + 00026e 0020 + 00026f 0020 + 000270 0020 + 000271 0020 + 000272 0020 + 000273 0020 + 000274 0020 + 000275 0020 + 000276 0020 + 000277 0020 + 000278 0020 + 000279 007C + 00027a 0020 + 00027b 0025 + 00027c 0069 + 00027d 0020 + 00027e 0020 + 00027f 0020 + 000280 0020 + 442 000281 0020 .string " | %i | %i |",10 + 000282 0020 + 000283 0020 + 000284 0020 + 000285 0020 + 000286 0020 + 000287 0020 + 000288 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 24 + + 000289 0020 + 00028a 0020 + 00028b 0020 + 00028c 0020 + 00028d 0020 + 00028e 0020 + 00028f 0020 + 000290 0020 + 000291 0020 + 000292 007C + 000293 0020 + 000294 0025 + 000295 0069 + 000296 0020 + 000297 0020 + 000298 0020 + 000299 0020 + 00029a 0020 + 00029b 0020 + 00029c 0020 + 00029d 0020 + 00029e 0020 + 00029f 0020 + 0002a0 0020 + 0002a1 0020 + 0002a2 0020 + 0002a3 0020 + 0002a4 0020 + 0002a5 0020 + 0002a6 0020 + 0002a7 0020 + 0002a8 007C + 0002a9 0020 + 0002aa 0025 + 0002ab 0069 + 0002ac 0020 + 0002ad 0020 + 0002ae 0020 + 0002af 0020 + 0002b0 0020 + 0002b1 0020 + 0002b2 0020 + 0002b3 0020 + 0002b4 0020 + 0002b5 0020 + 0002b6 0020 + 0002b7 0020 + 0002b8 007C + 0002b9 000A + 443 0002ba 0000 .string 0 + 444 .align 2 + 445 0002bc 007C $C$SL7: .string "| long long int | %hhi | %d " + 0002bd 0020 + 0002be 006C + 0002bf 006F + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 25 + + 0002c0 006E + 0002c1 0067 + 0002c2 0020 + 0002c3 006C + 0002c4 006F + 0002c5 006E + 0002c6 0067 + 0002c7 0020 + 0002c8 0069 + 0002c9 006E + 0002ca 0074 + 0002cb 0020 + 0002cc 0020 + 0002cd 0020 + 0002ce 0020 + 0002cf 0020 + 0002d0 0020 + 0002d1 0020 + 0002d2 0020 + 0002d3 0020 + 0002d4 0020 + 0002d5 0020 + 0002d6 0020 + 0002d7 007C + 0002d8 0020 + 0002d9 0025 + 0002da 0068 + 0002db 0068 + 0002dc 0069 + 0002dd 0020 + 0002de 0020 + 0002df 0020 + 0002e0 0020 + 0002e1 0020 + 0002e2 0020 + 0002e3 0020 + 0002e4 0020 + 0002e5 0020 + 0002e6 0020 + 0002e7 0020 + 0002e8 0020 + 0002e9 0020 + 0002ea 0020 + 0002eb 0020 + 0002ec 0020 + 0002ed 0020 + 0002ee 0020 + 0002ef 007C + 0002f0 0020 + 0002f1 0020 + 0002f2 0025 + 0002f3 0064 + 0002f4 0020 + 0002f5 0020 + 0002f6 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 26 + + 446 0002f7 0020 .string " | %d | %d |",10 + 0002f8 0020 + 0002f9 0020 + 0002fa 0020 + 0002fb 0020 + 0002fc 0020 + 0002fd 0020 + 0002fe 0020 + 0002ff 0020 + 000300 0020 + 000301 0020 + 000302 0020 + 000303 0020 + 000304 0020 + 000305 0020 + 000306 0020 + 000307 0020 + 000308 007C + 000309 0020 + 00030a 0025 + 00030b 0064 + 00030c 0020 + 00030d 0020 + 00030e 0020 + 00030f 0020 + 000310 0020 + 000311 0020 + 000312 0020 + 000313 0020 + 000314 0020 + 000315 0020 + 000316 0020 + 000317 0020 + 000318 0020 + 000319 0020 + 00031a 0020 + 00031b 0020 + 00031c 0020 + 00031d 0020 + 00031e 007C + 00031f 0020 + 000320 0025 + 000321 0064 + 000322 0020 + 000323 0020 + 000324 0020 + 000325 0020 + 000326 0020 + 000327 0020 + 000328 0020 + 000329 0020 + 00032a 0020 + 00032b 0020 + 00032c 0020 + 00032d 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 27 + + 00032e 007C + 00032f 000A + 447 000330 0000 .string 0 + 448 .align 2 + 449 000332 007C $C$SL8: .string "| unsigned char | '%c' | %d " + 000333 0020 + 000334 0075 + 000335 006E + 000336 0073 + 000337 0069 + 000338 0067 + 000339 006E + 00033a 0065 + 00033b 0064 + 00033c 0020 + 00033d 0063 + 00033e 0068 + 00033f 0061 + 000340 0072 + 000341 0020 + 000342 0020 + 000343 0020 + 000344 0020 + 000345 0020 + 000346 0020 + 000347 0020 + 000348 0020 + 000349 0020 + 00034a 0020 + 00034b 0020 + 00034c 0020 + 00034d 007C + 00034e 0020 + 00034f 0027 + 000350 0025 + 000351 0063 + 000352 0027 + 000353 0020 + 000354 0020 + 000355 0020 + 000356 0020 + 000357 0020 + 000358 0020 + 000359 0020 + 00035a 0020 + 00035b 0020 + 00035c 0020 + 00035d 0020 + 00035e 0020 + 00035f 0020 + 000360 0020 + 000361 0020 + 000362 0020 + 000363 0020 + 000364 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 28 + + 000365 007C + 000366 0020 + 000367 0025 + 000368 0064 + 000369 0020 + 00036a 0020 + 00036b 0020 + 00036c 0020 + 450 00036d 0020 .string " | %lu | %lu " + 00036e 0020 + 00036f 0020 + 000370 0020 + 000371 0020 + 000372 0020 + 000373 0020 + 000374 0020 + 000375 0020 + 000376 0020 + 000377 0020 + 000378 0020 + 000379 0020 + 00037a 0020 + 00037b 0020 + 00037c 0020 + 00037d 0020 + 00037e 007C + 00037f 0020 + 000380 0025 + 000381 006C + 000382 0075 + 000383 0020 + 000384 0020 + 000385 0020 + 000386 0020 + 000387 0020 + 000388 0020 + 000389 0020 + 00038a 0020 + 00038b 0020 + 00038c 0020 + 00038d 0020 + 00038e 0020 + 00038f 0020 + 000390 0020 + 000391 0020 + 000392 0020 + 000393 0020 + 000394 007C + 000395 0020 + 000396 0025 + 000397 006C + 000398 0075 + 000399 0020 + 00039a 0020 + 00039b 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 29 + + 00039c 0020 + 00039d 0020 + 00039e 0020 + 00039f 0020 + 0003a0 0020 + 0003a1 0020 + 0003a2 0020 + 0003a3 0020 + 0003a4 0020 + 0003a5 0020 + 0003a6 0020 + 0003a7 0020 + 451 0003a8 0020 .string " |",10,0 + 0003a9 0020 + 0003aa 0020 + 0003ab 0020 + 0003ac 0020 + 0003ad 007C + 0003ae 000A + 0003af 0000 + 452 .align 2 + 453 0003b0 007C $C$SL9: .string "| unsigned short int | %hu | %d " + 0003b1 0020 + 0003b2 0075 + 0003b3 006E + 0003b4 0073 + 0003b5 0069 + 0003b6 0067 + 0003b7 006E + 0003b8 0065 + 0003b9 0064 + 0003ba 0020 + 0003bb 0073 + 0003bc 0068 + 0003bd 006F + 0003be 0072 + 0003bf 0074 + 0003c0 0020 + 0003c1 0069 + 0003c2 006E + 0003c3 0074 + 0003c4 0020 + 0003c5 0020 + 0003c6 0020 + 0003c7 0020 + 0003c8 0020 + 0003c9 0020 + 0003ca 0020 + 0003cb 007C + 0003cc 0020 + 0003cd 0025 + 0003ce 0068 + 0003cf 0075 + 0003d0 0020 + 0003d1 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 30 + + 0003d2 0020 + 0003d3 0020 + 0003d4 0020 + 0003d5 0020 + 0003d6 0020 + 0003d7 0020 + 0003d8 0020 + 0003d9 0020 + 0003da 0020 + 0003db 0020 + 0003dc 0020 + 0003dd 0020 + 0003de 0020 + 0003df 0020 + 0003e0 0020 + 0003e1 0020 + 0003e2 0020 + 0003e3 0020 + 0003e4 007C + 0003e5 0020 + 0003e6 0025 + 0003e7 0064 + 0003e8 0020 + 0003e9 0020 + 0003ea 0020 + 454 0003eb 0020 .string " | %lu | %lu " + 0003ec 0020 + 0003ed 0020 + 0003ee 0020 + 0003ef 0020 + 0003f0 0020 + 0003f1 0020 + 0003f2 0020 + 0003f3 0020 + 0003f4 0020 + 0003f5 0020 + 0003f6 0020 + 0003f7 0020 + 0003f8 0020 + 0003f9 0020 + 0003fa 0020 + 0003fb 0020 + 0003fc 0020 + 0003fd 007C + 0003fe 0020 + 0003ff 0025 + 000400 006C + 000401 0075 + 000402 0020 + 000403 0020 + 000404 0020 + 000405 0020 + 000406 0020 + 000407 0020 + 000408 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 31 + + 000409 0020 + 00040a 0020 + 00040b 0020 + 00040c 0020 + 00040d 0020 + 00040e 0020 + 00040f 0020 + 000410 0020 + 000411 0020 + 000412 0020 + 000413 0020 + 000414 007C + 000415 0020 + 000416 0025 + 000417 006C + 000418 0075 + 000419 0020 + 00041a 0020 + 00041b 0020 + 00041c 0020 + 00041d 0020 + 00041e 0020 + 00041f 0020 + 000420 0020 + 000421 0020 + 000422 0020 + 000423 0020 + 000424 0020 + 000425 0020 + 455 000426 0020 .string " |",10,0 + 000427 0020 + 000428 0020 + 000429 0020 + 00042a 0020 + 00042b 0020 + 00042c 007C + 00042d 000A + 00042e 0000 + 456 .align 2 + 457 000430 007C $C$SL10: .string "| unsigned int | %u | %l " + 000431 0020 + 000432 0075 + 000433 006E + 000434 0073 + 000435 0069 + 000436 0067 + 000437 006E + 000438 0065 + 000439 0064 + 00043a 0020 + 00043b 0069 + 00043c 006E + 00043d 0074 + 00043e 0020 + 00043f 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 32 + + 000440 0020 + 000441 0020 + 000442 0020 + 000443 0020 + 000444 0020 + 000445 0020 + 000446 0020 + 000447 0020 + 000448 0020 + 000449 0020 + 00044a 0020 + 00044b 007C + 00044c 0020 + 00044d 0020 + 00044e 0025 + 00044f 0075 + 000450 0020 + 000451 0020 + 000452 0020 + 000453 0020 + 000454 0020 + 000455 0020 + 000456 0020 + 000457 0020 + 000458 0020 + 000459 0020 + 00045a 0020 + 00045b 0020 + 00045c 0020 + 00045d 0020 + 00045e 0020 + 00045f 0020 + 000460 0020 + 000461 0020 + 000462 0020 + 000463 0020 + 000464 007C + 000465 0020 + 000466 0025 + 000467 006C + 000468 0020 + 000469 0020 + 00046a 0020 + 458 00046b 0020 .string " | %u | %u " + 00046c 0020 + 00046d 0020 + 00046e 0020 + 00046f 0020 + 000470 0020 + 000471 0020 + 000472 0020 + 000473 0020 + 000474 0020 + 000475 0020 + 000476 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 33 + + 000477 0020 + 000478 0020 + 000479 0020 + 00047a 0020 + 00047b 0020 + 00047c 0020 + 00047d 007C + 00047e 0020 + 00047f 0025 + 000480 0075 + 000481 0020 + 000482 0020 + 000483 0020 + 000484 0020 + 000485 0020 + 000486 0020 + 000487 0020 + 000488 0020 + 000489 0020 + 00048a 0020 + 00048b 0020 + 00048c 0020 + 00048d 0020 + 00048e 0020 + 00048f 0020 + 000490 0020 + 000491 0020 + 000492 0020 + 000493 007C + 000494 0020 + 000495 0020 + 000496 0020 + 000497 0025 + 000498 0075 + 000499 0020 + 00049a 0020 + 00049b 0020 + 00049c 0020 + 00049d 0020 + 00049e 0020 + 00049f 0020 + 0004a0 0020 + 0004a1 0020 + 0004a2 0020 + 0004a3 0020 + 0004a4 0020 + 0004a5 0020 + 459 0004a6 0020 .string " |",10,0 + 0004a7 0020 + 0004a8 0020 + 0004a9 0020 + 0004aa 007C + 0004ab 000A + 0004ac 0000 + 460 .align 2 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 34 + + 461 0004ae 007C $C$SL11: .string "| unsigned long int | %lu | %lu " + 0004af 0020 + 0004b0 0075 + 0004b1 006E + 0004b2 0073 + 0004b3 0069 + 0004b4 0067 + 0004b5 006E + 0004b6 0065 + 0004b7 0064 + 0004b8 0020 + 0004b9 006C + 0004ba 006F + 0004bb 006E + 0004bc 0067 + 0004bd 0020 + 0004be 0069 + 0004bf 006E + 0004c0 0074 + 0004c1 0020 + 0004c2 0020 + 0004c3 0020 + 0004c4 0020 + 0004c5 0020 + 0004c6 0020 + 0004c7 0020 + 0004c8 0020 + 0004c9 007C + 0004ca 0020 + 0004cb 0020 + 0004cc 0025 + 0004cd 006C + 0004ce 0075 + 0004cf 0020 + 0004d0 0020 + 0004d1 0020 + 0004d2 0020 + 0004d3 0020 + 0004d4 0020 + 0004d5 0020 + 0004d6 0020 + 0004d7 0020 + 0004d8 0020 + 0004d9 0020 + 0004da 0020 + 0004db 0020 + 0004dc 0020 + 0004dd 0020 + 0004de 0020 + 0004df 0020 + 0004e0 0020 + 0004e1 0020 + 0004e2 007C + 0004e3 0020 + 0004e4 0025 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 35 + + 0004e5 006C + 0004e6 0075 + 0004e7 0020 + 0004e8 0020 + 462 0004e9 0020 .string " | %u | %ld " + 0004ea 0020 + 0004eb 0020 + 0004ec 0020 + 0004ed 0020 + 0004ee 0020 + 0004ef 0020 + 0004f0 0020 + 0004f1 0020 + 0004f2 0020 + 0004f3 0020 + 0004f4 0020 + 0004f5 0020 + 0004f6 0020 + 0004f7 0020 + 0004f8 0020 + 0004f9 0020 + 0004fa 0020 + 0004fb 007C + 0004fc 0020 + 0004fd 0025 + 0004fe 0075 + 0004ff 0020 + 000500 0020 + 000501 0020 + 000502 0020 + 000503 0020 + 000504 0020 + 000505 0020 + 000506 0020 + 000507 0020 + 000508 0020 + 000509 0020 + 00050a 0020 + 00050b 0020 + 00050c 0020 + 00050d 0020 + 00050e 0020 + 00050f 0020 + 000510 0020 + 000511 0020 + 000512 007C + 000513 0020 + 000514 0025 + 000515 006C + 000516 0064 + 000517 0020 + 000518 0020 + 000519 0020 + 00051a 0020 + 00051b 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 36 + + 00051c 0020 + 00051d 0020 + 00051e 0020 + 00051f 0020 + 000520 0020 + 000521 0020 + 000522 0020 + 000523 0020 + 463 000524 0020 .string " |",10,0 + 000525 0020 + 000526 0020 + 000527 0020 + 000528 007C + 000529 000A + 00052a 0000 + 464 .align 2 + 465 00052c 007C $C$SL12: .string "| unsigned long long int | %llu | %llu " + 00052d 0020 + 00052e 0075 + 00052f 006E + 000530 0073 + 000531 0069 + 000532 0067 + 000533 006E + 000534 0065 + 000535 0064 + 000536 0020 + 000537 006C + 000538 006F + 000539 006E + 00053a 0067 + 00053b 0020 + 00053c 006C + 00053d 006F + 00053e 006E + 00053f 0067 + 000540 0020 + 000541 0069 + 000542 006E + 000543 0074 + 000544 0020 + 000545 0020 + 000546 0020 + 000547 007C + 000548 0020 + 000549 0025 + 00054a 006C + 00054b 006C + 00054c 0075 + 00054d 0020 + 00054e 0020 + 00054f 0020 + 000550 0020 + 000551 0020 + 000552 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 37 + + 000553 0020 + 000554 0020 + 000555 0020 + 000556 0020 + 000557 0020 + 000558 0020 + 000559 0020 + 00055a 0020 + 00055b 0020 + 00055c 0020 + 00055d 007C + 00055e 0020 + 00055f 0025 + 000560 006C + 000561 006C + 000562 0075 + 000563 0020 + 000564 0020 + 000565 0020 + 000566 0020 + 466 000567 0020 .string " | %llu | %llu |" + 000568 0020 + 000569 0020 + 00056a 0020 + 00056b 0020 + 00056c 0020 + 00056d 0020 + 00056e 0020 + 00056f 0020 + 000570 0020 + 000571 0020 + 000572 0020 + 000573 0020 + 000574 0020 + 000575 0020 + 000576 007C + 000577 0020 + 000578 0025 + 000579 006C + 00057a 006C + 00057b 0075 + 00057c 0020 + 00057d 0020 + 00057e 0020 + 00057f 0020 + 000580 0020 + 000581 0020 + 000582 0020 + 000583 0020 + 000584 0020 + 000585 0020 + 000586 0020 + 000587 0020 + 000588 0020 + 000589 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 38 + + 00058a 0020 + 00058b 0020 + 00058c 0020 + 00058d 007C + 00058e 0020 + 00058f 0025 + 000590 006C + 000591 006C + 000592 0075 + 000593 0020 + 000594 0020 + 000595 0020 + 000596 0020 + 000597 0020 + 000598 0020 + 000599 0020 + 00059a 0020 + 00059b 0020 + 00059c 0020 + 00059d 0020 + 00059e 0020 + 00059f 0020 + 0005a0 0020 + 0005a1 007C + 467 0005a2 000A .string 10,0 + 0005a3 0000 + 468 .align 2 + 469 0005a4 007C $C$SL13: .string "| float | %f | %d " + 0005a5 0020 + 0005a6 0066 + 0005a7 006C + 0005a8 006F + 0005a9 0061 + 0005aa 0074 + 0005ab 0020 + 0005ac 0020 + 0005ad 0020 + 0005ae 0020 + 0005af 0020 + 0005b0 0020 + 0005b1 0020 + 0005b2 0020 + 0005b3 0020 + 0005b4 0020 + 0005b5 0020 + 0005b6 0020 + 0005b7 0020 + 0005b8 0020 + 0005b9 0020 + 0005ba 0020 + 0005bb 0020 + 0005bc 0020 + 0005bd 0020 + 0005be 0020 + 0005bf 007C + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 39 + + 0005c0 0020 + 0005c1 0025 + 0005c2 0066 + 0005c3 0020 + 0005c4 0020 + 0005c5 0020 + 0005c6 0020 + 0005c7 0020 + 0005c8 0020 + 0005c9 0020 + 0005ca 0020 + 0005cb 0020 + 0005cc 0020 + 0005cd 0020 + 0005ce 0020 + 0005cf 0020 + 0005d0 0020 + 0005d1 0020 + 0005d2 0020 + 0005d3 0020 + 0005d4 0020 + 0005d5 0020 + 0005d6 0020 + 0005d7 0020 + 0005d8 007C + 0005d9 0020 + 0005da 0025 + 0005db 0064 + 0005dc 0020 + 0005dd 0020 + 0005de 0020 + 470 0005df 0020 .string " | %f | %f " + 0005e0 0020 + 0005e1 0020 + 0005e2 0020 + 0005e3 0020 + 0005e4 0020 + 0005e5 0020 + 0005e6 0020 + 0005e7 0020 + 0005e8 0020 + 0005e9 0020 + 0005ea 0020 + 0005eb 0020 + 0005ec 0020 + 0005ed 0020 + 0005ee 0020 + 0005ef 0020 + 0005f0 0020 + 0005f1 0020 + 0005f2 007C + 0005f3 0020 + 0005f4 0025 + 0005f5 0066 + 0005f6 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 40 + + 0005f7 0020 + 0005f8 0020 + 0005f9 0020 + 0005fa 0020 + 0005fb 0020 + 0005fc 0020 + 0005fd 0020 + 0005fe 0020 + 0005ff 0020 + 000600 0020 + 000601 0020 + 000602 0020 + 000603 0020 + 000604 0020 + 000605 0020 + 000606 0020 + 000607 0020 + 000608 007C + 000609 0020 + 00060a 0025 + 00060b 0066 + 00060c 0020 + 00060d 0020 + 00060e 0020 + 00060f 0020 + 000610 0020 + 000611 0020 + 000612 0020 + 000613 0020 + 000614 0020 + 000615 0020 + 000616 0020 + 000617 0020 + 000618 0020 + 000619 0020 + 471 00061a 0020 .string " |",10,0 + 00061b 0020 + 00061c 007C + 00061d 000A + 00061e 0000 + 472 .align 2 + 473 000620 007C $C$SL14: .string "| double | '%E' | %d " + 000621 0020 + 000622 0064 + 000623 006F + 000624 0075 + 000625 0062 + 000626 006C + 000627 0065 + 000628 0020 + 000629 0020 + 00062a 0020 + 00062b 0020 + 00062c 0020 + 00062d 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 41 + + 00062e 0020 + 00062f 0020 + 000630 0020 + 000631 0020 + 000632 0020 + 000633 0020 + 000634 0020 + 000635 0020 + 000636 0020 + 000637 0020 + 000638 0020 + 000639 0020 + 00063a 0020 + 00063b 007C + 00063c 0020 + 00063d 0027 + 00063e 0025 + 00063f 0045 + 000640 0027 + 000641 0020 + 000642 0020 + 000643 0020 + 000644 0020 + 000645 0020 + 000646 0020 + 000647 0020 + 000648 0020 + 000649 0020 + 00064a 0020 + 00064b 0020 + 00064c 0020 + 00064d 0020 + 00064e 0020 + 00064f 0020 + 000650 0020 + 000651 0020 + 000652 0020 + 000653 0020 + 000654 007C + 000655 0020 + 000656 0025 + 000657 0064 + 000658 0020 + 000659 0020 + 00065a 0020 + 474 00065b 0020 .string " | %e | %e " + 00065c 0020 + 00065d 0020 + 00065e 0020 + 00065f 0020 + 000660 0020 + 000661 0020 + 000662 0020 + 000663 0020 + 000664 0020 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 42 + + 000665 0020 + 000666 0020 + 000667 0020 + 000668 0020 + 000669 0020 + 00066a 0020 + 00066b 0020 + 00066c 0020 + 00066d 0020 + 00066e 007C + 00066f 0020 + 000670 0025 + 000671 0065 + 000672 0020 + 000673 0020 + 000674 0020 + 000675 0020 + 000676 0020 + 000677 0020 + 000678 0020 + 000679 0020 + 00067a 0020 + 00067b 0020 + 00067c 0020 + 00067d 0020 + 00067e 0020 + 00067f 0020 + 000680 0020 + 000681 0020 + 000682 007C + 000683 0020 + 000684 0025 + 000685 0065 + 000686 0020 + 000687 0020 + 000688 0020 + 000689 0020 + 00068a 0020 + 00068b 0020 + 00068c 0020 + 00068d 0020 + 00068e 0020 + 00068f 0020 + 000690 0020 + 000691 0020 + 000692 0020 + 000693 0020 + 000694 0020 + 000695 0020 + 475 000696 0020 .string " |",10,0 + 000697 007C + 000698 000A + 000699 0000 + 476 ;***************************************************************************** + 477 ;* UNDEFINED EXTERNAL REFERENCES * + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 43 + + 478 ;***************************************************************************** + 479 .global WDTCTL + 480 .global printf + 481 .global __mspabi_cvtfd + 482 + 483 ;****************************************************************************** + 484 ;* BUILD ATTRIBUTES * + 485 ;****************************************************************************** + 486 .battr "TI", Tag_File, 1, Tag_LPM_INFO(1) + 487 .battr "TI", Tag_File, 1, Tag_PORTS_INIT_INFO("012345678901ABCDEFGHIJ0000000000001111000000000 + 488 .battr "TI", Tag_File, 1, Tag_LEA_INFO(1) + 489 .battr "TI", Tag_File, 1, Tag_HW_MPY32_INFO(2) + 490 .battr "TI", Tag_File, 1, Tag_HW_MPY_ISR_INFO(1) + 491 .battr "TI", Tag_File, 1, Tag_HW_MPY_INLINE_INFO(1) + 492 .battr "mspabi", Tag_File, 1, Tag_enum_size(3) + 493 + 494 ;****************************************************************************** + 495 ;* TYPE INFORMATION * + 496 ;****************************************************************************** + 497 + 498 $C$DW$T$21 .dwtag DW_TAG_structure_type + 499 .dwattr $C$DW$T$21, DW_AT_byte_size(0x10) + 500 $C$DW$35 .dwtag DW_TAG_member + 501 .dwattr $C$DW$35, DW_AT_type(*$C$DW$T$14) + 502 .dwattr $C$DW$35, DW_AT_name("__max_align1") + 503 .dwattr $C$DW$35, DW_AT_TI_symbol_name("__max_align1") + 504 .dwattr $C$DW$35, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 505 .dwattr $C$DW$35, DW_AT_accessibility(DW_ACCESS_public) + 506 .dwattr $C$DW$35, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 507 .dwattr $C$DW$35, DW_AT_decl_line(0x7b) + 508 .dwattr $C$DW$35, DW_AT_decl_column(0x0c) + 509 + 510 $C$DW$36 .dwtag DW_TAG_member + 511 .dwattr $C$DW$36, DW_AT_type(*$C$DW$T$18) + 512 .dwattr $C$DW$36, DW_AT_name("__max_align2") + 513 .dwattr $C$DW$36, DW_AT_TI_symbol_name("__max_align2") + 514 .dwattr $C$DW$36, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 515 .dwattr $C$DW$36, DW_AT_accessibility(DW_ACCESS_public) + 516 .dwattr $C$DW$36, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 517 .dwattr $C$DW$36, DW_AT_decl_line(0x7c) + 518 .dwattr $C$DW$36, DW_AT_decl_column(0x0e) + 519 + 520 .dwattr $C$DW$T$21, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 521 .dwattr $C$DW$T$21, DW_AT_decl_line(0x7a) + 522 .dwattr $C$DW$T$21, DW_AT_decl_column(0x10) + 523 .dwendtag $C$DW$T$21 + 524 + 525 $C$DW$T$24 .dwtag DW_TAG_typedef + 526 .dwattr $C$DW$T$24, DW_AT_name("__max_align_t") + 527 .dwattr $C$DW$T$24, DW_AT_type(*$C$DW$T$21) + 528 .dwattr $C$DW$T$24, DW_AT_language(DW_LANG_C) + 529 .dwattr $C$DW$T$24, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 530 .dwattr $C$DW$T$24, DW_AT_decl_line(0x7d) + 531 .dwattr $C$DW$T$24, DW_AT_decl_column(0x03) + 532 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 44 + + 533 $C$DW$T$2 .dwtag DW_TAG_unspecified_type + 534 .dwattr $C$DW$T$2, DW_AT_name("void") + 535 + 536 + 537 $C$DW$T$25 .dwtag DW_TAG_subroutine_type + 538 .dwattr $C$DW$T$25, DW_AT_language(DW_LANG_C) + 539 .dwendtag $C$DW$T$25 + 540 + 541 $C$DW$T$26 .dwtag DW_TAG_pointer_type + 542 .dwattr $C$DW$T$26, DW_AT_type(*$C$DW$T$25) + 543 .dwattr $C$DW$T$26, DW_AT_address_class(0x10) + 544 + 545 $C$DW$T$27 .dwtag DW_TAG_typedef + 546 .dwattr $C$DW$T$27, DW_AT_name("__SFR_FARPTR") + 547 .dwattr $C$DW$T$27, DW_AT_type(*$C$DW$T$26) + 548 .dwattr $C$DW$T$27, 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1246 .dwattr $C$DW$T$114, DW_AT_type(*$C$DW$T$109) + 1247 .dwattr $C$DW$T$114, DW_AT_language(DW_LANG_C) + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 57 + + 1248 .dwattr $C$DW$T$114, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1249 .dwattr $C$DW$T$114, DW_AT_decl_line(0x3d) + 1250 .dwattr $C$DW$T$114, DW_AT_decl_column(0x14) + 1251 + 1252 $C$DW$T$115 .dwtag DW_TAG_typedef + 1253 .dwattr $C$DW$T$115, DW_AT_name("__uint_fast64_t") + 1254 .dwattr $C$DW$T$115, DW_AT_type(*$C$DW$T$109) + 1255 .dwattr $C$DW$T$115, DW_AT_language(DW_LANG_C) + 1256 .dwattr $C$DW$T$115, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1257 .dwattr $C$DW$T$115, DW_AT_decl_line(0x73) + 1258 .dwattr $C$DW$T$115, DW_AT_decl_column(0x14) + 1259 + 1260 $C$DW$T$116 .dwtag DW_TAG_typedef + 1261 .dwattr $C$DW$T$116, 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DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1281 .dwattr $C$DW$T$118, DW_AT_decl_line(0x9a) + 1282 .dwattr $C$DW$T$118, DW_AT_decl_column(0x19) + 1283 + 1284 $C$DW$T$16 .dwtag DW_TAG_base_type + 1285 .dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float) + 1286 .dwattr $C$DW$T$16, DW_AT_name("float") + 1287 .dwattr $C$DW$T$16, DW_AT_byte_size(0x04) + 1288 + 1289 $C$DW$T$119 .dwtag DW_TAG_typedef + 1290 .dwattr $C$DW$T$119, DW_AT_name("__float_t") + 1291 .dwattr $C$DW$T$119, DW_AT_type(*$C$DW$T$16) + 1292 .dwattr $C$DW$T$119, DW_AT_language(DW_LANG_C) + 1293 .dwattr $C$DW$T$119, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1294 .dwattr $C$DW$T$119, DW_AT_decl_line(0x4d) + 1295 .dwattr $C$DW$T$119, DW_AT_decl_column(0x10) + 1296 + 1297 $C$DW$T$17 .dwtag DW_TAG_base_type + 1298 .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float) + 1299 .dwattr $C$DW$T$17, DW_AT_name("double") + 1300 .dwattr $C$DW$T$17, DW_AT_byte_size(0x08) + 1301 + 1302 $C$DW$T$120 .dwtag DW_TAG_typedef + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 58 + + 1303 .dwattr $C$DW$T$120, DW_AT_name("__double_t") + 1304 .dwattr $C$DW$T$120, DW_AT_type(*$C$DW$T$17) + 1305 .dwattr $C$DW$T$120, DW_AT_language(DW_LANG_C) + 1306 .dwattr $C$DW$T$120, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1307 .dwattr $C$DW$T$120, DW_AT_decl_line(0x4c) + 1308 .dwattr $C$DW$T$120, DW_AT_decl_column(0x11) + 1309 + 1310 $C$DW$T$18 .dwtag DW_TAG_base_type + 1311 .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float) + 1312 .dwattr $C$DW$T$18, DW_AT_name("long double") + 1313 .dwattr $C$DW$T$18, DW_AT_byte_size(0x08) + 1314 + 1315 $C$DW$T$37 .dwtag DW_TAG_const_type + 1316 .dwattr $C$DW$T$37, DW_AT_type(*$C$DW$T$6) + 1317 + 1318 $C$DW$T$38 .dwtag DW_TAG_pointer_type + 1319 .dwattr $C$DW$T$38, DW_AT_type(*$C$DW$T$37) + 1320 .dwattr $C$DW$T$38, DW_AT_address_class(0x10) + 1321 + 1322 $C$DW$T$39 .dwtag DW_TAG_restrict_type + 1323 .dwattr $C$DW$T$39, DW_AT_type(*$C$DW$T$38) + 1324 + 1325 $C$DW$T$121 .dwtag DW_TAG_pointer_type + 1326 .dwattr $C$DW$T$121, DW_AT_type(*$C$DW$T$6) + 1327 .dwattr $C$DW$T$121, DW_AT_address_class(0x10) + 1328 + 1329 $C$DW$T$122 .dwtag DW_TAG_typedef + 1330 .dwattr $C$DW$T$122, DW_AT_name("__va_list") + 1331 .dwattr $C$DW$T$122, DW_AT_type(*$C$DW$T$121) + 1332 .dwattr $C$DW$T$122, DW_AT_language(DW_LANG_C) + 1333 .dwattr $C$DW$T$122, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1334 .dwattr $C$DW$T$122, DW_AT_decl_line(0x92) + 1335 .dwattr $C$DW$T$122, DW_AT_decl_column(0x0f) + 1336 + 1337 $C$DW$T$123 .dwtag DW_TAG_typedef + 1338 .dwattr $C$DW$T$123, DW_AT_name("va_list") + 1339 .dwattr $C$DW$T$123, DW_AT_type(*$C$DW$T$122) + 1340 .dwattr $C$DW$T$123, DW_AT_language(DW_LANG_C) + 1341 .dwattr $C$DW$T$123, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1342 .dwattr $C$DW$T$123, DW_AT_decl_line(0x33) + 1343 .dwattr $C$DW$T$123, DW_AT_decl_column(0x13) + 1344 + 1345 + 1346 $C$DW$T$19 .dwtag DW_TAG_structure_type + 1347 .dwattr $C$DW$T$19, DW_AT_name("__mq") + 1348 .dwattr $C$DW$T$19, DW_AT_declaration + 1349 .dwattr $C$DW$T$19, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1350 .dwattr $C$DW$T$19, DW_AT_decl_line(0x4c) + 1351 .dwattr $C$DW$T$19, DW_AT_decl_column(0x10) + 1352 .dwendtag $C$DW$T$19 + 1353 + 1354 $C$DW$T$124 .dwtag DW_TAG_pointer_type + 1355 .dwattr $C$DW$T$124, DW_AT_type(*$C$DW$T$19) + 1356 .dwattr $C$DW$T$124, DW_AT_address_class(0x10) + 1357 + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 59 + + 1358 $C$DW$T$125 .dwtag DW_TAG_typedef + 1359 .dwattr $C$DW$T$125, DW_AT_name("__mqd_t") + 1360 .dwattr $C$DW$T$125, DW_AT_type(*$C$DW$T$124) + 1361 .dwattr $C$DW$T$125, DW_AT_language(DW_LANG_C) + 1362 .dwattr $C$DW$T$125, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1363 .dwattr $C$DW$T$125, DW_AT_decl_line(0x4c) + 1364 .dwattr $C$DW$T$125, DW_AT_decl_column(0x16) + 1365 + 1366 + 1367 $C$DW$T$23 .dwtag DW_TAG_structure_type + 1368 .dwattr $C$DW$T$23, DW_AT_name("__sFILE") + 1369 .dwattr $C$DW$T$23, DW_AT_byte_size(0x0c) + 1370 $C$DW$37 .dwtag DW_TAG_member + 1371 .dwattr $C$DW$37, DW_AT_type(*$C$DW$T$10) + 1372 .dwattr $C$DW$37, DW_AT_name("fd") + 1373 .dwattr $C$DW$37, DW_AT_TI_symbol_name("fd") + 1374 .dwattr $C$DW$37, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 1375 .dwattr $C$DW$37, DW_AT_accessibility(DW_ACCESS_public) + 1376 .dwattr $C$DW$37, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1377 .dwattr $C$DW$37, DW_AT_decl_line(0x52) + 1378 .dwattr $C$DW$37, DW_AT_decl_column(0x0b) + 1379 + 1380 $C$DW$38 .dwtag DW_TAG_member + 1381 .dwattr $C$DW$38, DW_AT_type(*$C$DW$T$22) + 1382 .dwattr $C$DW$38, DW_AT_name("buf") + 1383 .dwattr $C$DW$38, DW_AT_TI_symbol_name("buf") + 1384 .dwattr $C$DW$38, DW_AT_data_member_location[DW_OP_plus_uconst 0x2] + 1385 .dwattr $C$DW$38, DW_AT_accessibility(DW_ACCESS_public) + 1386 .dwattr $C$DW$38, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1387 .dwattr $C$DW$38, DW_AT_decl_line(0x53) + 1388 .dwattr $C$DW$38, DW_AT_decl_column(0x16) + 1389 + 1390 $C$DW$39 .dwtag DW_TAG_member + 1391 .dwattr $C$DW$39, DW_AT_type(*$C$DW$T$22) + 1392 .dwattr $C$DW$39, DW_AT_name("pos") + 1393 .dwattr $C$DW$39, DW_AT_TI_symbol_name("pos") + 1394 .dwattr $C$DW$39, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + 1395 .dwattr $C$DW$39, DW_AT_accessibility(DW_ACCESS_public) + 1396 .dwattr $C$DW$39, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1397 .dwattr $C$DW$39, DW_AT_decl_line(0x54) + 1398 .dwattr $C$DW$39, DW_AT_decl_column(0x16) + 1399 + 1400 $C$DW$40 .dwtag DW_TAG_member + 1401 .dwattr $C$DW$40, DW_AT_type(*$C$DW$T$22) + 1402 .dwattr $C$DW$40, DW_AT_name("bufend") + 1403 .dwattr $C$DW$40, DW_AT_TI_symbol_name("bufend") + 1404 .dwattr $C$DW$40, DW_AT_data_member_location[DW_OP_plus_uconst 0x6] + 1405 .dwattr $C$DW$40, DW_AT_accessibility(DW_ACCESS_public) + 1406 .dwattr $C$DW$40, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1407 .dwattr $C$DW$40, DW_AT_decl_line(0x55) + 1408 .dwattr $C$DW$40, DW_AT_decl_column(0x16) + 1409 + 1410 $C$DW$41 .dwtag DW_TAG_member + 1411 .dwattr $C$DW$41, DW_AT_type(*$C$DW$T$22) + 1412 .dwattr $C$DW$41, DW_AT_name("buff_stop") + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 60 + + 1413 .dwattr $C$DW$41, DW_AT_TI_symbol_name("buff_stop") + 1414 .dwattr $C$DW$41, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 1415 .dwattr $C$DW$41, DW_AT_accessibility(DW_ACCESS_public) + 1416 .dwattr $C$DW$41, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1417 .dwattr $C$DW$41, DW_AT_decl_line(0x56) + 1418 .dwattr $C$DW$41, DW_AT_decl_column(0x16) + 1419 + 1420 $C$DW$42 .dwtag DW_TAG_member + 1421 .dwattr $C$DW$42, DW_AT_type(*$C$DW$T$11) + 1422 .dwattr $C$DW$42, DW_AT_name("flags") + 1423 .dwattr $C$DW$42, DW_AT_TI_symbol_name("flags") + 1424 .dwattr $C$DW$42, DW_AT_data_member_location[DW_OP_plus_uconst 0xa] + 1425 .dwattr $C$DW$42, DW_AT_accessibility(DW_ACCESS_public) + 1426 .dwattr $C$DW$42, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1427 .dwattr $C$DW$42, DW_AT_decl_line(0x57) + 1428 .dwattr $C$DW$42, DW_AT_decl_column(0x16) + 1429 + 1430 .dwattr $C$DW$T$23, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1431 .dwattr $C$DW$T$23, DW_AT_decl_line(0x51) + 1432 .dwattr $C$DW$T$23, DW_AT_decl_column(0x08) + 1433 .dwendtag $C$DW$T$23 + 1434 + 1435 $C$DW$T$126 .dwtag DW_TAG_typedef + 1436 .dwattr $C$DW$T$126, DW_AT_name("FILE") + 1437 .dwattr $C$DW$T$126, DW_AT_type(*$C$DW$T$23) + 1438 .dwattr $C$DW$T$126, DW_AT_language(DW_LANG_C) + 1439 .dwattr $C$DW$T$126, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1440 .dwattr $C$DW$T$126, DW_AT_decl_line(0x5c) + 1441 .dwattr $C$DW$T$126, DW_AT_decl_column(0x18) + 1442 + 1443 + 1444 $C$DW$T$20 .dwtag DW_TAG_structure_type + 1445 .dwattr $C$DW$T$20, DW_AT_name("__timer") + 1446 .dwattr $C$DW$T$20, DW_AT_declaration + 1447 .dwattr $C$DW$T$20, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1448 .dwattr $C$DW$T$20, DW_AT_decl_line(0x4b) + 1449 .dwattr $C$DW$T$20, DW_AT_decl_column(0x10) + 1450 .dwendtag $C$DW$T$20 + 1451 + 1452 $C$DW$T$127 .dwtag DW_TAG_pointer_type + 1453 .dwattr $C$DW$T$127, DW_AT_type(*$C$DW$T$20) + 1454 .dwattr $C$DW$T$127, DW_AT_address_class(0x10) + 1455 + 1456 $C$DW$T$128 .dwtag DW_TAG_typedef + 1457 .dwattr $C$DW$T$128, DW_AT_name("__timer_t") + 1458 .dwattr $C$DW$T$128, DW_AT_type(*$C$DW$T$127) + 1459 .dwattr $C$DW$T$128, DW_AT_language(DW_LANG_C) + 1460 .dwattr $C$DW$T$128, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1461 .dwattr $C$DW$T$128, DW_AT_decl_line(0x4b) + 1462 .dwattr $C$DW$T$128, DW_AT_decl_column(0x19) + 1463 + 1464 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C) + 1465 + 1466 ;*************************************************************** + 1467 ;* DWARF CIE ENTRIES * + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 61 + + 1468 ;*************************************************************** + 1469 + 1470 $C$DW$CIE .dwcie 16 + 1471 .dwcfi cfa_register, 1 + 1472 .dwcfi cfa_offset, 0 + 1473 .dwcfi same_value, 0 + 1474 .dwcfi same_value, 1 + 1475 .dwcfi same_value, 3 + 1476 .dwcfi same_value, 4 + 1477 .dwcfi same_value, 5 + 1478 .dwcfi same_value, 6 + 1479 .dwcfi same_value, 7 + 1480 .dwcfi same_value, 8 + 1481 .dwcfi same_value, 9 + 1482 .dwcfi same_value, 10 + 1483 .dwendentry + 1484 + 1485 ;*************************************************************** + 1486 ;* DWARF REGISTER MAP * + 1487 ;*************************************************************** + 1488 + 1489 $C$DW$43 .dwtag DW_TAG_TI_assign_register + 1490 .dwattr $C$DW$43, DW_AT_name("PC") + 1491 .dwattr $C$DW$43, DW_AT_location[DW_OP_reg0] + 1492 + 1493 $C$DW$44 .dwtag DW_TAG_TI_assign_register + 1494 .dwattr $C$DW$44, DW_AT_name("SP") + 1495 .dwattr $C$DW$44, DW_AT_location[DW_OP_reg1] + 1496 + 1497 $C$DW$45 .dwtag DW_TAG_TI_assign_register + 1498 .dwattr $C$DW$45, DW_AT_name("SR") + 1499 .dwattr $C$DW$45, DW_AT_location[DW_OP_reg2] + 1500 + 1501 $C$DW$46 .dwtag DW_TAG_TI_assign_register + 1502 .dwattr $C$DW$46, DW_AT_name("CG") + 1503 .dwattr $C$DW$46, DW_AT_location[DW_OP_reg3] + 1504 + 1505 $C$DW$47 .dwtag DW_TAG_TI_assign_register + 1506 .dwattr $C$DW$47, DW_AT_name("r4") + 1507 .dwattr $C$DW$47, DW_AT_location[DW_OP_reg4] + 1508 + 1509 $C$DW$48 .dwtag DW_TAG_TI_assign_register + 1510 .dwattr $C$DW$48, DW_AT_name("r5") + 1511 .dwattr $C$DW$48, DW_AT_location[DW_OP_reg5] + 1512 + 1513 $C$DW$49 .dwtag DW_TAG_TI_assign_register + 1514 .dwattr $C$DW$49, DW_AT_name("r6") + 1515 .dwattr $C$DW$49, DW_AT_location[DW_OP_reg6] + 1516 + 1517 $C$DW$50 .dwtag DW_TAG_TI_assign_register + 1518 .dwattr $C$DW$50, DW_AT_name("r7") + 1519 .dwattr $C$DW$50, DW_AT_location[DW_OP_reg7] + 1520 + 1521 $C$DW$51 .dwtag DW_TAG_TI_assign_register + 1522 .dwattr $C$DW$51, DW_AT_name("r8") + MSP430 Assembler PC v20.2.5 Fri Sep 3 14:07:11 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{118F4CF4-F323-433D-AB66-43D810941C8C} PAGE 62 + + 1523 .dwattr $C$DW$51, DW_AT_location[DW_OP_reg8] + 1524 + 1525 $C$DW$52 .dwtag DW_TAG_TI_assign_register + 1526 .dwattr $C$DW$52, DW_AT_name("r9") + 1527 .dwattr $C$DW$52, DW_AT_location[DW_OP_reg9] + 1528 + 1529 $C$DW$53 .dwtag DW_TAG_TI_assign_register + 1530 .dwattr $C$DW$53, DW_AT_name("r10") + 1531 .dwattr $C$DW$53, DW_AT_location[DW_OP_reg10] + 1532 + 1533 $C$DW$54 .dwtag DW_TAG_TI_assign_register + 1534 .dwattr $C$DW$54, DW_AT_name("r11") + 1535 .dwattr $C$DW$54, DW_AT_location[DW_OP_reg11] + 1536 + 1537 $C$DW$55 .dwtag DW_TAG_TI_assign_register + 1538 .dwattr $C$DW$55, DW_AT_name("r12") + 1539 .dwattr $C$DW$55, DW_AT_location[DW_OP_reg12] + 1540 + 1541 $C$DW$56 .dwtag DW_TAG_TI_assign_register + 1542 .dwattr $C$DW$56, DW_AT_name("r13") + 1543 .dwattr $C$DW$56, DW_AT_location[DW_OP_reg13] + 1544 + 1545 $C$DW$57 .dwtag DW_TAG_TI_assign_register + 1546 .dwattr $C$DW$57, DW_AT_name("r14") + 1547 .dwattr $C$DW$57, DW_AT_location[DW_OP_reg14] + 1548 + 1549 $C$DW$58 .dwtag DW_TAG_TI_assign_register + 1550 .dwattr $C$DW$58, DW_AT_name("r15") + 1551 .dwattr $C$DW$58, DW_AT_location[DW_OP_reg15] + 1552 + 1553 $C$DW$59 .dwtag DW_TAG_TI_assign_register + 1554 .dwattr $C$DW$59, DW_AT_name("CIE_RETA") + 1555 .dwattr $C$DW$59, DW_AT_location[DW_OP_reg16] + 1556 + 1557 .dwendtag $C$DW$CU + 1558 + +No Assembly Errors, No Assembly Warnings diff --git a/CPE325/L2_P1/Debug/p1.obj b/CPE325/L2_P1/Debug/p1.obj new file mode 100644 index 0000000..4265740 Binary files /dev/null and b/CPE325/L2_P1/Debug/p1.obj differ diff --git a/CPE325/L2_P1/Debug/sources.mk b/CPE325/L2_P1/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/L2_P1/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/L2_P1/Debug/subdir_rules.mk b/CPE325/L2_P1/Debug/subdir_rules.mk new file mode 100644 index 0000000..1d96609 --- /dev/null +++ b/CPE325/L2_P1/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/L2_P1" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power="all" --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/L2_P1/p1.c b/CPE325/L2_P1/p1.c new file mode 100644 index 0000000..603a077 --- /dev/null +++ b/CPE325/L2_P1/p1.c @@ -0,0 +1,60 @@ +/*------------------------------------------------------------------------------ + * File: p1.c + * Function: Prints out variables according to their Data Type with the size and the ranges of the variables + * Description: This C program outputs numbers using + * Input: None + * Output: " + * Author(s): Noah Woodlee + * Lab Section: 09 + * Date: Aug 20, 2021 + *----------------------------------------------------------------------------*/ +#include +#include +#include +#include + +int main() +{ + WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer + // Printf statements + // Header + printf("-------------------------------------------------------------------------------------------------------------------\n"); + printf("| Data Type | Value | Size (in bytes) | Min | Max |\n"); + printf("-------------------------------------------------------------------------------------------------------------------\n"); + // signed char + char signedChar = 'a'; + printf("| signed char | '%c' | %d | %d | %d |\n",signedChar,sizeof(signedChar),SCHAR_MIN,SCHAR_MAX); + // short int + int shortInt = 12; + printf("| short int | %hd | %d | %d | %d |\n",shortInt,sizeof(shortInt),SHRT_MIN,SHRT_MAX); + // int + int integer = 900; + printf("| int | %d | %d | %d | %d |\n",integer,sizeof(integer),INT_MIN,INT_MAX); + // long int + int longInt = 200; + printf("| long int | %hi | %i | %i | %i |\n",longInt,sizeof(longInt),LONG_MIN,LONG_MAX); + // long long int + int longlongInt = -400; + printf("| long long int | %hhi | %d | %d | %d |\n",longlongInt,sizeof(longlongInt),LLONG_MIN,LLONG_MAX); + // unsigned char + char unsignedChar = 'o'; + printf("| unsigned char | '%c' | %d | %lu | %lu |\n",unsignedChar,sizeof(unsignedChar),0,UCHAR_MAX); + //unsigned short int + int unsignedshortInt = 500; + printf("| unsigned short int | %hu | %d | %lu | %lu |\n",unsignedshortInt,sizeof(unsignedshortInt),0,LONG_MAX); + //unsigned int + int unsignedInt = 500; + printf("| unsigned int | %u | %l | %u | %u |\n",unsignedInt,sizeof(unsignedInt),0,LONG_MAX); + //unsigned long int + int unsignedlongInt = 800; + printf("| unsigned long int | %lu | %lu | %u | %ld |\n",unsignedlongInt,sizeof(unsignedlongInt),0,ULONG_MAX); + //unsigned long long int + int unsignedlonglongInt = 5000; + printf("| unsigned long long int | %llu | %llu | %llu | %llu |\n",unsignedlonglongInt,sizeof(unsignedlonglongInt),0,ULLONG_MAX); + //float + float flo = 50.022; + printf("| float | %f | %d | %f | %f |\n",flo,sizeof(flo), 16777215,FLT_MAX); + //double + double dou = 5506; + printf("| double | '%E' | %d | %e | %e |\n",dou,sizeof(dou),DBL_MIN,DBL_MAX); +} diff --git a/CPE325/L2_P1/targetConfigs/MSP430F5529.ccxml b/CPE325/L2_P1/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/L2_P1/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/L2_P1/targetConfigs/readme.txt b/CPE325/L2_P1/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/L2_P1/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/L2_P3/Debug/ccsObjs.opt b/CPE325/L2_P3/Debug/ccsObjs.opt new file mode 100644 index 0000000..0b285e2 --- /dev/null +++ b/CPE325/L2_P3/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./p3.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/L2_P3/Debug/makefile b/CPE325/L2_P3/Debug/makefile new file mode 100644 index 0000000..ca5bc7c --- /dev/null +++ b/CPE325/L2_P3/Debug/makefile @@ -0,0 +1,168 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./p3.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +L2_P3.out \ + +EXE_OUTPUTS__QUOTED += \ +"L2_P3.out" \ + +BIN_OUTPUTS += \ +L2_P3.hex \ + +BIN_OUTPUTS__QUOTED += \ +"L2_P3.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "L2_P3.out" + +# Tool invocations +L2_P3.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --advice:power=all --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing -z -m"L2_P3.map" --heap_size=300 --stack_size=160 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="L2_P3_linkInfo.xml" --use_hw_mpy=F5 --rom_model -o "L2_P3.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +L2_P3.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "L2_P3.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "p3.lst" + -$(RM) "p3.obj" + -$(RM) "p3.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/L2_P3/Debug/objects.mk b/CPE325/L2_P3/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/L2_P3/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/L2_P3/Debug/p3.d b/CPE325/L2_P3/Debug/p3.d new file mode 100644 index 0000000..fc1e148 --- /dev/null +++ b/CPE325/L2_P3/Debug/p3.d @@ -0,0 +1,6 @@ +# FIXED + +p3.obj: ../p3.c + +../p3.c: + diff --git a/CPE325/L2_P3/Debug/sources.mk b/CPE325/L2_P3/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/L2_P3/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/L2_P3/Debug/subdir_rules.mk b/CPE325/L2_P3/Debug/subdir_rules.mk new file mode 100644 index 0000000..c37e7ca --- /dev/null +++ b/CPE325/L2_P3/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/L2_P3" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/L2_P3/p3.c b/CPE325/L2_P3/p3.c new file mode 100644 index 0000000..1ace872 --- /dev/null +++ b/CPE325/L2_P3/p3.c @@ -0,0 +1,32 @@ +/*------------------------------------------------------------------------------ + * File: p3.c + * Function: Prints out variables according to their Data Type with the size and the ranges of the variables + * Description: This C program outputs numbers using + * Input: None + * Output: " + * Author(s): Noah Woodlee + * Lab Section: 09 + * Date: Aug 20, 2021 + *----------------------------------------------------------------------------*/ + +int a[5]={0xA, 0x6, -0x8, 0x5, 0xC}; +int b[5] = {0xD, -0xE, 0x7, 0x2, 0x1}; + +int orOp_0 = (0xA | 0xD); +int andOp_0 = (0xA & 0xD); + +int orOp_1 = (0x6 | -0xE); +int andOp_1 = (0x6 & -0xE); + +int orOp_2 = (a[2] | b[2]); +int andOp_2 = (a[2] & b[2]); + +int orOp_3 = (a[3] | b[3]); +int andOp_3 = (a[3] & b[3]); + +int orOp_4 = (a[4] | b[4]); +int andOp_4 = (a[4] & b[4]); + +printf("Input array a: {0xA, 0x6, -0x8, 0x5, 0xC}\n"); +printf("Input array b: {0xD, -0xE, 0x7, 0x2, 0x1}\n"); +printf("The OR opperation for the 0th element is: %o",(a[0] | b[0])); diff --git a/CPE325/L2_P3/targetConfigs/MSP430F5529.ccxml b/CPE325/L2_P3/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/L2_P3/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/L2_P3/targetConfigs/readme.txt b/CPE325/L2_P3/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/L2_P3/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/L3/Debug/L3.d b/CPE325/L3/Debug/L3.d new file mode 100644 index 0000000..697da16 --- /dev/null +++ b/CPE325/L3/Debug/L3.d @@ -0,0 +1,42 @@ +# FIXED + +L3.obj: ../L3.c +L3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +L3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h +L3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +L3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h + +../L3.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + diff --git a/CPE325/L3/Debug/L3.map b/CPE325/L3/Debug/L3.map new file mode 100644 index 0000000..2cfc77b --- /dev/null +++ b/CPE325/L3/Debug/L3.map @@ -0,0 +1,1781 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Thu Dec 2 20:37:59 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noinit_noargs" address: 00004400 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 000000a0 00001f60 RWIX + FLASH 00004400 0000bb80 0000001c 0000bb64 RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 0000012a 000142ce RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.stack 0 00004360 000000a0 UNINITIALIZED + 00004360 00000004 rts430x_lc_rd_eabi.lib : boot.c.obj (.stack) + 00004364 0000009c --HOLE-- + +.text:_isr +* 0 00004400 0000001c + 00004400 00000014 rts430x_lc_rd_eabi.lib : boot.c.obj (.text:_isr:_c_int00_noinit_noargs) + 00004414 00000008 : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00004400 00000000 UNINITIALIZED + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430x_lc_rd_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430x_lc_rd_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430x_lc_rd_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430x_lc_rd_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430x_lc_rd_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430x_lc_rd_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430x_lc_rd_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430x_lc_rd_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430x_lc_rd_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430x_lc_rd_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430x_lc_rd_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430x_lc_rd_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430x_lc_rd_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430x_lc_rd_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430x_lc_rd_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430x_lc_rd_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430x_lc_rd_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430x_lc_rd_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430x_lc_rd_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430x_lc_rd_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430x_lc_rd_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430x_lc_rd_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430x_lc_rd_eabi.lib : boot.c.obj (.reset) + +.text 0 00010000 0000012a + 00010000 00000120 L3.obj (.text:main) + 00010120 00000006 rts430x_lc_rd_eabi.lib : exit.c.obj (.text:abort) + 00010126 00000004 : pre_init.c.obj (.text:_system_pre_init) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + L3.obj 288 0 0 + +--+------------------+------+---------+---------+ + Total: 288 0 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430x_lc_rd_eabi.lib + boot.c.obj 20 2 0 + isr_trap.asm.obj 8 0 0 + exit.c.obj 6 0 0 + pre_init.c.obj 4 0 0 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + +--+------------------+------+---------+---------+ + Total: 38 46 0 + + Stack: 0 0 160 + +--+------------------+------+---------+---------+ + Grand Total: 326 46 160 + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +00010120 C$$EXIT +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +00000902 USBCNF +00000903 USBCNF_H +00000902 USBCNF_L +0000093c USBCTL +0000093a USBFN +0000093b USBFN_H +0000093a USBFN_L +0000093f USBFUNADR +0000093d USBIE +00002378 USBIEP0BUF +000023c9 USBIEPBBAX_1 +000023d1 USBIEPBBAX_2 +000023d9 USBIEPBBAX_3 +000023e1 USBIEPBBAX_4 +000023e9 USBIEPBBAX_5 +000023f1 USBIEPBBAX_6 +000023f9 USBIEPBBAX_7 +000023cd USBIEPBBAY_1 +000023d5 USBIEPBBAY_2 +000023dd USBIEPBBAY_3 +000023e5 USBIEPBBAY_4 +000023ed USBIEPBBAY_5 +000023f5 USBIEPBBAY_6 +000023fd USBIEPBBAY_7 +000023ca USBIEPBCTX_1 +000023d2 USBIEPBCTX_2 +000023da USBIEPBCTX_3 +000023e2 USBIEPBCTX_4 +000023ea USBIEPBCTX_5 +000023f2 USBIEPBCTX_6 +000023fa USBIEPBCTX_7 +000023ce USBIEPBCTY_1 +000023d6 USBIEPBCTY_2 +000023de USBIEPBCTY_3 +000023e6 USBIEPBCTY_4 +000023ee USBIEPBCTY_5 +000023f6 USBIEPBCTY_6 +000023fe USBIEPBCTY_7 +00000920 USBIEPCNF_0 +000023c8 USBIEPCNF_1 +000023d0 USBIEPCNF_2 +000023d8 USBIEPCNF_3 +000023e0 USBIEPCNF_4 +000023e8 USBIEPCNF_5 +000023f0 USBIEPCNF_6 +000023f8 USBIEPCNF_7 +00000921 USBIEPCNT_0 +0000092e USBIEPIE +00000930 USBIEPIFG +000023cf USBIEPSIZXY_1 +000023d7 USBIEPSIZXY_2 +000023df USBIEPSIZXY_3 +000023e7 USBIEPSIZXY_4 +000023ef USBIEPSIZXY_5 +000023f7 USBIEPSIZXY_6 +000023ff USBIEPSIZXY_7 +0000093e USBIFG +00000900 USBKEYID +00000901 USBKEYID_H +00000900 USBKEYID_L +00000936 USBMAINT +00000937 USBMAINT_H +00000936 USBMAINT_L +00002370 USBOEP0BUF +00002389 USBOEPBBAX_1 +00002391 USBOEPBBAX_2 +00002399 USBOEPBBAX_3 +000023a1 USBOEPBBAX_4 +000023a9 USBOEPBBAX_5 +000023b1 USBOEPBBAX_6 +000023b9 USBOEPBBAX_7 +0000238d USBOEPBBAY_1 +00002395 USBOEPBBAY_2 +0000239d USBOEPBBAY_3 +000023a5 USBOEPBBAY_4 +000023ad USBOEPBBAY_5 +000023b5 USBOEPBBAY_6 +000023bd USBOEPBBAY_7 +0000238a USBOEPBCTX_1 +00002392 USBOEPBCTX_2 +0000239a USBOEPBCTX_3 +000023a2 USBOEPBCTX_4 +000023aa USBOEPBCTX_5 +000023b2 USBOEPBCTX_6 +000023ba USBOEPBCTX_7 +0000238e USBOEPBCTY_1 +00002396 USBOEPBCTY_2 +0000239e USBOEPBCTY_3 +000023a6 USBOEPBCTY_4 +000023ae USBOEPBCTY_5 +000023b6 USBOEPBCTY_6 +000023be USBOEPBCTY_7 +00000922 USBOEPCNF_0 +00002388 USBOEPCNF_1 +00002390 USBOEPCNF_2 +00002398 USBOEPCNF_3 +000023a0 USBOEPCNF_4 +000023a8 USBOEPCNF_5 +000023b0 USBOEPCNF_6 +000023b8 USBOEPCNF_7 +00000923 USBOEPCNT_0 +0000092f USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +00004400 __STACK_END +000000a0 __STACK_SIZE +00004414 __TI_ISR_TRAP +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ +00004400 _c_int00_noinit_noargs +0000fffe _reset_vector +00004360 _stack +00010126 _system_pre_init +00010120 abort +00010000 main + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +000000a0 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT 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ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H +00000726 ADC12MEM3 +00000726 ADC12MEM3_L +00000727 ADC12MEM3_H +00000728 ADC12MEM4 +00000728 ADC12MEM4_L +00000729 ADC12MEM4_H +0000072a ADC12MEM5 +0000072a ADC12MEM5_L +0000072b ADC12MEM5_H +0000072c ADC12MEM6 +0000072c ADC12MEM6_L +0000072d ADC12MEM6_H +0000072e ADC12MEM7 +0000072e ADC12MEM7_L +0000072f ADC12MEM7_H +00000730 ADC12MEM8 +00000730 ADC12MEM8_L +00000731 ADC12MEM8_H +00000732 ADC12MEM9 +00000732 ADC12MEM9_L +00000733 ADC12MEM9_H +00000734 ADC12MEM10 +00000734 ADC12MEM10_L +00000735 ADC12MEM10_H +00000736 ADC12MEM11 +00000736 ADC12MEM11_L +00000737 ADC12MEM11_H +00000738 ADC12MEM12 +00000738 ADC12MEM12_L +00000739 ADC12MEM12_H +0000073a ADC12MEM13 +0000073a ADC12MEM13_L +0000073b ADC12MEM13_H +0000073c ADC12MEM14 +0000073c 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_system_pre_init +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[766 symbols] diff --git a/CPE325/L3/Debug/L3.obj b/CPE325/L3/Debug/L3.obj new file mode 100644 index 0000000..4040ff7 Binary files /dev/null and b/CPE325/L3/Debug/L3.obj differ diff --git a/CPE325/L3/Debug/L3.out b/CPE325/L3/Debug/L3.out new file mode 100644 index 0000000..0ed6d7f Binary files /dev/null and b/CPE325/L3/Debug/L3.out differ diff --git a/CPE325/L3/Debug/L3_linkInfo.xml b/CPE325/L3/Debug/L3_linkInfo.xml new file mode 100644 index 0000000..44f4048 --- /dev/null +++ b/CPE325/L3/Debug/L3_linkInfo.xml @@ -0,0 +1,5677 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x61a98307 + 0x1 + L3.out + + _c_int00_noinit_noargs +
0x4400
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USBIEPBBAX_3 + 0x23d9 + + + USBIEPCNF_3 + 0x23d8 + + + USBIEPSIZXY_2 + 0x23d7 + + + USBIEPBCTY_2 + 0x23d6 + + + USBIEPBBAY_2 + 0x23d5 + + + USBIEPBCTX_2 + 0x23d2 + + + USBIEPBBAX_2 + 0x23d1 + + + USBIEPCNF_2 + 0x23d0 + + + USBIEPSIZXY_1 + 0x23cf + + + USBIEPBCTY_1 + 0x23ce + + + USBIEPBBAY_1 + 0x23cd + + + USBIEPBCTX_1 + 0x23ca + + + USBIEPBBAX_1 + 0x23c9 + + + USBIEPCNF_1 + 0x23c8 + + + USBOEPSIZXY_7 + 0x23bf + + + USBOEPBCTY_7 + 0x23be + + + USBOEPBBAY_7 + 0x23bd + + + USBOEPBCTX_7 + 0x23ba + + + USBOEPBBAX_7 + 0x23b9 + + + USBOEPCNF_7 + 0x23b8 + + + USBOEPSIZXY_6 + 0x23b7 + + + USBOEPBCTY_6 + 0x23b6 + + + USBOEPBBAY_6 + 0x23b5 + + + USBOEPBCTX_6 + 0x23b2 + + + USBOEPBBAX_6 + 0x23b1 + + + USBOEPCNF_6 + 0x23b0 + + + USBOEPSIZXY_5 + 0x23af + + + USBOEPBCTY_5 + 0x23ae + + + USBOEPBBAY_5 + 0x23ad + + + USBOEPBCTX_5 + 0x23aa + + + USBOEPBBAX_5 + 0x23a9 + + + USBOEPCNF_5 + 0x23a8 + + + USBOEPSIZXY_4 + 0x23a7 + + + USBOEPBCTY_4 + 0x23a6 + + + USBOEPBBAY_4 + 0x23a5 + + + USBOEPBCTX_4 + 0x23a2 + + + USBOEPBBAX_4 + 0x23a1 + + + USBOEPCNF_4 + 0x23a0 + + + USBOEPSIZXY_3 + 0x239f + + + USBOEPBCTY_3 + 0x239e + + + USBOEPBBAY_3 + 0x239d + + + USBOEPBCTX_3 + 0x239a + + + USBOEPBBAX_3 + 0x2399 + + + USBOEPCNF_3 + 0x2398 + + + USBOEPSIZXY_2 + 0x2397 + + + USBOEPBCTY_2 + 0x2396 + + + USBOEPBBAY_2 + 0x2395 + + + USBOEPBCTX_2 + 0x2392 + + + USBOEPBBAX_2 + 0x2391 + + + USBOEPCNF_2 + 0x2390 + + + USBOEPSIZXY_1 + 0x238f + + + USBOEPBCTY_1 + 0x238e + + + USBOEPBBAY_1 + 0x238d + + + USBOEPBCTX_1 + 0x238a + + + USBOEPBBAX_1 + 0x2389 + + + USBOEPCNF_1 + 0x2388 + + + USBSUBLK + 0x2380 + + + USBIEP0BUF + 0x2378 + + + USBOEP0BUF + 0x2370 + + + USBTOPBUFF + 0x236f + + + USBSTABUFF + 0x1c00 + + + UCSCTL0 + 0x160 + + + UCSCTL0_L + 0x160 + + + UCSCTL0_H + 0x161 + + + UCSCTL1 + 0x162 + + + UCSCTL1_L + 0x162 + + + UCSCTL1_H + 0x163 + + + UCSCTL2 + 0x164 + + + UCSCTL2_L + 0x164 + + + UCSCTL2_H + 0x165 + + + UCSCTL3 + 0x166 + + + UCSCTL3_L + 0x166 + + + UCSCTL3_H + 0x167 + + + UCSCTL4 + 0x168 + + + UCSCTL4_L + 0x168 + + + UCSCTL4_H + 0x169 + + + UCSCTL5 + 0x16a + + + UCSCTL5_L + 0x16a + + + UCSCTL5_H + 0x16b + + + UCSCTL6 + 0x16c + + + UCSCTL6_L + 0x16c + + + UCSCTL6_H + 0x16d + + + UCSCTL7 + 0x16e + + + UCSCTL7_L + 0x16e + + + UCSCTL7_H + 0x16f + + + UCSCTL8 + 0x170 + + + UCSCTL8_L + 0x170 + + + UCSCTL8_H + 0x171 + + + UCA0CTLW0 + 0x5c0 + + + UCA0CTLW0_L + 0x5c0 + + + UCA0CTLW0_H + 0x5c1 + + + UCA0BRW + 0x5c6 + + + UCA0BRW_L + 0x5c6 + + + UCA0BRW_H + 0x5c7 + + + UCA0MCTL + 0x5c8 + + + UCA0STAT + 0x5ca + + + UCA0RXBUF + 0x5cc + + + UCA0TXBUF + 0x5ce + + + UCA0ABCTL + 0x5d0 + + + UCA0IRCTL + 0x5d2 + + + UCA0IRCTL_L + 0x5d2 + + + UCA0IRCTL_H + 0x5d3 + + + UCA0ICTL + 0x5dc + + + UCA0ICTL_L + 0x5dc + + + UCA0ICTL_H + 0x5dd + + + UCA0IV + 0x5de + + + UCB0CTLW0 + 0x5e0 + + + UCB0CTLW0_L + 0x5e0 + + + UCB0CTLW0_H + 0x5e1 + + + UCB0BRW + 0x5e6 + + + UCB0BRW_L + 0x5e6 + + + UCB0BRW_H + 0x5e7 + + + UCB0STAT + 0x5ea + + + UCB0RXBUF + 0x5ec + + + UCB0TXBUF + 0x5ee + + + UCB0I2COA + 0x5f0 + + + UCB0I2COA_L + 0x5f0 + + + UCB0I2COA_H + 0x5f1 + + + UCB0I2CSA + 0x5f2 + + + UCB0I2CSA_L + 0x5f2 + + + UCB0I2CSA_H + 0x5f3 + + + UCB0ICTL + 0x5fc + + + UCB0ICTL_L + 0x5fc + + + UCB0ICTL_H + 0x5fd + + + UCB0IV + 0x5fe + + + UCA1CTLW0 + 0x600 + + + UCA1CTLW0_L + 0x600 + + + UCA1CTLW0_H + 0x601 + + + UCA1BRW + 0x606 + + + UCA1BRW_L + 0x606 + + + UCA1BRW_H + 0x607 + + + UCA1MCTL + 0x608 + + + UCA1STAT + 0x60a + + + UCA1RXBUF + 0x60c + + + UCA1TXBUF + 0x60e + + + UCA1ABCTL + 0x610 + + + UCA1IRCTL + 0x612 + + + UCA1IRCTL_L + 0x612 + + + UCA1IRCTL_H + 0x613 + + + UCA1ICTL + 0x61c + + + UCA1ICTL_L + 0x61c + + + UCA1ICTL_H + 0x61d + + + UCA1IV + 0x61e + + + UCB1CTLW0 + 0x620 + + + UCB1CTLW0_L + 0x620 + + + UCB1CTLW0_H + 0x621 + + + UCB1BRW + 0x626 + + + UCB1BRW_L + 0x626 + + + UCB1BRW_H + 0x627 + + + UCB1STAT + 0x62a + + + UCB1RXBUF + 0x62c + + + UCB1TXBUF + 0x62e + + + UCB1I2COA + 0x630 + + + UCB1I2COA_L + 0x630 + + + UCB1I2COA_H + 0x631 + + + UCB1I2CSA + 0x632 + + + UCB1I2CSA_L + 0x632 + + + UCB1I2CSA_H + 0x633 + + + UCB1ICTL + 0x63c + + + UCB1ICTL_L + 0x63c + + + UCB1ICTL_H + 0x63d + + + UCB1IV + 0x63e + + + WDTCTL + 0x15c + + + WDTCTL_L + 0x15c + + + WDTCTL_H + 0x15d + + + __STACK_SIZE + 0xa0 + + + __STACK_END + 0x4400 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + main + 0x10000 + + + + __TI_int41 + 0xffd2 + + + + __TI_int42 + 0xffd4 + + + + __TI_int43 + 0xffd6 + + + + __TI_int44 + 0xffd8 + + + + __TI_int45 + 0xffda + + + + __TI_int46 + 0xffdc + + + + __TI_int47 + 0xffde + + + + __TI_int48 + 0xffe0 + + + + __TI_int49 + 0xffe2 + + + + __TI_int50 + 0xffe4 + + + + __TI_int51 + 0xffe6 + + + + __TI_int52 + 0xffe8 + + + + __TI_int53 + 0xffea + + + + __TI_int54 + 0xffec + + + + __TI_int55 + 0xffee + + + + __TI_int56 + 0xfff0 + + + + __TI_int57 + 0xfff2 + + + + __TI_int58 + 0xfff4 + + + + __TI_int59 + 0xfff6 + + + + __TI_int60 + 0xfff8 + + + + __TI_int61 + 0xfffa + + + + __TI_int62 + 0xfffc + + + + __TI_ISR_TRAP + 0x4414 + + + + _c_int00_noinit_noargs + 0x4400 + + + + _stack + 0x4360 + + + + _reset_vector + 0xfffe + + + + _system_pre_init + 0x10126 + + + + C$$EXIT + 0x10120 + + + + abort + 0x10120 + + + + Link errors: red sections failed placement + diff --git a/CPE325/L3/Debug/Lab03_D2.d b/CPE325/L3/Debug/Lab03_D2.d new file mode 100644 index 0000000..d199d00 --- /dev/null +++ b/CPE325/L3/Debug/Lab03_D2.d @@ -0,0 +1,21 @@ +# FIXED + +Lab03_D2.obj: ../Lab03_D2.c +Lab03_D2.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +Lab03_D2.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h +Lab03_D2.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +Lab03_D2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +Lab03_D2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h + +../Lab03_D2.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + diff --git a/CPE325/L3/Debug/Lab03_D2.obj b/CPE325/L3/Debug/Lab03_D2.obj new file mode 100644 index 0000000..2265ae2 Binary files /dev/null and b/CPE325/L3/Debug/Lab03_D2.obj differ diff --git a/CPE325/L3/Debug/Lab03_D3.d b/CPE325/L3/Debug/Lab03_D3.d new file mode 100644 index 0000000..16d27b8 --- /dev/null +++ b/CPE325/L3/Debug/Lab03_D3.d @@ -0,0 +1,6 @@ +# FIXED + +Lab03_D3.obj: ../Lab03_D3.c + +../Lab03_D3.c: + diff --git a/CPE325/L3/Debug/Lab03_D3.obj b/CPE325/L3/Debug/Lab03_D3.obj new file mode 100644 index 0000000..6b99cbb Binary files /dev/null and b/CPE325/L3/Debug/Lab03_D3.obj differ diff --git a/CPE325/L3/Debug/ccsObjs.opt b/CPE325/L3/Debug/ccsObjs.opt new file mode 100644 index 0000000..e9e456c --- /dev/null +++ b/CPE325/L3/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./L3.obj" "./Lab03_D2.obj" "./Lab03_D3.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/L3/Debug/makefile b/CPE325/L3/Debug/makefile new file mode 100644 index 0000000..310302d --- /dev/null +++ b/CPE325/L3/Debug/makefile @@ -0,0 +1,169 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./L3.obj" \ +"./Lab03_D2.obj" \ +"./Lab03_D3.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +L3.out \ + +EXE_OUTPUTS__QUOTED += \ +"L3.out" \ + +BIN_OUTPUTS += \ +L3.hex \ + +BIN_OUTPUTS__QUOTED += \ +"L3.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "L3.out" + +# Tool invocations +L3.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=F5 --advice:power=all --define=__MSP430F5529__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 -z -m"L3.map" --heap_size=160 --stack_size=160 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="L3_linkInfo.xml" --use_hw_mpy=F5 --rom_model -o "L3.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +L3.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "L3.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "L3.obj" "Lab03_D2.obj" "Lab03_D3.obj" + -$(RM) "L3.d" "Lab03_D2.d" "Lab03_D3.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/L3/Debug/objects.mk b/CPE325/L3/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/L3/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/L3/Debug/sources.mk b/CPE325/L3/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/L3/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/L3/Debug/subdir_rules.mk b/CPE325/L3/Debug/subdir_rules.mk new file mode 100644 index 0000000..5a83fc7 --- /dev/null +++ b/CPE325/L3/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/L3" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430F5529__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --preproc_with_compile --preproc_dependency="$(basename $( +#include + +#define S1 (P2IN&BIT1) +#define S2 (P1IN&BIT1) +#define REDLED BIT0 +#define GREENLED BIT7 + +int main() +{ + WDTCTL = WDTPW + WDTHOLD; // Watchdog timer + P1DIR |= REDLED; // Set port 1 output direction + P4DIR |= GREENLED; // Set port 4 output direction + P2DIR &= ~BIT1; // Clear direction for P2.1 + P1DIR &= ~BIT1; // Clear direction for P1.1 + + P2REN |= BIT1; // Enable Pull-up resistor at P1 + P2OUT |= BIT1; // Required for proper IO + P1REN |= BIT1; // Enable Pull-up resistor at P2 + P1OUT |= BIT1; // Required for proper IO + + P1OUT |= REDLED; // LED 1 is ON + P4OUT |= GREENLED; // LED 2 is ON + + unsigned int i = 0; + while(1) + { + if((S1) == 0) // If S1 is pressed + { + for(i = 2000; i > 0; i--); //Debounce ~20ms + if((S1) == 0) + { + P4OUT |= GREENLED; // LED 2 is ON + for (i = 0;i < 20000; i++); //5 Hz + for (i = 0;i < 10000; i++); // Software delay + P1OUT ^= REDLED; // Toggle LED 1 + while ((S1) == 0) // As long as S1 is pressed + { + P4OUT |= GREENLED; // LED 2 is ON + for (i = 0;i < 20000; i++); //5 Hz + for (i = 0;i < 10000; i++); //Software delay + P1OUT ^= REDLED; // Toggle LED 1 + } + } + } + else if ((S2) == 0) // If S2 is pressed + { + for(i = 2000; i > 0; i--); //Debounce ~20ms + if((S2) == 0) + { + P1OUT |= REDLED; // LED 1 is ON + for (i = 0;i < 50000; i++); //2 Hz + for (i = 0;i < 25000; i++); // Software delay + P4OUT ^= GREENLED; // Toggle LED 2 + while ((S2) == 0) // As long as S2 is pressed + { + P1OUT |= REDLED; // LED 1 is ON + for (i = 0;i < 50000; i++); //2 Hz + for (i = 0;i < 25000; i++); // Software delay + P4OUT ^= GREENLED; // Toggle LED 2 + } + } + } + else + { + P1OUT |= REDLED; + P4OUT |= GREENLED; + } + } +} diff --git a/CPE325/L3/Lab03_D2.c b/CPE325/L3/Lab03_D2.c new file mode 100644 index 0000000..8f796d8 --- /dev/null +++ b/CPE325/L3/Lab03_D2.c @@ -0,0 +1,42 @@ +/*------------------------------------------------------------------------------ + * File: Lab03_D2.c + * Function: Blinking LED1 and LED2 + * Description: This C program toggle LED1 and LED2 at 1Hz by xoring P1.0 and + * P4.7 inside a loop. The LEDs are on when P1.0=1 and P4.7=1. + * The LED1 is initialized to be off and LED2 to be on. + * Clocks: ACLK = 32.768kHz, MCLK = SMCLK = default DCO (~1 MHz) + * MSP-EXP430F5529LP + * ----------------- + * /|\| | + * | | | + * --|RST | + * | P1.0|-->LED1(RED) + * | P4.7|-->LED2(GREEN) + * | | + * Input: None + * Output: LED1 and LED2 blink alternately at a frequency of 1 Hz + * Author(s): Aleksandar Milenkovic, milenkovic@computer.org + * Prawar Poudel, prawar.poudel@uah.edu + * Date: + * ---------------------------------------------------------------------------*/ +#include + +#define REDLED 0x01 // Mask for BIT0 = 0000_0001b +#define GREENLED 0x80 // Mask for BIT7 = 1000_0000b + +void main(void) +{ + WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer + P1DIR |= REDLED; // Set P1.0 to output direction + P4DIR |= GREENLED; // Set P4.7 to output direction + P1OUT &= ~REDLED; // LED1 is OFF + P4OUT |= GREENLED; // LED2 is ON + unsigned int i = 0; + while(1) // Infinite loop + { + for (i = 0; i < 50000; i++); // Delay 0.5s + // 0.5s on, 0.5s off => 1/(1s) = 1Hz + P1OUT ^= REDLED; // Toggle LED1 + P4OUT ^= GREENLED; // Toggle LED2 + } +} diff --git a/CPE325/L3/Lab03_D3.c b/CPE325/L3/Lab03_D3.c new file mode 100644 index 0000000..eac780b --- /dev/null +++ b/CPE325/L3/Lab03_D3.c @@ -0,0 +1,57 @@ +///*------------------------------------------------------------------------------ +// * File: Lab03_D3.c +// * Function: Turning on LED1 when S1 is pressed +// * Description: This C program turns on LED1 connected to P1.0 when the S1 is +// * pressed. S1 is connected to P2.1 and when it is pressed, +// * P2IN, bit 1 is read as a logic 0 (check the schematic). +// * To avoid faulty detection of button press, +// * debouncing delay of 20ms is added before turning on the LED1. +// * Clocks: ACLK = 32.768kHz, MCLK = SMCLK = default DCO (~1 MHz) +// * MSP-EXP430F5529LP +// * ----------------- +// * /|\| | +// * | | | +// * --|RST | +// * | P1.0|-->LED1(RED) +// * | P2.1|<--SW1 +// * | | +// * Input: Pressing S1 +// * Output: LED1 is turned on when S1 is pressed +// * Author(s): Aleksandar Milenkovic, milenkovic@computer.org +// * Prawar Poudel, prawar.poudel@uah.edu +// * Date: +// * ---------------------------------------------------------------------------*/ +//#include +// +//#define S1 P2IN&BIT1 +//#define REDLED 0x01 // Mask for BIT0 = 0000_0001b +//#define GREENLED 0x80 // Mask for BIT7 = 1000_0000b +// +//void main(void) +//{ +// WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer +// P1DIR |= REDLED; // Set P1.0 to output direction +// P1OUT &= ~REDLED; // LED1 is OFF +// +// P2DIR &= ~BIT1; // Set P2.1 as input for S1 input +// P2REN |= BIT1; // Enable the pull-up resistor at P2.1 +// P2OUT |= BIT1; // Required for proper IO +// +// unsigned int i = 0; +// while(1) // Infinite loop +// { +// if ((S1) == 0) // If S1 is pressed +// { +// for (i = 2000; i > 0; i--); // Debounce ~20 ms +// if ((S1) == 0) // If S1 is pressed +// { +// P1OUT |= REDLED; // Turn LED1 on +// } +// while ((S1) == 0); // Hang-on as long as S1 pressed +// } +// else +// { +// P1OUT &= ~REDLED; // Turn LED1 off +// } +// } +//} diff --git a/CPE325/L3/lnk_msp430f5529.cmd b/CPE325/L3/lnk_msp430f5529.cmd new file mode 100755 index 0000000..d595380 --- /dev/null +++ b/CPE325/L3/lnk_msp430f5529.cmd @@ -0,0 +1,251 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************************/ +/* lnk_msp430f5529.cmd - LINKER COMMAND FILE FOR LINKING MSP430F5529 PROGRAMS */ +/* */ +/* Usage: lnk430 -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/L3/targetConfigs/MSP430F5529.ccxml b/CPE325/L3/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/L3/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/L3/targetConfigs/readme.txt b/CPE325/L3/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/L3/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab10_Part1/Debug/Lab10_Part1.map b/CPE325/Lab10_Part1/Debug/Lab10_Part1.map new file mode 100644 index 0000000..5a9d155 --- /dev/null +++ b/CPE325/Lab10_Part1/Debug/Lab10_Part1.map @@ -0,0 +1,979 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Thu Nov 11 23:19:12 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00003124 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOB 00001000 00000080 00000000 00000080 RWIX + INFOA 00001080 00000080 00000000 00000080 RWIX + RAM 00001100 00002000 00000068 00001f98 RWIX + FLASH 00003100 0000cebe 0000006a 0000ce54 RWIX + BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff + INT00 0000ffc0 00000002 00000000 00000002 RWIX + INT01 0000ffc2 00000002 00000000 00000002 RWIX + INT02 0000ffc4 00000002 00000000 00000002 RWIX + INT03 0000ffc6 00000002 00000000 00000002 RWIX + INT04 0000ffc8 00000002 00000000 00000002 RWIX + INT05 0000ffca 00000002 00000000 00000002 RWIX + INT06 0000ffcc 00000002 00000000 00000002 RWIX + INT07 0000ffce 00000002 00000000 00000002 RWIX + INT08 0000ffd0 00000002 00000000 00000002 RWIX + INT09 0000ffd2 00000002 00000000 00000002 RWIX + INT10 0000ffd4 00000002 00000000 00000002 RWIX + INT11 0000ffd6 00000002 00000000 00000002 RWIX + INT12 0000ffd8 00000002 00000000 00000002 RWIX + INT13 0000ffda 00000002 00000000 00000002 RWIX + INT14 0000ffdc 00000002 00000002 00000000 RWIX + INT15 0000ffde 00000002 00000002 00000000 RWIX + INT16 0000ffe0 00000002 00000002 00000000 RWIX + INT17 0000ffe2 00000002 00000002 00000000 RWIX + INT18 0000ffe4 00000002 00000002 00000000 RWIX + INT19 0000ffe6 00000002 00000002 00000000 RWIX + INT20 0000ffe8 00000002 00000002 00000000 RWIX + INT21 0000ffea 00000002 00000002 00000000 RWIX + INT22 0000ffec 00000002 00000002 00000000 RWIX + INT23 0000ffee 00000002 00000002 00000000 RWIX + INT24 0000fff0 00000002 00000002 00000000 RWIX + INT25 0000fff2 00000002 00000002 00000000 RWIX + INT26 0000fff4 00000002 00000002 00000000 RWIX + INT27 0000fff6 00000002 00000002 00000000 RWIX + INT28 0000fff8 00000002 00000002 00000000 RWIX + INT29 0000fffa 00000002 00000002 00000000 RWIX + INT30 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 00010000 000018d2 0000e72e RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.bss 0 00001100 00000018 UNINITIALIZED + 00001100 00000004 (.common:ADCXval) + 00001104 00000004 (.common:ADCYval) + 00001108 00000004 (.common:ADCZval) + 0000110c 00000004 (.common:Xper) + 00001110 00000004 (.common:Yper) + 00001114 00000004 (.common:Zper) + +.stack 0 000030b0 00000050 UNINITIALIZED + 000030b0 00000004 rts430x_lc_rd_eabi.lib : boot.c.obj (.stack) + 000030b4 0000004c --HOLE-- + +.text:_isr +* 0 00003100 00000058 + 00003100 00000024 main.obj (.text:_isr:ADC12ISR) + 00003124 0000001c rts430x_lc_rd_eabi.lib : boot.c.obj (.text:_isr:_c_int00_noargs) + 00003140 00000010 main.obj (.text:_isr:timerA_isr) + 00003150 00000008 rts430x_lc_rd_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00003158 00000012 + 00003158 00000006 (.cinit..bss.load) [load image, compression = zero_init] + 0000315e 00000004 (__TI_handler_table) + 00003162 00000008 (__TI_cinit_table) + +.binit 0 00003100 00000000 + +.init_array +* 0 00003100 00000000 UNINITIALIZED + +$fill000 0 0000ffbe 00000002 + 0000ffbe 00000002 --HOLE-- [fill = ffff] + +DAC12 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430x_lc_rd_eabi.lib : int14.asm.obj (.int14) + +DMA 0 0000ffde 00000002 + 0000ffde 00000002 rts430x_lc_rd_eabi.lib : int15.asm.obj (.int15) + +BASICTIMER +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430x_lc_rd_eabi.lib : int16.asm.obj (.int16) + +PORT2 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430x_lc_rd_eabi.lib : int17.asm.obj (.int17) + +USART1TX 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430x_lc_rd_eabi.lib : int18.asm.obj (.int18) + +USART1RX 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430x_lc_rd_eabi.lib : int19.asm.obj (.int19) + +PORT1 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430x_lc_rd_eabi.lib : int20.asm.obj (.int20) + +TIMERA1 0 0000ffea 00000002 + 0000ffea 00000002 rts430x_lc_rd_eabi.lib : int21.asm.obj (.int21) + +TIMERA0 0 0000ffec 00000002 + 0000ffec 00000002 main.obj (.int22) + +ADC12 0 0000ffee 00000002 + 0000ffee 00000002 main.obj (.int23) + +USCIAB0TX +* 0 0000fff0 00000002 + 0000fff0 00000002 rts430x_lc_rd_eabi.lib : int24.asm.obj (.int24) + +USCIAB0RX +* 0 0000fff2 00000002 + 0000fff2 00000002 rts430x_lc_rd_eabi.lib : int25.asm.obj (.int25) + +WDT 0 0000fff4 00000002 + 0000fff4 00000002 rts430x_lc_rd_eabi.lib : int26.asm.obj (.int26) + +COMPARATORA +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430x_lc_rd_eabi.lib : int27.asm.obj (.int27) + +TIMERB1 0 0000fff8 00000002 + 0000fff8 00000002 rts430x_lc_rd_eabi.lib : int28.asm.obj (.int28) + +TIMERB0 0 0000fffa 00000002 + 0000fffa 00000002 rts430x_lc_rd_eabi.lib : int29.asm.obj (.int29) + +NMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430x_lc_rd_eabi.lib : int30.asm.obj (.int30) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430x_lc_rd_eabi.lib : boot.c.obj (.reset) + +.text 0 00010000 000018d2 + 00010000 0000072a rts430x_lc_rd_eabi.lib : addd.c.obj (.text:__mspabi_addd) + 0001072a 00000466 : frcdivd.c.obj (.text:__TI_frcdivd) + 00010b90 00000298 : mpyd.c.obj (.text:__mspabi_mpyd) + 00010e28 00000222 : divd.c.obj (.text:__mspabi_divd) + 0001104a 000001d0 main.obj (.text:sendData) + 0001121a 00000164 rts430x_lc_rd_eabi.lib : frcmpyd.c.obj (.text:__TI_frcmpyd) + 0001137e 000000b2 : cvtdf.c.obj (.text:__mspabi_cvtdf) + 00011430 0000009e : fltlid.c.obj (.text:__mspabi_fltlid) + 000114ce 00000096 : mult64_hw.asm.obj (.text:__mpyll) + 00011564 00000054 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 000115b8 0000004e : mult3264_hw.asm.obj (.text:__mpyull) + 00011606 00000046 main.obj (.text:ADC_setup) + 0001164c 00000040 rts430x_lc_rd_eabi.lib : asr64.c.obj (.text:__mspabi_srall) + 0001168c 0000003e : asr32.asm.obj (.text:l_asr_const) + 000116ca 0000003e : lsl32.asm.obj (.text:l_lsl_const) + 00011708 0000003e : lsr32.asm.obj (.text:l_lsr_const) + 00011746 0000003a : lsl64.c.obj (.text:__mspabi_sllll) + 00011780 0000003a : lsr64.c.obj (.text:__mspabi_srlll) + 000117ba 00000032 : subd.c.obj (.text:__mspabi_subd) + 000117ec 00000032 : mult32_hw.asm.obj (.text) + 0001181e 00000026 main.obj (.text:UART_setup) + 00011844 00000026 main.obj (.text:main) + 0001186a 00000024 rts430x_lc_rd_eabi.lib : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset:__TI_zero_init_nomemset) + 0001188e 00000018 : mult16_hw.asm.obj (.text) + 000118a6 00000014 main.obj (.text:TimerA_setup) + 000118ba 0000000c main.obj (.text:UART_putCharacter) + 000118c6 00000006 rts430x_lc_rd_eabi.lib : exit.c.obj (.text:abort) + 000118cc 00000004 : pre_init.c.obj (.text:_system_pre_init) + 000118d0 00000002 : startup.c.obj (.text:_system_post_cinit) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + main.obj 694 4 24 + +--+----------------------+------+---------+---------+ + Total: 694 4 24 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430x_lc_rd_eabi.lib + addd.c.obj 1834 0 0 + frcdivd.c.obj 1126 0 0 + mpyd.c.obj 664 0 0 + divd.c.obj 546 0 0 + frcmpyd.c.obj 356 0 0 + cvtdf.c.obj 178 0 0 + fltlid.c.obj 158 0 0 + mult64_hw.asm.obj 150 0 0 + autoinit.c.obj 84 0 0 + mult3264_hw.asm.obj 78 0 0 + asr64.c.obj 64 0 0 + asr32.asm.obj 62 0 0 + lsl32.asm.obj 62 0 0 + lsr32.asm.obj 62 0 0 + lsl64.c.obj 58 0 0 + lsr64.c.obj 58 0 0 + mult32_hw.asm.obj 50 0 0 + subd.c.obj 50 0 0 + copy_zero_init.c.obj 36 0 0 + boot.c.obj 28 2 0 + mult16_hw.asm.obj 24 0 0 + isr_trap.asm.obj 8 0 0 + exit.c.obj 6 0 0 + pre_init.c.obj 4 0 0 + int14.asm.obj 0 2 0 + int15.asm.obj 0 2 0 + int16.asm.obj 0 2 0 + int17.asm.obj 0 2 0 + int18.asm.obj 0 2 0 + int19.asm.obj 0 2 0 + int20.asm.obj 0 2 0 + int21.asm.obj 0 2 0 + int24.asm.obj 0 2 0 + int25.asm.obj 0 2 0 + int26.asm.obj 0 2 0 + int27.asm.obj 0 2 0 + int28.asm.obj 0 2 0 + int29.asm.obj 0 2 0 + int30.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------+------+---------+---------+ + Total: 5748 32 0 + + Stack: 0 0 80 + Linker Generated: 0 18 0 + +--+----------------------+------+---------+---------+ + Grand Total: 6442 54 104 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00003162 records: 1, size/record: 8, table size: 8 + .bss: load addr=00003158, load size=00000006 bytes, run addr=00001100, run size=00000018 bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 0000315e records: 1, size/record: 4, table size: 4 + index: 0, handler: __TI_zero_init + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a6 ADC12IE +000001a4 ADC12IFG +00003100 ADC12ISR +000001a8 ADC12IV +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00001100 ADCXval +00001104 ADCYval +00001108 ADCZval +00011606 ADC_setup +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +00000040 BTCTL +000118c6 C$$EXIT +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +000001c0 DAC12_0CTL +000001c8 DAC12_0DAT +000001c2 DAC12_1CTL +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d6 DMA0DA +000001d6 DMA0DAL +000001d2 DMA0SA +000001d2 DMA0SAL +000001da DMA0SZ +000001dc DMA1CTL +000001e2 DMA1DA +000001e2 DMA1DAL +000001de DMA1SA +000001de DMA1SAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ee DMA2DA +000001ee DMA2DAL +000001ea DMA2SA +000001ea DMA2SAL +000001f2 DMA2SZ +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000090 LCDACTL +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +00000091 LCDM1 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +00000092 LCDM2 +000000a4 LCDM20 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +00000134 MAC +00000136 MACS +00000005 ME2 +00000130 MPY +00000132 MPYS +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000138 OP2 +0000000d P10DIR +00000009 P10IN +0000000b P10OUT +0000000f P10SEL +00000022 P1DIR +00000025 P1IE +00000024 P1IES +00000023 P1IFG +00000020 P1IN +00000021 P1OUT +00000026 P1SEL +0000002a P2DIR +0000002d P2IE +0000002c P2IES +0000002b P2IFG +00000028 P2IN +00000029 P2OUT +0000002e P2SEL +0000001a P3DIR +00000018 P3IN +00000019 P3OUT +0000001b P3SEL +0000001e P4DIR +0000001c P4IN +0000001d P4OUT +0000001f P4SEL +00000032 P5DIR +00000030 P5IN +00000031 P5OUT +00000033 P5SEL +00000036 P6DIR +00000034 P6IN +00000035 P6OUT +00000037 P6SEL +0000003c P7DIR +00000038 P7IN +0000003a P7OUT +0000003e P7SEL +0000003d P8DIR +00000039 P8IN +0000003b P8OUT +0000003f P8SEL +0000000c P9DIR +00000008 P9IN +0000000a P9OUT +0000000e P9SEL +0000003c PADIR +00000038 PAIN +0000003a PAOUT +0000003e PASEL +0000000c PBDIR +00000008 PBIN +0000000a PBOUT +0000000e PBSEL +0000013c RESHI +0000013a RESLO +00000041 RTCCTL +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +00000042 RTCNT1 +00000043 RTCNT2 +00000044 RTCNT3 +00000045 RTCNT4 +00000042 RTCTIM0 +00000044 RTCTIM1 +00000040 RTCTL +0000004e RTCYEAR +0000004f RTCYEARH +0000004e RTCYEARL +00000050 SCFI0 +00000051 SCFI1 +00000052 SCFQCTL +0000013e SUMEXT +00000056 SVSCTL +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000160 TACTL +0000012e TAIV +00000170 TAR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000180 TBCTL +0000011e TBIV +00000190 TBR +000118a6 TimerA_setup +0000007c U1BR0 +0000007d U1BR1 +00000078 U1CTL +0000007b U1MCTL +0000007a U1RCTL +0000007e U1RXBUF +00000079 U1TCTL +0000007f U1TXBUF +000118ba UART_putCharacter +0001181e UART_setup +0000005d UCA0ABCTL +00000062 UCA0BR0 +00000063 UCA0BR1 +00000060 UCA0CTL0 +00000061 UCA0CTL1 +0000005f UCA0IRRCTL +0000005e UCA0IRTCTL +00000064 UCA0MCTL +00000066 UCA0RXBUF +00000065 UCA0STAT +00000067 UCA0TXBUF +0000006a UCB0BR0 +0000006b UCB0BR1 +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006c UCB0I2CIE +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000006e UCB0RXBUF +0000006d UCB0STAT +0000006f UCB0TXBUF +00000120 WDTCTL +0000110c Xper +00001110 Yper +00001114 Zper +00003100 __STACK_END +00000050 __STACK_SIZE +00003162 __TI_CINIT_Base +0000316a __TI_CINIT_Limit +0000315e __TI_Handler_Table_Base +00003162 __TI_Handler_Table_Limit +00003150 __TI_ISR_TRAP +00011564 __TI_auto_init_nobinit_nopinit_hold_wdt +0001072a __TI_frcdivd +0001121a __TI_frcmpyd +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 __TI_int20 +0000ffea __TI_int21 +0000ffec __TI_int22 +0000ffee __TI_int23 +0000fff0 __TI_int24 +0000fff2 __TI_int25 +0000fff4 __TI_int26 +0000fff6 __TI_int27 +0000fff8 __TI_int28 +0000fffa __TI_int29 +0000fffc __TI_int30 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +0001186a __TI_zero_init_nomemset +ffffffff __c_args__ +00010000 __mspabi_addd +0001137e __mspabi_cvtdf +00010e28 __mspabi_divd +00011430 __mspabi_fltlid +00010b90 __mspabi_mpyd +0001188e __mspabi_mpyi_hw +000117ec __mspabi_mpyl_hw +000114ce __mspabi_mpyll_hw +000115b8 __mspabi_mpyull_hw +00011702 __mspabi_slll_1 +000116de __mspabi_slll_10 +000116da __mspabi_slll_11 +000116d6 __mspabi_slll_12 +000116d2 __mspabi_slll_13 +000116ce __mspabi_slll_14 +000116ca __mspabi_slll_15 +000116fe __mspabi_slll_2 +000116fa __mspabi_slll_3 +000116f6 __mspabi_slll_4 +000116f2 __mspabi_slll_5 +000116ee __mspabi_slll_6 +000116ea __mspabi_slll_7 +000116e6 __mspabi_slll_8 +000116e2 __mspabi_slll_9 +00011746 __mspabi_sllll +000116c4 __mspabi_sral_1 +000116a0 __mspabi_sral_10 +0001169c __mspabi_sral_11 +00011698 __mspabi_sral_12 +00011694 __mspabi_sral_13 +00011690 __mspabi_sral_14 +0001168c __mspabi_sral_15 +000116c0 __mspabi_sral_2 +000116bc __mspabi_sral_3 +000116b8 __mspabi_sral_4 +000116b4 __mspabi_sral_5 +000116b0 __mspabi_sral_6 +000116ac __mspabi_sral_7 +000116a8 __mspabi_sral_8 +000116a4 __mspabi_sral_9 +0001164c __mspabi_srall +00011740 __mspabi_srll_1 +0001171c __mspabi_srll_10 +00011718 __mspabi_srll_11 +00011714 __mspabi_srll_12 +00011710 __mspabi_srll_13 +0001170c __mspabi_srll_14 +00011708 __mspabi_srll_15 +0001173c __mspabi_srll_2 +00011738 __mspabi_srll_3 +00011734 __mspabi_srll_4 +00011730 __mspabi_srll_5 +0001172c __mspabi_srll_6 +00011728 __mspabi_srll_7 +00011724 __mspabi_srll_8 +00011720 __mspabi_srll_9 +00011780 __mspabi_srlll +000117ba __mspabi_subd +00003124 _c_int00_noargs +0000fffe _reset_vector +000030b0 _stack +000118d0 _system_post_cinit +000118cc _system_pre_init +000118c6 abort +00011844 main +0001104a sendData +00003140 timerA_isr + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000005 ME2 +00000008 P9IN +00000008 PBIN +00000009 P10IN +0000000a P9OUT +0000000a PBOUT +0000000b P10OUT +0000000c P9DIR +0000000c PBDIR +0000000d P10DIR +0000000e P9SEL +0000000e PBSEL +0000000f P10SEL +00000018 P3IN +00000019 P3OUT +0000001a P3DIR +0000001b P3SEL +0000001c P4IN +0000001d P4OUT +0000001e P4DIR +0000001f P4SEL +00000020 P1IN +00000021 P1OUT +00000022 P1DIR +00000023 P1IFG +00000024 P1IES +00000025 P1IE +00000026 P1SEL +00000028 P2IN +00000029 P2OUT +0000002a P2DIR +0000002b P2IFG +0000002c P2IES +0000002d P2IE +0000002e P2SEL +00000030 P5IN +00000031 P5OUT +00000032 P5DIR +00000033 P5SEL +00000034 P6IN +00000035 P6OUT +00000036 P6DIR +00000037 P6SEL +00000038 P7IN +00000038 PAIN +00000039 P8IN +0000003a P7OUT +0000003a PAOUT +0000003b P8OUT +0000003c P7DIR +0000003c PADIR +0000003d P8DIR +0000003e P7SEL +0000003e PASEL +0000003f P8SEL +00000040 BTCTL +00000040 RTCTL +00000041 RTCCTL +00000042 RTCNT1 +00000042 RTCTIM0 +00000043 RTCNT2 +00000044 RTCNT3 +00000044 RTCTIM1 +00000045 RTCNT4 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +0000004e RTCYEAR +0000004e RTCYEARL +0000004f RTCYEARH +00000050 SCFI0 +00000050 __STACK_SIZE +00000051 SCFI1 +00000052 SCFQCTL +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000056 SVSCTL +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +0000005d UCA0ABCTL +0000005e UCA0IRTCTL +0000005f UCA0IRRCTL +00000060 UCA0CTL0 +00000061 UCA0CTL1 +00000062 UCA0BR0 +00000063 UCA0BR1 +00000064 UCA0MCTL +00000065 UCA0STAT +00000066 UCA0RXBUF +00000067 UCA0TXBUF +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006a UCB0BR0 +0000006b UCB0BR1 +0000006c UCB0I2CIE +0000006d UCB0STAT +0000006e UCB0RXBUF +0000006f UCB0TXBUF +00000078 U1CTL +00000079 U1TCTL +0000007a U1RCTL +0000007b U1MCTL +0000007c U1BR0 +0000007d U1BR1 +0000007e U1RXBUF +0000007f U1TXBUF +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000090 LCDACTL +00000091 LCDM1 +00000092 LCDM2 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +000000a4 LCDM20 +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000011e TBIV +00000120 WDTCTL +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +0000012e TAIV +00000130 MPY +00000132 MPYS +00000134 MAC +00000136 MACS +00000138 OP2 +0000013a RESLO +0000013c RESHI +0000013e SUMEXT +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000160 TACTL +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000170 TAR +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000180 TBCTL +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000190 TBR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a4 ADC12IFG +000001a6 ADC12IE +000001a8 ADC12IV +000001c0 DAC12_0CTL +000001c2 DAC12_1CTL +000001c8 DAC12_0DAT +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d2 DMA0SA +000001d2 DMA0SAL +000001d6 DMA0DA +000001d6 DMA0DAL +000001da DMA0SZ +000001dc DMA1CTL +000001de DMA1SA +000001de DMA1SAL +000001e2 DMA1DA +000001e2 DMA1DAL +000001e6 DMA1SZ +000001e8 DMA2CTL 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__mspabi_srll_3 + 0x11738 + + + + __mspabi_srll_1 + 0x11740 + + + + __mspabi_srll_15 + 0x11708 + + + + __mspabi_srll_14 + 0x1170c + + + + __mspabi_srll_13 + 0x11710 + + + + __mspabi_srll_12 + 0x11714 + + + + __mspabi_srll_11 + 0x11718 + + + + __mspabi_srll_10 + 0x1171c + + + + __mspabi_srlll + 0x11780 + + + + __mspabi_addd + 0x10000 + + + + __TI_frcmpyd + 0x1121a + + + + __mspabi_srall + 0x1164c + + + + __mspabi_sllll + 0x11746 + + + + Link successful + diff --git a/CPE325/Lab10_Part1/Debug/ccsObjs.opt b/CPE325/Lab10_Part1/Debug/ccsObjs.opt new file mode 100644 index 0000000..2f36690 --- /dev/null +++ b/CPE325/Lab10_Part1/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./main.obj" "../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/Lab10_Part1/Debug/main.d b/CPE325/Lab10_Part1/Debug/main.d new file mode 100644 index 0000000..225d0d5 --- /dev/null +++ b/CPE325/Lab10_Part1/Debug/main.d @@ -0,0 +1,18 @@ +# FIXED + +main.obj: ../main.c +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430xG46x.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h + +../main.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430xG46x.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + diff --git a/CPE325/Lab10_Part1/Debug/main.obj b/CPE325/Lab10_Part1/Debug/main.obj new file mode 100644 index 0000000..6913c3b Binary files /dev/null and b/CPE325/Lab10_Part1/Debug/main.obj differ diff --git a/CPE325/Lab10_Part1/Debug/makefile b/CPE325/Lab10_Part1/Debug/makefile new file mode 100644 index 0000000..3d6fbbf --- /dev/null +++ b/CPE325/Lab10_Part1/Debug/makefile @@ -0,0 +1,166 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab10_Part1.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab10_Part1.out" \ + +BIN_OUTPUTS += \ +Lab10_Part1.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab10_Part1.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab10_Part1.out" + +# Tool invocations +Lab10_Part1.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"Lab10_Part1.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab10_Part1_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "Lab10_Part1.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab10_Part1.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab10_Part1.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "main.obj" + -$(RM) "main.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab10_Part1/Debug/objects.mk b/CPE325/Lab10_Part1/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/Lab10_Part1/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/Lab10_Part1/Debug/sources.mk b/CPE325/Lab10_Part1/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab10_Part1/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab10_Part1/Debug/subdir_rules.mk b/CPE325/Lab10_Part1/Debug/subdir_rules.mk new file mode 100644 index 0000000..64c4ce0 --- /dev/null +++ b/CPE325/Lab10_Part1/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab10_Part1" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/Lab10_Part1/main.c b/CPE325/Lab10_Part1/main.c new file mode 100644 index 0000000..3251117 --- /dev/null +++ b/CPE325/Lab10_Part1/main.c @@ -0,0 +1,115 @@ +/*------------------------------------------------------------------------------ + * File: Lab10_D2.c (CPE 325 Lab10 Demo code) + * Function: Interfacing thumbstick (MPS430FG4618) + * Description: This C program interfaces with a thumbstick sensor that has + * x (HORZ) and y (VERT) axis and outputs from 0 to 3V. + * The value of x and y axis + * is sent as the percentage of power to the UAH Serial App. + * Clocks: ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO = default (~1MHz) + * An external watch crystal between XIN & XOUT is required for ACLK + * + * MSP430xG461x + * ------------------- + * /|\| XIN|- + * | | | 32kHz + * --|RST XOUT|- + * | | + * | P2.4/UCA0TXD|------------> + * | | 38400 - 8N1 + * | P2.5/UCA0RXD|<------------ + * | | + * Input: Connect thumbstick to the board + * Output: Displays % of power in UAH serial app + * Author: Micah Harvey + *------------------------------------------------------------------------------*/ + +#include + +volatile long int ADCXval, ADCYval, ADCZval; +volatile float Xper, Yper, Zper; + +void TimerA_setup(void) { + TACCR0 = 3277; // 3277 / 32768 Hz = 0.1s + TACTL = TASSEL_1 + MC_1; // ACLK, up mode + TACCTL0 = CCIE; // Enabled interrupt +} + +void ADC_setup(void) { + int i =0; + + P6DIR &= ~BIT3 + ~BIT5 + ~BIT7; // Configure P6.3, P6.5, and P6.7 as input pins + P6SEL |= BIT3 + BIT5 + BIT7; // Configure P6.3, P6.5, and P6.7 as analog pins + ADC12CTL0 = ADC12ON + SHT0_6 + MSC; // configure ADC converter + ADC12CTL1 = SHP + CONSEQ_1; // Use sample timer, single sequence + ADC12MCTL0 = INCH_3; // ADC A3 pin - Stick Z-axis + ADC12MCTL1 = INCH_5; // ADC A5 pin - Stick Y-axis + ADC12MCTL2 = INCH_7 + EOS; // ADC A7 pin - Stick X-axis + // EOS - End of Sequence for Conversions + ADC12IE |= 0x03; // Enable ADC12IFG.1 + for (i = 0; i < 0x3600; i++); // Delay for reference start-up + ADC12CTL0 |= ENC; // Enable conversions +} + +void UART_putCharacter(char c) { + while(!(IFG2 & UCA0TXIFG)); // Wait for previous character to be sent + UCA0TXBUF = c; // Send byte to the buffer for transmitting +} + +void UART_setup(void) { + P2SEL |= BIT4 + BIT5; // Set up Rx and Tx bits + UCA0CTL0 = 0; // Set up default RS-232 protocol + UCA0CTL1 |= BIT0 + UCSSEL_2; // Disable device, set clock + UCA0BR0 = 27; // 1048576 Hz / 38400 + UCA0BR1 = 0; + UCA0MCTL = 0x94; + UCA0CTL1 &= ~BIT0; // Start UART device +} + +void sendData(void) { + int i; + Xper = (((ADCXval*3.0/4095)-1.5)/0.3); // Calculate percentage outputs + Yper = (((ADCYval*3.0/4095)-1.5)/0.3); + Zper = (((ADCZval*3.0/4095)-1.5)/0.3); + // Use character pointers to send one byte at a time + char *xpointer=(char *)&Xper; + char *ypointer=(char *)&Yper; + char *zpointer=(char *)&Zper; + + UART_putCharacter(0x55); // Send header + for(i = 0; i < 4; i++) { // Send x percentage - one byte at a time + UART_putCharacter(xpointer[i]); + } + for(i = 0; i < 4; i++) { // Send y percentage - one byte at a time + UART_putCharacter(ypointer[i]); + } + for(i = 0; i < 4; i++) { // Send y percentage - one byte at a time + UART_putCharacter(zpointer[i]); + } +} + +void main(void) { + WDTCTL = WDTPW +WDTHOLD; // Stop WDT + TimerA_setup(); // Setup timer to send ADC data + ADC_setup(); // Setup ADC + UART_setup(); // Setup UART for RS-232 + _EINT(); + + while (1){ + ADC12CTL0 |= ADC12SC; // Start conversions + __bis_SR_register(LPM0_bits + GIE); // Enter LPM0 + } +} + +#pragma vector = ADC12_VECTOR +__interrupt void ADC12ISR(void) { + ADCXval = ADC12MEM0; // Move results, IFG is cleared + ADCYval = ADC12MEM1; + ADCZval = ADC12MEM2; + __bic_SR_register_on_exit(LPM0_bits); // Exit LPM0 +} + +#pragma vector = TIMERA0_VECTOR +__interrupt void timerA_isr() { + sendData(); // Send data to serial app + __bic_SR_register_on_exit(LPM0_bits); // Exit LPM0 +} diff --git a/CPE325/Lab10_Part1/targetConfigs/MSP430FG4618.ccxml b/CPE325/Lab10_Part1/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/Lab10_Part1/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab10_Part1/targetConfigs/readme.txt b/CPE325/Lab10_Part1/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab10_Part1/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab10_Part2/Debug/Lab10_Part2.d b/CPE325/Lab10_Part2/Debug/Lab10_Part2.d new file mode 100644 index 0000000..5ea2ec7 --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/Lab10_Part2.d @@ -0,0 +1,42 @@ +# FIXED + +Lab10_Part2.obj: ../Lab10_Part2.c +Lab10_Part2.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430xG46x.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/math.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_defs.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h +Lab10_Part2.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_limits.h + +../Lab10_Part2.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430xG46x.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/math.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_defs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_limits.h: + diff --git a/CPE325/Lab10_Part2/Debug/Lab10_Part2.map b/CPE325/Lab10_Part2/Debug/Lab10_Part2.map new file mode 100644 index 0000000..8e93292 --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/Lab10_Part2.map @@ -0,0 +1,1182 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Nov 12 14:32:01 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 000063b6 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOB 00001000 00000080 00000000 00000080 RWIX + INFOA 00001080 00000080 00000000 00000080 RWIX + RAM 00001100 00002000 0000006e 00001f92 RWIX + FLASH 00003100 0000cebe 000033f0 00009ace RWIX + BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff + INT00 0000ffc0 00000002 00000000 00000002 RWIX + INT01 0000ffc2 00000002 00000000 00000002 RWIX + INT02 0000ffc4 00000002 00000000 00000002 RWIX + INT03 0000ffc6 00000002 00000000 00000002 RWIX + INT04 0000ffc8 00000002 00000000 00000002 RWIX + INT05 0000ffca 00000002 00000000 00000002 RWIX + INT06 0000ffcc 00000002 00000000 00000002 RWIX + INT07 0000ffce 00000002 00000000 00000002 RWIX + INT08 0000ffd0 00000002 00000000 00000002 RWIX + INT09 0000ffd2 00000002 00000000 00000002 RWIX + INT10 0000ffd4 00000002 00000000 00000002 RWIX + INT11 0000ffd6 00000002 00000000 00000002 RWIX + INT12 0000ffd8 00000002 00000000 00000002 RWIX + INT13 0000ffda 00000002 00000000 00000002 RWIX + INT14 0000ffdc 00000002 00000002 00000000 RWIX + INT15 0000ffde 00000002 00000002 00000000 RWIX + INT16 0000ffe0 00000002 00000002 00000000 RWIX + INT17 0000ffe2 00000002 00000002 00000000 RWIX + INT18 0000ffe4 00000002 00000002 00000000 RWIX + INT19 0000ffe6 00000002 00000002 00000000 RWIX + INT20 0000ffe8 00000002 00000002 00000000 RWIX + INT21 0000ffea 00000002 00000002 00000000 RWIX + INT22 0000ffec 00000002 00000002 00000000 RWIX + INT23 0000ffee 00000002 00000002 00000000 RWIX + INT24 0000fff0 00000002 00000002 00000000 RWIX + INT25 0000fff2 00000002 00000002 00000000 RWIX + INT26 0000fff4 00000002 00000002 00000000 RWIX + INT27 0000fff6 00000002 00000002 00000000 RWIX + INT28 0000fff8 00000002 00000002 00000000 RWIX + INT29 0000fffa 00000002 00000002 00000000 RWIX + INT30 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 00010000 00000000 00010000 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.bss 0 00001100 0000001c UNINITIALIZED + 00001100 00000004 (.common:ADCXval) + 00001104 00000004 (.common:ADCYval) + 00001108 00000004 (.common:ADCZval) + 0000110c 00000004 (.common:M) + 00001110 00000004 (.common:Xper) + 00001114 00000004 (.common:Yper) + 00001118 00000004 (.common:Zper) + +.data 0 0000111c 00000002 UNINITIALIZED + 0000111c 00000002 rts430_eabi.lib : errno.c.obj (.data) + +.stack 0 000030b0 00000050 UNINITIALIZED + 000030b0 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 000030b2 0000004e --HOLE-- + +.text 0 00003100 000033a0 + 00003100 00001162 rts430_eabi.lib : e_pow.c.obj (.text:pow) + 00004262 00000736 : addd.c.obj (.text:__mspabi_addd) + 00004998 00000478 : frcdivd.c.obj (.text:__TI_frcdivd) + 00004e10 000002f8 : e_sqrt.c.obj (.text:sqrt) + 00005108 000002c0 : mpyd.c.obj (.text:__mspabi_mpyd) + 000053c8 00000244 Lab10_Part2.obj (.text:sendData) + 0000560c 00000238 rts430_eabi.lib : divd.c.obj (.text:__mspabi_divd) + 00005844 00000172 : frcmpyd.c.obj (.text:__TI_frcmpyd) + 000059b6 0000016a : s_scalbn.c.obj (.text:scalbn) + 00005b20 000000dc : cmpd.c.obj (.text:__mspabi_cmpd) + 00005bfc 000000b4 : cvtdf.c.obj (.text:__mspabi_cvtdf) + 00005cb0 000000ac : fltlid.c.obj (.text:__mspabi_fltlid) + 00005d5c 00000096 : mult64_hw.asm.obj (.text:__mpyll) + 00005df2 0000007c : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00005e6e 00000070 : cvtfd.c.obj (.text:__mspabi_cvtfd) + 00005ede 0000005c Lab10_Part2.obj (.text:ADC_setup) + 00005f3a 0000005c rts430_eabi.lib : lsr32.asm.obj (.text:l_lsr_const) + 00005f96 00000058 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 00005fee 0000004c : lsr16.asm.obj (.text) + 0000603a 0000004a : mult3264_hw.asm.obj (.text:__mpyull) + 00006084 0000004a : asr64.c.obj (.text:__mspabi_srall) + 000060ce 0000004a : fs_cmp.asm.obj (.text) + 00006118 00000046 : lsr64.c.obj (.text:__mspabi_srlll) + 0000615e 00000044 : lsl64.c.obj (.text:__mspabi_sllll) + 000061a2 0000003e : asr32.asm.obj (.text:l_asr_const) + 000061e0 0000003e : lsl32.asm.obj (.text:l_lsl_const) + 0000621e 0000002e : subd.c.obj (.text:__mspabi_subd) + 0000624c 0000002e : s_copysign.c.obj (.text:copysign) + 0000627a 0000002e : mult32_hw.asm.obj (.text) + 000062a8 0000002c : asr16.asm.obj (.text) + 000062d4 0000002c : lsl16.asm.obj (.text) + 00006300 0000002a : negd.c.obj (.text:__mspabi_negd) + 0000632a 00000026 Lab10_Part2.obj (.text:ADC12ISR) + 00006350 00000026 Lab10_Part2.obj (.text:UART_setup) + 00006376 00000020 Lab10_Part2.obj (.text:main) + 00006396 00000020 Lab10_Part2.obj (.text:timerA_isr) + 000063b6 0000001c rts430_eabi.lib : boot.c.obj (.text:_c_int00_noargs) + 000063d2 00000014 Lab10_Part2.obj (.text:Port2_ISR) + 000063e6 00000014 Lab10_Part2.obj (.text:TimerA_setup) + 000063fa 00000014 rts430_eabi.lib : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset:__TI_zero_init_nomemset) + 0000640e 00000014 : mult16_hw.asm.obj (.text) + 00006422 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00006434 00000012 : lsr32.asm.obj (.text:l_lsr) + 00006446 00000012 : memcpy.c.obj (.text:memcpy) + 00006458 00000010 : asr32.asm.obj (.text:l_asr) + 00006468 00000010 : lsl32.asm.obj (.text:l_lsl) + 00006478 00000010 : epilog.asm.obj (.text) + 00006488 0000000c Lab10_Part2.obj (.text:UART_putCharacter) + 00006494 00000006 rts430_eabi.lib : exit.c.obj (.text:abort) + 0000649a 00000004 : pre_init.c.obj (.text:_system_pre_init) + 0000649e 00000002 : startup.c.obj (.text:_system_post_cinit) + +.const 0 000064a0 00000030 + 000064a0 00000010 rts430_eabi.lib : e_pow.c.obj (.const:bp) + 000064b0 00000010 : e_pow.c.obj (.const:dp_h) + 000064c0 00000010 : e_pow.c.obj (.const:dp_l) + +.text:_isr +* 0 000064d0 00000008 + 000064d0 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 000064d8 00000018 + 000064d8 00000006 (.cinit..data.load) [load image] + 000064de 00000006 (__TI_handler_table) + 000064e4 00000004 (.cinit..bss.load) [load image, compression = zero_init] + 000064e8 00000008 (__TI_cinit_table) + +.binit 0 00003100 00000000 + +.init_array +* 0 00003100 00000000 UNINITIALIZED + +DAC12 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int14.asm.obj (.int14) + +DMA 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int15.asm.obj (.int15) + +BASICTIMER +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int16.asm.obj (.int16) + +PORT2 0 0000ffe2 00000002 + 0000ffe2 00000002 Lab10_Part2.obj (.int17) + +USART1TX 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int18.asm.obj (.int18) + +USART1RX 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int19.asm.obj (.int19) + +PORT1 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int20.asm.obj (.int20) + +TIMERA1 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int21.asm.obj (.int21) + +TIMERA0 0 0000ffec 00000002 + 0000ffec 00000002 Lab10_Part2.obj (.int22) + +ADC12 0 0000ffee 00000002 + 0000ffee 00000002 Lab10_Part2.obj (.int23) + +USCIAB0TX +* 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int24.asm.obj (.int24) + +USCIAB0RX +* 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int25.asm.obj (.int25) + +WDT 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int26.asm.obj (.int26) + +COMPARATORA +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int27.asm.obj (.int27) + +TIMERB1 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int28.asm.obj (.int28) + +TIMERB0 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int29.asm.obj (.int29) + +NMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int30.asm.obj (.int30) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +$fill000 0 0000ffbe 00000002 + 0000ffbe 00000002 --HOLE-- [fill = ffff] + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + Lab10_Part2.obj 864 6 28 + +--+----------------------------+-------+---------+---------+ + Total: 864 6 28 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + e_pow.c.obj 4450 48 0 + addd.c.obj 1846 0 0 + frcdivd.c.obj 1144 0 0 + e_sqrt.c.obj 760 0 0 + mpyd.c.obj 704 0 0 + divd.c.obj 568 0 0 + frcmpyd.c.obj 370 0 0 + s_scalbn.c.obj 362 0 0 + cmpd.c.obj 220 0 0 + cvtdf.c.obj 180 0 0 + fltlid.c.obj 172 0 0 + mult64_hw.asm.obj 150 0 0 + copy_decompress_lzss.c.obj 124 0 0 + cvtfd.c.obj 112 0 0 + lsr32.asm.obj 110 0 0 + autoinit.c.obj 88 0 0 + asr32.asm.obj 78 0 0 + lsl32.asm.obj 78 0 0 + lsr16.asm.obj 76 0 0 + asr64.c.obj 74 0 0 + fs_cmp.asm.obj 74 0 0 + mult3264_hw.asm.obj 74 0 0 + lsr64.c.obj 70 0 0 + lsl64.c.obj 68 0 0 + mult32_hw.asm.obj 46 0 0 + s_copysign.c.obj 46 0 0 + subd.c.obj 46 0 0 + asr16.asm.obj 44 0 0 + lsl16.asm.obj 44 0 0 + negd.c.obj 42 0 0 + boot.c.obj 28 2 0 + copy_zero_init.c.obj 20 0 0 + mult16_hw.asm.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + memcpy.c.obj 18 0 0 + epilog.asm.obj 16 0 0 + isr_trap.asm.obj 8 0 0 + exit.c.obj 6 0 0 + pre_init.c.obj 4 0 0 + errno.c.obj 0 0 2 + int14.asm.obj 0 2 0 + int15.asm.obj 0 2 0 + int16.asm.obj 0 2 0 + int18.asm.obj 0 2 0 + int19.asm.obj 0 2 0 + int20.asm.obj 0 2 0 + int21.asm.obj 0 2 0 + int24.asm.obj 0 2 0 + int25.asm.obj 0 2 0 + int26.asm.obj 0 2 0 + int27.asm.obj 0 2 0 + int28.asm.obj 0 2 0 + int29.asm.obj 0 2 0 + int30.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 12360 78 2 + + Stack: 0 0 80 + Linker Generated: 0 24 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 13224 108 110 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 000064e8 records: 2, size/record: 4, table size: 8 + .data: load addr=000064d8, load size=00000006 bytes, run addr=0000111c, run size=00000002 bytes, compression=copy + .bss: load addr=000064e4, load size=00000004 bytes, run addr=00001100, run size=0000001c bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 000064de records: 3, size/record: 2, table size: 6 + index: 0, handler: __TI_zero_init + index: 1, handler: __TI_decompress_lzss + index: 2, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a6 ADC12IE +000001a4 ADC12IFG +0000632a ADC12ISR +000001a8 ADC12IV +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00001100 ADCXval +00001104 ADCYval +00001108 ADCZval +00005ede ADC_setup +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +00000040 BTCTL +00006494 C$$EXIT +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +000001c0 DAC12_0CTL +000001c8 DAC12_0DAT +000001c2 DAC12_1CTL +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d6 DMA0DA +000001d6 DMA0DAL +000001d2 DMA0SA +000001d2 DMA0SAL +000001da DMA0SZ +000001dc DMA1CTL +000001e2 DMA1DA +000001e2 DMA1DAL +000001de DMA1SA +000001de DMA1SAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ee DMA2DA +000001ee DMA2DAL +000001ea DMA2SA +000001ea DMA2SAL +000001f2 DMA2SZ +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000090 LCDACTL +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +00000091 LCDM1 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +00000092 LCDM2 +000000a4 LCDM20 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +0000110c M +00000134 MAC +00000136 MACS +00000005 ME2 +00000130 MPY +00000132 MPYS +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000138 OP2 +0000000d P10DIR +00000009 P10IN +0000000b P10OUT +0000000f P10SEL +00000022 P1DIR +00000025 P1IE +00000024 P1IES +00000023 P1IFG +00000020 P1IN +00000021 P1OUT +00000026 P1SEL +0000002a P2DIR +0000002d P2IE +0000002c P2IES +0000002b P2IFG +00000028 P2IN +00000029 P2OUT +0000002e P2SEL +0000001a P3DIR +00000018 P3IN +00000019 P3OUT +0000001b P3SEL +0000001e P4DIR +0000001c P4IN +0000001d P4OUT +0000001f P4SEL +00000032 P5DIR +00000030 P5IN +00000031 P5OUT +00000033 P5SEL +00000036 P6DIR +00000034 P6IN +00000035 P6OUT +00000037 P6SEL +0000003c P7DIR +00000038 P7IN +0000003a P7OUT +0000003e P7SEL +0000003d P8DIR +00000039 P8IN +0000003b P8OUT +0000003f P8SEL +0000000c P9DIR +00000008 P9IN +0000000a P9OUT +0000000e P9SEL +0000003c PADIR +00000038 PAIN +0000003a PAOUT +0000003e PASEL +0000000c PBDIR +00000008 PBIN +0000000a PBOUT +0000000e PBSEL +000063d2 Port2_ISR +0000013c RESHI +0000013a RESLO +00000041 RTCCTL +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +00000042 RTCNT1 +00000043 RTCNT2 +00000044 RTCNT3 +00000045 RTCNT4 +00000042 RTCTIM0 +00000044 RTCTIM1 +00000040 RTCTL +0000004e RTCYEAR +0000004f RTCYEARH +0000004e RTCYEARL +00000050 SCFI0 +00000051 SCFI1 +00000052 SCFQCTL +0000013e SUMEXT +00000056 SVSCTL +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000160 TACTL +0000012e TAIV +00000170 TAR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000180 TBCTL +0000011e TBIV +00000190 TBR +000063e6 TimerA_setup +0000007c U1BR0 +0000007d U1BR1 +00000078 U1CTL +0000007b U1MCTL +0000007a U1RCTL +0000007e U1RXBUF +00000079 U1TCTL +0000007f U1TXBUF +00006488 UART_putCharacter +00006350 UART_setup +0000005d UCA0ABCTL +00000062 UCA0BR0 +00000063 UCA0BR1 +00000060 UCA0CTL0 +00000061 UCA0CTL1 +0000005f UCA0IRRCTL +0000005e UCA0IRTCTL +00000064 UCA0MCTL +00000066 UCA0RXBUF +00000065 UCA0STAT +00000067 UCA0TXBUF +0000006a UCB0BR0 +0000006b UCB0BR1 +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006c UCB0I2CIE +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000006e UCB0RXBUF +0000006d UCB0STAT +0000006f UCB0TXBUF +00000120 WDTCTL +00001110 Xper +00001114 Yper +00001118 Zper +00003100 __STACK_END +00000050 __STACK_SIZE +000064e8 __TI_CINIT_Base +000064f0 __TI_CINIT_Limit +000064de __TI_Handler_Table_Base +000064e4 __TI_Handler_Table_Limit +000064d0 __TI_ISR_TRAP +00005f96 __TI_auto_init_nobinit_nopinit_hold_wdt +00005df2 __TI_decompress_lzss +00006422 __TI_decompress_none +00004998 __TI_frcdivd +00005844 __TI_frcmpyd +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 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__TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[435 symbols] diff --git a/CPE325/Lab10_Part2/Debug/Lab10_Part2.obj b/CPE325/Lab10_Part2/Debug/Lab10_Part2.obj new file mode 100644 index 0000000..6387f37 Binary files /dev/null and b/CPE325/Lab10_Part2/Debug/Lab10_Part2.obj differ diff --git a/CPE325/Lab10_Part2/Debug/Lab10_Part2.out b/CPE325/Lab10_Part2/Debug/Lab10_Part2.out new file mode 100644 index 0000000..ce49859 Binary files /dev/null and b/CPE325/Lab10_Part2/Debug/Lab10_Part2.out differ diff --git a/CPE325/Lab10_Part2/Debug/Lab10_Part2_linkInfo.xml b/CPE325/Lab10_Part2/Debug/Lab10_Part2_linkInfo.xml new file mode 100644 index 0000000..e28edb1 --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/Lab10_Part2_linkInfo.xml @@ -0,0 +1,7888 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x618ecf41 + 0x0 + Lab10_Part2.out + + _c_int00_noargs +
0x63b6
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+ + __mspabi_srli_3 + 0x602c + + + + __mspabi_srli_1 + 0x6034 + + + + __mspabi_srli + 0x5fee + + + + __mspabi_srli_15 + 0x5ffc + + + + __mspabi_srli_14 + 0x6000 + + + + __mspabi_srli_13 + 0x6004 + + + + __mspabi_srli_12 + 0x6008 + + + + __mspabi_srli_11 + 0x600c + + + + __mspabi_srli_10 + 0x6010 + + + + __mspabi_srll_8 + 0x5f64 + + + + __mspabi_srll_9 + 0x5f5e + + + + __mspabi_srll_6 + 0x5f70 + + + + __mspabi_srll_7 + 0x5f6a + + + + __mspabi_srll_4 + 0x5f7c + + + + __mspabi_srll_5 + 0x5f76 + + + + __mspabi_srll_2 + 0x5f88 + + + + __mspabi_srll_3 + 0x5f82 + + + + __mspabi_srll_1 + 0x5f8e + + + + __mspabi_srll_15 + 0x5f3a + + + + __mspabi_srll_14 + 0x5f40 + + + + __mspabi_srll_13 + 0x5f46 + + + + __mspabi_srll_12 + 0x5f4c + + + + __mspabi_srll_11 + 0x5f52 + + + + __mspabi_srll_10 + 0x5f58 + + + + __mspabi_srll + 0x6434 + + + + __mspabi_mpyi_hw + 0x640e + + + + __mspabi_mpyl_hw + 0x627a + + + + __mspabi_mpyull_hw + 0x603a + + + + __mspabi_mpyll_hw + 0x5d5c + + + + _stack + 0x30b0 + + + + _c_int00_noargs + 0x63b6 + + + + _reset_vector + 0xfffe + + + + __TI_auto_init_nobinit_nopinit_hold_wdt + 0x5f96 + + + + __TI_zero_init_nomemset + 0x63fa + + + + __mspabi_srlll + 0x6118 + + + + _system_pre_init + 0x649a + + + + _system_post_cinit + 0x649e + + + + __TI_decompress_none + 0x6422 + + + + __TI_decompress_lzss + 0x5df2 + + + + __mspabi_addd + 0x4262 + + + + __mspabi_cmpd + 0x5b20 + + + + __mspabi_cvtfd + 0x5e6e + + + + __mspabi_divd + 0x560c + + + + __mspabi_fltlid + 0x5cb0 + + + + __TI_frcdivd + 0x4998 + + + + __mspabi_mpyd + 0x5108 + + + + __mspabi_negd + 0x6300 + + + + __mspabi_subd + 0x621e + + + + __mspabi_cvtdf + 0x5bfc + + + + C$$EXIT + 0x6494 + + + + abort + 0x6494 + + + + memcpy + 0x6446 + + + + errno + 0x111c + + + + copysign + 0x624c + + + + copysignl + 0x624c + + + + __mspabi_srall + 0x6084 + + + + __mspabi_sllll + 0x615e + + + + __TI_frcmpyd + 0x5844 + + + + Link successful + diff --git a/CPE325/Lab10_Part2/Debug/ccsObjs.opt b/CPE325/Lab10_Part2/Debug/ccsObjs.opt new file mode 100644 index 0000000..a973e24 --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./Lab10_Part2.obj" "../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/Lab10_Part2/Debug/main.d b/CPE325/Lab10_Part2/Debug/main.d new file mode 100644 index 0000000..de58a93 --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/main.d @@ -0,0 +1,42 @@ +# FIXED + +main.obj: ../main.c +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430xG46x.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/math.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_defs.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_limits.h + +../main.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430xG46x.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/math.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_defs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_limits.h: + diff --git a/CPE325/Lab10_Part2/Debug/makefile b/CPE325/Lab10_Part2/Debug/makefile new file mode 100644 index 0000000..f71dcad --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/makefile @@ -0,0 +1,166 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./Lab10_Part2.obj" \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab10_Part2.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab10_Part2.out" \ + +BIN_OUTPUTS += \ +Lab10_Part2.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab10_Part2.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab10_Part2.out" + +# Tool invocations +Lab10_Part2.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"Lab10_Part2.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab10_Part2_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "Lab10_Part2.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab10_Part2.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab10_Part2.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "Lab10_Part2.obj" + -$(RM) "Lab10_Part2.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab10_Part2/Debug/objects.mk b/CPE325/Lab10_Part2/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/Lab10_Part2/Debug/sources.mk b/CPE325/Lab10_Part2/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab10_Part2/Debug/subdir_rules.mk b/CPE325/Lab10_Part2/Debug/subdir_rules.mk new file mode 100644 index 0000000..e995db8 --- /dev/null +++ b/CPE325/Lab10_Part2/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab10_Part2" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --preproc_with_compile --preproc_dependency="$(basename $( +#include + +volatile long int ADCXval, ADCYval, ADCZval; +volatile float Xper, Yper, Zper, M; + +#define SW1_PRESSED ((BIT0&P1IFG)==0) // SW1 Status + +void TimerA_setup(void) { + TACCR0 = 3277; // 3277 / 32768 Hz = 0.1s + TACTL = TASSEL_1 + MC_1; // ACLK, up mode + TACCTL0 = CCIE; // Enabled interrupt +} + +void ADC_setup(void) { + int i =0; + _EINT(); // Enable interrupts + P1IE |= BIT1; // P1.1 interrupt enabled + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared + P2DIR |= BIT2; // Set P2 output direction + P2OUT &= ~BIT2; // Turn Off LED2 + P6DIR &= ~BIT3 + ~BIT5 + ~BIT7; // Configure P6.3, P6.5, and P6.7 as input pins + P6SEL |= BIT3 + BIT5 + BIT7; // Configure P6.3, P6.5, and P6.7 as analog pins +// P6DIR &= ~BIT2 + ~BIT4 + ~BIT6; // Configure P6.3, P6.5, and P6.7 as input pins +// P6SEL |= BIT2+ BIT4 + BIT6; // Configure P6.3, P6.5, and P6.7 as analog pins + ADC12CTL0 = ADC12ON + SHT0_6 + MSC; // configure ADC converter + ADC12CTL1 = SHP + CONSEQ_1; // Use sample timer, single sequence + ADC12MCTL0 = INCH_3; // ADC A3 pin - Stick Z-axis + ADC12MCTL1 = INCH_5; // ADC A5 pin - Stick Y-axis + ADC12MCTL2 = INCH_7 + EOS; // ADC A7 pin - Stick X-axis +// ADC12MCTL0 = INCH_2; // ADC A3 pin - Z-axis +// ADC12MCTL1 = INCH_4; // ADC A5 pin - Y-axis +// ADC12MCTL2 = INCH_6 + EOS; // ADC A7 pin - X-axis + // EOS - End of Sequence for Conversions + ADC12IE |= 0x03; // Enable ADC12IFG.1 + for (i = 0; i < 0x3600; i++); // Delay for reference start-up + ADC12CTL0 |= ENC; // Enable conversions +} + +void UART_putCharacter(char c) { + while(!(IFG2 & UCA0TXIFG)); // Wait for previous character to be sent + UCA0TXBUF = c; // Send byte to the buffer for transmitting +} + +void UART_setup(void) { + P2SEL |= BIT4 + BIT5; // Set up Rx and Tx bits + UCA0CTL0 = 0; // Set up default RS-232 protocol + UCA0CTL1 |= BIT0 + UCSSEL_2; // Disable device, set clock + UCA0BR0 = 27; // 1048576 Hz / 38400 + UCA0BR1 = 0; + UCA0MCTL = 0x94; + UCA0CTL1 &= ~BIT0; // Start UART device +} + +void sendData(void) { + int i; + Xper = (((ADCXval*(3.0/4095)) - 1.5)/0.3); // Calculate percentage outputs + Yper = (((ADCYval*(3.0/4095)) - 1.5)/0.3); + Zper = (((ADCZval*(3.0/4095)) - 1.5)/0.3); + M = sqrt(pow(Xper,2)+pow(Yper,2)+pow(Zper,2)); + if(M > 2){ + P2OUT |= BIT2; //Turn LED1 on + } + // Use character pointers to send one byte at a time + char *xpointer=(char *)&Xper; + char *ypointer=(char *)&Yper; + char *zpointer=(char *)&Zper; + + UART_putCharacter(0x55); // Send header + for(i = 0; i < 4; i++) { // Send x percentage - one byte at a time + UART_putCharacter(xpointer[i]); + } + for(i = 0; i < 4; i++) { // Send y percentage - one byte at a time + UART_putCharacter(ypointer[i]); + } + for(i = 0; i < 4; i++) { // Send y percentage - one byte at a time + UART_putCharacter(zpointer[i]); + } +} + +void main(void) { + WDTCTL = WDTPW +WDTHOLD; // Stop WDT + TimerA_setup(); // Setup timer to send ADC data + ADC_setup(); // Setup ADC + UART_setup(); // Setup UART for RS-232 + _EINT(); + while (1){ + ADC12CTL0 |= ADC12SC; // Start conversions + __bis_SR_register(LPM0_bits + GIE); // Enter LPM0 + } +} + +#pragma vector = ADC12_VECTOR +__interrupt void ADC12ISR(void) { + ADCXval = ADC12MEM0; // Move results, IFG is cleared + ADCYval = ADC12MEM1; + ADCZval = ADC12MEM2; + __bic_SR_register_on_exit(LPM0_bits); // Exit LPM0 +} + +#pragma vector = TIMERA0_VECTOR +__interrupt void timerA_isr() { + sendData(); // Send data to serial app + __bic_SR_register_on_exit(LPM0_bits); // Exit LPM0 +} + +// Port 1 interrupt service routine +#pragma vector = PORT2_VECTOR +__interrupt void Port2_ISR (void) { + if(!SW1_PRESSED){ + P2OUT &= ~BIT2; + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared + } +} diff --git a/CPE325/Lab10_Part2/lnk_msp430fg4618.cmd b/CPE325/Lab10_Part2/lnk_msp430fg4618.cmd new file mode 100755 index 0000000..557b664 --- /dev/null +++ b/CPE325/Lab10_Part2/lnk_msp430fg4618.cmd @@ -0,0 +1,184 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************************/ +/* lnk_msp430fg4618.cmd - LINKER COMMAND FILE FOR LINKING MSP430FG4618 PROGRAMS */ +/* */ +/* Usage: lnk430 -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/Lab10_Part2/targetConfigs/MSP430FG4618.ccxml b/CPE325/Lab10_Part2/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/Lab10_Part2/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab10_Part2/targetConfigs/readme.txt b/CPE325/Lab10_Part2/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab10_Part2/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab10_Part3/Debug/Lab10_Part3.d b/CPE325/Lab10_Part3/Debug/Lab10_Part3.d new file mode 100644 index 0000000..dfab371 --- /dev/null +++ b/CPE325/Lab10_Part3/Debug/Lab10_Part3.d @@ -0,0 +1,27 @@ +# FIXED + +Lab10_Part3.obj: ../Lab10_Part3.c +Lab10_Part3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +Lab10_Part3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h +Lab10_Part3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +Lab10_Part3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +Lab10_Part3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +Lab10_Part3.obj: C:/CPE325_Workspace/Lab10_Part3/sawtooth.h +Lab10_Part3.obj: C:/CPE325_Workspace/Lab10_Part3/sine_lut_512.h + +../Lab10_Part3.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/CPE325_Workspace/Lab10_Part3/sawtooth.h: + +C:/CPE325_Workspace/Lab10_Part3/sine_lut_512.h: + diff --git a/CPE325/Lab10_Part3/Debug/Lab10_Part3.map b/CPE325/Lab10_Part3/Debug/Lab10_Part3.map new file mode 100644 index 0000000..4ad3e85 --- /dev/null +++ b/CPE325/Lab10_Part3/Debug/Lab10_Part3.map @@ -0,0 +1,810 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Thu Dec 2 20:38:02 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00003100 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOB 00001000 00000080 00000000 00000080 RWIX + INFOA 00001080 00000080 00000000 00000080 RWIX + RAM 00001100 00002000 00000854 000017ac RWIX + FLASH 00003100 0000cebe 00000802 0000c6bc RWIX + BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff + INT00 0000ffc0 00000002 00000000 00000002 RWIX + INT01 0000ffc2 00000002 00000000 00000002 RWIX + INT02 0000ffc4 00000002 00000000 00000002 RWIX + INT03 0000ffc6 00000002 00000000 00000002 RWIX + INT04 0000ffc8 00000002 00000000 00000002 RWIX + INT05 0000ffca 00000002 00000000 00000002 RWIX + INT06 0000ffcc 00000002 00000000 00000002 RWIX + INT07 0000ffce 00000002 00000000 00000002 RWIX + INT08 0000ffd0 00000002 00000000 00000002 RWIX + INT09 0000ffd2 00000002 00000000 00000002 RWIX + INT10 0000ffd4 00000002 00000000 00000002 RWIX + INT11 0000ffd6 00000002 00000000 00000002 RWIX + INT12 0000ffd8 00000002 00000000 00000002 RWIX + INT13 0000ffda 00000002 00000000 00000002 RWIX + INT14 0000ffdc 00000002 00000002 00000000 RWIX + INT15 0000ffde 00000002 00000002 00000000 RWIX + INT16 0000ffe0 00000002 00000002 00000000 RWIX + INT17 0000ffe2 00000002 00000002 00000000 RWIX + INT18 0000ffe4 00000002 00000002 00000000 RWIX + INT19 0000ffe6 00000002 00000002 00000000 RWIX + INT20 0000ffe8 00000002 00000002 00000000 RWIX + INT21 0000ffea 00000002 00000002 00000000 RWIX + INT22 0000ffec 00000002 00000002 00000000 RWIX + INT23 0000ffee 00000002 00000002 00000000 RWIX + INT24 0000fff0 00000002 00000002 00000000 RWIX + INT25 0000fff2 00000002 00000002 00000000 RWIX + INT26 0000fff4 00000002 00000002 00000000 RWIX + INT27 0000fff6 00000002 00000002 00000000 RWIX + INT28 0000fff8 00000002 00000002 00000000 RWIX + INT29 0000fffa 00000002 00000002 00000000 RWIX + INT30 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 00010000 00000184 0000fe7c RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00001100 00000804 UNINITIALIZED + 00001100 00000402 Lab10_Part3.obj (.data:sawtooth) + 00001502 00000402 Lab10_Part3.obj (.data:sine) + +.stack 0 000030b0 00000050 UNINITIALIZED + 000030b0 00000004 rts430x_lc_rd_eabi.lib : boot.c.obj (.stack) + 000030b4 0000004c --HOLE-- + +.text:_isr +* 0 00003100 0000002c + 00003100 0000001c rts430x_lc_rd_eabi.lib : boot.c.obj (.text:_isr:_c_int00_noargs) + 0000311c 00000008 Lab10_Part3.obj (.text:_isr:TA0_ISR) + 00003124 00000008 rts430x_lc_rd_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 0000312c 000007d6 + 0000312c 000007c5 (.cinit..data.load) [load image, compression = lzss] + 000038f1 00000001 --HOLE-- [fill = 0] + 000038f2 00000008 (__TI_handler_table) + 000038fa 00000008 (__TI_cinit_table) + +.binit 0 00003100 00000000 + +.init_array +* 0 00003100 00000000 UNINITIALIZED + +$fill000 0 0000ffbe 00000002 + 0000ffbe 00000002 --HOLE-- [fill = ffff] + +DAC12 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430x_lc_rd_eabi.lib : int14.asm.obj (.int14) + +DMA 0 0000ffde 00000002 + 0000ffde 00000002 rts430x_lc_rd_eabi.lib : int15.asm.obj (.int15) + +BASICTIMER +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430x_lc_rd_eabi.lib : int16.asm.obj (.int16) + +PORT2 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430x_lc_rd_eabi.lib : int17.asm.obj (.int17) + +USART1TX 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430x_lc_rd_eabi.lib : int18.asm.obj (.int18) + +USART1RX 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430x_lc_rd_eabi.lib : int19.asm.obj (.int19) + +PORT1 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430x_lc_rd_eabi.lib : int20.asm.obj (.int20) + +TIMERA1 0 0000ffea 00000002 + 0000ffea 00000002 rts430x_lc_rd_eabi.lib : int21.asm.obj (.int21) + +TIMERA0 0 0000ffec 00000002 + 0000ffec 00000002 Lab10_Part3.obj (.int22) + +ADC12 0 0000ffee 00000002 + 0000ffee 00000002 rts430x_lc_rd_eabi.lib : int23.asm.obj (.int23) + +USCIAB0TX +* 0 0000fff0 00000002 + 0000fff0 00000002 rts430x_lc_rd_eabi.lib : int24.asm.obj (.int24) + +USCIAB0RX +* 0 0000fff2 00000002 + 0000fff2 00000002 rts430x_lc_rd_eabi.lib : int25.asm.obj (.int25) + +WDT 0 0000fff4 00000002 + 0000fff4 00000002 rts430x_lc_rd_eabi.lib : int26.asm.obj (.int26) + +COMPARATORA +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430x_lc_rd_eabi.lib : int27.asm.obj (.int27) + +TIMERB1 0 0000fff8 00000002 + 0000fff8 00000002 rts430x_lc_rd_eabi.lib : int28.asm.obj (.int28) + +TIMERB0 0 0000fffa 00000002 + 0000fffa 00000002 rts430x_lc_rd_eabi.lib : int29.asm.obj (.int29) + +NMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430x_lc_rd_eabi.lib : int30.asm.obj (.int30) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430x_lc_rd_eabi.lib : boot.c.obj (.reset) + +.text 0 00010000 00000184 + 00010000 00000076 rts430x_lc_rd_eabi.lib : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00010076 0000005e Lab10_Part3.obj (.text:main) + 000100d4 00000054 rts430x_lc_rd_eabi.lib : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 00010128 00000016 Lab10_Part3.obj (.text:DAC_setup) + 0001013e 00000014 Lab10_Part3.obj (.text:TimerA_setup) + 00010152 00000014 rts430x_lc_rd_eabi.lib : memcpy.c.obj (.text:memcpy) + 00010166 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00010178 00000006 : exit.c.obj (.text:abort) + 0001017e 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00010182 00000002 : startup.c.obj (.text:_system_post_cinit) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + Lab10_Part3.obj 144 2 2052 + +--+----------------------------+------+---------+---------+ + Total: 144 2 2052 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430x_lc_rd_eabi.lib + copy_decompress_lzss.c.obj 118 0 0 + autoinit.c.obj 84 0 0 + boot.c.obj 28 2 0 + memcpy.c.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + isr_trap.asm.obj 8 0 0 + exit.c.obj 6 0 0 + pre_init.c.obj 4 0 0 + int14.asm.obj 0 2 0 + int15.asm.obj 0 2 0 + int16.asm.obj 0 2 0 + int17.asm.obj 0 2 0 + int18.asm.obj 0 2 0 + int19.asm.obj 0 2 0 + int20.asm.obj 0 2 0 + int21.asm.obj 0 2 0 + int23.asm.obj 0 2 0 + int24.asm.obj 0 2 0 + int25.asm.obj 0 2 0 + int26.asm.obj 0 2 0 + int27.asm.obj 0 2 0 + int28.asm.obj 0 2 0 + int29.asm.obj 0 2 0 + int30.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+------+---------+---------+ + Total: 288 34 0 + + Stack: 0 0 80 + Linker Generated: 0 2005 0 + +--+----------------------------+------+---------+---------+ + Grand Total: 432 2041 2132 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 000038fa records: 1, size/record: 8, table size: 8 + .data: load addr=0000312c, load size=000007c5 bytes, run addr=00001100, run size=00000804 bytes, compression=lzss + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 000038f2 records: 2, size/record: 4, table size: 8 + index: 0, handler: __TI_decompress_lzss + index: 1, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a6 ADC12IE +000001a4 ADC12IFG +000001a8 ADC12IV +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +00000040 BTCTL +00010178 C$$EXIT +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +000001c0 DAC12_0CTL +000001c8 DAC12_0DAT +000001c2 DAC12_1CTL +000001ca DAC12_1DAT +00010128 DAC_setup +000001d0 DMA0CTL +000001d6 DMA0DA +000001d6 DMA0DAL +000001d2 DMA0SA +000001d2 DMA0SAL +000001da DMA0SZ +000001dc DMA1CTL +000001e2 DMA1DA +000001e2 DMA1DAL +000001de DMA1SA +000001de DMA1SAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ee DMA2DA +000001ee DMA2DAL +000001ea DMA2SA +000001ea DMA2SAL +000001f2 DMA2SZ +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000090 LCDACTL +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +00000091 LCDM1 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +00000092 LCDM2 +000000a4 LCDM20 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +00000134 MAC +00000136 MACS +00000005 ME2 +00000130 MPY +00000132 MPYS +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000138 OP2 +0000000d P10DIR +00000009 P10IN +0000000b P10OUT +0000000f P10SEL +00000022 P1DIR +00000025 P1IE +00000024 P1IES +00000023 P1IFG +00000020 P1IN +00000021 P1OUT +00000026 P1SEL +0000002a P2DIR +0000002d P2IE +0000002c P2IES +0000002b P2IFG +00000028 P2IN +00000029 P2OUT +0000002e P2SEL +0000001a P3DIR +00000018 P3IN +00000019 P3OUT +0000001b P3SEL +0000001e P4DIR +0000001c P4IN +0000001d P4OUT +0000001f P4SEL +00000032 P5DIR +00000030 P5IN +00000031 P5OUT +00000033 P5SEL +00000036 P6DIR +00000034 P6IN +00000035 P6OUT +00000037 P6SEL +0000003c P7DIR +00000038 P7IN +0000003a P7OUT +0000003e P7SEL +0000003d P8DIR +00000039 P8IN +0000003b P8OUT +0000003f P8SEL +0000000c P9DIR +00000008 P9IN +0000000a P9OUT +0000000e P9SEL +0000003c PADIR +00000038 PAIN +0000003a PAOUT +0000003e PASEL +0000000c PBDIR +00000008 PBIN +0000000a PBOUT +0000000e PBSEL +0000013c RESHI +0000013a RESLO +00000041 RTCCTL +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +00000042 RTCNT1 +00000043 RTCNT2 +00000044 RTCNT3 +00000045 RTCNT4 +00000042 RTCTIM0 +00000044 RTCTIM1 +00000040 RTCTL +0000004e RTCYEAR +0000004f RTCYEARH +0000004e RTCYEARL +00000050 SCFI0 +00000051 SCFI1 +00000052 SCFQCTL +0000013e SUMEXT +00000056 SVSCTL +0000311c TA0_ISR +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000160 TACTL +0000012e TAIV +00000170 TAR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000180 TBCTL +0000011e TBIV +00000190 TBR +0001013e TimerA_setup +0000007c U1BR0 +0000007d U1BR1 +00000078 U1CTL +0000007b U1MCTL +0000007a U1RCTL +0000007e U1RXBUF +00000079 U1TCTL +0000007f U1TXBUF +0000005d UCA0ABCTL +00000062 UCA0BR0 +00000063 UCA0BR1 +00000060 UCA0CTL0 +00000061 UCA0CTL1 +0000005f UCA0IRRCTL +0000005e UCA0IRTCTL +00000064 UCA0MCTL +00000066 UCA0RXBUF +00000065 UCA0STAT +00000067 UCA0TXBUF +0000006a UCB0BR0 +0000006b UCB0BR1 +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006c UCB0I2CIE +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000006e UCB0RXBUF +0000006d UCB0STAT +0000006f UCB0TXBUF +00000120 WDTCTL +00003100 __STACK_END +00000050 __STACK_SIZE +000038fa __TI_CINIT_Base +00003902 __TI_CINIT_Limit +000038f2 __TI_Handler_Table_Base +000038fa __TI_Handler_Table_Limit +00003124 __TI_ISR_TRAP +000100d4 __TI_auto_init_nobinit_nopinit_hold_wdt +00010000 __TI_decompress_lzss +00010166 __TI_decompress_none +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 __TI_int20 +0000ffea __TI_int21 +0000ffec __TI_int22 +0000ffee __TI_int23 +0000fff0 __TI_int24 +0000fff2 __TI_int25 +0000fff4 __TI_int26 +0000fff6 __TI_int27 +0000fff8 __TI_int28 +0000fffa __TI_int29 +0000fffc __TI_int30 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ +00003100 _c_int00_noargs +0000fffe _reset_vector +000030b0 _stack +00010182 _system_post_cinit +0001017e _system_pre_init +00010178 abort +00010076 main +00010152 memcpy +00001100 sawtooth +00001502 sine + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000005 ME2 +00000008 P9IN +00000008 PBIN +00000009 P10IN +0000000a P9OUT +0000000a PBOUT +0000000b P10OUT +0000000c P9DIR +0000000c PBDIR +0000000d P10DIR +0000000e P9SEL +0000000e PBSEL +0000000f P10SEL +00000018 P3IN +00000019 P3OUT +0000001a P3DIR +0000001b P3SEL +0000001c P4IN +0000001d P4OUT +0000001e P4DIR +0000001f P4SEL +00000020 P1IN +00000021 P1OUT +00000022 P1DIR +00000023 P1IFG +00000024 P1IES +00000025 P1IE +00000026 P1SEL +00000028 P2IN +00000029 P2OUT +0000002a P2DIR +0000002b P2IFG +0000002c P2IES +0000002d P2IE +0000002e P2SEL +00000030 P5IN +00000031 P5OUT +00000032 P5DIR +00000033 P5SEL +00000034 P6IN +00000035 P6OUT +00000036 P6DIR +00000037 P6SEL +00000038 P7IN +00000038 PAIN +00000039 P8IN +0000003a P7OUT +0000003a PAOUT +0000003b P8OUT +0000003c P7DIR +0000003c PADIR +0000003d P8DIR +0000003e P7SEL +0000003e PASEL +0000003f P8SEL +00000040 BTCTL +00000040 RTCTL +00000041 RTCCTL +00000042 RTCNT1 +00000042 RTCTIM0 +00000043 RTCNT2 +00000044 RTCNT3 +00000044 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+ __TI_prof_data_size + 0xffffffff + + + sine + 0x1502 + + + + __TI_int22 + 0xffec + + + + TimerA_setup + 0x1013e + + + + TA0_ISR + 0x311c + + + + main + 0x10076 + + + + DAC_setup + 0x10128 + + + + sawtooth + 0x1100 + + + + __TI_int14 + 0xffdc + + + + __TI_int15 + 0xffde + + + + __TI_int16 + 0xffe0 + + + + __TI_int17 + 0xffe2 + + + + __TI_int18 + 0xffe4 + + + + __TI_int19 + 0xffe6 + + + + __TI_int20 + 0xffe8 + + + + __TI_int21 + 0xffea + + + + __TI_int23 + 0xffee + + + + __TI_int24 + 0xfff0 + + + + __TI_int25 + 0xfff2 + + + + __TI_int26 + 0xfff4 + + + + __TI_int27 + 0xfff6 + + + + __TI_int28 + 0xfff8 + + + + __TI_int29 + 0xfffa + + + + __TI_int30 + 0xfffc + + + + __TI_ISR_TRAP + 0x3124 + + + + _stack + 0x30b0 + + + + _c_int00_noargs + 0x3100 + + + + _reset_vector + 0xfffe + + + + __TI_auto_init_nobinit_nopinit_hold_wdt + 0x100d4 + + + + _system_pre_init + 0x1017e + + + + _system_post_cinit + 0x10182 + + + + __TI_decompress_none + 0x10166 + + + + __TI_decompress_lzss + 0x10000 + + + + C$$EXIT + 0x10178 + + + + abort + 0x10178 + + + + memcpy + 0x10152 + + + + Link successful + diff --git a/CPE325/Lab10_Part3/Debug/ccsObjs.opt b/CPE325/Lab10_Part3/Debug/ccsObjs.opt new file mode 100644 index 0000000..eafe476 --- /dev/null +++ b/CPE325/Lab10_Part3/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./Lab10_Part3.obj" "../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/Lab10_Part3/Debug/main.d b/CPE325/Lab10_Part3/Debug/main.d new file mode 100644 index 0000000..ed8cf65 --- /dev/null +++ b/CPE325/Lab10_Part3/Debug/main.d @@ -0,0 +1,27 @@ +# FIXED + +main.obj: ../main.c +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +main.obj: C:/CPE325_Workspace/Lab10_Part3/sawtooth.h +main.obj: C:/CPE325_Workspace/Lab10_Part3/sine_lut_256.h + +../main.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/CPE325_Workspace/Lab10_Part3/sawtooth.h: + +C:/CPE325_Workspace/Lab10_Part3/sine_lut_256.h: + diff --git a/CPE325/Lab10_Part3/Debug/makefile b/CPE325/Lab10_Part3/Debug/makefile new file mode 100644 index 0000000..4dc3c68 --- /dev/null +++ b/CPE325/Lab10_Part3/Debug/makefile @@ -0,0 +1,166 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./Lab10_Part3.obj" \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab10_Part3.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab10_Part3.out" \ + +BIN_OUTPUTS += \ +Lab10_Part3.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab10_Part3.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab10_Part3.out" + +# Tool invocations +Lab10_Part3.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"Lab10_Part3.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab10_Part3_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "Lab10_Part3.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab10_Part3.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab10_Part3.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "Lab10_Part3.obj" + -$(RM) "Lab10_Part3.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab10_Part3/Debug/objects.mk b/CPE325/Lab10_Part3/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/Lab10_Part3/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/Lab10_Part3/Debug/sources.mk b/CPE325/Lab10_Part3/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab10_Part3/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab10_Part3/Debug/subdir_rules.mk b/CPE325/Lab10_Part3/Debug/subdir_rules.mk new file mode 100644 index 0000000..5098f20 --- /dev/null +++ b/CPE325/Lab10_Part3/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab10_Part3" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --preproc_with_compile --preproc_dependency="$(basename $( sine (10Hz) + * | | + * Input: None + * Output: Sinusoidal wave with 10Hz frequency at P6.6 + * Author: Aleksandar Milenkovic, milenkovic@computer.org + * Max Avula, ma0004@uah.edu + *------------------------------------------------------------------------------*/ +#include +#include /*512 samples are stored in this table */ +#include /*256 samples are stored in this table */ + + +#define SW1 ((P1IN&BIT0)==0) // Switch 1 status +#define SW2 ((P1IN&BIT1)==0) // Switch 2 status + +void TimerA_setup(void) { + TACTL = TASSEL_2 + MC_1; // SMCLK, up mode + TACCR0 = 164; // Sets Timer Freq (1048576*0.1sec/256) + TACCTL0 = CCIE; // CCR0 interrupt enabled +} + +void DAC_setup(void) { + ADC12CTL0 = REF2_5V + REFON; // Turn on 2.5V internal ref volage + unsigned int i = 0; + for (i = 50000; i > 0; i--); // Delay to allow Ref to settle + DAC12_0CTL = DAC12IR + DAC12AMP_5 + DAC12ENC; //Sets DAC12 +} + +void main(void) { + P1DIR &= ~BIT0; // Set P1.1 to output direction + P1DIR &= ~BIT1; // Set P1.0 to output direction + FLL_CTL0 |= DCOPLUS + XCAP18PF; // DCO+ set, freq = xtal x D x N+1 + SCFI0 |= FN_4 + FLLD_2; // DCO range control, multiplier D + SCFQCTL = 63; // (61+1) x 32768 x 2 = 4.19 MHz + WDTCTL = WDTPW + WDTHOLD; // Stop WDT + TimerA_setup(); // Set timer to uniformly distribute the samples + DAC_setup(); // Setup DAC + unsigned int i = 0; + unsigned int o = 0; + while (1) { + __bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled + if(SW1){ + o = sine[i]; + } + else{ + o = sawtooth[i]; + } + if(!SW2){ + o = o>>1; + } + DAC12_0DAT = o; + i=(i+1)%512; + } +} + +#pragma vector = TIMERA0_VECTOR +__interrupt void TA0_ISR(void) { + __bic_SR_register_on_exit(LPM0_bits); // Exit LPMx, interrupts enabled +} diff --git a/CPE325/Lab10_Part3/lnk_msp430fg4618.cmd b/CPE325/Lab10_Part3/lnk_msp430fg4618.cmd new file mode 100755 index 0000000..557b664 --- /dev/null +++ b/CPE325/Lab10_Part3/lnk_msp430fg4618.cmd @@ -0,0 +1,184 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************************/ +/* lnk_msp430fg4618.cmd - LINKER COMMAND FILE FOR LINKING MSP430FG4618 PROGRAMS */ +/* */ +/* Usage: lnk430 -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/Lab10_Part3/sawtooth.h b/CPE325/Lab10_Part3/sawtooth.h new file mode 100644 index 0000000..d421c63 --- /dev/null +++ b/CPE325/Lab10_Part3/sawtooth.h @@ -0,0 +1 @@ +int sawtooth[] = {0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240,256,272,288,304,320,336,352,368,384,400,416,432,448,464,480,496,512,528,544,560,576,592,608,624,640,656,672,688,704,720,736,752,768,784,800,816,832,848,864,880,896,912,928,944,960,976,992,1008,1024,1040,1056,1072,1088,1104,1120,1136,1152,1168,1184,1200,1216,1232,1248,1264,1280,1296,1312,1328,1344,1360,1376,1392,1408,1424,1440,1456,1472,1488,1504,1520,1536,1552,1568,1584,1600,1616,1632,1648,1664,1680,1696,1712,1728,1744,1760,1776,1792,1808,1824,1840,1856,1872,1888,1904,1920,1936,1952,1968,1984,2000,2016,2032,2048,2063,2079,2095,2111,2127,2143,2159,2175,2191,2207,2223,2239,2255,2271,2287,2303,2319,2335,2351,2367,2383,2399,2415,2431,2447,2463,2479,2495,2511,2527,2543,2559,2575,2591,2607,2623,2639,2655,2671,2687,2703,2719,2735,2751,2767,2783,2799,2815,2831,2847,2863,2879,2895,2911,2927,2943,2959,2975,2991,3007,3023,3039,3055,3071,3087,3103,3119,3135,3151,3167,3183,3199,3215,3231,3247,3263,3279,3295,3311,3327,3343,3359,3375,3391,3407,3423,3439,3455,3471,3487,3503,3519,3535,3551,3567,3583,3599,3615,3631,3647,3663,3679,3695,3711,3727,3743,3759,3775,3791,3807,3823,3839,3855,3871,3887,3903,3919,3935,3951,3967,3983,3999,4015,4031,4047,4063,4079,4095,4079,4063,4047,4031,4015,3999,3983,3967,3951,3935,3919,3903,3887,3871,3855,3839,3823,3807,3791,3775,3759,3743,3727,3711,3695,3679,3663,3647,3631,3615,3599,3583,3567,3551,3535,3519,3503,3487,3471,3455,3439,3423,3407,3391,3375,3359,3343,3327,3311,3295,3279,3263,3247,3231,3215,3199,3183,3167,3151,3135,3119,3103,3087,3071,3055,3039,3023,3007,2991,2975,2959,2943,2927,2911,2895,2879,2863,2847,2831,2815,2799,2783,2767,2751,2735,2719,2703,2687,2671,2655,2639,2623,2607,2591,2575,2559,2543,2527,2511,2495,2479,2463,2447,2431,2415,2399,2383,2367,2351,2335,2319,2303,2287,2271,2255,2239,2223,2207,2191,2175,2159,2143,2127,2111,2095,2079,2063,2048,2032,2016,2000,1984,1968,1952,1936,1920,1904,1888,1872,1856,1840,1824,1808,1792,1776,1760,1744,1728,1712,1696,1680,1664,1648,1632,1616,1600,1584,1568,1552,1536,1520,1504,1488,1472,1456,1440,1424,1408,1392,1376,1360,1344,1328,1312,1296,1280,1264,1248,1232,1216,1200,1184,1168,1152,1136,1120,1104,1088,1072,1056,1040,1024,1008,992,976,960,944,928,912,896,880,864,848,832,816,800,784,768,752,736,720,704,688,672,656,640,624,608,592,576,560,544,528,512,496,480,464,448,432,416,400,384,368,352,336,320,304,288,272,256,240,224,208,192,176,160,144,128,112,96,80,64,48,32,16,0}; diff --git a/CPE325/Lab10_Part3/sine_lut_256.h b/CPE325/Lab10_Part3/sine_lut_256.h new file mode 100644 index 0000000..c210ccd --- /dev/null +++ b/CPE325/Lab10_Part3/sine_lut_256.h @@ -0,0 +1 @@ +int LUT256[] = { 2048, 2098, 2148, 2198, 2248, 2298, 2348, 2398, 2447, 2496, 2545, 2594, 2642, 2690, 2737, 2784, 2831, 2877, 2923, 2968, 3013, 3057, 3100, 3143, 3185, 3226, 3267, 3307, 3346, 3385, 3423, 3459, 3495, 3530, 3565, 3598, 3630, 3662, 3692, 3722, 3750, 3777, 3804, 3829, 3853, 3876, 3898, 3919, 3939, 3958, 3975, 3992, 4007, 4021, 4034, 4045, 4056, 4065, 4073, 4080, 4085, 4089, 4093, 4094, 4095, 4094, 4093, 4089, 4085, 4080, 4073, 4065, 4056, 4045, 4034, 4021, 4007, 3992, 3975, 3958, 3939, 3919, 3898, 3876, 3853, 3829, 3804, 3777, 3750, 3722, 3692, 3662, 3630, 3598, 3565, 3530, 3495, 3459, 3423, 3385, 3346, 3307, 3267, 3226, 3185, 3143, 3100, 3057, 3013, 2968, 2923, 2877, 2831, 2784, 2737, 2690, 2642, 2594, 2545, 2496, 2447, 2398, 2348, 2298, 2248, 2198, 2148, 2098, 2048, 1997, 1947, 1897, 1847, 1797, 1747, 1697, 1648, 1599, 1550, 1501, 1453, 1405, 1358, 1311, 1264, 1218, 1172, 1127, 1082, 1038, 995, 952, 910, 869, 828, 788, 749, 710, 672, 636, 600, 565, 530, 497, 465, 433, 403, 373, 345, 318, 291, 266, 242, 219, 197, 176, 156, 137, 120, 103, 88, 74, 61, 50, 39, 30, 22, 15, 10, 6, 2, 1, 0, 1, 2, 6, 10, 15, 22, 30, 39, 50, 61, 74, 88, 103, 120, 137, 156, 176, 197, 219, 242, 266, 291, 318, 345, 373, 403, 433, 465, 497, 530, 565, 600, 636, 672, 710, 749, 788, 828, 869, 910, 952, 995, 1038, 1082, 1127, 1172, 1218, 1264, 1311, 1358, 1405, 1453, 1501, 1550, 1599, 1648, 1697, 1747, 1797, 1847, 1897, 1947, 1997, 2047 }; diff --git a/CPE325/Lab10_Part3/sine_lut_512.h b/CPE325/Lab10_Part3/sine_lut_512.h new file mode 100644 index 0000000..10af175 --- /dev/null +++ b/CPE325/Lab10_Part3/sine_lut_512.h @@ -0,0 +1 @@ +int sine[] = {2048,2073,2098,2123,2148,2173,2198,2223,2248,2273,2298,2323,2348,2373,2398,2422,2447,2472,2496,2521,2545,2569,2594,2618,2642,2666,2690,2714,2737,2761,2784,2808,2831,2854,2877,2900,2923,2946,2968,2990,3013,3035,3057,3078,3100,3122,3143,3164,3185,3206,3226,3247,3267,3287,3307,3327,3346,3366,3385,3404,3423,3441,3459,3477,3495,3513,3530,3548,3565,3581,3598,3614,3630,3646,3662,3677,3692,3707,3722,3736,3750,3764,3777,3791,3804,3816,3829,3841,3853,3865,3876,3888,3898,3909,3919,3929,3939,3949,3958,3967,3975,3984,3992,3999,4007,4014,4021,4027,4034,4040,4045,4051,4056,4060,4065,4069,4073,4076,4080,4083,4085,4087,4089,4091,4093,4094,4094,4095,4095,4095,4094,4094,4093,4091,4089,4087,4085,4083,4080,4076,4073,4069,4065,4060,4056,4051,4045,4040,4034,4027,4021,4014,4007,3999,3992,3984,3975,3967,3958,3949,3939,3929,3919,3909,3898,3888,3876,3865,3853,3841,3829,3816,3804,3791,3777,3764,3750,3736,3722,3707,3692,3677,3662,3646,3630,3614,3598,3581,3565,3548,3530,3513,3495,3477,3459,3441,3423,3404,3385,3366,3346,3327,3307,3287,3267,3247,3226,3206,3185,3164,3143,3122,3100,3078,3057,3035,3013,2990,2968,2946,2923,2900,2877,2854,2831,2808,2784,2761,2737,2714,2690,2666,2642,2618,2594,2569,2545,2521,2496,2472,2447,2422,2398,2373,2348,2323,2298,2273,2248,2223,2198,2173,2148,2123,2098,2073,2048,2022,1997,1972,1947,1922,1897,1872,1847,1822,1797,1772,1747,1722,1697,1673,1648,1623,1599,1574,1550,1526,1501,1477,1453,1429,1405,1381,1358,1334,1311,1287,1264,1241,1218,1195,1172,1149,1127,1105,1082,1060,1038,1017,995,973,952,931,910,889,869,848,828,808,788,768,749,729,710,691,672,654,636,618,600,582,565,547,530,514,497,481,465,449,433,418,403,388,373,359,345,331,318,304,291,279,266,254,242,230,219,207,197,186,176,166,156,146,137,128,120,111,103,96,88,81,74,68,61,55,50,44,39,35,30,26,22,19,15,12,10,8,6,4,2,1,1,0,0,0,1,1,2,4,6,8,10,12,15,19,22,26,30,35,39,44,50,55,61,68,74,81,88,96,103,111,120,128,137,146,156,166,176,186,197,207,219,230,242,254,266,279,291,304,318,331,345,359,373,388,403,418,433,449,465,481,497,514,530,547,565,582,600,618,636,654,672,691,710,729,749,768,788,808,828,848,869,889,910,931,952,973,995,1017,1038,1060,1082,1105,1127,1149,1172,1195,1218,1241,1264,1287,1311,1334,1358,1381,1405,1429,1453,1477,1501,1526,1550,1574,1599,1623,1648,1673,1697,1722,1747,1772,1797,1822,1847,1872,1897,1922,1947,1972,1997,2022,2047}; diff --git a/CPE325/Lab10_Part3/targetConfigs/MSP430FG4618.ccxml b/CPE325/Lab10_Part3/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/Lab10_Part3/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab10_Part3/targetConfigs/readme.txt b/CPE325/Lab10_Part3/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab10_Part3/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab11/Debug/ccsObjs.opt b/CPE325/Lab11/Debug/ccsObjs.opt new file mode 100644 index 0000000..4135955 --- /dev/null +++ b/CPE325/Lab11/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/Lab11/Debug/makefile b/CPE325/Lab11/Debug/makefile new file mode 100644 index 0000000..e204bcc --- /dev/null +++ b/CPE325/Lab11/Debug/makefile @@ -0,0 +1,163 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab11.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab11.out" \ + +BIN_OUTPUTS += \ +Lab11.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab11.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab11.out" + +# Tool invocations +Lab11.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"Lab11.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab11_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "Lab11.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab11.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab11.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab11/Debug/objects.mk b/CPE325/Lab11/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/Lab11/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/Lab11/Debug/sources.mk b/CPE325/Lab11/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab11/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab11/Debug/subdir_rules.mk b/CPE325/Lab11/Debug/subdir_rules.mk new file mode 100644 index 0000000..228691f --- /dev/null +++ b/CPE325/Lab11/Debug/subdir_rules.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes + diff --git a/CPE325/Lab11/Debug/subdir_vars.mk b/CPE325/Lab11/Debug/subdir_vars.mk new file mode 100644 index 0000000..dfb26fc --- /dev/null +++ b/CPE325/Lab11/Debug/subdir_vars.mk @@ -0,0 +1,17 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +../lnk_msp430fg4618.cmd + +OUT_SRCS += \ +../crack_me.out + +OUT_SRCS__QUOTED += \ +"../crack_me.out" + + diff --git a/CPE325/Lab11/Log/log.txt b/CPE325/Lab11/Log/log.txt new file mode 100644 index 0000000..77fb612 --- /dev/null +++ b/CPE325/Lab11/Log/log.txt @@ -0,0 +1,493 @@ +Thu Nov 18 19:58:34 2021: * -----/|-------------------------------------------------------------------- * +Thu Nov 18 19:58:34 2021: * / |__ * +Thu Nov 18 19:58:34 2021: * /_ / MSP Flasher v1.3.20 * +Thu Nov 18 19:58:34 2021: * | / * +Thu Nov 18 19:58:34 2021: * -----|/-------------------------------------------------------------------- * +Thu Nov 18 19:58:34 2021: * +Thu Nov 18 19:58:34 2021: * Evaluating triggers...done +Thu Nov 18 19:58:34 2021: * Checking for available FET debuggers: +Thu Nov 18 19:58:34 2021: * Found USB FET @ COM14 <- Selected +Thu Nov 18 19:58:34 2021: * Initializing interface @ COM14...done +Thu Nov 18 19:58:34 2021: * Checking firmware compatibility: +Thu Nov 18 19:58:34 2021: * FET firmware is up to date. +Thu Nov 18 19:58:34 2021: * Reading FW version...done +Thu Nov 18 19:58:34 2021: * Setting VCC to 3000 mV...done +Thu Nov 18 19:58:40 2021: * Accessing device...done +Thu Nov 18 19:58:40 2021: * Reading device information...done +Thu Nov 18 19:58:40 2021: * Loading file into device...done +Thu Nov 18 19:58:41 2021: * Verifying memory (reverse_me_corrected.txt)...done +Thu Nov 18 19:58:41 2021: * +Thu Nov 18 19:58:41 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 19:58:41 2021: * Arguments : -n MSP430FG4618 -w reverse_me_corrected.txt -v -z [Vcc] +Thu Nov 18 19:58:41 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 19:58:41 2021: * Driver : loaded +Thu Nov 18 19:58:41 2021: * Dll Version : 31400000 +Thu Nov 18 19:58:41 2021: * FwVersion : 31200000 +Thu Nov 18 19:58:41 2021: * Interface : TIUSB +Thu Nov 18 19:58:41 2021: * HwVersion : U 3.0 +Thu Nov 18 19:58:41 2021: * JTAG Mode : AUTO +Thu Nov 18 19:58:41 2021: * Device : MSP430FG4618 +Thu Nov 18 19:58:41 2021: * EEM : Level 3, ClockCntrl 2 +Thu Nov 18 19:58:41 2021: * Erase Mode : ERASE_ALL +Thu Nov 18 19:58:41 2021: * Prog.File : reverse_me_corrected.txt +Thu Nov 18 19:58:41 2021: * Verified : TRUE +Thu Nov 18 19:58:41 2021: * BSL Unlock : FALSE +Thu Nov 18 19:58:41 2021: * InfoA Access: FALSE +Thu Nov 18 19:58:41 2021: * VCC ON : 3000 mV +Thu Nov 18 19:58:41 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 19:58:41 2021: * Starting target code execution...done +Thu Nov 18 19:58:42 2021: * Disconnecting from device...done +Thu Nov 18 19:58:42 2021: * +Thu Nov 18 19:58:42 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 19:58:42 2021: * Driver : closed (No error) +Thu Nov 18 19:58:42 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 19:58:42 2021: */ +Thu Nov 18 20:31:36 2021: * -----/|-------------------------------------------------------------------- * +Thu Nov 18 20:31:36 2021: * / |__ * +Thu Nov 18 20:31:36 2021: * /_ / MSP Flasher v1.3.20 * +Thu Nov 18 20:31:36 2021: * | / * +Thu Nov 18 20:31:36 2021: * -----|/-------------------------------------------------------------------- * +Thu Nov 18 20:31:36 2021: * +Thu Nov 18 20:31:36 2021: * Evaluating triggers...done +Thu Nov 18 20:31:36 2021: * Checking for available FET debuggers: +Thu Nov 18 20:31:36 2021: * Found USB FET @ COM14 <- Selected +Thu Nov 18 20:31:36 2021: * Initializing interface @ COM14...done +Thu Nov 18 20:31:37 2021: * Checking firmware compatibility: +Thu Nov 18 20:31:37 2021: * FET firmware is up to date. +Thu Nov 18 20:31:37 2021: * Reading FW version...done +Thu Nov 18 20:31:37 2021: * Setting VCC to 3000 mV...done +Thu Nov 18 20:31:42 2021: * Accessing device...done +Thu Nov 18 20:31:42 2021: * Reading device information...done +Thu Nov 18 20:31:42 2021: * Dumping memory from MAIN into RetrievedHEX.txt...done +Thu Nov 18 20:31:45 2021: * +Thu Nov 18 20:31:45 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 20:31:45 2021: * Arguments : -r [RetrievedHEX.txt MAIN] +Thu Nov 18 20:31:45 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 20:31:45 2021: * Driver : loaded +Thu Nov 18 20:31:45 2021: * Dll Version : 31400000 +Thu Nov 18 20:31:45 2021: * FwVersion : 31200000 +Thu Nov 18 20:31:45 2021: * Interface : TIUSB +Thu Nov 18 20:31:45 2021: * HwVersion : U 3.0 +Thu Nov 18 20:31:45 2021: * JTAG Mode : AUTO +Thu Nov 18 20:31:45 2021: * Device : MSP430FG4618 +Thu Nov 18 20:31:45 2021: * EEM : Level 3, ClockCntrl 2 +Thu Nov 18 20:31:45 2021: * Read File : RetrievedHEX.txt (memory segment = MAIN) +Thu Nov 18 20:31:45 2021: * VCC OFF +Thu Nov 18 20:31:45 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 20:31:45 2021: * Powering down...done +Thu Nov 18 20:31:45 2021: * Disconnecting from device...done +Thu Nov 18 20:31:45 2021: * +Thu Nov 18 20:31:45 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 20:31:45 2021: * Driver : closed (No error) +Thu Nov 18 20:31:45 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 20:31:45 2021: */ +Thu Nov 18 23:17:15 2021: * -----/|-------------------------------------------------------------------- * +Thu Nov 18 23:17:15 2021: * / |__ * +Thu Nov 18 23:17:15 2021: * /_ / MSP Flasher v1.3.20 * +Thu Nov 18 23:17:15 2021: * | / * +Thu Nov 18 23:17:15 2021: * -----|/-------------------------------------------------------------------- * +Thu Nov 18 23:17:15 2021: * +Thu Nov 18 23:17:15 2021: * Evaluating triggers...done +Thu Nov 18 23:17:15 2021: * Checking for available FET debuggers: +Thu Nov 18 23:17:15 2021: * Found USB FET @ COM14 <- Selected +Thu Nov 18 23:17:15 2021: * Initializing interface @ COM14...done +Thu Nov 18 23:17:16 2021: * Checking firmware compatibility: +Thu Nov 18 23:17:16 2021: * FET firmware is up to date. +Thu Nov 18 23:17:16 2021: * Reading FW version...done +Thu Nov 18 23:17:16 2021: * Setting VCC to 3000 mV...done +Thu Nov 18 23:17:16 2021: * Accessing device...done +Thu Nov 18 23:17:16 2021: * Reading device information...done +Thu Nov 18 23:17:16 2021: * Loading file into device...done +Thu Nov 18 23:17:17 2021: * Verifying memory (reverse_me_modified.txt)...done +Thu Nov 18 23:17:18 2021: * +Thu Nov 18 23:17:18 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:18 2021: * Arguments : -n MSP430FG4618 -w reverse_me_modified.txt -v -z [Vcc] +Thu Nov 18 23:17:18 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:18 2021: * Driver : loaded +Thu Nov 18 23:17:18 2021: * Dll Version : 31400000 +Thu Nov 18 23:17:18 2021: * FwVersion : 31200000 +Thu Nov 18 23:17:18 2021: * Interface : TIUSB +Thu Nov 18 23:17:18 2021: * HwVersion : U 3.0 +Thu Nov 18 23:17:18 2021: * JTAG Mode : AUTO +Thu Nov 18 23:17:18 2021: * Device : MSP430FG4618 +Thu Nov 18 23:17:18 2021: * EEM : Level 3, ClockCntrl 2 +Thu Nov 18 23:17:18 2021: * Erase Mode : ERASE_ALL +Thu Nov 18 23:17:18 2021: * Prog.File : reverse_me_modified.txt +Thu Nov 18 23:17:18 2021: * Verified : TRUE +Thu Nov 18 23:17:18 2021: * BSL Unlock : FALSE +Thu Nov 18 23:17:18 2021: * InfoA Access: FALSE +Thu Nov 18 23:17:18 2021: * VCC ON : 3000 mV +Thu Nov 18 23:17:18 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:18 2021: * Starting target code execution...done +Thu Nov 18 23:17:18 2021: * Disconnecting from device...done +Thu Nov 18 23:17:18 2021: * +Thu Nov 18 23:17:18 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:18 2021: * Driver : closed (No error) +Thu Nov 18 23:17:18 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:18 2021: */ +Thu Nov 18 23:17:41 2021: * -----/|-------------------------------------------------------------------- * +Thu Nov 18 23:17:41 2021: * / |__ * +Thu Nov 18 23:17:41 2021: * /_ / MSP Flasher v1.3.20 * +Thu Nov 18 23:17:41 2021: * | / * +Thu Nov 18 23:17:41 2021: * -----|/-------------------------------------------------------------------- * +Thu Nov 18 23:17:41 2021: * +Thu Nov 18 23:17:41 2021: * Evaluating triggers...done +Thu Nov 18 23:17:41 2021: * Checking for available FET debuggers: +Thu Nov 18 23:17:41 2021: * Found USB FET @ COM14 <- Selected +Thu Nov 18 23:17:41 2021: * Initializing interface @ COM14...done +Thu Nov 18 23:17:42 2021: * Checking firmware compatibility: +Thu Nov 18 23:17:42 2021: * FET firmware is up to date. +Thu Nov 18 23:17:42 2021: * Reading FW version...done +Thu Nov 18 23:17:42 2021: * Setting VCC to 3000 mV...done +Thu Nov 18 23:17:42 2021: * Accessing device...done +Thu Nov 18 23:17:42 2021: * Reading device information...done +Thu Nov 18 23:17:42 2021: * Loading file into device...done +Thu Nov 18 23:17:43 2021: * Verifying memory (reverse_me_modified.txt)...done +Thu Nov 18 23:17:44 2021: * +Thu Nov 18 23:17:44 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:44 2021: * Arguments : -n MSP430FG4618 -w reverse_me_modified.txt -v -z [Vcc] +Thu Nov 18 23:17:44 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:44 2021: * Driver : loaded +Thu Nov 18 23:17:44 2021: * Dll Version : 31400000 +Thu Nov 18 23:17:44 2021: * FwVersion : 31200000 +Thu Nov 18 23:17:44 2021: * Interface : TIUSB +Thu Nov 18 23:17:44 2021: * HwVersion : U 3.0 +Thu Nov 18 23:17:44 2021: * JTAG Mode : AUTO +Thu Nov 18 23:17:44 2021: * Device : MSP430FG4618 +Thu Nov 18 23:17:44 2021: * EEM : Level 3, ClockCntrl 2 +Thu Nov 18 23:17:44 2021: * Erase Mode : ERASE_ALL +Thu Nov 18 23:17:44 2021: * Prog.File : reverse_me_modified.txt +Thu Nov 18 23:17:44 2021: * Verified : TRUE +Thu Nov 18 23:17:44 2021: * BSL Unlock : FALSE +Thu Nov 18 23:17:44 2021: * InfoA Access: FALSE +Thu Nov 18 23:17:44 2021: * VCC ON : 3000 mV +Thu Nov 18 23:17:44 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:44 2021: * Starting target code execution...done +Thu Nov 18 23:17:44 2021: * Disconnecting from device...done +Thu Nov 18 23:17:44 2021: * +Thu Nov 18 23:17:44 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:44 2021: * Driver : closed (No error) +Thu Nov 18 23:17:44 2021: * ---------------------------------------------------------------------------- +Thu Nov 18 23:17:44 2021: */ +Fri Nov 19 13:44:24 2021: * -----/|-------------------------------------------------------------------- * +Fri Nov 19 13:44:24 2021: * / |__ * +Fri Nov 19 13:44:24 2021: * /_ / MSP Flasher v1.3.20 * +Fri Nov 19 13:44:24 2021: * | / * +Fri Nov 19 13:44:24 2021: * -----|/-------------------------------------------------------------------- * +Fri Nov 19 13:44:24 2021: * +Fri Nov 19 13:44:24 2021: * Evaluating triggers...done +Fri Nov 19 13:44:24 2021: * Checking for available FET debuggers: +Fri Nov 19 13:44:24 2021: * Found USB FET @ COM16 <- Selected +Fri Nov 19 13:44:24 2021: * Initializing interface @ COM16...done +Fri Nov 19 13:44:25 2021: * Checking firmware compatibility: +Fri Nov 19 13:44:25 2021: * The firmware of your FET is outdated. +Fri Nov 19 13:44:25 2021: - Would you like to update it? (Y/N): Fri Nov 19 13:44:30 2021: y +Fri Nov 19 13:44:30 2021: +********************************************************* +Fri Nov 19 13:44:30 2021: * +Fri Nov 19 13:44:30 2021: * Initializing Update Bootloader. +Fri Nov 19 13:44:30 2021: * Programming new firmware: +Fri Nov 19 13:44:30 2021: Fri Nov 19 13:44:30 2021: * PROGRESS BAR +Fri Nov 19 13:44:38 2021: +* Update was successfully finished. +Fri Nov 19 13:44:38 2021: * +Fri Nov 19 13:44:38 2021: ********************************************************* +Fri Nov 19 13:44:38 2021: +Fri Nov 19 13:44:38 2021: * Exit Update Bootlader and reboot firmware. +Fri Nov 19 13:44:39 2021: * FET firmware is up to date. +Fri Nov 19 13:44:39 2021: * Reading FW version...done +Fri Nov 19 13:44:39 2021: * Setting VCC to 3000 mV...done +Fri Nov 19 13:44:44 2021: * Accessing device...done +Fri Nov 19 13:44:44 2021: * Reading device information...done +Fri Nov 19 13:44:44 2021: * Loading file into device...done +Fri Nov 19 13:44:45 2021: * Verifying memory (reverse_me_corrected.txt)...done +Fri Nov 19 13:44:45 2021: * +Fri Nov 19 13:44:45 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 13:44:45 2021: * Arguments : -n MSP430FG4618 -w reverse_me_corrected.txt -v -z [Vcc] +Fri Nov 19 13:44:45 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 13:44:45 2021: * Driver : loaded +Fri Nov 19 13:44:45 2021: * Dll Version : 31400000 +Fri Nov 19 13:44:45 2021: * FwVersion : 31200000 +Fri Nov 19 13:44:45 2021: * Interface : TIUSB +Fri Nov 19 13:44:45 2021: * HwVersion : U 3.0 +Fri Nov 19 13:44:45 2021: * JTAG Mode : AUTO +Fri Nov 19 13:44:45 2021: * Device : MSP430FG4618 +Fri Nov 19 13:44:45 2021: * EEM : Level 3, ClockCntrl 2 +Fri Nov 19 13:44:45 2021: * Erase Mode : ERASE_ALL +Fri Nov 19 13:44:45 2021: * Prog.File : reverse_me_corrected.txt +Fri Nov 19 13:44:45 2021: * Verified : TRUE +Fri Nov 19 13:44:45 2021: * BSL Unlock : FALSE +Fri Nov 19 13:44:45 2021: * InfoA Access: FALSE +Fri Nov 19 13:44:45 2021: * VCC ON : 3000 mV +Fri Nov 19 13:44:45 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 13:44:45 2021: * Starting target code execution...done +Fri Nov 19 13:44:46 2021: * Disconnecting from device...done +Fri Nov 19 13:44:46 2021: * +Fri Nov 19 13:44:46 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 13:44:46 2021: * Driver : closed (No error) +Fri Nov 19 13:44:46 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 13:44:46 2021: */ +Fri Nov 19 14:09:01 2021: * -----/|-------------------------------------------------------------------- * +Fri Nov 19 14:09:01 2021: * / |__ * +Fri Nov 19 14:09:01 2021: * /_ / MSP Flasher v1.3.20 * +Fri Nov 19 14:09:01 2021: * | / * +Fri Nov 19 14:09:01 2021: * -----|/-------------------------------------------------------------------- * +Fri Nov 19 14:09:01 2021: * +Fri Nov 19 14:09:01 2021: * Evaluating triggers...done +Fri Nov 19 14:09:01 2021: * Checking for available FET debuggers: +Fri Nov 19 14:09:01 2021: * Found USB FET @ COM16 <- Selected +Fri Nov 19 14:09:01 2021: * Initializing interface @ COM16...done +Fri Nov 19 14:09:01 2021: * Checking firmware compatibility: +Fri Nov 19 14:09:01 2021: * FET firmware is up to date. +Fri Nov 19 14:09:01 2021: * Reading FW version...done +Fri Nov 19 14:09:01 2021: * Setting VCC to 3000 mV...done +Fri Nov 19 14:09:02 2021: * Accessing device...done +Fri Nov 19 14:09:02 2021: * Reading device information...done +Fri Nov 19 14:09:02 2021: * Loading file into device...done +Fri Nov 19 14:09:02 2021: * Verifying memory (reverse_me_corrected.txt)...done +Fri Nov 19 14:09:03 2021: * +Fri Nov 19 14:09:03 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:03 2021: * Arguments : -n MSP430FG4618 -w reverse_me_corrected.txt -v -z [Vcc] +Fri Nov 19 14:09:03 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:03 2021: * Driver : loaded +Fri Nov 19 14:09:03 2021: * Dll Version : 31400000 +Fri Nov 19 14:09:03 2021: * FwVersion : 31200000 +Fri Nov 19 14:09:03 2021: * Interface : TIUSB +Fri Nov 19 14:09:03 2021: * HwVersion : U 3.0 +Fri Nov 19 14:09:03 2021: * JTAG Mode : AUTO +Fri Nov 19 14:09:03 2021: * Device : MSP430FG4618 +Fri Nov 19 14:09:03 2021: * EEM : Level 3, ClockCntrl 2 +Fri Nov 19 14:09:03 2021: * Erase Mode : ERASE_ALL +Fri Nov 19 14:09:03 2021: * Prog.File : reverse_me_corrected.txt +Fri Nov 19 14:09:03 2021: * Verified : TRUE +Fri Nov 19 14:09:03 2021: * BSL Unlock : FALSE +Fri Nov 19 14:09:03 2021: * InfoA Access: FALSE +Fri Nov 19 14:09:03 2021: * VCC ON : 3000 mV +Fri Nov 19 14:09:03 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:03 2021: * Starting target code execution...done +Fri Nov 19 14:09:04 2021: * Disconnecting from device...done +Fri Nov 19 14:09:04 2021: * +Fri Nov 19 14:09:04 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:04 2021: * Driver : closed (No error) +Fri Nov 19 14:09:04 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:04 2021: */ +Fri Nov 19 14:09:13 2021: * -----/|-------------------------------------------------------------------- * +Fri Nov 19 14:09:13 2021: * / |__ * +Fri Nov 19 14:09:13 2021: * /_ / MSP Flasher v1.3.20 * +Fri Nov 19 14:09:13 2021: * | / * +Fri Nov 19 14:09:13 2021: * -----|/-------------------------------------------------------------------- * +Fri Nov 19 14:09:13 2021: * +Fri Nov 19 14:09:13 2021: * Evaluating triggers...done +Fri Nov 19 14:09:13 2021: * Checking for available FET debuggers: +Fri Nov 19 14:09:13 2021: * Found USB FET @ COM16 <- Selected +Fri Nov 19 14:09:13 2021: * Initializing interface @ COM16...done +Fri Nov 19 14:09:13 2021: * Checking firmware compatibility: +Fri Nov 19 14:09:13 2021: * FET firmware is up to date. +Fri Nov 19 14:09:13 2021: * Reading FW version...done +Fri Nov 19 14:09:13 2021: * Setting VCC to 3000 mV...done +Fri Nov 19 14:09:13 2021: * Accessing device...done +Fri Nov 19 14:09:13 2021: * Reading device information...done +Fri Nov 19 14:09:13 2021: * Loading file into device...done +Fri Nov 19 14:09:14 2021: * Verifying memory (reverse_me_modified.txt)...done +Fri Nov 19 14:09:15 2021: * +Fri Nov 19 14:09:15 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:15 2021: * Arguments : -n MSP430FG4618 -w reverse_me_modified.txt -v -z [Vcc] +Fri Nov 19 14:09:15 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:15 2021: * Driver : loaded +Fri Nov 19 14:09:15 2021: * Dll Version : 31400000 +Fri Nov 19 14:09:15 2021: * FwVersion : 31200000 +Fri Nov 19 14:09:15 2021: * Interface : TIUSB +Fri Nov 19 14:09:15 2021: * HwVersion : U 3.0 +Fri Nov 19 14:09:15 2021: * JTAG Mode : AUTO +Fri Nov 19 14:09:15 2021: * Device : MSP430FG4618 +Fri Nov 19 14:09:15 2021: * EEM : Level 3, ClockCntrl 2 +Fri Nov 19 14:09:15 2021: * Erase Mode : ERASE_ALL +Fri Nov 19 14:09:15 2021: * Prog.File : reverse_me_modified.txt +Fri Nov 19 14:09:15 2021: * Verified : TRUE +Fri Nov 19 14:09:15 2021: * BSL Unlock : FALSE +Fri Nov 19 14:09:15 2021: * InfoA Access: FALSE +Fri Nov 19 14:09:15 2021: * VCC ON : 3000 mV +Fri Nov 19 14:09:15 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:15 2021: * Starting target code execution...done +Fri Nov 19 14:09:15 2021: * Disconnecting from device...done +Fri Nov 19 14:09:15 2021: * +Fri Nov 19 14:09:15 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:15 2021: * Driver : closed (No error) +Fri Nov 19 14:09:15 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:15 2021: */ +Fri Nov 19 14:09:21 2021: * -----/|-------------------------------------------------------------------- * +Fri Nov 19 14:09:21 2021: * / |__ * +Fri Nov 19 14:09:21 2021: * /_ / MSP Flasher v1.3.20 * +Fri Nov 19 14:09:21 2021: * | / * +Fri Nov 19 14:09:21 2021: * -----|/-------------------------------------------------------------------- * +Fri Nov 19 14:09:21 2021: * +Fri Nov 19 14:09:21 2021: * Evaluating triggers...done +Fri Nov 19 14:09:21 2021: * Checking for available FET debuggers: +Fri Nov 19 14:09:21 2021: * Found USB FET @ COM16 <- Selected +Fri Nov 19 14:09:21 2021: * Initializing interface @ COM16...done +Fri Nov 19 14:09:22 2021: * Checking firmware compatibility: +Fri Nov 19 14:09:22 2021: * FET firmware is up to date. +Fri Nov 19 14:09:22 2021: * Reading FW version...done +Fri Nov 19 14:09:22 2021: * Setting VCC to 3000 mV...done +Fri Nov 19 14:09:22 2021: * Accessing device...done +Fri Nov 19 14:09:22 2021: * Reading device information...done +Fri Nov 19 14:09:22 2021: * Loading file into device...done +Fri Nov 19 14:09:23 2021: * Verifying memory (reverse_me_corrected.txt)...done +Fri Nov 19 14:09:23 2021: * +Fri Nov 19 14:09:23 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:23 2021: * Arguments : -n MSP430FG4618 -w reverse_me_corrected.txt -v -z [Vcc] +Fri Nov 19 14:09:24 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:24 2021: * Driver : loaded +Fri Nov 19 14:09:24 2021: * Dll Version : 31400000 +Fri Nov 19 14:09:24 2021: * FwVersion : 31200000 +Fri Nov 19 14:09:24 2021: * Interface : TIUSB +Fri Nov 19 14:09:24 2021: * HwVersion : U 3.0 +Fri Nov 19 14:09:24 2021: * JTAG Mode : AUTO +Fri Nov 19 14:09:24 2021: * Device : MSP430FG4618 +Fri Nov 19 14:09:24 2021: * EEM : Level 3, ClockCntrl 2 +Fri Nov 19 14:09:24 2021: * Erase Mode : ERASE_ALL +Fri Nov 19 14:09:24 2021: * Prog.File : reverse_me_corrected.txt +Fri Nov 19 14:09:24 2021: * Verified : TRUE +Fri Nov 19 14:09:24 2021: * BSL Unlock : FALSE +Fri Nov 19 14:09:24 2021: * InfoA Access: FALSE +Fri Nov 19 14:09:24 2021: * VCC ON : 3000 mV +Fri Nov 19 14:09:24 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:24 2021: * Starting target code execution...done +Fri Nov 19 14:09:24 2021: * Disconnecting from device...done +Fri Nov 19 14:09:24 2021: * +Fri Nov 19 14:09:24 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:24 2021: * Driver : closed (No error) +Fri Nov 19 14:09:24 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:09:24 2021: */ +Fri Nov 19 14:12:43 2021: * -----/|-------------------------------------------------------------------- * +Fri Nov 19 14:12:43 2021: * / |__ * +Fri Nov 19 14:12:43 2021: * /_ / MSP Flasher v1.3.20 * +Fri Nov 19 14:12:43 2021: * | / * +Fri Nov 19 14:12:43 2021: * -----|/-------------------------------------------------------------------- * +Fri Nov 19 14:12:43 2021: * +Fri Nov 19 14:12:43 2021: * Evaluating triggers...done +Fri Nov 19 14:12:43 2021: * Checking for available FET debuggers: +Fri Nov 19 14:12:43 2021: * Found USB FET @ COM16 <- Selected +Fri Nov 19 14:12:43 2021: * Initializing interface @ COM16...done +Fri Nov 19 14:12:43 2021: * Checking firmware compatibility: +Fri Nov 19 14:12:43 2021: * FET firmware is up to date. +Fri Nov 19 14:12:43 2021: * Reading FW version...done +Fri Nov 19 14:12:43 2021: * Setting VCC to 3000 mV...done +Fri Nov 19 14:12:44 2021: * Accessing device...done +Fri Nov 19 14:12:44 2021: * Reading device information...done +Fri Nov 19 14:12:44 2021: * Loading file into device...done +Fri Nov 19 14:12:45 2021: * Verifying memory (reverse_me_corrected.txt)...done +Fri Nov 19 14:12:45 2021: * +Fri Nov 19 14:12:45 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:12:45 2021: * Arguments : -n MSP430FG4618 -w reverse_me_corrected.txt -v -z [Vcc] +Fri Nov 19 14:12:45 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:12:45 2021: * Driver : loaded +Fri Nov 19 14:12:45 2021: * Dll Version : 31400000 +Fri Nov 19 14:12:45 2021: * FwVersion : 31200000 +Fri Nov 19 14:12:45 2021: * Interface : TIUSB +Fri Nov 19 14:12:45 2021: * HwVersion : U 3.0 +Fri Nov 19 14:12:45 2021: * JTAG Mode : AUTO +Fri Nov 19 14:12:45 2021: * Device : MSP430FG4618 +Fri Nov 19 14:12:45 2021: * EEM : Level 3, ClockCntrl 2 +Fri Nov 19 14:12:45 2021: * Erase Mode : ERASE_ALL +Fri Nov 19 14:12:45 2021: * Prog.File : reverse_me_corrected.txt +Fri Nov 19 14:12:45 2021: * Verified : TRUE +Fri Nov 19 14:12:45 2021: * BSL Unlock : FALSE +Fri Nov 19 14:12:45 2021: * InfoA Access: FALSE +Fri Nov 19 14:12:45 2021: * VCC ON : 3000 mV +Fri Nov 19 14:12:45 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:12:45 2021: * Starting target code execution...done +Fri Nov 19 14:12:46 2021: * Disconnecting from device...done +Fri Nov 19 14:12:46 2021: * +Fri Nov 19 14:12:46 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:12:46 2021: * Driver : closed (No error) +Fri Nov 19 14:12:46 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:12:46 2021: */ +Fri Nov 19 14:16:51 2021: * -----/|-------------------------------------------------------------------- * +Fri Nov 19 14:16:51 2021: * / |__ * +Fri Nov 19 14:16:51 2021: * /_ / MSP Flasher v1.3.20 * +Fri Nov 19 14:16:51 2021: * | / * +Fri Nov 19 14:16:51 2021: * -----|/-------------------------------------------------------------------- * +Fri Nov 19 14:16:51 2021: * +Fri Nov 19 14:16:51 2021: * Evaluating triggers...done +Fri Nov 19 14:16:51 2021: * Checking for available FET debuggers: +Fri Nov 19 14:16:52 2021: * Found USB FET @ COM16 <- Selected +Fri Nov 19 14:16:52 2021: * Initializing interface @ COM16...done +Fri Nov 19 14:16:52 2021: * Checking firmware compatibility: +Fri Nov 19 14:16:52 2021: * FET firmware is up to date. +Fri Nov 19 14:16:52 2021: * Reading FW version...done +Fri Nov 19 14:16:52 2021: * Setting VCC to 3000 mV...done +Fri Nov 19 14:16:52 2021: * Accessing device...done +Fri Nov 19 14:16:52 2021: * Reading device information...done +Fri Nov 19 14:16:52 2021: * Loading file into device...done +Fri Nov 19 14:16:53 2021: * Verifying memory (reverse_me_corrected.txt)...done +Fri Nov 19 14:16:54 2021: * +Fri Nov 19 14:16:54 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:16:54 2021: * Arguments : -n MSP430FG4618 -w reverse_me_corrected.txt -v -z [Vcc] +Fri Nov 19 14:16:54 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:16:54 2021: * Driver : loaded +Fri Nov 19 14:16:54 2021: * Dll Version : 31400000 +Fri Nov 19 14:16:54 2021: * FwVersion : 31200000 +Fri Nov 19 14:16:54 2021: * Interface : TIUSB +Fri Nov 19 14:16:54 2021: * HwVersion : U 3.0 +Fri Nov 19 14:16:54 2021: * JTAG Mode : AUTO +Fri Nov 19 14:16:54 2021: * Device : MSP430FG4618 +Fri Nov 19 14:16:54 2021: * EEM : Level 3, ClockCntrl 2 +Fri Nov 19 14:16:54 2021: * Erase Mode : ERASE_ALL +Fri Nov 19 14:16:54 2021: * Prog.File : reverse_me_corrected.txt +Fri Nov 19 14:16:54 2021: * Verified : TRUE +Fri Nov 19 14:16:54 2021: * BSL Unlock : FALSE +Fri Nov 19 14:16:54 2021: * InfoA Access: FALSE +Fri Nov 19 14:16:54 2021: * VCC ON : 3000 mV +Fri Nov 19 14:16:54 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:16:54 2021: * Starting target code execution...done +Fri Nov 19 14:16:54 2021: * Disconnecting from device...done +Fri Nov 19 14:16:54 2021: * +Fri Nov 19 14:16:54 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:16:54 2021: * Driver : closed (No error) +Fri Nov 19 14:16:54 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:16:54 2021: */ +Fri Nov 19 14:17:17 2021: * -----/|-------------------------------------------------------------------- * +Fri Nov 19 14:17:17 2021: * / |__ * +Fri Nov 19 14:17:17 2021: * /_ / MSP Flasher v1.3.20 * +Fri Nov 19 14:17:17 2021: * | / * +Fri Nov 19 14:17:17 2021: * -----|/-------------------------------------------------------------------- * +Fri Nov 19 14:17:17 2021: * +Fri Nov 19 14:17:17 2021: * Evaluating triggers...done +Fri Nov 19 14:17:17 2021: * Checking for available FET debuggers: +Fri Nov 19 14:17:17 2021: * Found USB FET @ COM16 <- Selected +Fri Nov 19 14:17:17 2021: * Initializing interface @ COM16...done +Fri Nov 19 14:17:18 2021: * Checking firmware compatibility: +Fri Nov 19 14:17:18 2021: * FET firmware is up to date. +Fri Nov 19 14:17:18 2021: * Reading FW version...done +Fri Nov 19 14:17:18 2021: * Setting VCC to 3000 mV...done +Fri Nov 19 14:17:18 2021: * Accessing device...done +Fri Nov 19 14:17:18 2021: * Reading device information...done +Fri Nov 19 14:17:18 2021: * Loading file into device...done +Fri Nov 19 14:17:19 2021: * Verifying memory (reverse_me_modified.txt)...done +Fri Nov 19 14:17:20 2021: * +Fri Nov 19 14:17:20 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:17:20 2021: * Arguments : -n MSP430FG4618 -w reverse_me_modified.txt -v -z [Vcc] +Fri Nov 19 14:17:20 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:17:20 2021: * Driver : loaded +Fri Nov 19 14:17:20 2021: * Dll Version : 31400000 +Fri Nov 19 14:17:20 2021: * FwVersion : 31200000 +Fri Nov 19 14:17:20 2021: * Interface : TIUSB +Fri Nov 19 14:17:20 2021: * HwVersion : U 3.0 +Fri Nov 19 14:17:20 2021: * JTAG Mode : AUTO +Fri Nov 19 14:17:20 2021: * Device : MSP430FG4618 +Fri Nov 19 14:17:20 2021: * EEM : Level 3, ClockCntrl 2 +Fri Nov 19 14:17:20 2021: * Erase Mode : ERASE_ALL +Fri Nov 19 14:17:20 2021: * Prog.File : reverse_me_modified.txt +Fri Nov 19 14:17:20 2021: * Verified : TRUE +Fri Nov 19 14:17:20 2021: * BSL Unlock : FALSE +Fri Nov 19 14:17:20 2021: * InfoA Access: FALSE +Fri Nov 19 14:17:20 2021: * VCC ON : 3000 mV +Fri Nov 19 14:17:20 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:17:20 2021: * Starting target code execution...done +Fri Nov 19 14:17:20 2021: * Disconnecting from device...done +Fri Nov 19 14:17:20 2021: * +Fri Nov 19 14:17:20 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:17:20 2021: * Driver : closed (No error) +Fri Nov 19 14:17:20 2021: * ---------------------------------------------------------------------------- +Fri Nov 19 14:17:20 2021: */ diff --git a/CPE325/Lab11/RetrievedHEX.txt b/CPE325/Lab11/RetrievedHEX.txt new file mode 100644 index 0000000..2f1d7cc --- /dev/null +++ b/CPE325/Lab11/RetrievedHEX.txt @@ -0,0 +1,16 @@ +@3100 +B2 40 80 5A 20 01 E2 D2 2A 00 E2 D3 2A 00 E2 C2 +29 00 E2 C3 29 00 D2 C3 22 00 E2 C3 22 00 E2 B3 +20 00 FD 23 0D 12 3D 40 1D 03 1D 83 FE 23 3D 41 +00 3C E2 B3 20 00 F3 23 E2 B3 20 00 FD 23 0D 12 +3D 40 1D 03 1D 83 FE 23 3D 41 00 3C E2 B3 20 00 +F3 23 D2 B3 20 00 FD 23 0D 12 3D 40 1D 03 1D 83 +FE 23 3D 41 00 3C D2 B3 20 00 F3 23 E2 E2 29 00 +0D 12 0E 12 3D 40 80 8B 0E 43 1D 83 0E 73 FD 23 +0D 93 FB 23 3E 41 3D 41 00 3C 03 43 E2 E3 29 00 +0D 12 0E 12 3D 40 44 28 1E 43 1D 83 0E 73 FD 23 +0D 93 FB 23 3E 41 3D 41 00 3C 03 43 DF 3F 31 40 +00 31 B0 12 C8 31 0C 43 B0 12 00 31 1C 43 B0 12 +C2 31 03 43 FF 3F 03 43 1C 43 30 41 32 D0 10 00 +FD 3F 03 43 +q diff --git a/CPE325/Lab11/RetrievedHEX_Stripped.txt b/CPE325/Lab11/RetrievedHEX_Stripped.txt new file mode 100644 index 0000000..2f1d7cc --- /dev/null +++ b/CPE325/Lab11/RetrievedHEX_Stripped.txt @@ -0,0 +1,16 @@ +@3100 +B2 40 80 5A 20 01 E2 D2 2A 00 E2 D3 2A 00 E2 C2 +29 00 E2 C3 29 00 D2 C3 22 00 E2 C3 22 00 E2 B3 +20 00 FD 23 0D 12 3D 40 1D 03 1D 83 FE 23 3D 41 +00 3C E2 B3 20 00 F3 23 E2 B3 20 00 FD 23 0D 12 +3D 40 1D 03 1D 83 FE 23 3D 41 00 3C E2 B3 20 00 +F3 23 D2 B3 20 00 FD 23 0D 12 3D 40 1D 03 1D 83 +FE 23 3D 41 00 3C D2 B3 20 00 F3 23 E2 E2 29 00 +0D 12 0E 12 3D 40 80 8B 0E 43 1D 83 0E 73 FD 23 +0D 93 FB 23 3E 41 3D 41 00 3C 03 43 E2 E3 29 00 +0D 12 0E 12 3D 40 44 28 1E 43 1D 83 0E 73 FD 23 +0D 93 FB 23 3E 41 3D 41 00 3C 03 43 DF 3F 31 40 +00 31 B0 12 C8 31 0C 43 B0 12 00 31 1C 43 B0 12 +C2 31 03 43 FF 3F 03 43 1C 43 30 41 32 D0 10 00 +FD 3F 03 43 +q diff --git a/CPE325/Lab11/ReverseMe.txt b/CPE325/Lab11/ReverseMe.txt new file mode 100644 index 0000000..2ddc3ca Binary files /dev/null and b/CPE325/Lab11/ReverseMe.txt differ diff --git a/CPE325/Lab11/ReverseMe2.txt b/CPE325/Lab11/ReverseMe2.txt new file mode 100644 index 0000000..fd40c0c Binary files /dev/null and b/CPE325/Lab11/ReverseMe2.txt differ diff --git a/CPE325/Lab11/ReverseMeModifed.txt b/CPE325/Lab11/ReverseMeModifed.txt new file mode 100644 index 0000000..9fd971b Binary files /dev/null and b/CPE325/Lab11/ReverseMeModifed.txt differ diff --git a/CPE325/Lab11/ReverseMe_Modified.txt b/CPE325/Lab11/ReverseMe_Modified.txt new file mode 100644 index 0000000..3dc7a08 Binary files /dev/null and b/CPE325/Lab11/ReverseMe_Modified.txt differ diff --git a/CPE325/Lab11/crack_me.out b/CPE325/Lab11/crack_me.out new file mode 100644 index 0000000..036cb89 Binary files /dev/null and b/CPE325/Lab11/crack_me.out differ diff --git a/CPE325/Lab11/crack_me.txt b/CPE325/Lab11/crack_me.txt new file mode 100644 index 0000000..ed2e765 Binary files /dev/null and b/CPE325/Lab11/crack_me.txt differ diff --git a/CPE325/Lab11/disassembly.txt b/CPE325/Lab11/disassembly.txt new file mode 100644 index 0000000..85814e6 Binary files /dev/null and b/CPE325/Lab11/disassembly.txt differ diff --git a/CPE325/Lab11/lnk_msp430fg4618.cmd b/CPE325/Lab11/lnk_msp430fg4618.cmd new file mode 100755 index 0000000..557b664 --- /dev/null +++ b/CPE325/Lab11/lnk_msp430fg4618.cmd @@ -0,0 +1,184 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************************/ +/* lnk_msp430fg4618.cmd - LINKER COMMAND FILE FOR LINKING MSP430FG4618 PROGRAMS */ +/* */ +/* Usage: lnk430 -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/Lab11/reverse_me_corrected.txt b/CPE325/Lab11/reverse_me_corrected.txt new file mode 100644 index 0000000..6266189 --- /dev/null +++ b/CPE325/Lab11/reverse_me_corrected.txt @@ -0,0 +1,22 @@ +@3100 +B2 40 80 5A 20 01 E2 D2 2A 00 E2 D3 2A 00 E2 C2 +29 00 E2 C3 29 00 D2 C3 22 00 E2 C3 22 00 E2 B3 +20 00 FD 23 0D 12 3D 40 1D 03 1D 83 FE 23 3D 41 +00 3C E2 B3 20 00 F3 23 E2 B3 20 00 FD 23 0D 12 +3D 40 1D 03 1D 83 FE 23 3D 41 00 3C E2 B3 20 00 +F3 23 D2 B3 20 00 FD 23 0D 12 3D 40 1D 03 1D 83 +FE 23 3D 41 00 3C D2 B3 20 00 F3 23 E2 E2 29 00 +0D 12 0E 12 3D 40 80 8B 0E 43 1D 83 0E 73 FD 23 +0D 93 FB 23 3E 41 3D 41 00 3C 03 43 E2 E3 29 00 +0D 12 0E 12 3D 40 44 28 1E 43 1D 83 0E 73 FD 23 +0D 93 FB 23 3E 41 3D 41 00 3C 03 43 DF 3F 31 40 +00 31 B0 12 C8 31 0C 43 B0 12 00 31 1C 43 B0 12 +C2 31 03 43 FF 3F 03 43 1C 43 30 41 32 D0 10 00 +FD 3F 03 43 +@ffbe +FF FF +@ffdc +CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 +CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 +CC 31 AE 31 +q diff --git a/CPE325/Lab11/reverse_me_modified.txt b/CPE325/Lab11/reverse_me_modified.txt new file mode 100644 index 0000000..7968ed3 --- /dev/null +++ b/CPE325/Lab11/reverse_me_modified.txt @@ -0,0 +1,22 @@ +@3100 +B2 40 80 5A 20 01 E2 D2 2A 00 E2 D3 2A 00 E2 C2 +29 00 E2 D3 29 00 D2 C3 22 00 E2 C3 22 00 E2 B3 +20 00 FD 23 0D 12 3D 40 1D 03 1D 83 FE 23 3D 41 +00 3C E2 B3 20 00 F3 23 E2 B3 20 00 FD 23 0D 12 +3D 40 1D 03 1D 83 FE 23 3D 41 00 3C E2 B3 20 00 +F3 23 D2 B3 20 00 FD 23 0D 12 3D 40 1D 03 1D 83 +FE 23 3D 41 00 3C D2 B3 20 00 F3 23 E2 E2 29 00 +0D 12 0E 12 3D 40 80 8B 0E 43 1D 83 0E 73 FD 23 +0D 93 FB 23 3E 41 3D 41 00 3C 03 43 E2 E3 29 00 +0D 12 0E 12 3D 40 44 28 1E 43 1D 83 0E 73 FD 23 +0D 93 FB 23 3E 41 3D 41 00 3C 03 43 DF 3F 31 40 +00 31 B0 12 C8 31 0C 43 B0 12 00 31 1C 43 B0 12 +C2 31 03 43 FF 3F 03 43 1C 43 30 41 32 D0 10 00 +FD 3F 03 43 +@ffbe +FF FF +@ffdc +CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 +CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 CC 31 +CC 31 AE 31 +q diff --git a/CPE325/Lab11/targetConfigs/MSP430FG4618.ccxml b/CPE325/Lab11/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/Lab11/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab11/targetConfigs/readme.txt b/CPE325/Lab11/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab11/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab1_Problem1/Debug/Lab1_Problem1.map b/CPE325/Lab1_Problem1/Debug/Lab1_Problem1.map new file mode 100644 index 0000000..78a907a --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/Lab1_Problem1.map @@ -0,0 +1,2440 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Aug 27 14:28:11 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 0000897e + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 00000494 00001b6c RWIX + FLASH 00004400 0000bb80 000048a2 000072de RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 0000264c 000000fe UNINITIALIZED + 0000264c 00000078 rts430_eabi.lib : defs.c.obj (.data:_ftable) + 000026c4 0000004e : host_device.c.obj (.data:_device) + 00002712 00000028 : host_device.c.obj (.data:_stream) + 0000273a 00000002 : exit_gvars.c.obj (.data:__TI_cleanup_ptr) + 0000273c 00000002 : exit_gvars.c.obj (.data:__TI_dtors_ptr) + 0000273e 00000002 : _lock.c.obj (.data:_lock) + 00002740 00000002 : _lock.c.obj (.data:_unlock) + 00002742 00000002 : defs.c.obj (.data) + 00002744 00000002 : errno.c.obj (.data) + 00002746 00000002 : exit.c.obj (.data) + 00002748 00000002 : memory.c.obj (.data) + +.bss 0 0000274a 000000aa UNINITIALIZED + 0000274a 000000a0 (.common:__TI_tmpnams) + 000027ea 00000008 (.common:parmbuf) + 000027f2 00000002 rts430_eabi.lib : memory.c.obj (.bss) + +.sysmem 0 00002400 0000012c UNINITIALIZED + 00002400 00000008 rts430_eabi.lib : memory.c.obj (.sysmem) + 00002408 00000124 --HOLE-- + +.cio 0 0000252c 00000120 UNINITIALIZED + 0000252c 00000120 rts430_eabi.lib : trgmsg.c.obj (.cio) + +.stack 0 00004360 000000a0 UNINITIALIZED + 00004360 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 00004362 0000009e --HOLE-- + +.text 0 00004400 00004708 + 00004400 00000736 rts430_eabi.lib : addd.c.obj (.text:__mspabi_addd) + 00004b36 00000478 : frcdivd.c.obj (.text:__TI_frcdivd) + 00004fae 00000360 : div64u.c.obj (.text:__mspabi_divull) + 0000530e 000002c0 : mpyd.c.obj (.text:__mspabi_mpyd) + 000055ce 00000288 : _printfi.c.obj (.text:__TI_printfi) + 00005856 0000026e : _printfi.c.obj (.text:_pproc_fgea) + 00005ac4 00000252 : _printfi.c.obj (.text:_setfield) + 00005d16 00000244 : _printfi.c.obj (.text:acvt) + 00005f5a 00000238 : divd.c.obj (.text:__mspabi_divd) + 00006192 000001ec : _printfi.c.obj (.text:_getarg_diouxp) + 0000637e 000001de : _printfi.c.obj (.text:ecvt) + 0000655c 000001c4 : _printfi.c.obj (.text:fcvt) + 00006720 000001a6 : _printfi.c.obj (.text:_pconv_e) + 000068c6 00000174 : _printfi.c.obj (.text:_pconv_a) + 00006a3a 00000172 : frcmpyd.c.obj (.text:__TI_frcmpyd) + 00006bac 0000016a : s_scalbn.c.obj (.text:scalbn) + 00006d16 0000014c : _printfi.c.obj (.text:_pproc_diouxp) + 00006e62 0000012e : _printfi.c.obj (.text:_ltostr) + 00006f90 000000f8 : _printfi.c.obj (.text:_pconv_g) + 00007088 000000f6 : memory.c.obj (.text:aligned_alloc) + 0000717e 000000ea : fputs.c.obj (.text:fputs) + 00007268 000000e0 : _printfi.c.obj (.text:_pproc_fwp) + 00007348 000000dc : cmpd.c.obj (.text:__mspabi_cmpd) + 00007424 000000d2 : memory.c.obj (.text:free) + 000074f6 000000d0 : setvbuf.c.obj (.text:setvbuf) + 000075c6 000000c4 : _printfi.c.obj (.text:_pproc_wstr) + 0000768a 000000b0 : s_frexp.c.obj (.text:frexp) + 0000773a 000000ac : fltlid.c.obj (.text:__mspabi_fltlid) + 000077e6 000000ac : _printfi.c.obj (.text:_pproc_str) + 00007892 00000092 : _printfi.c.obj (.text:_mcpy) + 00007924 00000090 : fputc.c.obj (.text:fputc) + 000079b4 0000008e : _printfi.c.obj (.text:_ecpy) + 00007a42 00000088 : hostlseek.c.obj (.text:HOSTlseek) + 00007aca 00000084 : _ltoa.c.obj (.text:__TI_ltoa) + 00007b4e 0000007c : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00007bca 0000007a : _io_perm.c.obj (.text:__TI_wrt_ok) + 00007c44 0000007a : _printfi.c.obj (.text:_pconv_f) + 00007cbe 00000072 : fclose.c.obj (.text:__TI_closefile) + 00007d30 00000072 : fixdli.c.obj (.text:__mspabi_fixdli) + 00007da2 00000070 : fseek.c.obj (.text:fseek) + 00007e12 0000006a : hostrename.c.obj (.text:HOSTrename) + 00007e7c 00000068 : memory.c.obj (.text:split) + 00007ee4 00000066 : hostopen.c.obj (.text:HOSTopen) + 00007f4a 00000062 : hostwrite.c.obj (.text:HOSTwrite) + 00007fac 00000062 : fflush.c.obj (.text:__TI_doflush) + 0000800e 00000060 : hostread.c.obj (.text:HOSTread) + 0000806e 0000005e : mult64_f5hw.asm.obj (.text:__mpyll) + 000080cc 0000005c : lsr32.asm.obj (.text:l_lsr_const) + 00008128 00000058 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 00008180 00000058 : getdevice.c.obj (.text:getdevice) + 000081d8 00000058 : div32u.asm.obj (.text) + 00008230 00000052 : atoi.c.obj (.text:atoi) + 00008282 00000052 P1a.obj (.text:main) + 000082d4 0000004e rts430_eabi.lib : _printfi.c.obj (.text:_fcpy) + 00008322 0000004c : lsr16.asm.obj (.text) + 0000836e 0000004a : asr64.c.obj (.text:__mspabi_srall) + 000083b8 0000004a : close.c.obj (.text:close) + 00008402 00000046 : lsr64.c.obj (.text:__mspabi_srlll) + 00008448 00000044 : hostclose.c.obj (.text:HOSTclose) + 0000848c 00000044 : lsl64.c.obj (.text:__mspabi_sllll) + 000084d0 00000044 : exit.c.obj (.text:exit) + 00008514 00000040 : hostunlink.c.obj (.text:HOSTunlink) + 00008554 00000040 : div32s.asm.obj (.text) + 00008594 0000003e : asr32.asm.obj (.text:l_asr_const) + 000085d2 0000003e : lsl32.asm.obj (.text:l_lsl_const) + 00008610 0000003c : printf.c.obj (.text:printf) + 0000864c 0000003a P1a.obj (.text:prod) + 00008686 00000034 rts430_eabi.lib : fopen.c.obj (.text:__TI_cleanup) + 000086ba 00000034 : getdevice.c.obj (.text:finddevice) + 000086ee 0000002e : trgmsg.c.obj (.text:__TI_writemsg) + 0000871c 0000002e : subd.c.obj (.text:__mspabi_subd) + 0000874a 0000002e : s_copysign.c.obj (.text:copysign) + 00008778 0000002c : trgmsg.c.obj (.text:__TI_readmsg) + 000087a4 0000002c : asr16.asm.obj (.text) + 000087d0 0000002c : lsl16.asm.obj (.text) + 000087fc 0000002c : strncpy.c.obj (.text:strncpy) + 00008828 0000002a : negd.c.obj (.text:__mspabi_negd) + 00008852 00000028 : mult3264_f5hw.asm.obj (.text:__mpyull) + 0000887a 00000028 : fixdi.c.obj (.text:__mspabi_fixdi) + 000088a2 00000028 : memory.c.obj (.text:free_list_insert) + 000088ca 00000028 : unlink.c.obj (.text:unlink) + 000088f2 00000026 : lseek.c.obj (.text:lseek) + 00008918 00000024 : write.c.obj (.text:write) + 0000893c 00000022 : memccpy.c.obj (.text:memccpy) + 0000895e 00000020 : mult32_f5hw.asm.obj (.text) + 0000897e 0000001c : boot.c.obj (.text:_c_int00_noargs) + 0000899a 0000001c : memory.c.obj (.text:free_list_remove) + 000089b6 0000001a : strchr.c.obj (.text:strchr) + 000089d0 00000018 : strcmp.c.obj (.text:strcmp) + 000089e8 00000016 : div16u.asm.obj (.text) + 000089fe 00000014 : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset:__TI_zero_init_nomemset) + 00008a12 00000014 : memchr.c.obj (.text:memchr) + 00008a26 00000014 : memset.c.obj (.text:memset) + 00008a3a 00000014 : mult16_f5hw.asm.obj (.text) + 00008a4e 00000014 : wcslen.c.obj (.text:wcslen) + 00008a62 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00008a74 00000012 : lsr32.asm.obj (.text:l_lsr) + 00008a86 00000012 : memcpy.c.obj (.text:memcpy) + 00008a98 00000010 : epilog.asm.obj (.text) + 00008aa8 00000010 : strcpy.c.obj (.text:strcpy) + 00008ab8 0000000e : strlen.c.obj (.text:strlen) + 00008ac6 0000000c : fltid.c.obj (.text:__mspabi_fltid) + 00008ad2 0000000c : toupper.c.obj (.text:toupper) + 00008ade 0000000a : abs.c.obj (.text:abs) + 00008ae8 00000008 : memory.c.obj (.text:malloc) + 00008af0 00000006 : printf.c.obj (.text:_outc) + 00008af6 00000006 : exit.c.obj (.text:abort) + 00008afc 00000004 : printf.c.obj (.text:_outs) + 00008b00 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00008b04 00000002 : _lock.c.obj (.text:_nop) + 00008b06 00000002 : startup.c.obj (.text:_system_post_cinit) + +.const 0 00008b08 0000013c + 00008b08 00000101 rts430_eabi.lib : ctype.c.obj (.const:.string:_ctypes_) + 00008c09 00000001 --HOLE-- [fill = 0] + 00008c0a 00000026 : _printfi.c.obj (.const:.string) + 00008c30 00000014 P1a.obj (.const:.string) + +.text:_isr +* 0 00008c44 00000008 + 00008c44 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00008c4c 00000056 + 00008c4c 00000044 (.cinit..data.load) [load image, compression = lzss] + 00008c90 00000006 (__TI_handler_table) + 00008c96 00000004 (.cinit..bss.load) [load image, compression = zero_init] + 00008c9a 00000008 (__TI_cinit_table) + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + P1a.obj 140 20 0 + +--+----------------------------+-------+---------+---------+ + Total: 140 20 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + _printfi.c.obj 6622 38 0 + addd.c.obj 1846 0 0 + frcdivd.c.obj 1144 0 0 + div64u.c.obj 864 0 0 + mpyd.c.obj 704 0 0 + memory.c.obj 636 0 4 + divd.c.obj 568 0 0 + trgmsg.c.obj 90 0 288 + frcmpyd.c.obj 370 0 0 + s_scalbn.c.obj 362 0 0 + defs.c.obj 0 0 282 + ctype.c.obj 0 257 0 + fputs.c.obj 234 0 0 + cmpd.c.obj 220 0 0 + setvbuf.c.obj 208 0 0 + s_frexp.c.obj 176 0 0 + fltlid.c.obj 172 0 0 + fputc.c.obj 144 0 0 + getdevice.c.obj 140 0 0 + hostlseek.c.obj 136 0 0 + _ltoa.c.obj 132 0 0 + copy_decompress_lzss.c.obj 124 0 0 + _io_perm.c.obj 122 0 0 + host_device.c.obj 0 0 118 + fclose.c.obj 114 0 0 + fixdli.c.obj 114 0 0 + fseek.c.obj 112 0 0 + hostopen.c.obj 102 0 8 + lsr32.asm.obj 110 0 0 + hostrename.c.obj 106 0 0 + fflush.c.obj 98 0 0 + hostwrite.c.obj 98 0 0 + hostread.c.obj 96 0 0 + mult64_f5hw.asm.obj 94 0 0 + autoinit.c.obj 88 0 0 + div32u.asm.obj 88 0 0 + atoi.c.obj 82 0 0 + exit.c.obj 74 0 2 + lsr16.asm.obj 76 0 0 + asr64.c.obj 74 0 0 + close.c.obj 74 0 0 + lsr64.c.obj 70 0 0 + printf.c.obj 70 0 0 + hostclose.c.obj 68 0 0 + lsl64.c.obj 68 0 0 + div32s.asm.obj 64 0 0 + hostunlink.c.obj 64 0 0 + asr32.asm.obj 62 0 0 + lsl32.asm.obj 62 0 0 + fopen.c.obj 52 0 0 + s_copysign.c.obj 46 0 0 + subd.c.obj 46 0 0 + asr16.asm.obj 44 0 0 + lsl16.asm.obj 44 0 0 + strncpy.c.obj 44 0 0 + negd.c.obj 42 0 0 + fixdi.c.obj 40 0 0 + mult3264_f5hw.asm.obj 40 0 0 + unlink.c.obj 40 0 0 + lseek.c.obj 38 0 0 + write.c.obj 36 0 0 + memccpy.c.obj 34 0 0 + mult32_f5hw.asm.obj 32 0 0 + boot.c.obj 28 2 0 + strchr.c.obj 26 0 0 + strcmp.c.obj 24 0 0 + div16u.asm.obj 22 0 0 + copy_zero_init.c.obj 20 0 0 + memchr.c.obj 20 0 0 + memset.c.obj 20 0 0 + mult16_f5hw.asm.obj 20 0 0 + wcslen.c.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + memcpy.c.obj 18 0 0 + epilog.asm.obj 16 0 0 + strcpy.c.obj 16 0 0 + strlen.c.obj 14 0 0 + fltid.c.obj 12 0 0 + toupper.c.obj 12 0 0 + abs.c.obj 10 0 0 + isr_trap.asm.obj 8 0 0 + _lock.c.obj 2 0 4 + exit_gvars.c.obj 0 0 4 + pre_init.c.obj 4 0 0 + errno.c.obj 0 0 2 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 18052 341 712 + + Heap: 0 0 300 + Stack: 0 0 160 + Linker Generated: 0 86 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 18192 447 1172 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00008c9a records: 2, size/record: 4, table size: 8 + .data: load addr=00008c4c, load size=00000044 bytes, run addr=0000264c, run size=000000fe bytes, compression=lzss + .bss: load addr=00008c96, load size=00000004 bytes, run addr=0000274a, run size=000000aa bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 00008c90 records: 3, size/record: 2, table size: 6 + index: 0, handler: __TI_zero_init + index: 1, handler: __TI_decompress_lzss + index: 2, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +00008af6 C$$EXIT +00008718 C$$IO$$ +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +00008448 HOSTclose +00007a42 HOSTlseek +00007ee4 HOSTopen +0000800e HOSTread +00007e12 HOSTrename +00008514 HOSTunlink +00007f4a HOSTwrite +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +00000902 USBCNF +00000903 USBCNF_H +00000902 USBCNF_L +0000093c USBCTL +0000093a USBFN +0000093b USBFN_H +0000093a USBFN_L +0000093f USBFUNADR +0000093d USBIE +00002378 USBIEP0BUF +000023c9 USBIEPBBAX_1 +000023d1 USBIEPBBAX_2 +000023d9 USBIEPBBAX_3 +000023e1 USBIEPBBAX_4 +000023e9 USBIEPBBAX_5 +000023f1 USBIEPBBAX_6 +000023f9 USBIEPBBAX_7 +000023cd USBIEPBBAY_1 +000023d5 USBIEPBBAY_2 +000023dd USBIEPBBAY_3 +000023e5 USBIEPBBAY_4 +000023ed USBIEPBBAY_5 +000023f5 USBIEPBBAY_6 +000023fd USBIEPBBAY_7 +000023ca USBIEPBCTX_1 +000023d2 USBIEPBCTX_2 +000023da USBIEPBCTX_3 +000023e2 USBIEPBCTX_4 +000023ea USBIEPBCTX_5 +000023f2 USBIEPBCTX_6 +000023fa USBIEPBCTX_7 +000023ce USBIEPBCTY_1 +000023d6 USBIEPBCTY_2 +000023de USBIEPBCTY_3 +000023e6 USBIEPBCTY_4 +000023ee USBIEPBCTY_5 +000023f6 USBIEPBCTY_6 +000023fe USBIEPBCTY_7 +00000920 USBIEPCNF_0 +000023c8 USBIEPCNF_1 +000023d0 USBIEPCNF_2 +000023d8 USBIEPCNF_3 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USBOEPBCTY_2 +0000239e USBOEPBCTY_3 +000023a6 USBOEPBCTY_4 +000023ae USBOEPBCTY_5 +000023b6 USBOEPBCTY_6 +000023be USBOEPBCTY_7 +00000922 USBOEPCNF_0 +00002388 USBOEPCNF_1 +00002390 USBOEPCNF_2 +00002398 USBOEPCNF_3 +000023a0 USBOEPCNF_4 +000023a8 USBOEPCNF_5 +000023b0 USBOEPCNF_6 +000023b8 USBOEPCNF_7 +00000923 USBOEPCNT_0 +0000092f USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +0000252c _CIOBUF_ +00004400 __STACK_END +000000a0 __STACK_SIZE +0000012c __SYSMEM_SIZE +00008c9a __TI_CINIT_Base +00008ca2 __TI_CINIT_Limit +00008c90 __TI_Handler_Table_Base +00008c96 __TI_Handler_Table_Limit +00008c44 __TI_ISR_TRAP +00008128 __TI_auto_init_nobinit_nopinit_hold_wdt +00008686 __TI_cleanup +0000273a __TI_cleanup_ptr +00007cbe __TI_closefile +00007b4e __TI_decompress_lzss +00008a62 __TI_decompress_none +00007fac __TI_doflush +0000273c __TI_dtors_ptr +00002746 __TI_enable_exit_profile_output +00004b36 __TI_frcdivd +00006a3a __TI_frcmpyd +00002742 __TI_ft_end +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 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__mspabi_mpyl_f5hw +0000806e __mspabi_mpyll_f5hw +00008852 __mspabi_mpyull_f5hw +00008828 __mspabi_negd +00008554 __mspabi_remli +000089e8 __mspabi_remu +000081d8 __mspabi_remul +000087d0 __mspabi_slli +000087f8 __mspabi_slli_1 +000087e6 __mspabi_slli_10 +000087e4 __mspabi_slli_11 +000087e2 __mspabi_slli_12 +000087e0 __mspabi_slli_13 +000087de __mspabi_slli_14 +000087dc __mspabi_slli_15 +000087f6 __mspabi_slli_2 +000087f4 __mspabi_slli_3 +000087f2 __mspabi_slli_4 +000087f0 __mspabi_slli_5 +000087ee __mspabi_slli_6 +000087ec __mspabi_slli_7 +000087ea __mspabi_slli_8 +000087e8 __mspabi_slli_9 +0000860a __mspabi_slll_1 +000085e6 __mspabi_slll_10 +000085e2 __mspabi_slll_11 +000085de __mspabi_slll_12 +000085da __mspabi_slll_13 +000085d6 __mspabi_slll_14 +000085d2 __mspabi_slll_15 +00008606 __mspabi_slll_2 +00008602 __mspabi_slll_3 +000085fe __mspabi_slll_4 +000085fa __mspabi_slll_5 +000085f6 __mspabi_slll_6 +000085f2 __mspabi_slll_7 +000085ee __mspabi_slll_8 +000085ea __mspabi_slll_9 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_system_pre_init +00002740 _unlock +00008af6 abort +00008ade abs +00007088 aligned_alloc +00008230 atoi +000083b8 close +0000874a copysign +0000874a copysignl +00002744 errno +000084d0 exit +000086ba finddevice +00007924 fputc +0000717e fputs +00007424 free +0000768a frexp +0000768a frexpl +00007da2 fseek +00008180 getdevice +00006bac ldexp +00006bac ldexpl +000088f2 lseek +00008282 main +00008ae8 malloc +00007088 memalign +0000893c memccpy +00008a12 memchr +00008a86 memcpy +00008a26 memset +000027ea parmbuf +00008610 printf +0000864c prod +00007924 putc +000088ca remove +00006bac scalbn +00006bac scalbnl +000074f6 setvbuf +000089b6 strchr +000089d0 strcmp +00008aa8 strcpy +00008ab8 strlen +000087fc strncpy +00008ad2 toupper +000088ca unlink +00008a4e wcslen +00008918 write + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +000000a0 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012c __SYSMEM_SIZE +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L 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USBIEPBCTY_6 +000023f7 USBIEPSIZXY_6 +000023f8 USBIEPCNF_7 +000023f9 USBIEPBBAX_7 +000023fa USBIEPBCTX_7 +000023fd USBIEPBBAY_7 +000023fe USBIEPBCTY_7 +000023ff USBIEPSIZXY_7 +00002400 _sys_memory +0000252c _CIOBUF_ +0000264c _ftable +000026c4 _device +00002712 _stream +0000273a __TI_cleanup_ptr +0000273c __TI_dtors_ptr +0000273e _lock +00002740 _unlock +00002742 __TI_ft_end +00002744 errno +00002746 __TI_enable_exit_profile_output +0000274a __TI_tmpnams +000027ea parmbuf +00004360 _stack +00004400 __STACK_END +00004400 __mspabi_addd +00004b36 __TI_frcdivd +00004fae __mspabi_divull +0000530e __mspabi_mpyd +000055ce __TI_printfi +00005f5a __mspabi_divd +00006a3a __TI_frcmpyd +00006bac ldexp +00006bac ldexpl +00006bac scalbn +00006bac scalbnl +00007088 aligned_alloc +00007088 memalign +0000717e fputs +00007348 __mspabi_cmpd +00007424 free +000074f6 setvbuf +0000768a frexp +0000768a frexpl +0000773a __mspabi_fltlid +00007924 fputc +00007924 putc +00007a42 HOSTlseek +00007aca __TI_ltoa +00007b4e __TI_decompress_lzss +00007bca __TI_wrt_ok +00007cbe __TI_closefile +00007d30 __mspabi_fixdli +00007da2 fseek +00007e12 HOSTrename +00007ee4 HOSTopen +00007f4a HOSTwrite +00007fac __TI_doflush +0000800e HOSTread +0000806e __mspabi_mpyll_f5hw +000080cc __mspabi_srll_15 +000080d2 __mspabi_srll_14 +000080d8 __mspabi_srll_13 +000080de __mspabi_srll_12 +000080e4 __mspabi_srll_11 +000080ea __mspabi_srll_10 +000080f0 __mspabi_srll_9 +000080f6 __mspabi_srll_8 +000080fc __mspabi_srll_7 +00008102 __mspabi_srll_6 +00008108 __mspabi_srll_5 +0000810e __mspabi_srll_4 +00008114 __mspabi_srll_3 +0000811a __mspabi_srll_2 +00008120 __mspabi_srll_1 +00008128 __TI_auto_init_nobinit_nopinit_hold_wdt +00008180 getdevice +000081d8 __mspabi_divul +000081d8 __mspabi_remul +00008230 atoi +00008282 main +00008322 __mspabi_srli +00008330 __mspabi_srli_15 +00008334 __mspabi_srli_14 +00008338 __mspabi_srli_13 +0000833c __mspabi_srli_12 +00008340 __mspabi_srli_11 +00008344 __mspabi_srli_10 +00008348 __mspabi_srli_9 +0000834c __mspabi_srli_8 +00008350 __mspabi_srli_7 +00008354 __mspabi_srli_6 +00008358 __mspabi_srli_5 +0000835c __mspabi_srli_4 +00008360 __mspabi_srli_3 +00008364 __mspabi_srli_2 +00008368 __mspabi_srli_1 +0000836e __mspabi_srall +000083b8 close +00008402 __mspabi_srlll +00008448 HOSTclose +0000848c __mspabi_sllll +000084d0 exit +00008514 HOSTunlink +00008554 __mspabi_divli +00008554 __mspabi_remli +00008594 __mspabi_sral_15 +00008598 __mspabi_sral_14 +0000859c __mspabi_sral_13 +000085a0 __mspabi_sral_12 +000085a4 __mspabi_sral_11 +000085a8 __mspabi_sral_10 +000085ac __mspabi_sral_9 +000085b0 __mspabi_sral_8 +000085b4 __mspabi_sral_7 +000085b8 __mspabi_sral_6 +000085bc __mspabi_sral_5 +000085c0 __mspabi_sral_4 +000085c4 __mspabi_sral_3 +000085c8 __mspabi_sral_2 +000085cc __mspabi_sral_1 +000085d2 __mspabi_slll_15 +000085d6 __mspabi_slll_14 +000085da __mspabi_slll_13 +000085de __mspabi_slll_12 +000085e2 __mspabi_slll_11 +000085e6 __mspabi_slll_10 +000085ea __mspabi_slll_9 +000085ee __mspabi_slll_8 +000085f2 __mspabi_slll_7 +000085f6 __mspabi_slll_6 +000085fa __mspabi_slll_5 +000085fe __mspabi_slll_4 +00008602 __mspabi_slll_3 +00008606 __mspabi_slll_2 +0000860a __mspabi_slll_1 +00008610 printf +0000864c prod +00008686 __TI_cleanup +000086ba finddevice +000086ee __TI_writemsg +00008718 C$$IO$$ +0000871c __mspabi_subd +0000874a copysign +0000874a copysignl +00008778 __TI_readmsg +000087a4 __mspabi_srai +000087b0 __mspabi_srai_15 +000087b2 __mspabi_srai_14 +000087b4 __mspabi_srai_13 +000087b6 __mspabi_srai_12 +000087b8 __mspabi_srai_11 +000087ba __mspabi_srai_10 +000087bc __mspabi_srai_9 +000087be __mspabi_srai_8 +000087c0 __mspabi_srai_7 +000087c2 __mspabi_srai_6 +000087c4 __mspabi_srai_5 +000087c6 __mspabi_srai_4 +000087c8 __mspabi_srai_3 +000087ca __mspabi_srai_2 +000087cc __mspabi_srai_1 +000087d0 __mspabi_slli +000087dc __mspabi_slli_15 +000087de __mspabi_slli_14 +000087e0 __mspabi_slli_13 +000087e2 __mspabi_slli_12 +000087e4 __mspabi_slli_11 +000087e6 __mspabi_slli_10 +000087e8 __mspabi_slli_9 +000087ea __mspabi_slli_8 +000087ec __mspabi_slli_7 +000087ee __mspabi_slli_6 +000087f0 __mspabi_slli_5 +000087f2 __mspabi_slli_4 +000087f4 __mspabi_slli_3 +000087f6 __mspabi_slli_2 +000087f8 __mspabi_slli_1 +000087fc strncpy +00008828 __mspabi_negd +00008852 __mspabi_mpyull_f5hw +0000887a __mspabi_fixdi +000088ca remove +000088ca unlink +000088f2 lseek +00008918 write +0000893c memccpy +0000895e __mspabi_mpyl_f5hw +0000897e _c_int00_noargs +000089b6 strchr +000089d0 strcmp +000089e8 __mspabi_divu +000089e8 __mspabi_remu +000089fe __TI_zero_init_nomemset +00008a12 memchr +00008a26 memset +00008a3a __mspabi_mpyi_f5hw +00008a4e wcslen +00008a62 __TI_decompress_none +00008a74 __mspabi_srll +00008a86 memcpy +00008a98 __mspabi_func_epilog_7 +00008a9a __mspabi_func_epilog_6 +00008a9c __mspabi_func_epilog_5 +00008a9e __mspabi_func_epilog_4 +00008aa0 __mspabi_func_epilog_3 +00008aa2 __mspabi_func_epilog_2 +00008aa4 __mspabi_func_epilog_1 +00008aa8 strcpy +00008ab8 strlen +00008ac6 __mspabi_fltid +00008ad2 toupper +00008ade abs +00008ae8 malloc +00008af6 C$$EXIT +00008af6 abort +00008b00 _system_pre_init +00008b04 _nop +00008b06 _system_post_cinit +00008b08 _ctypes_ +00008c44 __TI_ISR_TRAP +00008c90 __TI_Handler_Table_Base +00008c96 __TI_Handler_Table_Limit +00008c9a __TI_CINIT_Base +00008ca2 __TI_CINIT_Limit +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +0000fffe _reset_vector +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[975 symbols] diff --git a/CPE325/Lab1_Problem1/Debug/Lab1_Problem1.out b/CPE325/Lab1_Problem1/Debug/Lab1_Problem1.out new file mode 100644 index 0000000..c308b0c Binary files /dev/null and b/CPE325/Lab1_Problem1/Debug/Lab1_Problem1.out differ diff --git a/CPE325/Lab1_Problem1/Debug/Lab1_Problem1_linkInfo.xml b/CPE325/Lab1_Problem1/Debug/Lab1_Problem1_linkInfo.xml new file mode 100644 index 0000000..92e67d8 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/Lab1_Problem1_linkInfo.xml @@ -0,0 +1,16383 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x61293ccb + 0x0 + Lab1_Problem1.out + + _c_int00_noargs +
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0x1c00 + + + UCSCTL0 + 0x160 + + + UCSCTL0_L + 0x160 + + + UCSCTL0_H + 0x161 + + + UCSCTL1 + 0x162 + + + UCSCTL1_L + 0x162 + + + UCSCTL1_H + 0x163 + + + UCSCTL2 + 0x164 + + + UCSCTL2_L + 0x164 + + + UCSCTL2_H + 0x165 + + + UCSCTL3 + 0x166 + + + UCSCTL3_L + 0x166 + + + UCSCTL3_H + 0x167 + + + UCSCTL4 + 0x168 + + + UCSCTL4_L + 0x168 + + + UCSCTL4_H + 0x169 + + + UCSCTL5 + 0x16a + + + UCSCTL5_L + 0x16a + + + UCSCTL5_H + 0x16b + + + UCSCTL6 + 0x16c + + + UCSCTL6_L + 0x16c + + + UCSCTL6_H + 0x16d + + + UCSCTL7 + 0x16e + + + UCSCTL7_L + 0x16e + + + UCSCTL7_H + 0x16f + + + UCSCTL8 + 0x170 + + + UCSCTL8_L + 0x170 + + + UCSCTL8_H + 0x171 + + + UCA0CTLW0 + 0x5c0 + + + UCA0CTLW0_L + 0x5c0 + + + UCA0CTLW0_H + 0x5c1 + + + UCA0BRW + 0x5c6 + + + UCA0BRW_L + 0x5c6 + + + UCA0BRW_H + 0x5c7 + + + UCA0MCTL + 0x5c8 + + + UCA0STAT + 0x5ca + + + UCA0RXBUF + 0x5cc + + + UCA0TXBUF + 0x5ce + + + UCA0ABCTL + 0x5d0 + + + UCA0IRCTL + 0x5d2 + + + UCA0IRCTL_L + 0x5d2 + + + UCA0IRCTL_H + 0x5d3 + + + UCA0ICTL + 0x5dc + + + UCA0ICTL_L + 0x5dc + + + UCA0ICTL_H + 0x5dd + + + UCA0IV + 0x5de + + + UCB0CTLW0 + 0x5e0 + + + UCB0CTLW0_L + 0x5e0 + + + UCB0CTLW0_H + 0x5e1 + + + UCB0BRW + 0x5e6 + + + UCB0BRW_L + 0x5e6 + + + UCB0BRW_H + 0x5e7 + + + UCB0STAT + 0x5ea + + + UCB0RXBUF + 0x5ec + + + UCB0TXBUF + 0x5ee + + + UCB0I2COA + 0x5f0 + + + UCB0I2COA_L + 0x5f0 + + + UCB0I2COA_H + 0x5f1 + + + UCB0I2CSA + 0x5f2 + + + UCB0I2CSA_L + 0x5f2 + + + UCB0I2CSA_H + 0x5f3 + + + UCB0ICTL + 0x5fc + + + UCB0ICTL_L + 0x5fc + + + UCB0ICTL_H + 0x5fd + + + UCB0IV + 0x5fe + + + UCA1CTLW0 + 0x600 + + + UCA1CTLW0_L + 0x600 + + + UCA1CTLW0_H + 0x601 + + + UCA1BRW + 0x606 + + + UCA1BRW_L + 0x606 + + + UCA1BRW_H + 0x607 + + + UCA1MCTL + 0x608 + + + UCA1STAT + 0x60a + + + UCA1RXBUF + 0x60c + + + UCA1TXBUF + 0x60e + + + UCA1ABCTL + 0x610 + + + UCA1IRCTL + 0x612 + + + UCA1IRCTL_L + 0x612 + + + UCA1IRCTL_H + 0x613 + + + UCA1ICTL + 0x61c + + + UCA1ICTL_L + 0x61c + + + UCA1ICTL_H + 0x61d + + + UCA1IV + 0x61e + + + UCB1CTLW0 + 0x620 + + + UCB1CTLW0_L + 0x620 + + + UCB1CTLW0_H + 0x621 + + + UCB1BRW + 0x626 + + + UCB1BRW_L + 0x626 + + + UCB1BRW_H + 0x627 + + + UCB1STAT + 0x62a + + + UCB1RXBUF + 0x62c + + + UCB1TXBUF + 0x62e + + + UCB1I2COA + 0x630 + + + UCB1I2COA_L + 0x630 + + + UCB1I2COA_H + 0x631 + + + UCB1I2CSA + 0x632 + + + UCB1I2CSA_L + 0x632 + + + UCB1I2CSA_H + 0x633 + + + UCB1ICTL + 0x63c + + + UCB1ICTL_L + 0x63c + + + UCB1ICTL_H + 0x63d + + + UCB1IV + 0x63e + + + WDTCTL + 0x15c + + + WDTCTL_L + 0x15c + + + WDTCTL_H + 0x15d + + + __TI_CINIT_Base + 0x8c9a + + + __TI_CINIT_Limit + 0x8ca2 + + + __TI_Handler_Table_Base + 0x8c90 + + + __TI_Handler_Table_Limit + 0x8c96 + + + __STACK_SIZE + 0xa0 + + + __STACK_END + 0x4400 + + + __SYSMEM_SIZE + 0x12c + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + prod + 0x864c + + + + main + 0x8282 + + + + printf + 0x8610 + + + + __TI_printfi + 0x55ce + + + + putc + 0x7924 + + + + fputc + 0x7924 + + + + fputs + 0x717e + + + + __TI_wrt_ok + 0x7bca + + + + setvbuf + 0x74f6 + + + + wcslen + 0x8a4e + + + + frexpl + 0x768a + + + + frexp + 0x768a + + + + scalbn + 0x6bac + + + + scalbnl + 0x6bac + + + + ldexpl + 0x6bac + + + + ldexp + 0x6bac + + + + __mspabi_srai + 0x87a4 + + + + __mspabi_srai_8 + 0x87be + + + + __mspabi_srai_9 + 0x87bc + + + + __mspabi_srai_6 + 0x87c2 + + + + __mspabi_srai_7 + 0x87c0 + + + + __mspabi_srai_4 + 0x87c6 + + + + __mspabi_srai_5 + 0x87c4 + + + + __mspabi_srai_2 + 0x87ca + + + + __mspabi_srai_3 + 0x87c8 + + + + __mspabi_srai_1 + 0x87cc + + + + __mspabi_srai_15 + 0x87b0 + + + + __mspabi_srai_14 + 0x87b2 + + + + __mspabi_srai_13 + 0x87b4 + + + + __mspabi_srai_12 + 0x87b6 + + + + __mspabi_srai_11 + 0x87b8 + + + + __mspabi_srai_10 + 0x87ba + + + + __mspabi_remu + 0x89e8 + + + + __mspabi_divu + 0x89e8 + + + + __mspabi_remul + 0x81d8 + + + + __mspabi_divul + 0x81d8 + + + + __mspabi_func_epilog_2 + 0x8aa2 + + + + __mspabi_func_epilog_3 + 0x8aa0 + + + + __mspabi_func_epilog_1 + 0x8aa4 + + + + __mspabi_func_epilog_6 + 0x8a9a + + + + __mspabi_func_epilog_7 + 0x8a98 + + + + __mspabi_func_epilog_4 + 0x8a9e + + + + __mspabi_func_epilog_5 + 0x8a9c + + + + __TI_int41 + 0xffd2 + + + + __TI_int42 + 0xffd4 + + + + __TI_int43 + 0xffd6 + + + + __TI_int44 + 0xffd8 + + + + __TI_int45 + 0xffda + + + + __TI_int46 + 0xffdc + + + + __TI_int47 + 0xffde + + + + __TI_int48 + 0xffe0 + + + + __TI_int49 + 0xffe2 + + + + __TI_int50 + 0xffe4 + + + + __TI_int51 + 0xffe6 + + + + __TI_int52 + 0xffe8 + + + + __TI_int53 + 0xffea + + + + __TI_int54 + 0xffec + + + + __TI_int55 + 0xffee + + + + __TI_int56 + 0xfff0 + + + + __TI_int57 + 0xfff2 + + + + __TI_int58 + 0xfff4 + + + + __TI_int59 + 0xfff6 + + + + __TI_int60 + 0xfff8 + + + + __TI_int61 + 0xfffa + + + + __TI_int62 + 0xfffc + + + + __TI_ISR_TRAP + 0x8c44 + + + + __mspabi_slli + 0x87d0 + + + + __mspabi_slli_9 + 0x87e8 + + + + __mspabi_slli_8 + 0x87ea + + + + __mspabi_slli_7 + 0x87ec + + + + __mspabi_slli_6 + 0x87ee + + + + __mspabi_slli_5 + 0x87f0 + + + + __mspabi_slli_4 + 0x87f2 + + + + __mspabi_slli_3 + 0x87f4 + + + + __mspabi_slli_2 + 0x87f6 + + + + __mspabi_slli_1 + 0x87f8 + + + + __mspabi_slli_15 + 0x87dc + + + + __mspabi_slli_14 + 0x87de + + + + __mspabi_slli_13 + 0x87e0 + + + + __mspabi_slli_12 + 0x87e2 + + + + __mspabi_slli_11 + 0x87e4 + + + + __mspabi_slli_10 + 0x87e6 + + + + __mspabi_srli_8 + 0x834c + + + + __mspabi_srli_9 + 0x8348 + + + + __mspabi_srli_6 + 0x8354 + + + + __mspabi_srli_7 + 0x8350 + + + + __mspabi_srli_4 + 0x835c + + + + __mspabi_srli_5 + 0x8358 + + + + __mspabi_srli_2 + 0x8364 + + + + __mspabi_srli_3 + 0x8360 + + + + __mspabi_srli_1 + 0x8368 + + + + __mspabi_srli + 0x8322 + + + + __mspabi_srli_15 + 0x8330 + + + + __mspabi_srli_14 + 0x8334 + + + + __mspabi_srli_13 + 0x8338 + + + + __mspabi_srli_12 + 0x833c + + + + __mspabi_srli_11 + 0x8340 + + + + __mspabi_srli_10 + 0x8344 + + + + __mspabi_mpyi_f5hw + 0x8a3a + + + + __mspabi_mpyl_f5hw + 0x895e + + + + __mspabi_mpyull_f5hw + 0x8852 + + + + __mspabi_mpyll_f5hw + 0x806e + + + + _stack + 0x4360 + + + + _c_int00_noargs + 0x897e + + + + _reset_vector + 0xfffe + + + + __TI_auto_init_nobinit_nopinit_hold_wdt + 0x8128 + + + + __TI_zero_init_nomemset + 0x89fe + + + + __TI_dtors_ptr + 0x273c + + + + __TI_cleanup_ptr + 0x273a + + + + __mspabi_srlll + 0x8402 + + + + __mspabi_divull + 0x4fae + + + + _system_pre_init + 0x8b00 + + + + _system_post_cinit + 0x8b06 + + + + __TI_decompress_none + 0x8a62 + + + + __TI_decompress_lzss + 0x7b4e + + + + __mspabi_addd + 0x4400 + + + + __mspabi_cmpd + 0x7348 + + + + __mspabi_divd + 0x5f5a + + + + __mspabi_fixdi + 0x887a + + + + __mspabi_fixdli + 0x7d30 + + + + __mspabi_fltid + 0x8ac6 + + + + __mspabi_fltlid + 0x773a + + + + __TI_frcdivd + 0x4b36 + + + + __mspabi_mpyd + 0x530e + + + + __mspabi_negd + 0x8828 + + + + __mspabi_subd + 0x871c + + + + C$$EXIT + 0x8af6 + + + + abort + 0x8af6 + + + + __TI_enable_exit_profile_output + 0x2746 + + + + exit + 0x84d0 + + + + _nop + 0x8b04 + + + + _lock + 0x273e + + + + _unlock + 0x2740 + + + + __TI_ltoa + 0x7aca + + + + atoi + 0x8230 + + + + _ctypes_ + 0x8b08 + + + + __TI_tmpnams + 0x274a + + + _ftable + 0x264c + + + + __TI_ft_end + 0x2742 + + + + memccpy + 0x893c + + + + memchr + 0x8a12 + + + + memcpy + 0x8a86 + + + + _sys_memory + 0x2400 + + + + free + 0x7424 + + + + memalign + 0x7088 + + + + malloc + 0x8ae8 + + + + aligned_alloc + 0x7088 + + + + memset + 0x8a26 + + + + strchr + 0x89b6 + + + + strlen + 0x8ab8 + + + + toupper + 0x8ad2 + + + + write + 0x8918 + + + + _stream + 0x2712 + + + + _device + 0x26c4 + + + + abs + 0x8ade + + + + errno + 0x2744 + + + + __TI_doflush + 0x7fac + + + + __TI_cleanup + 0x8686 + + + + fseek + 0x7da2 + + + + copysign + 0x874a + + + + copysignl + 0x874a + + + + __mspabi_sral_15 + 0x8594 + + + + __mspabi_sral_14 + 0x8598 + + + + __mspabi_sral_13 + 0x859c + + + + __mspabi_sral_12 + 0x85a0 + + + + __mspabi_sral_11 + 0x85a4 + + + + __mspabi_sral_10 + 0x85a8 + + + + __mspabi_sral_8 + 0x85b0 + + + + __mspabi_sral_9 + 0x85ac + + + + __mspabi_sral_6 + 0x85b8 + + + + __mspabi_sral_7 + 0x85b4 + + + + __mspabi_sral_4 + 0x85c0 + + + + __mspabi_sral_5 + 0x85bc + + + + __mspabi_sral_2 + 0x85c8 + + + + __mspabi_sral_3 + 0x85c4 + + + + __mspabi_sral_1 + 0x85cc + + + + __mspabi_remli + 0x8554 + + + + __mspabi_divli + 0x8554 + + + + __mspabi_slll_9 + 0x85ea + + + + __mspabi_slll_8 + 0x85ee + + + + __mspabi_slll_7 + 0x85f2 + + + + __mspabi_slll_6 + 0x85f6 + + + + __mspabi_slll_5 + 0x85fa + + + + __mspabi_slll_4 + 0x85fe + + + + __mspabi_slll_3 + 0x8602 + + + + __mspabi_slll_2 + 0x8606 + + + + __mspabi_slll_1 + 0x860a + + + + __mspabi_slll_15 + 0x85d2 + + + + __mspabi_slll_14 + 0x85d6 + + + + __mspabi_slll_13 + 0x85da + + + + __mspabi_slll_12 + 0x85de + + + + __mspabi_slll_11 + 0x85e2 + + + + __mspabi_slll_10 + 0x85e6 + + + + __mspabi_srll_8 + 0x80f6 + + + + __mspabi_srll_9 + 0x80f0 + + + + __mspabi_srll_6 + 0x8102 + + + + __mspabi_srll_7 + 0x80fc + + + + __mspabi_srll_4 + 0x810e + + + + __mspabi_srll_5 + 0x8108 + + + + __mspabi_srll_2 + 0x811a + + + + __mspabi_srll_3 + 0x8114 + + + + __mspabi_srll_1 + 0x8120 + + + + __mspabi_srll_15 + 0x80cc + + + + __mspabi_srll_14 + 0x80d2 + + + + __mspabi_srll_13 + 0x80d8 + + + + __mspabi_srll_12 + 0x80de + + + + __mspabi_srll_11 + 0x80e4 + + + + __mspabi_srll_10 + 0x80ea + + + + __mspabi_srll + 0x8a74 + + + + __mspabi_srall + 0x836e + + + + __mspabi_sllll + 0x848c + + + + __TI_frcmpyd + 0x6a3a + + + + HOSTclose + 0x8448 + + + + HOSTlseek + 0x7a42 + + + + parmbuf + 0x27ea + + + HOSTopen + 0x7ee4 + + + + HOSTread + 0x800e + + + + HOSTrename + 0x7e12 + + + + HOSTunlink + 0x8514 + + + + HOSTwrite + 0x7f4a + + + + __TI_readmsg + 0x8778 + + + + C$$IO$$ + 0x8718 + + + + _CIOBUF_ + 0x252c + + + + __TI_writemsg + 0x86ee + + + + lseek + 0x88f2 + + + + __TI_closefile + 0x7cbe + + + + finddevice + 0x86ba + + + + getdevice + 0x8180 + + + + strcmp + 0x89d0 + + + + strcpy + 0x8aa8 + + + + strncpy + 0x87fc + + + + close + 0x83b8 + + + + unlink + 0x88ca + + + + remove + 0x88ca + + + Link successful + diff --git a/CPE325/Lab1_Problem1/Debug/P1a.d b/CPE325/Lab1_Problem1/Debug/P1a.d new file mode 100644 index 0000000..807922d --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/P1a.d @@ -0,0 +1,42 @@ +# FIXED + +P1a.obj: ../P1a.c +P1a.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +P1a.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h +P1a.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +P1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h + +../P1a.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + diff --git a/CPE325/Lab1_Problem1/Debug/P1a.lst b/CPE325/Lab1_Problem1/Debug/P1a.lst new file mode 100644 index 0000000..b48e1c0 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/P1a.lst @@ -0,0 +1,1539 @@ +MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 1 + + 1 ;****************************************************************************** + 2 ;* MSP430 G3 C/C++ Codegen PC v20.2.5.LTS * + 3 ;* Date/Time created: Fri Aug 27 14:28:10 2021 * + 4 ;****************************************************************************** + 5 .compiler_opts --abi=eabi --diag_wrap=off --hll_source=on --mem_model:code=small --mem_model:d + 6 + 7 $C$DW$CU .dwtag DW_TAG_compile_unit + 8 .dwattr $C$DW$CU, DW_AT_name("../P1a.c") + 9 .dwattr $C$DW$CU, DW_AT_producer("TI MSP430 G3 C/C++ Codegen PC v20.2.5.LTS Copyright (c) 2003 + 10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + 11 .dwattr $C$DW$CU, DW_AT_comp_dir("C:\CPE325_Workspace\Lab1_Problem1\Debug") + 12 + 13 $C$DW$1 .dwtag DW_TAG_subprogram + 14 .dwattr $C$DW$1, DW_AT_name("printf") + 15 .dwattr $C$DW$1, DW_AT_TI_symbol_name("printf") + 16 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$10) + 17 .dwattr $C$DW$1, DW_AT_declaration + 18 .dwattr $C$DW$1, DW_AT_external + 19 .dwattr $C$DW$1, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/in + 20 .dwattr $C$DW$1, DW_AT_decl_line(0xf6) + 21 .dwattr $C$DW$1, DW_AT_decl_column(0x19) + 22 $C$DW$2 .dwtag DW_TAG_formal_parameter + 23 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$39) + 24 + 25 $C$DW$3 .dwtag DW_TAG_unspecified_parameters + 26 + 27 .dwendtag $C$DW$1 + 28 + 29 ; C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\bin\acpia430.exe -@C:\\Users\\LIBRAR + 30 000000 .sect ".text:main" + 31 .clink + 32 .global main + 33 + 34 $C$DW$4 .dwtag DW_TAG_subprogram + 35 .dwattr $C$DW$4, DW_AT_name("main") + 36 .dwattr $C$DW$4, DW_AT_low_pc(main) + 37 .dwattr $C$DW$4, DW_AT_high_pc(0x00) + 38 .dwattr $C$DW$4, DW_AT_TI_symbol_name("main") + 39 .dwattr $C$DW$4, DW_AT_external + 40 .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$10) + 41 .dwattr $C$DW$4, DW_AT_TI_begin_file("../P1a.c") + 42 .dwattr $C$DW$4, DW_AT_TI_begin_line(0x11) + 43 .dwattr $C$DW$4, DW_AT_TI_begin_column(0x05) + 44 .dwattr $C$DW$4, DW_AT_decl_file("../P1a.c") + 45 .dwattr $C$DW$4, DW_AT_decl_line(0x11) + 46 .dwattr $C$DW$4, DW_AT_decl_column(0x05) + 47 .dwattr $C$DW$4, DW_AT_TI_max_frame_size(0x14) + 48 .dwpsn file "../P1a.c",line 17,column 12,is_stmt,address main,isa 0 + 49 + 50 .dwfde $C$DW$CIE, main + 51 + 52 ;***************************************************************************** + 53 ;* FUNCTION NAME: main * + 54 ;* * + 55 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 2 + + 56 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 57 ;* Local Frame Size : 8 Args + 10 Auto + 0 Save = 18 byte * + 58 ;***************************************************************************** + 59 000000 main: + 60 ;* --------------------------------------------------------------------------* + 61 .dwcfi cfa_offset, 2 + 62 .dwcfi save_reg_to_mem, 16, -2 + 63 000000 8031 SUB.W #18,SP ; [] + 000002 0012 + 64 .dwcfi cfa_offset, 20 + 65 $C$DW$5 .dwtag DW_TAG_variable + 66 .dwattr $C$DW$5, DW_AT_name("first") + 67 .dwattr $C$DW$5, DW_AT_TI_symbol_name("first") + 68 .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$10) + 69 .dwattr $C$DW$5, DW_AT_location[DW_OP_breg1 8] + 70 + 71 $C$DW$6 .dwtag DW_TAG_variable + 72 .dwattr $C$DW$6, DW_AT_name("second") + 73 .dwattr $C$DW$6, DW_AT_TI_symbol_name("second") + 74 .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$10) + 75 .dwattr $C$DW$6, DW_AT_location[DW_OP_breg1 10] + 76 + 77 $C$DW$7 .dwtag DW_TAG_variable + 78 .dwattr $C$DW$7, DW_AT_name("counter") + 79 .dwattr $C$DW$7, DW_AT_TI_symbol_name("counter") + 80 .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$10) + 81 .dwattr $C$DW$7, DW_AT_location[DW_OP_breg1 12] + 82 + 83 $C$DW$8 .dwtag DW_TAG_variable + 84 .dwattr $C$DW$8, DW_AT_name("pr") + 85 .dwattr $C$DW$8, DW_AT_TI_symbol_name("pr") + 86 .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$10) + 87 .dwattr $C$DW$8, DW_AT_location[DW_OP_breg1 14] + 88 + 89 $C$DW$9 .dwtag DW_TAG_variable + 90 .dwattr $C$DW$9, DW_AT_name("product") + 91 .dwattr $C$DW$9, DW_AT_TI_symbol_name("product") + 92 .dwattr $C$DW$9, DW_AT_type(*$C$DW$T$10) + 93 .dwattr $C$DW$9, DW_AT_location[DW_OP_breg1 16] + 94 + 95 .dwpsn file "../P1a.c",line 20,column 15,is_stmt,isa 0 + 96 000004 42A1 MOV.W #4,8(SP) ; [] |20| + 000006 0008 + 97 .dwpsn file "../P1a.c",line 21,column 16,is_stmt,isa 0 + 98 000008 42B1 MOV.W #8,10(SP) ; [] |21| + 00000a 000A + 99 .dwpsn file "../P1a.c",line 22,column 17,is_stmt,isa 0 + 100 00000c 4381 MOV.W #0,12(SP) ; [] |22| + 00000e 000C + 101 .dwpsn file "../P1a.c",line 23,column 12,is_stmt,isa 0 + 102 000010 4381 MOV.W #0,14(SP) ; [] |23| + 000012 000E + 103 .dwpsn file "../P1a.c",line 24,column 17,is_stmt,isa 0 + 104 000014 4381 MOV.W #0,16(SP) ; [] |24| + 000016 0010 + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 3 + + 105 .dwpsn file "../P1a.c",line 26,column 5,is_stmt,isa 0 + 106 000018 411C MOV.W 8(SP),r12 ; [] |26| + 00001a 0008 + 107 00001c 411D MOV.W 10(SP),r13 ; [] |26| + 00001e 000A + 108 000020 411E MOV.W 12(SP),r14 ; [] |26| + 000022 000C + 109 000024 4E0F MOV.W r14,r15 ; [] + 110 $C$DW$10 .dwtag DW_TAG_TI_branch + 111 .dwattr $C$DW$10, DW_AT_low_pc(0x00) + 112 .dwattr $C$DW$10, DW_AT_name("prod") + 113 .dwattr $C$DW$10, DW_AT_TI_call + 114 + 115 000026 12B0 CALL #prod ; [] |26| + 000028 0000! + 116 ; [] |26| + 117 00002a 4C81 MOV.W r12,16(SP) ; [] |26| + 00002c 0010 + 118 .dwpsn file "../P1a.c",line 28,column 5,is_stmt,isa 0 + 119 00002e 40B1 MOV.W #$C$SL1+0,0(SP) ; [] |28| + 000030 0000! + 000032 0000 + 120 000034 4191 MOV.W 8(SP),2(SP) ; [] |28| + 000036 0008 + 000038 0002 + 121 00003a 4191 MOV.W 10(SP),4(SP) ; [] |28| + 00003c 000A + 00003e 0004 + 122 000040 4191 MOV.W 16(SP),6(SP) ; [] |28| + 000042 0010 + 000044 0006 + 123 $C$DW$11 .dwtag DW_TAG_TI_branch + 124 .dwattr $C$DW$11, DW_AT_low_pc(0x00) + 125 .dwattr $C$DW$11, DW_AT_name("printf") + 126 .dwattr $C$DW$11, DW_AT_TI_call + 127 + 128 000046 12B0 CALL #printf ; [] |28| + 000048 0000! + 129 ; [] |28| + 130 .dwpsn file "../P1a.c",line 29,column 1,is_stmt,isa 0 + 131 00004a 430C MOV.W #0,r12 ; [] |29| + 132 00004c 5031 ADD.W #18,SP ; [] + 00004e 0012 + 133 .dwcfi cfa_offset, 2 + 134 $C$DW$12 .dwtag DW_TAG_TI_branch + 135 .dwattr $C$DW$12, DW_AT_low_pc(0x00) + 136 .dwattr $C$DW$12, DW_AT_TI_return + 137 + 138 000050 4130 RET ; [] + 139 ; [] + 140 .dwattr $C$DW$4, DW_AT_TI_end_file("../P1a.c") + 141 .dwattr $C$DW$4, DW_AT_TI_end_line(0x1d) + 142 .dwattr $C$DW$4, DW_AT_TI_end_column(0x01) + 143 .dwendentry + 144 .dwendtag $C$DW$4 + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 4 + + 145 + 146 000000 .sect ".text:prod" + 147 .clink + 148 .global prod + 149 + 150 $C$DW$13 .dwtag DW_TAG_subprogram + 151 .dwattr $C$DW$13, DW_AT_name("prod") + 152 .dwattr $C$DW$13, DW_AT_low_pc(prod) + 153 .dwattr $C$DW$13, DW_AT_high_pc(0x00) + 154 .dwattr $C$DW$13, DW_AT_TI_symbol_name("prod") + 155 .dwattr $C$DW$13, DW_AT_external + 156 .dwattr $C$DW$13, DW_AT_type(*$C$DW$T$10) + 157 .dwattr $C$DW$13, DW_AT_TI_begin_file("../P1a.c") + 158 .dwattr $C$DW$13, DW_AT_TI_begin_line(0x1f) + 159 .dwattr $C$DW$13, DW_AT_TI_begin_column(0x05) + 160 .dwattr $C$DW$13, DW_AT_decl_file("../P1a.c") + 161 .dwattr $C$DW$13, DW_AT_decl_line(0x1f) + 162 .dwattr $C$DW$13, DW_AT_decl_column(0x05) + 163 .dwattr $C$DW$13, DW_AT_TI_max_frame_size(0x0a) + 164 .dwpsn file "../P1a.c",line 31,column 37,is_stmt,address prod,isa 0 + 165 + 166 .dwfde $C$DW$CIE, prod + 167 $C$DW$14 .dwtag DW_TAG_formal_parameter + 168 .dwattr $C$DW$14, DW_AT_name("f") + 169 .dwattr $C$DW$14, DW_AT_TI_symbol_name("f") + 170 .dwattr $C$DW$14, DW_AT_type(*$C$DW$T$10) + 171 .dwattr $C$DW$14, DW_AT_location[DW_OP_reg12] + 172 + 173 $C$DW$15 .dwtag DW_TAG_formal_parameter + 174 .dwattr $C$DW$15, DW_AT_name("s") + 175 .dwattr $C$DW$15, DW_AT_TI_symbol_name("s") + 176 .dwattr $C$DW$15, DW_AT_type(*$C$DW$T$10) + 177 .dwattr $C$DW$15, DW_AT_location[DW_OP_reg13] + 178 + 179 $C$DW$16 .dwtag DW_TAG_formal_parameter + 180 .dwattr $C$DW$16, DW_AT_name("c") + 181 .dwattr $C$DW$16, DW_AT_TI_symbol_name("c") + 182 .dwattr $C$DW$16, DW_AT_type(*$C$DW$T$10) + 183 .dwattr $C$DW$16, DW_AT_location[DW_OP_reg14] + 184 + 185 $C$DW$17 .dwtag DW_TAG_formal_parameter + 186 .dwattr $C$DW$17, DW_AT_name("p") + 187 .dwattr $C$DW$17, DW_AT_TI_symbol_name("p") + 188 .dwattr $C$DW$17, DW_AT_type(*$C$DW$T$10) + 189 .dwattr $C$DW$17, DW_AT_location[DW_OP_reg15] + 190 + 191 + 192 ;***************************************************************************** + 193 ;* FUNCTION NAME: prod * + 194 ;* * + 195 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + 196 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 197 ;* Local Frame Size : 0 Args + 8 Auto + 0 Save = 8 byte * + 198 ;***************************************************************************** + 199 000000 prod: + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 5 + + 200 ;* --------------------------------------------------------------------------* + 201 .dwcfi cfa_offset, 2 + 202 .dwcfi save_reg_to_mem, 16, -2 + 203 000000 8231 SUB.W #8,SP ; [] + 204 .dwcfi cfa_offset, 10 + 205 $C$DW$18 .dwtag DW_TAG_variable + 206 .dwattr $C$DW$18, DW_AT_name("f") + 207 .dwattr $C$DW$18, DW_AT_TI_symbol_name("f") + 208 .dwattr $C$DW$18, DW_AT_type(*$C$DW$T$10) + 209 .dwattr $C$DW$18, DW_AT_location[DW_OP_breg1 0] + 210 + 211 $C$DW$19 .dwtag DW_TAG_variable + 212 .dwattr $C$DW$19, DW_AT_name("s") + 213 .dwattr $C$DW$19, DW_AT_TI_symbol_name("s") + 214 .dwattr $C$DW$19, DW_AT_type(*$C$DW$T$10) + 215 .dwattr $C$DW$19, DW_AT_location[DW_OP_breg1 2] + 216 + 217 $C$DW$20 .dwtag DW_TAG_variable + 218 .dwattr $C$DW$20, DW_AT_name("c") + 219 .dwattr $C$DW$20, DW_AT_TI_symbol_name("c") + 220 .dwattr $C$DW$20, DW_AT_type(*$C$DW$T$10) + 221 .dwattr $C$DW$20, DW_AT_location[DW_OP_breg1 4] + 222 + 223 $C$DW$21 .dwtag DW_TAG_variable + 224 .dwattr $C$DW$21, DW_AT_name("p") + 225 .dwattr $C$DW$21, DW_AT_TI_symbol_name("p") + 226 .dwattr $C$DW$21, DW_AT_type(*$C$DW$T$10) + 227 .dwattr $C$DW$21, DW_AT_location[DW_OP_breg1 6] + 228 + 229 000002 4F81 MOV.W r15,6(SP) ; [] |31| + 000004 0006 + 230 000006 4E81 MOV.W r14,4(SP) ; [] |31| + 000008 0004 + 231 00000a 4D81 MOV.W r13,2(SP) ; [] |31| + 00000c 0002 + 232 00000e 4C81 MOV.W r12,0(SP) ; [] |31| + 000010 0000 + 233 .dwpsn file "../P1a.c",line 32,column 5,is_stmt,isa 0 + 234 000012 51A1 ADD.W 0(SP),6(SP) ; [] |32| + 000014 0006 + 235 .dwpsn file "../P1a.c",line 33,column 5,is_stmt,isa 0 + 236 000016 5391 ADD.W #1,4(SP) ; [] |33| + 000018 0004 + 237 .dwpsn file "../P1a.c",line 34,column 5,is_stmt,isa 0 + 238 00001a 9191 CMP.W 2(SP),4(SP) ; [] |34| + 00001c 0002 + 00001e 0004 + 239 000020 2408 JEQ $C$L1 ; [] |34| + 240 ; [] |34| + 241 ;* --------------------------------------------------------------------------* + 242 .dwpsn file "../P1a.c",line 34,column 15,is_stmt,isa 0 + 243 000022 411E MOV.W 4(SP),r14 ; [] |34| + 000024 0004 + 244 000026 411F MOV.W 6(SP),r15 ; [] |34| + 000028 0006 + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 6 + + 245 $C$DW$22 .dwtag DW_TAG_TI_branch + 246 .dwattr $C$DW$22, DW_AT_low_pc(0x00) + 247 .dwattr $C$DW$22, DW_AT_name("prod") + 248 .dwattr $C$DW$22, DW_AT_TI_call + 249 + 250 00002a 12B0 CALL #prod ; [] |34| + 00002c 0000! + 251 ; [] |34| + 252 00002e 4C81 MOV.W r12,6(SP) ; [] |34| + 000030 0006 + 253 ;* --------------------------------------------------------------------------* + 254 000032 $C$L1: + 255 .dwpsn file "../P1a.c",line 36,column 5,is_stmt,isa 0 + 256 000032 411C MOV.W 6(SP),r12 ; [] |36| + 000034 0006 + 257 .dwpsn file "../P1a.c",line 37,column 1,is_stmt,isa 0 + 258 000036 5231 ADD.W #8,SP ; [] + 259 .dwcfi cfa_offset, 2 + 260 $C$DW$23 .dwtag DW_TAG_TI_branch + 261 .dwattr $C$DW$23, DW_AT_low_pc(0x00) + 262 .dwattr $C$DW$23, DW_AT_TI_return + 263 + 264 000038 4130 RET ; [] + 265 ; [] + 266 .dwattr $C$DW$13, DW_AT_TI_end_file("../P1a.c") + 267 .dwattr $C$DW$13, DW_AT_TI_end_line(0x25) + 268 .dwattr $C$DW$13, DW_AT_TI_end_column(0x01) + 269 .dwendentry + 270 .dwendtag $C$DW$13 + 271 + 272 ;****************************************************************************** + 273 ;* STRINGS * + 274 ;****************************************************************************** + 275 000000 .sect ".const:.string" + 276 .align 2 + 277 000000 0025 $C$SL1: .string "%d times %d is %d",10,0 + 000001 0064 + 000002 0020 + 000003 0074 + 000004 0069 + 000005 006D + 000006 0065 + 000007 0073 + 000008 0020 + 000009 0025 + 00000a 0064 + 00000b 0020 + 00000c 0069 + 00000d 0073 + 00000e 0020 + 00000f 0025 + 000010 0064 + 000011 000A + 000012 0000 + 278 ;***************************************************************************** + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 7 + + 279 ;* UNDEFINED EXTERNAL REFERENCES * + 280 ;***************************************************************************** + 281 .global printf + 282 + 283 ;****************************************************************************** + 284 ;* BUILD ATTRIBUTES * + 285 ;****************************************************************************** + 286 .battr "TI", Tag_File, 1, Tag_LPM_INFO(1) + 287 .battr "TI", Tag_File, 1, Tag_PORTS_INIT_INFO("012345678901ABCDEFGHIJ0000000000001111000000000 + 288 .battr "TI", Tag_File, 1, Tag_LEA_INFO(1) + 289 .battr "TI", Tag_File, 1, Tag_HW_MPY32_INFO(2) + 290 .battr "TI", Tag_File, 1, Tag_HW_MPY_ISR_INFO(1) + 291 .battr "TI", Tag_File, 1, Tag_HW_MPY_INLINE_INFO(1) + 292 .battr "mspabi", Tag_File, 1, Tag_enum_size(3) + 293 + 294 ;****************************************************************************** + 295 ;* TYPE INFORMATION * + 296 ;****************************************************************************** + 297 + 298 $C$DW$T$21 .dwtag DW_TAG_structure_type + 299 .dwattr $C$DW$T$21, DW_AT_byte_size(0x10) + 300 $C$DW$24 .dwtag DW_TAG_member + 301 .dwattr $C$DW$24, DW_AT_type(*$C$DW$T$14) + 302 .dwattr $C$DW$24, DW_AT_name("__max_align1") + 303 .dwattr $C$DW$24, DW_AT_TI_symbol_name("__max_align1") + 304 .dwattr $C$DW$24, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 305 .dwattr $C$DW$24, DW_AT_accessibility(DW_ACCESS_public) + 306 .dwattr $C$DW$24, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 307 .dwattr $C$DW$24, DW_AT_decl_line(0x7b) + 308 .dwattr $C$DW$24, DW_AT_decl_column(0x0c) + 309 + 310 $C$DW$25 .dwtag DW_TAG_member + 311 .dwattr $C$DW$25, DW_AT_type(*$C$DW$T$18) + 312 .dwattr $C$DW$25, DW_AT_name("__max_align2") + 313 .dwattr $C$DW$25, DW_AT_TI_symbol_name("__max_align2") + 314 .dwattr $C$DW$25, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 315 .dwattr $C$DW$25, DW_AT_accessibility(DW_ACCESS_public) + 316 .dwattr $C$DW$25, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 317 .dwattr $C$DW$25, DW_AT_decl_line(0x7c) + 318 .dwattr $C$DW$25, DW_AT_decl_column(0x0e) + 319 + 320 .dwattr $C$DW$T$21, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 321 .dwattr $C$DW$T$21, DW_AT_decl_line(0x7a) + 322 .dwattr $C$DW$T$21, DW_AT_decl_column(0x10) + 323 .dwendtag $C$DW$T$21 + 324 + 325 $C$DW$T$24 .dwtag DW_TAG_typedef + 326 .dwattr $C$DW$T$24, DW_AT_name("__max_align_t") + 327 .dwattr $C$DW$T$24, DW_AT_type(*$C$DW$T$21) + 328 .dwattr $C$DW$T$24, DW_AT_language(DW_LANG_C) + 329 .dwattr $C$DW$T$24, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 330 .dwattr $C$DW$T$24, DW_AT_decl_line(0x7d) + 331 .dwattr $C$DW$T$24, DW_AT_decl_column(0x03) + 332 + 333 $C$DW$T$2 .dwtag DW_TAG_unspecified_type + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 8 + + 334 .dwattr $C$DW$T$2, DW_AT_name("void") + 335 + 336 + 337 $C$DW$T$25 .dwtag DW_TAG_subroutine_type + 338 .dwattr $C$DW$T$25, DW_AT_language(DW_LANG_C) + 339 .dwendtag $C$DW$T$25 + 340 + 341 $C$DW$T$26 .dwtag DW_TAG_pointer_type + 342 .dwattr $C$DW$T$26, DW_AT_type(*$C$DW$T$25) + 343 .dwattr $C$DW$T$26, DW_AT_address_class(0x10) + 344 + 345 $C$DW$T$27 .dwtag DW_TAG_typedef + 346 .dwattr $C$DW$T$27, DW_AT_name("__SFR_FARPTR") + 347 .dwattr $C$DW$T$27, DW_AT_type(*$C$DW$T$26) + 348 .dwattr $C$DW$T$27, DW_AT_language(DW_LANG_C) + 349 .dwattr $C$DW$T$27, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430f5529.h") + 350 .dwattr $C$DW$T$27, DW_AT_decl_line(0x4a) + 351 .dwattr $C$DW$T$27, DW_AT_decl_column(0x11) + 352 + 353 $C$DW$T$4 .dwtag DW_TAG_base_type + 354 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + 355 .dwattr $C$DW$T$4, DW_AT_name("bool") + 356 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01) + 357 + 358 $C$DW$T$5 .dwtag DW_TAG_base_type + 359 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char) + 360 .dwattr $C$DW$T$5, DW_AT_name("signed char") + 361 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01) + 362 + 363 $C$DW$T$28 .dwtag DW_TAG_typedef + 364 .dwattr $C$DW$T$28, DW_AT_name("__int8_t") + 365 .dwattr $C$DW$T$28, DW_AT_type(*$C$DW$T$5) + 366 .dwattr $C$DW$T$28, DW_AT_language(DW_LANG_C) + 367 .dwattr $C$DW$T$28, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 368 .dwattr $C$DW$T$28, DW_AT_decl_line(0x36) + 369 .dwattr $C$DW$T$28, DW_AT_decl_column(0x16) + 370 + 371 $C$DW$T$29 .dwtag DW_TAG_typedef + 372 .dwattr $C$DW$T$29, DW_AT_name("__int_least8_t") + 373 .dwattr $C$DW$T$29, DW_AT_type(*$C$DW$T$28) + 374 .dwattr $C$DW$T$29, DW_AT_language(DW_LANG_C) + 375 .dwattr $C$DW$T$29, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 376 .dwattr $C$DW$T$29, DW_AT_decl_line(0x5a) + 377 .dwattr $C$DW$T$29, DW_AT_decl_column(0x12) + 378 + 379 $C$DW$T$6 .dwtag DW_TAG_base_type + 380 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char) + 381 .dwattr $C$DW$T$6, DW_AT_name("unsigned char") + 382 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01) + 383 + 384 $C$DW$T$22 .dwtag DW_TAG_pointer_type + 385 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$6) + 386 .dwattr $C$DW$T$22, DW_AT_address_class(0x10) + 387 + 388 $C$DW$T$30 .dwtag DW_TAG_typedef + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 9 + + 389 .dwattr $C$DW$T$30, DW_AT_name("__uint8_t") + 390 .dwattr $C$DW$T$30, DW_AT_type(*$C$DW$T$6) + 391 .dwattr $C$DW$T$30, DW_AT_language(DW_LANG_C) + 392 .dwattr $C$DW$T$30, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 393 .dwattr $C$DW$T$30, DW_AT_decl_line(0x37) + 394 .dwattr $C$DW$T$30, DW_AT_decl_column(0x18) + 395 + 396 $C$DW$T$31 .dwtag DW_TAG_typedef + 397 .dwattr $C$DW$T$31, DW_AT_name("__sa_family_t") + 398 .dwattr $C$DW$T$31, DW_AT_type(*$C$DW$T$30) + 399 .dwattr $C$DW$T$31, DW_AT_language(DW_LANG_C) + 400 .dwattr $C$DW$T$31, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 401 .dwattr $C$DW$T$31, DW_AT_decl_line(0x47) + 402 .dwattr $C$DW$T$31, DW_AT_decl_column(0x13) + 403 + 404 $C$DW$T$32 .dwtag DW_TAG_typedef + 405 .dwattr $C$DW$T$32, DW_AT_name("__uint_least8_t") + 406 .dwattr $C$DW$T$32, DW_AT_type(*$C$DW$T$30) + 407 .dwattr $C$DW$T$32, DW_AT_language(DW_LANG_C) + 408 .dwattr $C$DW$T$32, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 409 .dwattr $C$DW$T$32, DW_AT_decl_line(0x74) + 410 .dwattr $C$DW$T$32, DW_AT_decl_column(0x13) + 411 + 412 $C$DW$T$7 .dwtag DW_TAG_base_type + 413 .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char) + 414 .dwattr $C$DW$T$7, DW_AT_name("wchar_t") + 415 .dwattr $C$DW$T$7, DW_AT_byte_size(0x02) + 416 + 417 $C$DW$T$8 .dwtag DW_TAG_base_type + 418 .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed) + 419 .dwattr $C$DW$T$8, DW_AT_name("short") + 420 .dwattr $C$DW$T$8, DW_AT_byte_size(0x02) + 421 + 422 $C$DW$T$9 .dwtag DW_TAG_base_type + 423 .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned) + 424 .dwattr $C$DW$T$9, DW_AT_name("unsigned short") + 425 .dwattr $C$DW$T$9, DW_AT_byte_size(0x02) + 426 + 427 $C$DW$T$10 .dwtag DW_TAG_base_type + 428 .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed) + 429 .dwattr $C$DW$T$10, DW_AT_name("int") + 430 .dwattr $C$DW$T$10, DW_AT_byte_size(0x02) + 431 + 432 $C$DW$T$33 .dwtag DW_TAG_typedef + 433 .dwattr $C$DW$T$33, DW_AT_name("_Mbstatet") + 434 .dwattr $C$DW$T$33, DW_AT_type(*$C$DW$T$10) + 435 .dwattr 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$C$DW$T$35, DW_AT_language(DW_LANG_C) + 452 .dwattr $C$DW$T$35, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 453 .dwattr $C$DW$T$35, DW_AT_decl_line(0x3b) + 454 .dwattr $C$DW$T$35, DW_AT_decl_column(0x0e) + 455 + 456 $C$DW$T$45 .dwtag DW_TAG_typedef + 457 .dwattr $C$DW$T$45, DW_AT_name("__cpulevel_t") + 458 .dwattr $C$DW$T$45, DW_AT_type(*$C$DW$T$10) + 459 .dwattr $C$DW$T$45, DW_AT_language(DW_LANG_C) + 460 .dwattr $C$DW$T$45, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 461 .dwattr $C$DW$T$45, DW_AT_decl_line(0x50) + 462 .dwattr $C$DW$T$45, DW_AT_decl_column(0x0e) + 463 + 464 $C$DW$T$46 .dwtag DW_TAG_typedef + 465 .dwattr $C$DW$T$46, DW_AT_name("__cpusetid_t") + 466 .dwattr $C$DW$T$46, DW_AT_type(*$C$DW$T$10) + 467 .dwattr $C$DW$T$46, DW_AT_language(DW_LANG_C) + 468 .dwattr $C$DW$T$46, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 469 .dwattr $C$DW$T$46, DW_AT_decl_line(0x51) + 470 .dwattr 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$C$DW$T$51, DW_AT_language(DW_LANG_C) + 508 .dwattr $C$DW$T$51, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 509 .dwattr $C$DW$T$51, DW_AT_decl_line(0x38) + 510 .dwattr $C$DW$T$51, DW_AT_decl_column(0x0f) + 511 + 512 $C$DW$T$52 .dwtag DW_TAG_typedef + 513 .dwattr $C$DW$T$52, DW_AT_name("__int_fast16_t") + 514 .dwattr $C$DW$T$52, DW_AT_type(*$C$DW$T$51) + 515 .dwattr $C$DW$T$52, DW_AT_language(DW_LANG_C) + 516 .dwattr $C$DW$T$52, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 517 .dwattr $C$DW$T$52, DW_AT_decl_line(0x57) + 518 .dwattr $C$DW$T$52, DW_AT_decl_column(0x13) + 519 + 520 $C$DW$T$53 .dwtag DW_TAG_typedef + 521 .dwattr $C$DW$T$53, DW_AT_name("__int_fast8_t") + 522 .dwattr $C$DW$T$53, DW_AT_type(*$C$DW$T$51) + 523 .dwattr $C$DW$T$53, DW_AT_language(DW_LANG_C) + 524 .dwattr $C$DW$T$53, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 525 .dwattr $C$DW$T$53, DW_AT_decl_line(0x56) + 526 .dwattr $C$DW$T$53, DW_AT_decl_column(0x13) + 527 + 528 $C$DW$T$54 .dwtag DW_TAG_typedef + 529 .dwattr $C$DW$T$54, DW_AT_name("__int_least16_t") + 530 .dwattr $C$DW$T$54, DW_AT_type(*$C$DW$T$51) + 531 .dwattr $C$DW$T$54, DW_AT_language(DW_LANG_C) + 532 .dwattr $C$DW$T$54, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 533 .dwattr $C$DW$T$54, DW_AT_decl_line(0x5b) + 534 .dwattr $C$DW$T$54, DW_AT_decl_column(0x13) + 535 + 536 $C$DW$T$55 .dwtag DW_TAG_typedef + 537 .dwattr $C$DW$T$55, DW_AT_name("__intptr_t") + 538 .dwattr $C$DW$T$55, DW_AT_type(*$C$DW$T$51) + 539 .dwattr $C$DW$T$55, DW_AT_language(DW_LANG_C) + 540 .dwattr $C$DW$T$55, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 541 .dwattr $C$DW$T$55, DW_AT_decl_line(0x53) + 542 .dwattr $C$DW$T$55, DW_AT_decl_column(0x19) + 543 + 544 $C$DW$T$56 .dwtag DW_TAG_typedef + 545 .dwattr $C$DW$T$56, DW_AT_name("__register_t") + 546 .dwattr $C$DW$T$56, DW_AT_type(*$C$DW$T$51) + 547 .dwattr $C$DW$T$56, DW_AT_language(DW_LANG_C) + 548 .dwattr $C$DW$T$56, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 549 .dwattr $C$DW$T$56, DW_AT_decl_line(0x5f) + 550 .dwattr $C$DW$T$56, DW_AT_decl_column(0x13) + 551 + 552 $C$DW$T$57 .dwtag DW_TAG_typedef + 553 .dwattr $C$DW$T$57, DW_AT_name("__nl_item") + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 12 + + 554 .dwattr $C$DW$T$57, DW_AT_type(*$C$DW$T$10) + 555 .dwattr $C$DW$T$57, DW_AT_language(DW_LANG_C) + 556 .dwattr $C$DW$T$57, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 557 .dwattr $C$DW$T$57, DW_AT_decl_line(0x3c) + 558 .dwattr $C$DW$T$57, DW_AT_decl_column(0x0e) + 559 + 560 $C$DW$T$58 .dwtag DW_TAG_typedef + 561 .dwattr $C$DW$T$58, DW_AT_name("__ptrdiff_t") + 562 .dwattr $C$DW$T$58, DW_AT_type(*$C$DW$T$10) + 563 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DW_TAG_typedef + 1087 .dwattr $C$DW$T$120, DW_AT_name("__float_t") + 1088 .dwattr $C$DW$T$120, DW_AT_type(*$C$DW$T$16) + 1089 .dwattr $C$DW$T$120, DW_AT_language(DW_LANG_C) + 1090 .dwattr $C$DW$T$120, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1091 .dwattr $C$DW$T$120, DW_AT_decl_line(0x4d) + 1092 .dwattr $C$DW$T$120, DW_AT_decl_column(0x10) + 1093 + 1094 $C$DW$T$17 .dwtag DW_TAG_base_type + 1095 .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float) + 1096 .dwattr $C$DW$T$17, DW_AT_name("double") + 1097 .dwattr $C$DW$T$17, DW_AT_byte_size(0x08) + 1098 + 1099 $C$DW$T$121 .dwtag DW_TAG_typedef + 1100 .dwattr $C$DW$T$121, DW_AT_name("__double_t") + 1101 .dwattr $C$DW$T$121, DW_AT_type(*$C$DW$T$17) + 1102 .dwattr $C$DW$T$121, DW_AT_language(DW_LANG_C) + 1103 .dwattr $C$DW$T$121, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 22 + + 1104 .dwattr $C$DW$T$121, DW_AT_decl_line(0x4c) + 1105 .dwattr $C$DW$T$121, DW_AT_decl_column(0x11) + 1106 + 1107 $C$DW$T$18 .dwtag DW_TAG_base_type + 1108 .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float) + 1109 .dwattr $C$DW$T$18, DW_AT_name("long double") + 1110 .dwattr $C$DW$T$18, DW_AT_byte_size(0x08) + 1111 + 1112 $C$DW$T$37 .dwtag DW_TAG_const_type + 1113 .dwattr $C$DW$T$37, DW_AT_type(*$C$DW$T$6) + 1114 + 1115 $C$DW$T$38 .dwtag DW_TAG_pointer_type + 1116 .dwattr $C$DW$T$38, DW_AT_type(*$C$DW$T$37) + 1117 .dwattr $C$DW$T$38, DW_AT_address_class(0x10) + 1118 + 1119 $C$DW$T$39 .dwtag DW_TAG_restrict_type + 1120 .dwattr $C$DW$T$39, DW_AT_type(*$C$DW$T$38) + 1121 + 1122 $C$DW$T$122 .dwtag DW_TAG_pointer_type + 1123 .dwattr $C$DW$T$122, DW_AT_type(*$C$DW$T$6) + 1124 .dwattr $C$DW$T$122, DW_AT_address_class(0x10) + 1125 + 1126 $C$DW$T$123 .dwtag DW_TAG_typedef + 1127 .dwattr $C$DW$T$123, DW_AT_name("__va_list") + 1128 .dwattr $C$DW$T$123, DW_AT_type(*$C$DW$T$122) + 1129 .dwattr $C$DW$T$123, DW_AT_language(DW_LANG_C) + 1130 .dwattr $C$DW$T$123, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1131 .dwattr $C$DW$T$123, DW_AT_decl_line(0x92) + 1132 .dwattr $C$DW$T$123, DW_AT_decl_column(0x0f) + 1133 + 1134 $C$DW$T$124 .dwtag DW_TAG_typedef + 1135 .dwattr $C$DW$T$124, DW_AT_name("va_list") + 1136 .dwattr $C$DW$T$124, DW_AT_type(*$C$DW$T$123) + 1137 .dwattr $C$DW$T$124, DW_AT_language(DW_LANG_C) + 1138 .dwattr $C$DW$T$124, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1139 .dwattr $C$DW$T$124, DW_AT_decl_line(0x33) + 1140 .dwattr $C$DW$T$124, DW_AT_decl_column(0x13) + 1141 + 1142 + 1143 $C$DW$T$19 .dwtag DW_TAG_structure_type + 1144 .dwattr $C$DW$T$19, DW_AT_name("__mq") + 1145 .dwattr $C$DW$T$19, DW_AT_declaration + 1146 .dwattr $C$DW$T$19, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1147 .dwattr $C$DW$T$19, DW_AT_decl_line(0x4c) + 1148 .dwattr $C$DW$T$19, DW_AT_decl_column(0x10) + 1149 .dwendtag $C$DW$T$19 + 1150 + 1151 $C$DW$T$125 .dwtag DW_TAG_pointer_type + 1152 .dwattr $C$DW$T$125, DW_AT_type(*$C$DW$T$19) + 1153 .dwattr $C$DW$T$125, DW_AT_address_class(0x10) + 1154 + 1155 $C$DW$T$126 .dwtag DW_TAG_typedef + 1156 .dwattr $C$DW$T$126, DW_AT_name("__mqd_t") + 1157 .dwattr $C$DW$T$126, DW_AT_type(*$C$DW$T$125) + 1158 .dwattr $C$DW$T$126, DW_AT_language(DW_LANG_C) + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 23 + + 1159 .dwattr $C$DW$T$126, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1160 .dwattr $C$DW$T$126, DW_AT_decl_line(0x4c) + 1161 .dwattr $C$DW$T$126, DW_AT_decl_column(0x16) + 1162 + 1163 + 1164 $C$DW$T$23 .dwtag DW_TAG_structure_type + 1165 .dwattr $C$DW$T$23, DW_AT_name("__sFILE") + 1166 .dwattr $C$DW$T$23, DW_AT_byte_size(0x0c) + 1167 $C$DW$26 .dwtag DW_TAG_member + 1168 .dwattr $C$DW$26, DW_AT_type(*$C$DW$T$10) + 1169 .dwattr $C$DW$26, DW_AT_name("fd") + 1170 .dwattr $C$DW$26, DW_AT_TI_symbol_name("fd") + 1171 .dwattr $C$DW$26, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 1172 .dwattr $C$DW$26, DW_AT_accessibility(DW_ACCESS_public) + 1173 .dwattr $C$DW$26, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1174 .dwattr $C$DW$26, DW_AT_decl_line(0x52) + 1175 .dwattr $C$DW$26, DW_AT_decl_column(0x0b) + 1176 + 1177 $C$DW$27 .dwtag DW_TAG_member + 1178 .dwattr $C$DW$27, DW_AT_type(*$C$DW$T$22) + 1179 .dwattr $C$DW$27, DW_AT_name("buf") + 1180 .dwattr $C$DW$27, DW_AT_TI_symbol_name("buf") + 1181 .dwattr $C$DW$27, DW_AT_data_member_location[DW_OP_plus_uconst 0x2] + 1182 .dwattr $C$DW$27, DW_AT_accessibility(DW_ACCESS_public) + 1183 .dwattr $C$DW$27, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1184 .dwattr $C$DW$27, DW_AT_decl_line(0x53) + 1185 .dwattr $C$DW$27, DW_AT_decl_column(0x16) + 1186 + 1187 $C$DW$28 .dwtag DW_TAG_member + 1188 .dwattr $C$DW$28, DW_AT_type(*$C$DW$T$22) + 1189 .dwattr $C$DW$28, DW_AT_name("pos") + 1190 .dwattr $C$DW$28, DW_AT_TI_symbol_name("pos") + 1191 .dwattr $C$DW$28, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + 1192 .dwattr $C$DW$28, DW_AT_accessibility(DW_ACCESS_public) + 1193 .dwattr $C$DW$28, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1194 .dwattr $C$DW$28, DW_AT_decl_line(0x54) + 1195 .dwattr $C$DW$28, DW_AT_decl_column(0x16) + 1196 + 1197 $C$DW$29 .dwtag DW_TAG_member + 1198 .dwattr $C$DW$29, DW_AT_type(*$C$DW$T$22) + 1199 .dwattr $C$DW$29, DW_AT_name("bufend") + 1200 .dwattr $C$DW$29, DW_AT_TI_symbol_name("bufend") + 1201 .dwattr $C$DW$29, DW_AT_data_member_location[DW_OP_plus_uconst 0x6] + 1202 .dwattr $C$DW$29, DW_AT_accessibility(DW_ACCESS_public) + 1203 .dwattr $C$DW$29, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1204 .dwattr $C$DW$29, DW_AT_decl_line(0x55) + 1205 .dwattr $C$DW$29, DW_AT_decl_column(0x16) + 1206 + 1207 $C$DW$30 .dwtag DW_TAG_member + 1208 .dwattr $C$DW$30, DW_AT_type(*$C$DW$T$22) + 1209 .dwattr $C$DW$30, DW_AT_name("buff_stop") + 1210 .dwattr $C$DW$30, DW_AT_TI_symbol_name("buff_stop") + 1211 .dwattr $C$DW$30, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 1212 .dwattr $C$DW$30, DW_AT_accessibility(DW_ACCESS_public) + 1213 .dwattr $C$DW$30, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 24 + + 1214 .dwattr $C$DW$30, DW_AT_decl_line(0x56) + 1215 .dwattr $C$DW$30, DW_AT_decl_column(0x16) + 1216 + 1217 $C$DW$31 .dwtag DW_TAG_member + 1218 .dwattr $C$DW$31, DW_AT_type(*$C$DW$T$11) + 1219 .dwattr $C$DW$31, DW_AT_name("flags") + 1220 .dwattr $C$DW$31, DW_AT_TI_symbol_name("flags") + 1221 .dwattr $C$DW$31, DW_AT_data_member_location[DW_OP_plus_uconst 0xa] + 1222 .dwattr $C$DW$31, DW_AT_accessibility(DW_ACCESS_public) + 1223 .dwattr $C$DW$31, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1224 .dwattr $C$DW$31, DW_AT_decl_line(0x57) + 1225 .dwattr $C$DW$31, DW_AT_decl_column(0x16) + 1226 + 1227 .dwattr $C$DW$T$23, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1228 .dwattr $C$DW$T$23, DW_AT_decl_line(0x51) + 1229 .dwattr $C$DW$T$23, DW_AT_decl_column(0x08) + 1230 .dwendtag $C$DW$T$23 + 1231 + 1232 $C$DW$T$127 .dwtag DW_TAG_typedef + 1233 .dwattr $C$DW$T$127, DW_AT_name("FILE") + 1234 .dwattr $C$DW$T$127, DW_AT_type(*$C$DW$T$23) + 1235 .dwattr $C$DW$T$127, DW_AT_language(DW_LANG_C) + 1236 .dwattr $C$DW$T$127, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1237 .dwattr $C$DW$T$127, DW_AT_decl_line(0x5c) + 1238 .dwattr $C$DW$T$127, DW_AT_decl_column(0x18) + 1239 + 1240 + 1241 $C$DW$T$20 .dwtag DW_TAG_structure_type + 1242 .dwattr $C$DW$T$20, DW_AT_name("__timer") + 1243 .dwattr $C$DW$T$20, DW_AT_declaration + 1244 .dwattr $C$DW$T$20, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1245 .dwattr $C$DW$T$20, DW_AT_decl_line(0x4b) + 1246 .dwattr $C$DW$T$20, DW_AT_decl_column(0x10) + 1247 .dwendtag $C$DW$T$20 + 1248 + 1249 $C$DW$T$128 .dwtag DW_TAG_pointer_type + 1250 .dwattr $C$DW$T$128, DW_AT_type(*$C$DW$T$20) + 1251 .dwattr $C$DW$T$128, DW_AT_address_class(0x10) + 1252 + 1253 $C$DW$T$129 .dwtag DW_TAG_typedef + 1254 .dwattr $C$DW$T$129, DW_AT_name("__timer_t") + 1255 .dwattr $C$DW$T$129, DW_AT_type(*$C$DW$T$128) + 1256 .dwattr $C$DW$T$129, DW_AT_language(DW_LANG_C) + 1257 .dwattr $C$DW$T$129, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1258 .dwattr $C$DW$T$129, DW_AT_decl_line(0x4b) + 1259 .dwattr $C$DW$T$129, DW_AT_decl_column(0x19) + 1260 + 1261 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C) + 1262 + 1263 ;*************************************************************** + 1264 ;* DWARF CIE ENTRIES * + 1265 ;*************************************************************** + 1266 + 1267 $C$DW$CIE .dwcie 16 + 1268 .dwcfi cfa_register, 1 + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 25 + + 1269 .dwcfi cfa_offset, 0 + 1270 .dwcfi same_value, 0 + 1271 .dwcfi same_value, 1 + 1272 .dwcfi same_value, 3 + 1273 .dwcfi same_value, 4 + 1274 .dwcfi same_value, 5 + 1275 .dwcfi same_value, 6 + 1276 .dwcfi same_value, 7 + 1277 .dwcfi same_value, 8 + 1278 .dwcfi same_value, 9 + 1279 .dwcfi same_value, 10 + 1280 .dwendentry + 1281 + 1282 ;*************************************************************** + 1283 ;* DWARF REGISTER MAP * + 1284 ;*************************************************************** + 1285 + 1286 $C$DW$32 .dwtag DW_TAG_TI_assign_register + 1287 .dwattr $C$DW$32, DW_AT_name("PC") + 1288 .dwattr $C$DW$32, DW_AT_location[DW_OP_reg0] + 1289 + 1290 $C$DW$33 .dwtag DW_TAG_TI_assign_register + 1291 .dwattr $C$DW$33, DW_AT_name("SP") + 1292 .dwattr $C$DW$33, DW_AT_location[DW_OP_reg1] + 1293 + 1294 $C$DW$34 .dwtag DW_TAG_TI_assign_register + 1295 .dwattr $C$DW$34, DW_AT_name("SR") + 1296 .dwattr $C$DW$34, DW_AT_location[DW_OP_reg2] + 1297 + 1298 $C$DW$35 .dwtag DW_TAG_TI_assign_register + 1299 .dwattr $C$DW$35, DW_AT_name("CG") + 1300 .dwattr $C$DW$35, DW_AT_location[DW_OP_reg3] + 1301 + 1302 $C$DW$36 .dwtag DW_TAG_TI_assign_register + 1303 .dwattr $C$DW$36, DW_AT_name("r4") + 1304 .dwattr $C$DW$36, DW_AT_location[DW_OP_reg4] + 1305 + 1306 $C$DW$37 .dwtag DW_TAG_TI_assign_register + 1307 .dwattr $C$DW$37, DW_AT_name("r5") + 1308 .dwattr $C$DW$37, DW_AT_location[DW_OP_reg5] + 1309 + 1310 $C$DW$38 .dwtag DW_TAG_TI_assign_register + 1311 .dwattr $C$DW$38, DW_AT_name("r6") + 1312 .dwattr $C$DW$38, DW_AT_location[DW_OP_reg6] + 1313 + 1314 $C$DW$39 .dwtag DW_TAG_TI_assign_register + 1315 .dwattr $C$DW$39, DW_AT_name("r7") + 1316 .dwattr $C$DW$39, DW_AT_location[DW_OP_reg7] + 1317 + 1318 $C$DW$40 .dwtag DW_TAG_TI_assign_register + 1319 .dwattr $C$DW$40, DW_AT_name("r8") + 1320 .dwattr $C$DW$40, DW_AT_location[DW_OP_reg8] + 1321 + 1322 $C$DW$41 .dwtag DW_TAG_TI_assign_register + 1323 .dwattr $C$DW$41, DW_AT_name("r9") + MSP430 Assembler PC v20.2.5 Fri Aug 27 14:28:10 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{8A6638BE-D8A3-476E-B8E4-BD42D2E29C23} PAGE 26 + + 1324 .dwattr $C$DW$41, DW_AT_location[DW_OP_reg9] + 1325 + 1326 $C$DW$42 .dwtag DW_TAG_TI_assign_register + 1327 .dwattr $C$DW$42, DW_AT_name("r10") + 1328 .dwattr $C$DW$42, DW_AT_location[DW_OP_reg10] + 1329 + 1330 $C$DW$43 .dwtag DW_TAG_TI_assign_register + 1331 .dwattr $C$DW$43, DW_AT_name("r11") + 1332 .dwattr $C$DW$43, DW_AT_location[DW_OP_reg11] + 1333 + 1334 $C$DW$44 .dwtag DW_TAG_TI_assign_register + 1335 .dwattr $C$DW$44, DW_AT_name("r12") + 1336 .dwattr $C$DW$44, DW_AT_location[DW_OP_reg12] + 1337 + 1338 $C$DW$45 .dwtag DW_TAG_TI_assign_register + 1339 .dwattr $C$DW$45, DW_AT_name("r13") + 1340 .dwattr $C$DW$45, DW_AT_location[DW_OP_reg13] + 1341 + 1342 $C$DW$46 .dwtag DW_TAG_TI_assign_register + 1343 .dwattr $C$DW$46, DW_AT_name("r14") + 1344 .dwattr $C$DW$46, DW_AT_location[DW_OP_reg14] + 1345 + 1346 $C$DW$47 .dwtag DW_TAG_TI_assign_register + 1347 .dwattr $C$DW$47, DW_AT_name("r15") + 1348 .dwattr $C$DW$47, DW_AT_location[DW_OP_reg15] + 1349 + 1350 $C$DW$48 .dwtag DW_TAG_TI_assign_register + 1351 .dwattr $C$DW$48, DW_AT_name("CIE_RETA") + 1352 .dwattr $C$DW$48, DW_AT_location[DW_OP_reg16] + 1353 + 1354 .dwendtag $C$DW$CU + 1355 + +No Assembly Errors, No Assembly Warnings diff --git a/CPE325/Lab1_Problem1/Debug/P1a.obj b/CPE325/Lab1_Problem1/Debug/P1a.obj new file mode 100644 index 0000000..595e4da Binary files /dev/null and b/CPE325/Lab1_Problem1/Debug/P1a.obj differ diff --git a/CPE325/Lab1_Problem1/Debug/Problem1.d b/CPE325/Lab1_Problem1/Debug/Problem1.d new file mode 100644 index 0000000..07aed86 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/Problem1.d @@ -0,0 +1,42 @@ +# FIXED + +Problem1.obj: ../Problem1.c +Problem1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +Problem1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h +Problem1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +Problem1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h + +../Problem1.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + diff --git a/CPE325/Lab1_Problem1/Debug/Problem1.lst b/CPE325/Lab1_Problem1/Debug/Problem1.lst new file mode 100644 index 0000000..03972b3 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/Problem1.lst @@ -0,0 +1,1544 @@ +MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 1 + + 1 ;****************************************************************************** + 2 ;* MSP430 G3 C/C++ Codegen PC v20.2.5.LTS * + 3 ;* Date/Time created: Mon Aug 23 10:52:59 2021 * + 4 ;****************************************************************************** + 5 .compiler_opts --abi=eabi --diag_wrap=off --hll_source=on --mem_model:code=small --mem_model:d + 6 + 7 $C$DW$CU .dwtag DW_TAG_compile_unit + 8 .dwattr $C$DW$CU, DW_AT_name("../Problem1.c") + 9 .dwattr $C$DW$CU, DW_AT_producer("TI MSP430 G3 C/C++ Codegen PC v20.2.5.LTS Copyright (c) 2003 + 10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + 11 .dwattr $C$DW$CU, DW_AT_comp_dir("C:\CPE325_Workspace\Lab1_Problem1\Debug") + 12 + 13 $C$DW$1 .dwtag DW_TAG_subprogram + 14 .dwattr $C$DW$1, DW_AT_name("printf") + 15 .dwattr $C$DW$1, DW_AT_TI_symbol_name("printf") + 16 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$10) + 17 .dwattr $C$DW$1, DW_AT_declaration + 18 .dwattr $C$DW$1, DW_AT_external + 19 .dwattr $C$DW$1, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/in + 20 .dwattr $C$DW$1, DW_AT_decl_line(0xf6) + 21 .dwattr $C$DW$1, DW_AT_decl_column(0x19) + 22 $C$DW$2 .dwtag DW_TAG_formal_parameter + 23 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$39) + 24 + 25 $C$DW$3 .dwtag DW_TAG_unspecified_parameters + 26 + 27 .dwendtag $C$DW$1 + 28 + 29 ; C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\bin\acpia430.exe -@C:\\Users\\LIBRAR + 30 000000 .sect ".text:main" + 31 .clink + 32 .global main + 33 + 34 $C$DW$4 .dwtag DW_TAG_subprogram + 35 .dwattr $C$DW$4, DW_AT_name("main") + 36 .dwattr $C$DW$4, DW_AT_low_pc(main) + 37 .dwattr $C$DW$4, DW_AT_high_pc(0x00) + 38 .dwattr $C$DW$4, DW_AT_TI_symbol_name("main") + 39 .dwattr $C$DW$4, DW_AT_external + 40 .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$10) + 41 .dwattr $C$DW$4, DW_AT_TI_begin_file("../Problem1.c") + 42 .dwattr $C$DW$4, DW_AT_TI_begin_line(0x10) + 43 .dwattr $C$DW$4, DW_AT_TI_begin_column(0x05) + 44 .dwattr $C$DW$4, DW_AT_decl_file("../Problem1.c") + 45 .dwattr $C$DW$4, DW_AT_decl_line(0x10) + 46 .dwattr $C$DW$4, DW_AT_decl_column(0x05) + 47 .dwattr $C$DW$4, DW_AT_TI_max_frame_size(0x14) + 48 .dwpsn file "../Problem1.c",line 16,column 12,is_stmt,address main,isa 0 + 49 + 50 .dwfde $C$DW$CIE, main + 51 + 52 ;***************************************************************************** + 53 ;* FUNCTION NAME: main * + 54 ;* * + 55 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 2 + + 56 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 57 ;* Local Frame Size : 8 Args + 10 Auto + 0 Save = 18 byte * + 58 ;***************************************************************************** + 59 000000 main: + 60 ;* --------------------------------------------------------------------------* + 61 .dwcfi cfa_offset, 2 + 62 .dwcfi save_reg_to_mem, 16, -2 + 63 000000 8031 SUB.W #18,SP ; [] + 000002 0012 + 64 .dwcfi cfa_offset, 20 + 65 $C$DW$5 .dwtag DW_TAG_variable + 66 .dwattr $C$DW$5, DW_AT_name("first") + 67 .dwattr $C$DW$5, DW_AT_TI_symbol_name("first") + 68 .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$10) + 69 .dwattr $C$DW$5, DW_AT_location[DW_OP_breg1 8] + 70 + 71 $C$DW$6 .dwtag DW_TAG_variable + 72 .dwattr $C$DW$6, DW_AT_name("second") + 73 .dwattr $C$DW$6, DW_AT_TI_symbol_name("second") + 74 .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$10) + 75 .dwattr $C$DW$6, DW_AT_location[DW_OP_breg1 10] + 76 + 77 $C$DW$7 .dwtag DW_TAG_variable + 78 .dwattr $C$DW$7, DW_AT_name("counter") + 79 .dwattr $C$DW$7, DW_AT_TI_symbol_name("counter") + 80 .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$10) + 81 .dwattr $C$DW$7, DW_AT_location[DW_OP_breg1 12] + 82 + 83 $C$DW$8 .dwtag DW_TAG_variable + 84 .dwattr $C$DW$8, DW_AT_name("pr") + 85 .dwattr $C$DW$8, DW_AT_TI_symbol_name("pr") + 86 .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$10) + 87 .dwattr $C$DW$8, DW_AT_location[DW_OP_breg1 14] + 88 + 89 $C$DW$9 .dwtag DW_TAG_variable + 90 .dwattr $C$DW$9, DW_AT_name("product") + 91 .dwattr $C$DW$9, DW_AT_TI_symbol_name("product") + 92 .dwattr $C$DW$9, DW_AT_type(*$C$DW$T$10) + 93 .dwattr $C$DW$9, DW_AT_location[DW_OP_breg1 16] + 94 + 95 .dwpsn file "../Problem1.c",line 17,column 12,is_stmt,isa 0 + 96 000004 42A1 MOV.W #4,8(SP) ; [] |17| + 000006 0008 + 97 .dwpsn file "../Problem1.c",line 18,column 13,is_stmt,isa 0 + 98 000008 42B1 MOV.W #8,10(SP) ; [] |18| + 00000a 000A + 99 .dwpsn file "../Problem1.c",line 19,column 14,is_stmt,isa 0 + 100 00000c 4381 MOV.W #0,12(SP) ; [] |19| + 00000e 000C + 101 .dwpsn file "../Problem1.c",line 20,column 9,is_stmt,isa 0 + 102 000010 4381 MOV.W #0,14(SP) ; [] |20| + 000012 000E + 103 .dwpsn file "../Problem1.c",line 21,column 14,is_stmt,isa 0 + 104 000014 4381 MOV.W #0,16(SP) ; [] |21| + 000016 0010 + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 3 + + 105 .dwpsn file "../Problem1.c",line 22,column 2,is_stmt,isa 0 + 106 000018 411C MOV.W 8(SP),r12 ; [] |22| + 00001a 0008 + 107 00001c 411D MOV.W 10(SP),r13 ; [] |22| + 00001e 000A + 108 000020 411E MOV.W 12(SP),r14 ; [] |22| + 000022 000C + 109 000024 4E0F MOV.W r14,r15 ; [] + 110 $C$DW$10 .dwtag DW_TAG_TI_branch + 111 .dwattr $C$DW$10, DW_AT_low_pc(0x00) + 112 .dwattr $C$DW$10, DW_AT_name("prod") + 113 .dwattr $C$DW$10, DW_AT_TI_call + 114 + 115 000026 12B0 CALL #prod ; [] |22| + 000028 0000! + 116 ; [] |22| + 117 00002a 4C81 MOV.W r12,16(SP) ; [] |22| + 00002c 0010 + 118 .dwpsn file "../Problem1.c",line 23,column 2,is_stmt,isa 0 + 119 00002e 40B1 MOV.W #$C$SL1+0,0(SP) ; [] |23| + 000030 0000! + 000032 0000 + 120 000034 4191 MOV.W 8(SP),2(SP) ; [] |23| + 000036 0008 + 000038 0002 + 121 00003a 4191 MOV.W 10(SP),4(SP) ; [] |23| + 00003c 000A + 00003e 0004 + 122 000040 4191 MOV.W 16(SP),6(SP) ; [] |23| + 000042 0010 + 000044 0006 + 123 $C$DW$11 .dwtag DW_TAG_TI_branch + 124 .dwattr $C$DW$11, DW_AT_low_pc(0x00) + 125 .dwattr $C$DW$11, DW_AT_name("printf") + 126 .dwattr $C$DW$11, DW_AT_TI_call + 127 + 128 000046 12B0 CALL #printf ; [] |23| + 000048 0000! + 129 ; [] |23| + 130 .dwpsn file "../Problem1.c",line 24,column 1,is_stmt,isa 0 + 131 00004a 430C MOV.W #0,r12 ; [] |24| + 132 00004c 5031 ADD.W #18,SP ; [] + 00004e 0012 + 133 .dwcfi cfa_offset, 2 + 134 $C$DW$12 .dwtag DW_TAG_TI_branch + 135 .dwattr $C$DW$12, DW_AT_low_pc(0x00) + 136 .dwattr $C$DW$12, DW_AT_TI_return + 137 + 138 000050 4130 RET ; [] + 139 ; [] + 140 .dwattr $C$DW$4, DW_AT_TI_end_file("../Problem1.c") + 141 .dwattr $C$DW$4, DW_AT_TI_end_line(0x18) + 142 .dwattr $C$DW$4, DW_AT_TI_end_column(0x01) + 143 .dwendentry + 144 .dwendtag $C$DW$4 + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 4 + + 145 + 146 000000 .sect ".text:prod" + 147 .clink + 148 .global prod + 149 + 150 $C$DW$13 .dwtag DW_TAG_subprogram + 151 .dwattr $C$DW$13, DW_AT_name("prod") + 152 .dwattr $C$DW$13, DW_AT_low_pc(prod) + 153 .dwattr $C$DW$13, DW_AT_high_pc(0x00) + 154 .dwattr $C$DW$13, DW_AT_TI_symbol_name("prod") + 155 .dwattr $C$DW$13, DW_AT_external + 156 .dwattr $C$DW$13, DW_AT_type(*$C$DW$T$10) + 157 .dwattr $C$DW$13, DW_AT_TI_begin_file("../Problem1.c") + 158 .dwattr $C$DW$13, DW_AT_TI_begin_line(0x1a) + 159 .dwattr $C$DW$13, DW_AT_TI_begin_column(0x05) + 160 .dwattr $C$DW$13, DW_AT_decl_file("../Problem1.c") + 161 .dwattr $C$DW$13, DW_AT_decl_line(0x1a) + 162 .dwattr $C$DW$13, DW_AT_decl_column(0x05) + 163 .dwattr $C$DW$13, DW_AT_TI_max_frame_size(0x0a) + 164 .dwpsn file "../Problem1.c",line 26,column 37,is_stmt,address prod,isa 0 + 165 + 166 .dwfde $C$DW$CIE, prod + 167 $C$DW$14 .dwtag DW_TAG_formal_parameter + 168 .dwattr $C$DW$14, DW_AT_name("f") + 169 .dwattr $C$DW$14, DW_AT_TI_symbol_name("f") + 170 .dwattr $C$DW$14, DW_AT_type(*$C$DW$T$10) + 171 .dwattr $C$DW$14, DW_AT_location[DW_OP_reg12] + 172 + 173 $C$DW$15 .dwtag DW_TAG_formal_parameter + 174 .dwattr $C$DW$15, DW_AT_name("s") + 175 .dwattr $C$DW$15, DW_AT_TI_symbol_name("s") + 176 .dwattr $C$DW$15, DW_AT_type(*$C$DW$T$10) + 177 .dwattr $C$DW$15, DW_AT_location[DW_OP_reg13] + 178 + 179 $C$DW$16 .dwtag DW_TAG_formal_parameter + 180 .dwattr $C$DW$16, DW_AT_name("c") + 181 .dwattr $C$DW$16, DW_AT_TI_symbol_name("c") + 182 .dwattr $C$DW$16, DW_AT_type(*$C$DW$T$10) + 183 .dwattr $C$DW$16, DW_AT_location[DW_OP_reg14] + 184 + 185 $C$DW$17 .dwtag DW_TAG_formal_parameter + 186 .dwattr $C$DW$17, DW_AT_name("p") + 187 .dwattr $C$DW$17, DW_AT_TI_symbol_name("p") + 188 .dwattr $C$DW$17, DW_AT_type(*$C$DW$T$10) + 189 .dwattr $C$DW$17, DW_AT_location[DW_OP_reg15] + 190 + 191 + 192 ;***************************************************************************** + 193 ;* FUNCTION NAME: prod * + 194 ;* * + 195 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + 196 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 197 ;* Local Frame Size : 0 Args + 8 Auto + 0 Save = 8 byte * + 198 ;***************************************************************************** + 199 000000 prod: + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 5 + + 200 ;* --------------------------------------------------------------------------* + 201 .dwcfi cfa_offset, 2 + 202 .dwcfi save_reg_to_mem, 16, -2 + 203 000000 8231 SUB.W #8,SP ; [] + 204 .dwcfi cfa_offset, 10 + 205 $C$DW$18 .dwtag DW_TAG_variable + 206 .dwattr $C$DW$18, DW_AT_name("f") + 207 .dwattr $C$DW$18, DW_AT_TI_symbol_name("f") + 208 .dwattr $C$DW$18, DW_AT_type(*$C$DW$T$10) + 209 .dwattr $C$DW$18, DW_AT_location[DW_OP_breg1 0] + 210 + 211 $C$DW$19 .dwtag DW_TAG_variable + 212 .dwattr $C$DW$19, DW_AT_name("s") + 213 .dwattr $C$DW$19, DW_AT_TI_symbol_name("s") + 214 .dwattr $C$DW$19, DW_AT_type(*$C$DW$T$10) + 215 .dwattr $C$DW$19, DW_AT_location[DW_OP_breg1 2] + 216 + 217 $C$DW$20 .dwtag DW_TAG_variable + 218 .dwattr $C$DW$20, DW_AT_name("c") + 219 .dwattr $C$DW$20, DW_AT_TI_symbol_name("c") + 220 .dwattr $C$DW$20, DW_AT_type(*$C$DW$T$10) + 221 .dwattr $C$DW$20, DW_AT_location[DW_OP_breg1 4] + 222 + 223 $C$DW$21 .dwtag DW_TAG_variable + 224 .dwattr $C$DW$21, DW_AT_name("p") + 225 .dwattr $C$DW$21, DW_AT_TI_symbol_name("p") + 226 .dwattr $C$DW$21, DW_AT_type(*$C$DW$T$10) + 227 .dwattr $C$DW$21, DW_AT_location[DW_OP_breg1 6] + 228 + 229 000002 4F81 MOV.W r15,6(SP) ; [] |26| + 000004 0006 + 230 000006 4E81 MOV.W r14,4(SP) ; [] |26| + 000008 0004 + 231 00000a 4D81 MOV.W r13,2(SP) ; [] |26| + 00000c 0002 + 232 00000e 4C81 MOV.W r12,0(SP) ; [] |26| + 000010 0000 + 233 .dwpsn file "../Problem1.c",line 27,column 2,is_stmt,isa 0 + 234 000012 51A1 ADD.W 0(SP),6(SP) ; [] |27| + 000014 0006 + 235 .dwpsn file "../Problem1.c",line 28,column 2,is_stmt,isa 0 + 236 000016 5391 ADD.W #1,4(SP) ; [] |28| + 000018 0004 + 237 .dwpsn file "../Problem1.c",line 29,column 2,is_stmt,isa 0 + 238 00001a 9191 CMP.W 2(SP),4(SP) ; [] |29| + 00001c 0002 + 00001e 0004 + 239 000020 2407 JEQ $C$L1 ; [] |29| + 240 ; [] |29| + 241 ;* --------------------------------------------------------------------------* + 242 .dwpsn file "../Problem1.c",line 29,column 12,is_stmt,isa 0 + 243 000022 411E MOV.W 4(SP),r14 ; [] |29| + 000024 0004 + 244 000026 411F MOV.W 6(SP),r15 ; [] |29| + 000028 0006 + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 6 + + 245 $C$DW$22 .dwtag DW_TAG_TI_branch + 246 .dwattr $C$DW$22, DW_AT_low_pc(0x00) + 247 .dwattr $C$DW$22, DW_AT_name("prod") + 248 .dwattr $C$DW$22, DW_AT_TI_call + 249 + 250 00002a 12B0 CALL #prod ; [] |29| + 00002c 0000! + 251 ; [] |29| + 252 00002e 3C03 JMP $C$L2 ; [] + 253 ; [] + 254 ;* --------------------------------------------------------------------------* + 255 000030 $C$L1: + 256 .dwpsn file "../Problem1.c",line 31,column 4,is_stmt,isa 0 + 257 000030 411C MOV.W 6(SP),r12 ; [] |31| + 000032 0006 + 258 000034 3C00 JMP $C$L2 ; [] |31| + 259 ; [] |31| + 260 ;* --------------------------------------------------------------------------* + 261 ;* --------------------------------------------------------------------------* + 262 000036 $C$L2: + 263 .dwpsn file "../Problem1.c",line 33,column 1,is_stmt,isa 0 + 264 000036 5231 ADD.W #8,SP ; [] + 265 .dwcfi cfa_offset, 2 + 266 $C$DW$23 .dwtag DW_TAG_TI_branch + 267 .dwattr $C$DW$23, DW_AT_low_pc(0x00) + 268 .dwattr $C$DW$23, DW_AT_TI_return + 269 + 270 000038 4130 RET ; [] + 271 ; [] + 272 .dwattr $C$DW$13, DW_AT_TI_end_file("../Problem1.c") + 273 .dwattr $C$DW$13, DW_AT_TI_end_line(0x21) + 274 .dwattr $C$DW$13, DW_AT_TI_end_column(0x01) + 275 .dwendentry + 276 .dwendtag $C$DW$13 + 277 + 278 ;****************************************************************************** + 279 ;* STRINGS * + 280 ;****************************************************************************** + 281 000000 .sect ".const:.string" + 282 .align 2 + 283 000000 0025 $C$SL1: .string "%d times %d is %d",10,0 + 000001 0064 + 000002 0020 + 000003 0074 + 000004 0069 + 000005 006D + 000006 0065 + 000007 0073 + 000008 0020 + 000009 0025 + 00000a 0064 + 00000b 0020 + 00000c 0069 + 00000d 0073 + 00000e 0020 + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 7 + + 00000f 0025 + 000010 0064 + 000011 000A + 000012 0000 + 284 ;***************************************************************************** + 285 ;* UNDEFINED EXTERNAL REFERENCES * + 286 ;***************************************************************************** + 287 .global printf + 288 + 289 ;****************************************************************************** + 290 ;* BUILD ATTRIBUTES * + 291 ;****************************************************************************** + 292 .battr "TI", Tag_File, 1, Tag_LPM_INFO(1) + 293 .battr "TI", Tag_File, 1, Tag_PORTS_INIT_INFO("012345678901ABCDEFGHIJ0000000000001111000000000 + 294 .battr "TI", Tag_File, 1, Tag_LEA_INFO(1) + 295 .battr "TI", Tag_File, 1, Tag_HW_MPY32_INFO(2) + 296 .battr "TI", Tag_File, 1, Tag_HW_MPY_ISR_INFO(1) + 297 .battr "TI", Tag_File, 1, Tag_HW_MPY_INLINE_INFO(1) + 298 .battr "mspabi", Tag_File, 1, Tag_enum_size(3) + 299 + 300 ;****************************************************************************** + 301 ;* TYPE INFORMATION * + 302 ;****************************************************************************** + 303 + 304 $C$DW$T$21 .dwtag DW_TAG_structure_type + 305 .dwattr $C$DW$T$21, DW_AT_byte_size(0x10) + 306 $C$DW$24 .dwtag DW_TAG_member + 307 .dwattr $C$DW$24, DW_AT_type(*$C$DW$T$14) + 308 .dwattr $C$DW$24, DW_AT_name("__max_align1") + 309 .dwattr $C$DW$24, DW_AT_TI_symbol_name("__max_align1") + 310 .dwattr $C$DW$24, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 311 .dwattr $C$DW$24, DW_AT_accessibility(DW_ACCESS_public) + 312 .dwattr $C$DW$24, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 313 .dwattr $C$DW$24, DW_AT_decl_line(0x7b) + 314 .dwattr $C$DW$24, DW_AT_decl_column(0x0c) + 315 + 316 $C$DW$25 .dwtag DW_TAG_member + 317 .dwattr $C$DW$25, DW_AT_type(*$C$DW$T$18) + 318 .dwattr $C$DW$25, DW_AT_name("__max_align2") + 319 .dwattr $C$DW$25, DW_AT_TI_symbol_name("__max_align2") + 320 .dwattr $C$DW$25, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 321 .dwattr $C$DW$25, DW_AT_accessibility(DW_ACCESS_public) + 322 .dwattr $C$DW$25, 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DW_AT_decl_column(0x03) + 338 + 339 $C$DW$T$2 .dwtag DW_TAG_unspecified_type + 340 .dwattr $C$DW$T$2, DW_AT_name("void") + 341 + 342 + 343 $C$DW$T$25 .dwtag DW_TAG_subroutine_type + 344 .dwattr $C$DW$T$25, DW_AT_language(DW_LANG_C) + 345 .dwendtag $C$DW$T$25 + 346 + 347 $C$DW$T$26 .dwtag DW_TAG_pointer_type + 348 .dwattr $C$DW$T$26, DW_AT_type(*$C$DW$T$25) + 349 .dwattr $C$DW$T$26, DW_AT_address_class(0x10) + 350 + 351 $C$DW$T$27 .dwtag DW_TAG_typedef + 352 .dwattr $C$DW$T$27, DW_AT_name("__SFR_FARPTR") + 353 .dwattr $C$DW$T$27, DW_AT_type(*$C$DW$T$26) + 354 .dwattr $C$DW$T$27, DW_AT_language(DW_LANG_C) + 355 .dwattr $C$DW$T$27, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430f5529.h") + 356 .dwattr $C$DW$T$27, DW_AT_decl_line(0x4a) + 357 .dwattr $C$DW$T$27, DW_AT_decl_column(0x11) + 358 + 359 $C$DW$T$4 .dwtag DW_TAG_base_type + 360 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + 361 .dwattr $C$DW$T$4, DW_AT_name("bool") + 362 .dwattr $C$DW$T$4, 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DW_AT_decl_column(0x12) + 384 + 385 $C$DW$T$6 .dwtag DW_TAG_base_type + 386 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char) + 387 .dwattr $C$DW$T$6, DW_AT_name("unsigned char") + 388 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01) + 389 + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 9 + + 390 $C$DW$T$22 .dwtag DW_TAG_pointer_type + 391 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$6) + 392 .dwattr $C$DW$T$22, DW_AT_address_class(0x10) + 393 + 394 $C$DW$T$30 .dwtag DW_TAG_typedef + 395 .dwattr $C$DW$T$30, DW_AT_name("__uint8_t") + 396 .dwattr $C$DW$T$30, DW_AT_type(*$C$DW$T$6) + 397 .dwattr $C$DW$T$30, DW_AT_language(DW_LANG_C) + 398 .dwattr $C$DW$T$30, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 399 .dwattr $C$DW$T$30, DW_AT_decl_line(0x37) + 400 .dwattr $C$DW$T$30, DW_AT_decl_column(0x18) + 401 + 402 $C$DW$T$31 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Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 10 + + 445 + 446 $C$DW$T$34 .dwtag DW_TAG_typedef + 447 .dwattr $C$DW$T$34, DW_AT_name("__mbstate_t") + 448 .dwattr $C$DW$T$34, DW_AT_type(*$C$DW$T$33) + 449 .dwattr $C$DW$T$34, DW_AT_language(DW_LANG_C) + 450 .dwattr $C$DW$T$34, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 451 .dwattr $C$DW$T$34, DW_AT_decl_line(0x92) + 452 .dwattr $C$DW$T$34, DW_AT_decl_column(0x13) + 453 + 454 $C$DW$T$35 .dwtag DW_TAG_typedef + 455 .dwattr $C$DW$T$35, DW_AT_name("__accmode_t") + 456 .dwattr $C$DW$T$35, DW_AT_type(*$C$DW$T$10) + 457 .dwattr $C$DW$T$35, DW_AT_language(DW_LANG_C) + 458 .dwattr $C$DW$T$35, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 459 .dwattr $C$DW$T$35, DW_AT_decl_line(0x3b) + 460 .dwattr $C$DW$T$35, DW_AT_decl_column(0x0e) + 461 + 462 $C$DW$T$45 .dwtag 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Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 11 + + 500 .dwattr $C$DW$T$49, DW_AT_decl_column(0x15) + 501 + 502 $C$DW$T$50 .dwtag DW_TAG_typedef + 503 .dwattr $C$DW$T$50, DW_AT_name("__wint_t") + 504 .dwattr $C$DW$T$50, DW_AT_type(*$C$DW$T$48) + 505 .dwattr $C$DW$T$50, DW_AT_language(DW_LANG_C) + 506 .dwattr $C$DW$T$50, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 507 .dwattr $C$DW$T$50, DW_AT_decl_line(0x6d) + 508 .dwattr $C$DW$T$50, DW_AT_decl_column(0x15) + 509 + 510 $C$DW$T$51 .dwtag DW_TAG_typedef + 511 .dwattr $C$DW$T$51, DW_AT_name("__int16_t") + 512 .dwattr $C$DW$T$51, DW_AT_type(*$C$DW$T$10) + 513 .dwattr $C$DW$T$51, DW_AT_language(DW_LANG_C) + 514 .dwattr $C$DW$T$51, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 515 .dwattr $C$DW$T$51, DW_AT_decl_line(0x38) + 516 .dwattr $C$DW$T$51, DW_AT_decl_column(0x0f) + 517 + 518 $C$DW$T$52 .dwtag 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+ 1059 .dwattr $C$DW$T$116, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1060 .dwattr $C$DW$T$116, DW_AT_decl_line(0x73) + 1061 .dwattr $C$DW$T$116, DW_AT_decl_column(0x14) + 1062 + 1063 $C$DW$T$117 .dwtag DW_TAG_typedef + 1064 .dwattr $C$DW$T$117, DW_AT_name("__uint_least64_t") + 1065 .dwattr $C$DW$T$117, DW_AT_type(*$C$DW$T$110) + 1066 .dwattr $C$DW$T$117, DW_AT_language(DW_LANG_C) + 1067 .dwattr $C$DW$T$117, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1068 .dwattr $C$DW$T$117, DW_AT_decl_line(0x77) + 1069 .dwattr $C$DW$T$117, DW_AT_decl_column(0x14) + 1070 + 1071 $C$DW$T$118 .dwtag DW_TAG_typedef + 1072 .dwattr $C$DW$T$118, DW_AT_name("__uintmax_t") + 1073 .dwattr $C$DW$T$118, DW_AT_type(*$C$DW$T$110) + 1074 .dwattr $C$DW$T$118, DW_AT_language(DW_LANG_C) + 1075 .dwattr $C$DW$T$118, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1076 .dwattr $C$DW$T$118, DW_AT_decl_line(0x69) + 1077 .dwattr $C$DW$T$118, DW_AT_decl_column(0x14) + 1078 + 1079 $C$DW$T$119 .dwtag DW_TAG_typedef + 1080 .dwattr $C$DW$T$119, DW_AT_name("__rman_res_t") + 1081 .dwattr $C$DW$T$119, DW_AT_type(*$C$DW$T$118) + 1082 .dwattr $C$DW$T$119, DW_AT_language(DW_LANG_C) + 1083 .dwattr $C$DW$T$119, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1084 .dwattr $C$DW$T$119, DW_AT_decl_line(0x9a) + 1085 .dwattr $C$DW$T$119, DW_AT_decl_column(0x19) + 1086 + 1087 $C$DW$T$16 .dwtag DW_TAG_base_type + 1088 .dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float) + 1089 .dwattr $C$DW$T$16, DW_AT_name("float") + 1090 .dwattr $C$DW$T$16, DW_AT_byte_size(0x04) + 1091 + 1092 $C$DW$T$120 .dwtag DW_TAG_typedef + 1093 .dwattr $C$DW$T$120, DW_AT_name("__float_t") + 1094 .dwattr $C$DW$T$120, DW_AT_type(*$C$DW$T$16) + 1095 .dwattr $C$DW$T$120, DW_AT_language(DW_LANG_C) + 1096 .dwattr $C$DW$T$120, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1097 .dwattr $C$DW$T$120, DW_AT_decl_line(0x4d) + 1098 .dwattr $C$DW$T$120, DW_AT_decl_column(0x10) + 1099 + 1100 $C$DW$T$17 .dwtag DW_TAG_base_type + 1101 .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float) + 1102 .dwattr $C$DW$T$17, DW_AT_name("double") + 1103 .dwattr $C$DW$T$17, DW_AT_byte_size(0x08) + 1104 + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 22 + + 1105 $C$DW$T$121 .dwtag DW_TAG_typedef + 1106 .dwattr $C$DW$T$121, DW_AT_name("__double_t") + 1107 .dwattr $C$DW$T$121, DW_AT_type(*$C$DW$T$17) + 1108 .dwattr $C$DW$T$121, DW_AT_language(DW_LANG_C) + 1109 .dwattr $C$DW$T$121, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1110 .dwattr $C$DW$T$121, DW_AT_decl_line(0x4c) + 1111 .dwattr $C$DW$T$121, DW_AT_decl_column(0x11) + 1112 + 1113 $C$DW$T$18 .dwtag DW_TAG_base_type + 1114 .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float) + 1115 .dwattr $C$DW$T$18, DW_AT_name("long double") + 1116 .dwattr $C$DW$T$18, DW_AT_byte_size(0x08) + 1117 + 1118 $C$DW$T$37 .dwtag DW_TAG_const_type + 1119 .dwattr $C$DW$T$37, DW_AT_type(*$C$DW$T$6) + 1120 + 1121 $C$DW$T$38 .dwtag DW_TAG_pointer_type + 1122 .dwattr $C$DW$T$38, DW_AT_type(*$C$DW$T$37) + 1123 .dwattr $C$DW$T$38, DW_AT_address_class(0x10) + 1124 + 1125 $C$DW$T$39 .dwtag DW_TAG_restrict_type + 1126 .dwattr $C$DW$T$39, DW_AT_type(*$C$DW$T$38) + 1127 + 1128 $C$DW$T$122 .dwtag DW_TAG_pointer_type + 1129 .dwattr $C$DW$T$122, DW_AT_type(*$C$DW$T$6) + 1130 .dwattr $C$DW$T$122, DW_AT_address_class(0x10) + 1131 + 1132 $C$DW$T$123 .dwtag DW_TAG_typedef + 1133 .dwattr $C$DW$T$123, DW_AT_name("__va_list") + 1134 .dwattr $C$DW$T$123, DW_AT_type(*$C$DW$T$122) + 1135 .dwattr $C$DW$T$123, DW_AT_language(DW_LANG_C) + 1136 .dwattr $C$DW$T$123, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1137 .dwattr $C$DW$T$123, DW_AT_decl_line(0x92) + 1138 .dwattr $C$DW$T$123, DW_AT_decl_column(0x0f) + 1139 + 1140 $C$DW$T$124 .dwtag DW_TAG_typedef + 1141 .dwattr $C$DW$T$124, DW_AT_name("va_list") + 1142 .dwattr $C$DW$T$124, DW_AT_type(*$C$DW$T$123) + 1143 .dwattr $C$DW$T$124, DW_AT_language(DW_LANG_C) + 1144 .dwattr $C$DW$T$124, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1145 .dwattr $C$DW$T$124, DW_AT_decl_line(0x33) + 1146 .dwattr $C$DW$T$124, DW_AT_decl_column(0x13) + 1147 + 1148 + 1149 $C$DW$T$19 .dwtag DW_TAG_structure_type + 1150 .dwattr $C$DW$T$19, DW_AT_name("__mq") + 1151 .dwattr $C$DW$T$19, DW_AT_declaration + 1152 .dwattr $C$DW$T$19, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1153 .dwattr $C$DW$T$19, DW_AT_decl_line(0x4c) + 1154 .dwattr $C$DW$T$19, DW_AT_decl_column(0x10) + 1155 .dwendtag $C$DW$T$19 + 1156 + 1157 $C$DW$T$125 .dwtag DW_TAG_pointer_type + 1158 .dwattr $C$DW$T$125, DW_AT_type(*$C$DW$T$19) + 1159 .dwattr $C$DW$T$125, DW_AT_address_class(0x10) + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 23 + + 1160 + 1161 $C$DW$T$126 .dwtag DW_TAG_typedef + 1162 .dwattr $C$DW$T$126, DW_AT_name("__mqd_t") + 1163 .dwattr $C$DW$T$126, DW_AT_type(*$C$DW$T$125) + 1164 .dwattr $C$DW$T$126, DW_AT_language(DW_LANG_C) + 1165 .dwattr $C$DW$T$126, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1166 .dwattr $C$DW$T$126, DW_AT_decl_line(0x4c) + 1167 .dwattr $C$DW$T$126, DW_AT_decl_column(0x16) + 1168 + 1169 + 1170 $C$DW$T$23 .dwtag DW_TAG_structure_type + 1171 .dwattr $C$DW$T$23, DW_AT_name("__sFILE") + 1172 .dwattr $C$DW$T$23, DW_AT_byte_size(0x0c) + 1173 $C$DW$26 .dwtag DW_TAG_member + 1174 .dwattr $C$DW$26, DW_AT_type(*$C$DW$T$10) + 1175 .dwattr $C$DW$26, DW_AT_name("fd") + 1176 .dwattr $C$DW$26, DW_AT_TI_symbol_name("fd") + 1177 .dwattr $C$DW$26, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 1178 .dwattr $C$DW$26, DW_AT_accessibility(DW_ACCESS_public) + 1179 .dwattr $C$DW$26, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1180 .dwattr $C$DW$26, DW_AT_decl_line(0x52) + 1181 .dwattr $C$DW$26, DW_AT_decl_column(0x0b) + 1182 + 1183 $C$DW$27 .dwtag DW_TAG_member + 1184 .dwattr $C$DW$27, DW_AT_type(*$C$DW$T$22) + 1185 .dwattr $C$DW$27, DW_AT_name("buf") + 1186 .dwattr $C$DW$27, DW_AT_TI_symbol_name("buf") + 1187 .dwattr $C$DW$27, DW_AT_data_member_location[DW_OP_plus_uconst 0x2] + 1188 .dwattr $C$DW$27, DW_AT_accessibility(DW_ACCESS_public) + 1189 .dwattr $C$DW$27, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1190 .dwattr $C$DW$27, DW_AT_decl_line(0x53) + 1191 .dwattr $C$DW$27, DW_AT_decl_column(0x16) + 1192 + 1193 $C$DW$28 .dwtag DW_TAG_member + 1194 .dwattr $C$DW$28, DW_AT_type(*$C$DW$T$22) + 1195 .dwattr $C$DW$28, DW_AT_name("pos") + 1196 .dwattr $C$DW$28, DW_AT_TI_symbol_name("pos") + 1197 .dwattr $C$DW$28, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + 1198 .dwattr $C$DW$28, DW_AT_accessibility(DW_ACCESS_public) + 1199 .dwattr $C$DW$28, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1200 .dwattr $C$DW$28, DW_AT_decl_line(0x54) + 1201 .dwattr $C$DW$28, DW_AT_decl_column(0x16) + 1202 + 1203 $C$DW$29 .dwtag DW_TAG_member + 1204 .dwattr $C$DW$29, DW_AT_type(*$C$DW$T$22) + 1205 .dwattr $C$DW$29, DW_AT_name("bufend") + 1206 .dwattr $C$DW$29, DW_AT_TI_symbol_name("bufend") + 1207 .dwattr $C$DW$29, DW_AT_data_member_location[DW_OP_plus_uconst 0x6] + 1208 .dwattr $C$DW$29, DW_AT_accessibility(DW_ACCESS_public) + 1209 .dwattr $C$DW$29, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1210 .dwattr $C$DW$29, DW_AT_decl_line(0x55) + 1211 .dwattr $C$DW$29, DW_AT_decl_column(0x16) + 1212 + 1213 $C$DW$30 .dwtag DW_TAG_member + 1214 .dwattr $C$DW$30, DW_AT_type(*$C$DW$T$22) + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 24 + + 1215 .dwattr $C$DW$30, DW_AT_name("buff_stop") + 1216 .dwattr $C$DW$30, DW_AT_TI_symbol_name("buff_stop") + 1217 .dwattr $C$DW$30, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 1218 .dwattr $C$DW$30, DW_AT_accessibility(DW_ACCESS_public) + 1219 .dwattr $C$DW$30, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1220 .dwattr $C$DW$30, DW_AT_decl_line(0x56) + 1221 .dwattr $C$DW$30, DW_AT_decl_column(0x16) + 1222 + 1223 $C$DW$31 .dwtag DW_TAG_member + 1224 .dwattr $C$DW$31, DW_AT_type(*$C$DW$T$11) + 1225 .dwattr $C$DW$31, DW_AT_name("flags") + 1226 .dwattr $C$DW$31, DW_AT_TI_symbol_name("flags") + 1227 .dwattr $C$DW$31, DW_AT_data_member_location[DW_OP_plus_uconst 0xa] + 1228 .dwattr $C$DW$31, DW_AT_accessibility(DW_ACCESS_public) + 1229 .dwattr $C$DW$31, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 1230 .dwattr $C$DW$31, DW_AT_decl_line(0x57) + 1231 .dwattr $C$DW$31, DW_AT_decl_column(0x16) + 1232 + 1233 .dwattr $C$DW$T$23, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1234 .dwattr $C$DW$T$23, DW_AT_decl_line(0x51) + 1235 .dwattr $C$DW$T$23, DW_AT_decl_column(0x08) + 1236 .dwendtag $C$DW$T$23 + 1237 + 1238 $C$DW$T$127 .dwtag DW_TAG_typedef + 1239 .dwattr $C$DW$T$127, DW_AT_name("FILE") + 1240 .dwattr $C$DW$T$127, DW_AT_type(*$C$DW$T$23) + 1241 .dwattr $C$DW$T$127, DW_AT_language(DW_LANG_C) + 1242 .dwattr $C$DW$T$127, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1243 .dwattr $C$DW$T$127, DW_AT_decl_line(0x5c) + 1244 .dwattr $C$DW$T$127, DW_AT_decl_column(0x18) + 1245 + 1246 + 1247 $C$DW$T$20 .dwtag DW_TAG_structure_type + 1248 .dwattr $C$DW$T$20, DW_AT_name("__timer") + 1249 .dwattr $C$DW$T$20, DW_AT_declaration + 1250 .dwattr $C$DW$T$20, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 1251 .dwattr $C$DW$T$20, DW_AT_decl_line(0x4b) + 1252 .dwattr $C$DW$T$20, DW_AT_decl_column(0x10) + 1253 .dwendtag $C$DW$T$20 + 1254 + 1255 $C$DW$T$128 .dwtag DW_TAG_pointer_type + 1256 .dwattr $C$DW$T$128, DW_AT_type(*$C$DW$T$20) + 1257 .dwattr $C$DW$T$128, DW_AT_address_class(0x10) + 1258 + 1259 $C$DW$T$129 .dwtag DW_TAG_typedef + 1260 .dwattr $C$DW$T$129, DW_AT_name("__timer_t") + 1261 .dwattr $C$DW$T$129, DW_AT_type(*$C$DW$T$128) + 1262 .dwattr $C$DW$T$129, DW_AT_language(DW_LANG_C) + 1263 .dwattr $C$DW$T$129, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LT + 1264 .dwattr $C$DW$T$129, DW_AT_decl_line(0x4b) + 1265 .dwattr $C$DW$T$129, DW_AT_decl_column(0x19) + 1266 + 1267 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C) + 1268 + 1269 ;*************************************************************** + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 25 + + 1270 ;* DWARF CIE ENTRIES * + 1271 ;*************************************************************** + 1272 + 1273 $C$DW$CIE .dwcie 16 + 1274 .dwcfi cfa_register, 1 + 1275 .dwcfi cfa_offset, 0 + 1276 .dwcfi same_value, 0 + 1277 .dwcfi same_value, 1 + 1278 .dwcfi same_value, 3 + 1279 .dwcfi same_value, 4 + 1280 .dwcfi same_value, 5 + 1281 .dwcfi same_value, 6 + 1282 .dwcfi same_value, 7 + 1283 .dwcfi same_value, 8 + 1284 .dwcfi same_value, 9 + 1285 .dwcfi same_value, 10 + 1286 .dwendentry + 1287 + 1288 ;*************************************************************** + 1289 ;* DWARF REGISTER MAP * + 1290 ;*************************************************************** + 1291 + 1292 $C$DW$32 .dwtag DW_TAG_TI_assign_register + 1293 .dwattr $C$DW$32, DW_AT_name("PC") + 1294 .dwattr $C$DW$32, DW_AT_location[DW_OP_reg0] + 1295 + 1296 $C$DW$33 .dwtag DW_TAG_TI_assign_register + 1297 .dwattr $C$DW$33, DW_AT_name("SP") + 1298 .dwattr $C$DW$33, DW_AT_location[DW_OP_reg1] + 1299 + 1300 $C$DW$34 .dwtag DW_TAG_TI_assign_register + 1301 .dwattr $C$DW$34, DW_AT_name("SR") + 1302 .dwattr $C$DW$34, DW_AT_location[DW_OP_reg2] + 1303 + 1304 $C$DW$35 .dwtag DW_TAG_TI_assign_register + 1305 .dwattr $C$DW$35, DW_AT_name("CG") + 1306 .dwattr $C$DW$35, DW_AT_location[DW_OP_reg3] + 1307 + 1308 $C$DW$36 .dwtag DW_TAG_TI_assign_register + 1309 .dwattr $C$DW$36, DW_AT_name("r4") + 1310 .dwattr $C$DW$36, DW_AT_location[DW_OP_reg4] + 1311 + 1312 $C$DW$37 .dwtag DW_TAG_TI_assign_register + 1313 .dwattr $C$DW$37, DW_AT_name("r5") + 1314 .dwattr $C$DW$37, DW_AT_location[DW_OP_reg5] + 1315 + 1316 $C$DW$38 .dwtag DW_TAG_TI_assign_register + 1317 .dwattr $C$DW$38, DW_AT_name("r6") + 1318 .dwattr $C$DW$38, DW_AT_location[DW_OP_reg6] + 1319 + 1320 $C$DW$39 .dwtag DW_TAG_TI_assign_register + 1321 .dwattr $C$DW$39, DW_AT_name("r7") + 1322 .dwattr $C$DW$39, DW_AT_location[DW_OP_reg7] + 1323 + 1324 $C$DW$40 .dwtag DW_TAG_TI_assign_register + MSP430 Assembler PC v20.2.5 Mon Aug 23 10:52:59 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{A7EDCDCA-598D-4880-9FB3-A8E795AAD2E9} PAGE 26 + + 1325 .dwattr $C$DW$40, DW_AT_name("r8") + 1326 .dwattr $C$DW$40, DW_AT_location[DW_OP_reg8] + 1327 + 1328 $C$DW$41 .dwtag DW_TAG_TI_assign_register + 1329 .dwattr $C$DW$41, DW_AT_name("r9") + 1330 .dwattr $C$DW$41, DW_AT_location[DW_OP_reg9] + 1331 + 1332 $C$DW$42 .dwtag DW_TAG_TI_assign_register + 1333 .dwattr $C$DW$42, DW_AT_name("r10") + 1334 .dwattr $C$DW$42, DW_AT_location[DW_OP_reg10] + 1335 + 1336 $C$DW$43 .dwtag DW_TAG_TI_assign_register + 1337 .dwattr $C$DW$43, DW_AT_name("r11") + 1338 .dwattr $C$DW$43, DW_AT_location[DW_OP_reg11] + 1339 + 1340 $C$DW$44 .dwtag DW_TAG_TI_assign_register + 1341 .dwattr $C$DW$44, DW_AT_name("r12") + 1342 .dwattr $C$DW$44, DW_AT_location[DW_OP_reg12] + 1343 + 1344 $C$DW$45 .dwtag DW_TAG_TI_assign_register + 1345 .dwattr $C$DW$45, DW_AT_name("r13") + 1346 .dwattr $C$DW$45, DW_AT_location[DW_OP_reg13] + 1347 + 1348 $C$DW$46 .dwtag DW_TAG_TI_assign_register + 1349 .dwattr $C$DW$46, DW_AT_name("r14") + 1350 .dwattr $C$DW$46, DW_AT_location[DW_OP_reg14] + 1351 + 1352 $C$DW$47 .dwtag DW_TAG_TI_assign_register + 1353 .dwattr $C$DW$47, DW_AT_name("r15") + 1354 .dwattr $C$DW$47, DW_AT_location[DW_OP_reg15] + 1355 + 1356 $C$DW$48 .dwtag DW_TAG_TI_assign_register + 1357 .dwattr $C$DW$48, DW_AT_name("CIE_RETA") + 1358 .dwattr $C$DW$48, DW_AT_location[DW_OP_reg16] + 1359 + 1360 .dwendtag $C$DW$CU + 1361 + +No Assembly Errors, No Assembly Warnings diff --git a/CPE325/Lab1_Problem1/Debug/Problem1a.d b/CPE325/Lab1_Problem1/Debug/Problem1a.d new file mode 100644 index 0000000..5c7463e --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/Problem1a.d @@ -0,0 +1,42 @@ +# FIXED + +Problem1a.obj: ../Problem1a.c +Problem1a.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +Problem1a.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h +Problem1a.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h +Problem1a.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h + +../Problem1a.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430f5529.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdio.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/_ti_config.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/linkage.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/stdarg.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/_types.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/sys/cdefs.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/machine/_types.h: + diff --git a/CPE325/Lab1_Problem1/Debug/Problem1a.lst b/CPE325/Lab1_Problem1/Debug/Problem1a.lst new file mode 100644 index 0000000..62de2b3 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/Problem1a.lst @@ -0,0 +1,1539 @@ +MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 1 + + 1 ;****************************************************************************** + 2 ;* MSP430 G3 C/C++ Codegen PC v20.2.5.LTS * + 3 ;* Date/Time created: Fri Aug 27 13:51:57 2021 * + 4 ;****************************************************************************** + 5 .compiler_opts --abi=eabi --diag_wrap=off --hll_source=on --mem_model:code=small --mem_model:d + 6 + 7 $C$DW$CU .dwtag DW_TAG_compile_unit + 8 .dwattr $C$DW$CU, DW_AT_name("../Problem1a.c") + 9 .dwattr $C$DW$CU, DW_AT_producer("TI MSP430 G3 C/C++ Codegen PC v20.2.5.LTS Copyright (c) 2003 + 10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + 11 .dwattr $C$DW$CU, DW_AT_comp_dir("C:\CPE325_Workspace\Lab1_Problem1\Debug") + 12 + 13 $C$DW$1 .dwtag DW_TAG_subprogram + 14 .dwattr $C$DW$1, DW_AT_name("printf") + 15 .dwattr $C$DW$1, DW_AT_TI_symbol_name("printf") + 16 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$10) + 17 .dwattr $C$DW$1, DW_AT_declaration + 18 .dwattr $C$DW$1, DW_AT_external + 19 .dwattr $C$DW$1, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/in + 20 .dwattr $C$DW$1, DW_AT_decl_line(0xf6) + 21 .dwattr $C$DW$1, DW_AT_decl_column(0x19) + 22 $C$DW$2 .dwtag DW_TAG_formal_parameter + 23 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$39) + 24 + 25 $C$DW$3 .dwtag DW_TAG_unspecified_parameters + 26 + 27 .dwendtag $C$DW$1 + 28 + 29 ; C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\bin\acpia430.exe -@C:\\Users\\LIBRAR + 30 000000 .sect ".text:main" + 31 .clink + 32 .global main + 33 + 34 $C$DW$4 .dwtag DW_TAG_subprogram + 35 .dwattr $C$DW$4, DW_AT_name("main") + 36 .dwattr $C$DW$4, DW_AT_low_pc(main) + 37 .dwattr $C$DW$4, DW_AT_high_pc(0x00) + 38 .dwattr $C$DW$4, DW_AT_TI_symbol_name("main") + 39 .dwattr $C$DW$4, DW_AT_external + 40 .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$10) + 41 .dwattr $C$DW$4, DW_AT_TI_begin_file("../Problem1a.c") + 42 .dwattr $C$DW$4, DW_AT_TI_begin_line(0x11) + 43 .dwattr $C$DW$4, DW_AT_TI_begin_column(0x05) + 44 .dwattr $C$DW$4, DW_AT_decl_file("../Problem1a.c") + 45 .dwattr $C$DW$4, DW_AT_decl_line(0x11) + 46 .dwattr $C$DW$4, DW_AT_decl_column(0x05) + 47 .dwattr $C$DW$4, DW_AT_TI_max_frame_size(0x14) + 48 .dwpsn file "../Problem1a.c",line 17,column 12,is_stmt,address main,isa 0 + 49 + 50 .dwfde $C$DW$CIE, main + 51 + 52 ;***************************************************************************** + 53 ;* FUNCTION NAME: main * + 54 ;* * + 55 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 2 + + 56 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 57 ;* Local Frame Size : 8 Args + 10 Auto + 0 Save = 18 byte * + 58 ;***************************************************************************** + 59 000000 main: + 60 ;* --------------------------------------------------------------------------* + 61 .dwcfi cfa_offset, 2 + 62 .dwcfi save_reg_to_mem, 16, -2 + 63 000000 8031 SUB.W #18,SP ; [] + 000002 0012 + 64 .dwcfi cfa_offset, 20 + 65 $C$DW$5 .dwtag DW_TAG_variable + 66 .dwattr $C$DW$5, DW_AT_name("first") + 67 .dwattr $C$DW$5, DW_AT_TI_symbol_name("first") + 68 .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$10) + 69 .dwattr $C$DW$5, DW_AT_location[DW_OP_breg1 8] + 70 + 71 $C$DW$6 .dwtag DW_TAG_variable + 72 .dwattr $C$DW$6, DW_AT_name("second") + 73 .dwattr $C$DW$6, DW_AT_TI_symbol_name("second") + 74 .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$10) + 75 .dwattr $C$DW$6, DW_AT_location[DW_OP_breg1 10] + 76 + 77 $C$DW$7 .dwtag DW_TAG_variable + 78 .dwattr $C$DW$7, DW_AT_name("counter") + 79 .dwattr $C$DW$7, DW_AT_TI_symbol_name("counter") + 80 .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$10) + 81 .dwattr $C$DW$7, DW_AT_location[DW_OP_breg1 12] + 82 + 83 $C$DW$8 .dwtag DW_TAG_variable + 84 .dwattr $C$DW$8, DW_AT_name("pr") + 85 .dwattr $C$DW$8, DW_AT_TI_symbol_name("pr") + 86 .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$10) + 87 .dwattr $C$DW$8, DW_AT_location[DW_OP_breg1 14] + 88 + 89 $C$DW$9 .dwtag DW_TAG_variable + 90 .dwattr $C$DW$9, DW_AT_name("product") + 91 .dwattr $C$DW$9, DW_AT_TI_symbol_name("product") + 92 .dwattr $C$DW$9, DW_AT_type(*$C$DW$T$10) + 93 .dwattr $C$DW$9, DW_AT_location[DW_OP_breg1 16] + 94 + 95 .dwpsn file "../Problem1a.c",line 19,column 12,is_stmt,isa 0 + 96 000004 42A1 MOV.W #4,8(SP) ; [] |19| + 000006 0008 + 97 .dwpsn file "../Problem1a.c",line 20,column 13,is_stmt,isa 0 + 98 000008 42B1 MOV.W #8,10(SP) ; [] |20| + 00000a 000A + 99 .dwpsn file "../Problem1a.c",line 21,column 14,is_stmt,isa 0 + 100 00000c 4381 MOV.W #0,12(SP) ; [] |21| + 00000e 000C + 101 .dwpsn file "../Problem1a.c",line 22,column 9,is_stmt,isa 0 + 102 000010 4381 MOV.W #0,14(SP) ; [] |22| + 000012 000E + 103 .dwpsn file "../Problem1a.c",line 23,column 14,is_stmt,isa 0 + 104 000014 4381 MOV.W #0,16(SP) ; [] |23| + 000016 0010 + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 3 + + 105 .dwpsn file "../Problem1a.c",line 25,column 2,is_stmt,isa 0 + 106 000018 411C MOV.W 8(SP),r12 ; [] |25| + 00001a 0008 + 107 00001c 411D MOV.W 10(SP),r13 ; [] |25| + 00001e 000A + 108 000020 411E MOV.W 12(SP),r14 ; [] |25| + 000022 000C + 109 000024 4E0F MOV.W r14,r15 ; [] + 110 $C$DW$10 .dwtag DW_TAG_TI_branch + 111 .dwattr $C$DW$10, DW_AT_low_pc(0x00) + 112 .dwattr $C$DW$10, DW_AT_name("prod") + 113 .dwattr $C$DW$10, DW_AT_TI_call + 114 + 115 000026 12B0 CALL #prod ; [] |25| + 000028 0000! + 116 ; [] |25| + 117 00002a 4C81 MOV.W r12,16(SP) ; [] |25| + 00002c 0010 + 118 .dwpsn file "../Problem1a.c",line 27,column 2,is_stmt,isa 0 + 119 00002e 40B1 MOV.W #$C$SL1+0,0(SP) ; [] |27| + 000030 0000! + 000032 0000 + 120 000034 4191 MOV.W 8(SP),2(SP) ; [] |27| + 000036 0008 + 000038 0002 + 121 00003a 4191 MOV.W 10(SP),4(SP) ; [] |27| + 00003c 000A + 00003e 0004 + 122 000040 4191 MOV.W 16(SP),6(SP) ; [] |27| + 000042 0010 + 000044 0006 + 123 $C$DW$11 .dwtag DW_TAG_TI_branch + 124 .dwattr $C$DW$11, DW_AT_low_pc(0x00) + 125 .dwattr $C$DW$11, DW_AT_name("printf") + 126 .dwattr $C$DW$11, DW_AT_TI_call + 127 + 128 000046 12B0 CALL #printf ; [] |27| + 000048 0000! + 129 ; [] |27| + 130 .dwpsn file "../Problem1a.c",line 28,column 1,is_stmt,isa 0 + 131 00004a 430C MOV.W #0,r12 ; [] |28| + 132 00004c 5031 ADD.W #18,SP ; [] + 00004e 0012 + 133 .dwcfi cfa_offset, 2 + 134 $C$DW$12 .dwtag DW_TAG_TI_branch + 135 .dwattr $C$DW$12, DW_AT_low_pc(0x00) + 136 .dwattr $C$DW$12, DW_AT_TI_return + 137 + 138 000050 4130 RET ; [] + 139 ; [] + 140 .dwattr $C$DW$4, DW_AT_TI_end_file("../Problem1a.c") + 141 .dwattr $C$DW$4, DW_AT_TI_end_line(0x1c) + 142 .dwattr $C$DW$4, DW_AT_TI_end_column(0x01) + 143 .dwendentry + 144 .dwendtag $C$DW$4 + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 4 + + 145 + 146 000000 .sect ".text:prod" + 147 .clink + 148 .global prod + 149 + 150 $C$DW$13 .dwtag DW_TAG_subprogram + 151 .dwattr $C$DW$13, DW_AT_name("prod") + 152 .dwattr $C$DW$13, DW_AT_low_pc(prod) + 153 .dwattr $C$DW$13, DW_AT_high_pc(0x00) + 154 .dwattr $C$DW$13, DW_AT_TI_symbol_name("prod") + 155 .dwattr $C$DW$13, DW_AT_external + 156 .dwattr $C$DW$13, DW_AT_type(*$C$DW$T$10) + 157 .dwattr $C$DW$13, DW_AT_TI_begin_file("../Problem1a.c") + 158 .dwattr $C$DW$13, DW_AT_TI_begin_line(0x1e) + 159 .dwattr $C$DW$13, DW_AT_TI_begin_column(0x05) + 160 .dwattr $C$DW$13, DW_AT_decl_file("../Problem1a.c") + 161 .dwattr $C$DW$13, DW_AT_decl_line(0x1e) + 162 .dwattr $C$DW$13, DW_AT_decl_column(0x05) + 163 .dwattr $C$DW$13, DW_AT_TI_max_frame_size(0x0a) + 164 .dwpsn file "../Problem1a.c",line 30,column 37,is_stmt,address prod,isa 0 + 165 + 166 .dwfde $C$DW$CIE, prod + 167 $C$DW$14 .dwtag DW_TAG_formal_parameter + 168 .dwattr $C$DW$14, DW_AT_name("f") + 169 .dwattr $C$DW$14, DW_AT_TI_symbol_name("f") + 170 .dwattr $C$DW$14, DW_AT_type(*$C$DW$T$10) + 171 .dwattr $C$DW$14, DW_AT_location[DW_OP_reg12] + 172 + 173 $C$DW$15 .dwtag DW_TAG_formal_parameter + 174 .dwattr $C$DW$15, DW_AT_name("s") + 175 .dwattr $C$DW$15, DW_AT_TI_symbol_name("s") + 176 .dwattr $C$DW$15, DW_AT_type(*$C$DW$T$10) + 177 .dwattr $C$DW$15, DW_AT_location[DW_OP_reg13] + 178 + 179 $C$DW$16 .dwtag DW_TAG_formal_parameter + 180 .dwattr $C$DW$16, DW_AT_name("c") + 181 .dwattr $C$DW$16, DW_AT_TI_symbol_name("c") + 182 .dwattr $C$DW$16, DW_AT_type(*$C$DW$T$10) + 183 .dwattr $C$DW$16, DW_AT_location[DW_OP_reg14] + 184 + 185 $C$DW$17 .dwtag DW_TAG_formal_parameter + 186 .dwattr $C$DW$17, DW_AT_name("p") + 187 .dwattr $C$DW$17, DW_AT_TI_symbol_name("p") + 188 .dwattr $C$DW$17, DW_AT_type(*$C$DW$T$10) + 189 .dwattr $C$DW$17, DW_AT_location[DW_OP_reg15] + 190 + 191 + 192 ;***************************************************************************** + 193 ;* FUNCTION NAME: prod * + 194 ;* * + 195 ;* Regs Modified : SP,SR,r11,r12,r13,r14,r15 * + 196 ;* Regs Used : SP,SR,r11,r12,r13,r14,r15 * + 197 ;* Local Frame Size : 0 Args + 8 Auto + 0 Save = 8 byte * + 198 ;***************************************************************************** + 199 000000 prod: + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 5 + + 200 ;* --------------------------------------------------------------------------* + 201 .dwcfi cfa_offset, 2 + 202 .dwcfi save_reg_to_mem, 16, -2 + 203 000000 8231 SUB.W #8,SP ; [] + 204 .dwcfi cfa_offset, 10 + 205 $C$DW$18 .dwtag DW_TAG_variable + 206 .dwattr $C$DW$18, DW_AT_name("f") + 207 .dwattr $C$DW$18, DW_AT_TI_symbol_name("f") + 208 .dwattr $C$DW$18, DW_AT_type(*$C$DW$T$10) + 209 .dwattr $C$DW$18, DW_AT_location[DW_OP_breg1 0] + 210 + 211 $C$DW$19 .dwtag DW_TAG_variable + 212 .dwattr $C$DW$19, DW_AT_name("s") + 213 .dwattr $C$DW$19, DW_AT_TI_symbol_name("s") + 214 .dwattr $C$DW$19, DW_AT_type(*$C$DW$T$10) + 215 .dwattr $C$DW$19, DW_AT_location[DW_OP_breg1 2] + 216 + 217 $C$DW$20 .dwtag DW_TAG_variable + 218 .dwattr $C$DW$20, DW_AT_name("c") + 219 .dwattr $C$DW$20, DW_AT_TI_symbol_name("c") + 220 .dwattr $C$DW$20, DW_AT_type(*$C$DW$T$10) + 221 .dwattr $C$DW$20, DW_AT_location[DW_OP_breg1 4] + 222 + 223 $C$DW$21 .dwtag DW_TAG_variable + 224 .dwattr $C$DW$21, DW_AT_name("p") + 225 .dwattr $C$DW$21, DW_AT_TI_symbol_name("p") + 226 .dwattr $C$DW$21, DW_AT_type(*$C$DW$T$10) + 227 .dwattr $C$DW$21, DW_AT_location[DW_OP_breg1 6] + 228 + 229 000002 4F81 MOV.W r15,6(SP) ; [] |30| + 000004 0006 + 230 000006 4E81 MOV.W r14,4(SP) ; [] |30| + 000008 0004 + 231 00000a 4D81 MOV.W r13,2(SP) ; [] |30| + 00000c 0002 + 232 00000e 4C81 MOV.W r12,0(SP) ; [] |30| + 000010 0000 + 233 .dwpsn file "../Problem1a.c",line 31,column 2,is_stmt,isa 0 + 234 000012 51A1 ADD.W 0(SP),6(SP) ; [] |31| + 000014 0006 + 235 .dwpsn file "../Problem1a.c",line 32,column 2,is_stmt,isa 0 + 236 000016 5391 ADD.W #1,4(SP) ; [] |32| + 000018 0004 + 237 .dwpsn file "../Problem1a.c",line 33,column 2,is_stmt,isa 0 + 238 00001a 9191 CMP.W 2(SP),4(SP) ; [] |33| + 00001c 0002 + 00001e 0004 + 239 000020 2408 JEQ $C$L1 ; [] |33| + 240 ; [] |33| + 241 ;* --------------------------------------------------------------------------* + 242 .dwpsn file "../Problem1a.c",line 33,column 12,is_stmt,isa 0 + 243 000022 411E MOV.W 4(SP),r14 ; [] |33| + 000024 0004 + 244 000026 411F MOV.W 6(SP),r15 ; [] |33| + 000028 0006 + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 6 + + 245 $C$DW$22 .dwtag DW_TAG_TI_branch + 246 .dwattr $C$DW$22, DW_AT_low_pc(0x00) + 247 .dwattr $C$DW$22, DW_AT_name("prod") + 248 .dwattr $C$DW$22, DW_AT_TI_call + 249 + 250 00002a 12B0 CALL #prod ; [] |33| + 00002c 0000! + 251 ; [] |33| + 252 00002e 4C81 MOV.W r12,6(SP) ; [] |33| + 000030 0006 + 253 ;* --------------------------------------------------------------------------* + 254 000032 $C$L1: + 255 .dwpsn file "../Problem1a.c",line 35,column 2,is_stmt,isa 0 + 256 000032 411C MOV.W 6(SP),r12 ; [] |35| + 000034 0006 + 257 .dwpsn file "../Problem1a.c",line 36,column 1,is_stmt,isa 0 + 258 000036 5231 ADD.W #8,SP ; [] + 259 .dwcfi cfa_offset, 2 + 260 $C$DW$23 .dwtag DW_TAG_TI_branch + 261 .dwattr $C$DW$23, DW_AT_low_pc(0x00) + 262 .dwattr $C$DW$23, DW_AT_TI_return + 263 + 264 000038 4130 RET ; [] + 265 ; [] + 266 .dwattr $C$DW$13, DW_AT_TI_end_file("../Problem1a.c") + 267 .dwattr $C$DW$13, DW_AT_TI_end_line(0x24) + 268 .dwattr $C$DW$13, DW_AT_TI_end_column(0x01) + 269 .dwendentry + 270 .dwendtag $C$DW$13 + 271 + 272 ;****************************************************************************** + 273 ;* STRINGS * + 274 ;****************************************************************************** + 275 000000 .sect ".const:.string" + 276 .align 2 + 277 000000 0025 $C$SL1: .string "%d times %d is %d",10,0 + 000001 0064 + 000002 0020 + 000003 0074 + 000004 0069 + 000005 006D + 000006 0065 + 000007 0073 + 000008 0020 + 000009 0025 + 00000a 0064 + 00000b 0020 + 00000c 0069 + 00000d 0073 + 00000e 0020 + 00000f 0025 + 000010 0064 + 000011 000A + 000012 0000 + 278 ;***************************************************************************** + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 7 + + 279 ;* UNDEFINED EXTERNAL REFERENCES * + 280 ;***************************************************************************** + 281 .global printf + 282 + 283 ;****************************************************************************** + 284 ;* BUILD ATTRIBUTES * + 285 ;****************************************************************************** + 286 .battr "TI", Tag_File, 1, Tag_LPM_INFO(1) + 287 .battr "TI", Tag_File, 1, Tag_PORTS_INIT_INFO("012345678901ABCDEFGHIJ0000000000001111000000000 + 288 .battr "TI", Tag_File, 1, Tag_LEA_INFO(1) + 289 .battr "TI", Tag_File, 1, Tag_HW_MPY32_INFO(2) + 290 .battr "TI", Tag_File, 1, Tag_HW_MPY_ISR_INFO(1) + 291 .battr "TI", Tag_File, 1, Tag_HW_MPY_INLINE_INFO(1) + 292 .battr "mspabi", Tag_File, 1, Tag_enum_size(3) + 293 + 294 ;****************************************************************************** + 295 ;* TYPE INFORMATION * + 296 ;****************************************************************************** + 297 + 298 $C$DW$T$21 .dwtag DW_TAG_structure_type + 299 .dwattr $C$DW$T$21, DW_AT_byte_size(0x10) + 300 $C$DW$24 .dwtag DW_TAG_member + 301 .dwattr $C$DW$24, DW_AT_type(*$C$DW$T$14) + 302 .dwattr $C$DW$24, DW_AT_name("__max_align1") + 303 .dwattr $C$DW$24, DW_AT_TI_symbol_name("__max_align1") + 304 .dwattr $C$DW$24, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + 305 .dwattr $C$DW$24, DW_AT_accessibility(DW_ACCESS_public) + 306 .dwattr $C$DW$24, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 307 .dwattr $C$DW$24, DW_AT_decl_line(0x7b) + 308 .dwattr $C$DW$24, DW_AT_decl_column(0x0c) + 309 + 310 $C$DW$25 .dwtag DW_TAG_member + 311 .dwattr $C$DW$25, DW_AT_type(*$C$DW$T$18) + 312 .dwattr $C$DW$25, DW_AT_name("__max_align2") + 313 .dwattr $C$DW$25, DW_AT_TI_symbol_name("__max_align2") + 314 .dwattr $C$DW$25, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 315 .dwattr $C$DW$25, DW_AT_accessibility(DW_ACCESS_public) + 316 .dwattr $C$DW$25, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/i + 317 .dwattr $C$DW$25, DW_AT_decl_line(0x7c) + 318 .dwattr $C$DW$25, DW_AT_decl_column(0x0e) + 319 + 320 .dwattr $C$DW$T$21, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 321 .dwattr $C$DW$T$21, DW_AT_decl_line(0x7a) + 322 .dwattr $C$DW$T$21, DW_AT_decl_column(0x10) + 323 .dwendtag $C$DW$T$21 + 324 + 325 $C$DW$T$24 .dwtag DW_TAG_typedef + 326 .dwattr $C$DW$T$24, DW_AT_name("__max_align_t") + 327 .dwattr $C$DW$T$24, DW_AT_type(*$C$DW$T$21) + 328 .dwattr $C$DW$T$24, DW_AT_language(DW_LANG_C) + 329 .dwattr $C$DW$T$24, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 330 .dwattr $C$DW$T$24, DW_AT_decl_line(0x7d) + 331 .dwattr $C$DW$T$24, DW_AT_decl_column(0x03) + 332 + 333 $C$DW$T$2 .dwtag DW_TAG_unspecified_type + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 8 + + 334 .dwattr $C$DW$T$2, DW_AT_name("void") + 335 + 336 + 337 $C$DW$T$25 .dwtag DW_TAG_subroutine_type + 338 .dwattr $C$DW$T$25, DW_AT_language(DW_LANG_C) + 339 .dwendtag $C$DW$T$25 + 340 + 341 $C$DW$T$26 .dwtag DW_TAG_pointer_type + 342 .dwattr $C$DW$T$26, DW_AT_type(*$C$DW$T$25) + 343 .dwattr $C$DW$T$26, DW_AT_address_class(0x10) + 344 + 345 $C$DW$T$27 .dwtag DW_TAG_typedef + 346 .dwattr $C$DW$T$27, DW_AT_name("__SFR_FARPTR") + 347 .dwattr $C$DW$T$27, DW_AT_type(*$C$DW$T$26) + 348 .dwattr $C$DW$T$27, DW_AT_language(DW_LANG_C) + 349 .dwattr $C$DW$T$27, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430f5529.h") + 350 .dwattr $C$DW$T$27, DW_AT_decl_line(0x4a) + 351 .dwattr $C$DW$T$27, DW_AT_decl_column(0x11) + 352 + 353 $C$DW$T$4 .dwtag DW_TAG_base_type + 354 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + 355 .dwattr $C$DW$T$4, DW_AT_name("bool") + 356 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01) + 357 + 358 $C$DW$T$5 .dwtag DW_TAG_base_type + 359 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char) + 360 .dwattr $C$DW$T$5, DW_AT_name("signed char") + 361 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01) + 362 + 363 $C$DW$T$28 .dwtag DW_TAG_typedef + 364 .dwattr $C$DW$T$28, DW_AT_name("__int8_t") + 365 .dwattr $C$DW$T$28, DW_AT_type(*$C$DW$T$5) + 366 .dwattr $C$DW$T$28, DW_AT_language(DW_LANG_C) + 367 .dwattr $C$DW$T$28, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 368 .dwattr $C$DW$T$28, DW_AT_decl_line(0x36) + 369 .dwattr $C$DW$T$28, DW_AT_decl_column(0x16) + 370 + 371 $C$DW$T$29 .dwtag DW_TAG_typedef + 372 .dwattr $C$DW$T$29, DW_AT_name("__int_least8_t") + 373 .dwattr $C$DW$T$29, DW_AT_type(*$C$DW$T$28) + 374 .dwattr $C$DW$T$29, DW_AT_language(DW_LANG_C) + 375 .dwattr $C$DW$T$29, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 376 .dwattr $C$DW$T$29, DW_AT_decl_line(0x5a) + 377 .dwattr $C$DW$T$29, DW_AT_decl_column(0x12) + 378 + 379 $C$DW$T$6 .dwtag DW_TAG_base_type + 380 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char) + 381 .dwattr $C$DW$T$6, DW_AT_name("unsigned char") + 382 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01) + 383 + 384 $C$DW$T$22 .dwtag DW_TAG_pointer_type + 385 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$6) + 386 .dwattr $C$DW$T$22, DW_AT_address_class(0x10) + 387 + 388 $C$DW$T$30 .dwtag DW_TAG_typedef + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 9 + + 389 .dwattr $C$DW$T$30, DW_AT_name("__uint8_t") + 390 .dwattr $C$DW$T$30, DW_AT_type(*$C$DW$T$6) + 391 .dwattr $C$DW$T$30, DW_AT_language(DW_LANG_C) + 392 .dwattr $C$DW$T$30, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 393 .dwattr $C$DW$T$30, DW_AT_decl_line(0x37) + 394 .dwattr $C$DW$T$30, DW_AT_decl_column(0x18) + 395 + 396 $C$DW$T$31 .dwtag DW_TAG_typedef + 397 .dwattr $C$DW$T$31, DW_AT_name("__sa_family_t") + 398 .dwattr $C$DW$T$31, DW_AT_type(*$C$DW$T$30) + 399 .dwattr $C$DW$T$31, DW_AT_language(DW_LANG_C) + 400 .dwattr $C$DW$T$31, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 401 .dwattr $C$DW$T$31, DW_AT_decl_line(0x47) + 402 .dwattr $C$DW$T$31, DW_AT_decl_column(0x13) + 403 + 404 $C$DW$T$32 .dwtag DW_TAG_typedef + 405 .dwattr $C$DW$T$32, DW_AT_name("__uint_least8_t") + 406 .dwattr $C$DW$T$32, DW_AT_type(*$C$DW$T$30) + 407 .dwattr $C$DW$T$32, DW_AT_language(DW_LANG_C) + 408 .dwattr $C$DW$T$32, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 409 .dwattr $C$DW$T$32, DW_AT_decl_line(0x74) + 410 .dwattr $C$DW$T$32, DW_AT_decl_column(0x13) + 411 + 412 $C$DW$T$7 .dwtag DW_TAG_base_type + 413 .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char) + 414 .dwattr $C$DW$T$7, DW_AT_name("wchar_t") + 415 .dwattr $C$DW$T$7, DW_AT_byte_size(0x02) + 416 + 417 $C$DW$T$8 .dwtag DW_TAG_base_type + 418 .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed) + 419 .dwattr $C$DW$T$8, DW_AT_name("short") + 420 .dwattr $C$DW$T$8, DW_AT_byte_size(0x02) + 421 + 422 $C$DW$T$9 .dwtag DW_TAG_base_type + 423 .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned) + 424 .dwattr $C$DW$T$9, DW_AT_name("unsigned short") + 425 .dwattr $C$DW$T$9, DW_AT_byte_size(0x02) + 426 + 427 $C$DW$T$10 .dwtag DW_TAG_base_type + 428 .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed) + 429 .dwattr $C$DW$T$10, DW_AT_name("int") + 430 .dwattr $C$DW$T$10, DW_AT_byte_size(0x02) + 431 + 432 $C$DW$T$33 .dwtag DW_TAG_typedef + 433 .dwattr $C$DW$T$33, DW_AT_name("_Mbstatet") + 434 .dwattr $C$DW$T$33, DW_AT_type(*$C$DW$T$10) + 435 .dwattr $C$DW$T$33, DW_AT_language(DW_LANG_C) + 436 .dwattr $C$DW$T$33, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 437 .dwattr $C$DW$T$33, DW_AT_decl_line(0x8f) + 438 .dwattr $C$DW$T$33, DW_AT_decl_column(0x0d) + 439 + 440 $C$DW$T$34 .dwtag DW_TAG_typedef + 441 .dwattr $C$DW$T$34, DW_AT_name("__mbstate_t") + 442 .dwattr $C$DW$T$34, DW_AT_type(*$C$DW$T$33) + 443 .dwattr $C$DW$T$34, DW_AT_language(DW_LANG_C) + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 10 + + 444 .dwattr $C$DW$T$34, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 445 .dwattr $C$DW$T$34, DW_AT_decl_line(0x92) + 446 .dwattr $C$DW$T$34, DW_AT_decl_column(0x13) + 447 + 448 $C$DW$T$35 .dwtag DW_TAG_typedef + 449 .dwattr $C$DW$T$35, DW_AT_name("__accmode_t") + 450 .dwattr $C$DW$T$35, DW_AT_type(*$C$DW$T$10) + 451 .dwattr $C$DW$T$35, DW_AT_language(DW_LANG_C) + 452 .dwattr $C$DW$T$35, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 453 .dwattr $C$DW$T$35, DW_AT_decl_line(0x3b) + 454 .dwattr $C$DW$T$35, DW_AT_decl_column(0x0e) + 455 + 456 $C$DW$T$45 .dwtag DW_TAG_typedef + 457 .dwattr $C$DW$T$45, DW_AT_name("__cpulevel_t") + 458 .dwattr $C$DW$T$45, DW_AT_type(*$C$DW$T$10) + 459 .dwattr $C$DW$T$45, DW_AT_language(DW_LANG_C) + 460 .dwattr $C$DW$T$45, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 461 .dwattr $C$DW$T$45, DW_AT_decl_line(0x50) + 462 .dwattr $C$DW$T$45, DW_AT_decl_column(0x0e) + 463 + 464 $C$DW$T$46 .dwtag DW_TAG_typedef + 465 .dwattr $C$DW$T$46, DW_AT_name("__cpusetid_t") + 466 .dwattr $C$DW$T$46, DW_AT_type(*$C$DW$T$10) + 467 .dwattr $C$DW$T$46, DW_AT_language(DW_LANG_C) + 468 .dwattr $C$DW$T$46, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 469 .dwattr $C$DW$T$46, DW_AT_decl_line(0x51) + 470 .dwattr $C$DW$T$46, DW_AT_decl_column(0x0e) + 471 + 472 $C$DW$T$47 .dwtag DW_TAG_typedef + 473 .dwattr $C$DW$T$47, DW_AT_name("__cpuwhich_t") + 474 .dwattr $C$DW$T$47, DW_AT_type(*$C$DW$T$10) + 475 .dwattr $C$DW$T$47, DW_AT_language(DW_LANG_C) + 476 .dwattr $C$DW$T$47, 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DW_TAG_typedef + 497 .dwattr $C$DW$T$50, DW_AT_name("__wint_t") + 498 .dwattr $C$DW$T$50, DW_AT_type(*$C$DW$T$48) + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 11 + + 499 .dwattr $C$DW$T$50, DW_AT_language(DW_LANG_C) + 500 .dwattr $C$DW$T$50, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 501 .dwattr $C$DW$T$50, DW_AT_decl_line(0x6d) + 502 .dwattr $C$DW$T$50, DW_AT_decl_column(0x15) + 503 + 504 $C$DW$T$51 .dwtag DW_TAG_typedef + 505 .dwattr $C$DW$T$51, DW_AT_name("__int16_t") + 506 .dwattr $C$DW$T$51, DW_AT_type(*$C$DW$T$10) + 507 .dwattr $C$DW$T$51, DW_AT_language(DW_LANG_C) + 508 .dwattr $C$DW$T$51, DW_AT_decl_file("C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + 509 .dwattr $C$DW$T$51, DW_AT_decl_line(0x38) + 510 .dwattr $C$DW$T$51, DW_AT_decl_column(0x0f) + 511 + 512 $C$DW$T$52 .dwtag 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;*************************************************************** + 1266 + 1267 $C$DW$CIE .dwcie 16 + 1268 .dwcfi cfa_register, 1 + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 25 + + 1269 .dwcfi cfa_offset, 0 + 1270 .dwcfi same_value, 0 + 1271 .dwcfi same_value, 1 + 1272 .dwcfi same_value, 3 + 1273 .dwcfi same_value, 4 + 1274 .dwcfi same_value, 5 + 1275 .dwcfi same_value, 6 + 1276 .dwcfi same_value, 7 + 1277 .dwcfi same_value, 8 + 1278 .dwcfi same_value, 9 + 1279 .dwcfi same_value, 10 + 1280 .dwendentry + 1281 + 1282 ;*************************************************************** + 1283 ;* DWARF REGISTER MAP * + 1284 ;*************************************************************** + 1285 + 1286 $C$DW$32 .dwtag DW_TAG_TI_assign_register + 1287 .dwattr $C$DW$32, DW_AT_name("PC") + 1288 .dwattr $C$DW$32, DW_AT_location[DW_OP_reg0] + 1289 + 1290 $C$DW$33 .dwtag DW_TAG_TI_assign_register + 1291 .dwattr $C$DW$33, DW_AT_name("SP") + 1292 .dwattr $C$DW$33, DW_AT_location[DW_OP_reg1] + 1293 + 1294 $C$DW$34 .dwtag DW_TAG_TI_assign_register + 1295 .dwattr $C$DW$34, DW_AT_name("SR") + 1296 .dwattr $C$DW$34, DW_AT_location[DW_OP_reg2] + 1297 + 1298 $C$DW$35 .dwtag DW_TAG_TI_assign_register + 1299 .dwattr $C$DW$35, DW_AT_name("CG") + 1300 .dwattr $C$DW$35, DW_AT_location[DW_OP_reg3] + 1301 + 1302 $C$DW$36 .dwtag DW_TAG_TI_assign_register + 1303 .dwattr $C$DW$36, DW_AT_name("r4") + 1304 .dwattr $C$DW$36, DW_AT_location[DW_OP_reg4] + 1305 + 1306 $C$DW$37 .dwtag DW_TAG_TI_assign_register + 1307 .dwattr $C$DW$37, DW_AT_name("r5") + 1308 .dwattr $C$DW$37, DW_AT_location[DW_OP_reg5] + 1309 + 1310 $C$DW$38 .dwtag DW_TAG_TI_assign_register + 1311 .dwattr $C$DW$38, DW_AT_name("r6") + 1312 .dwattr $C$DW$38, DW_AT_location[DW_OP_reg6] + 1313 + 1314 $C$DW$39 .dwtag DW_TAG_TI_assign_register + 1315 .dwattr $C$DW$39, DW_AT_name("r7") + 1316 .dwattr $C$DW$39, DW_AT_location[DW_OP_reg7] + 1317 + 1318 $C$DW$40 .dwtag DW_TAG_TI_assign_register + 1319 .dwattr $C$DW$40, DW_AT_name("r8") + 1320 .dwattr $C$DW$40, DW_AT_location[DW_OP_reg8] + 1321 + 1322 $C$DW$41 .dwtag DW_TAG_TI_assign_register + 1323 .dwattr $C$DW$41, DW_AT_name("r9") + MSP430 Assembler PC v20.2.5 Fri Aug 27 13:51:57 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{C5D659B1-256F-488C-8D8B-384A069659A3} PAGE 26 + + 1324 .dwattr $C$DW$41, DW_AT_location[DW_OP_reg9] + 1325 + 1326 $C$DW$42 .dwtag DW_TAG_TI_assign_register + 1327 .dwattr $C$DW$42, DW_AT_name("r10") + 1328 .dwattr $C$DW$42, DW_AT_location[DW_OP_reg10] + 1329 + 1330 $C$DW$43 .dwtag DW_TAG_TI_assign_register + 1331 .dwattr $C$DW$43, DW_AT_name("r11") + 1332 .dwattr $C$DW$43, DW_AT_location[DW_OP_reg11] + 1333 + 1334 $C$DW$44 .dwtag DW_TAG_TI_assign_register + 1335 .dwattr $C$DW$44, DW_AT_name("r12") + 1336 .dwattr $C$DW$44, DW_AT_location[DW_OP_reg12] + 1337 + 1338 $C$DW$45 .dwtag DW_TAG_TI_assign_register + 1339 .dwattr $C$DW$45, DW_AT_name("r13") + 1340 .dwattr $C$DW$45, DW_AT_location[DW_OP_reg13] + 1341 + 1342 $C$DW$46 .dwtag DW_TAG_TI_assign_register + 1343 .dwattr $C$DW$46, DW_AT_name("r14") + 1344 .dwattr $C$DW$46, DW_AT_location[DW_OP_reg14] + 1345 + 1346 $C$DW$47 .dwtag DW_TAG_TI_assign_register + 1347 .dwattr $C$DW$47, DW_AT_name("r15") + 1348 .dwattr $C$DW$47, DW_AT_location[DW_OP_reg15] + 1349 + 1350 $C$DW$48 .dwtag DW_TAG_TI_assign_register + 1351 .dwattr $C$DW$48, DW_AT_name("CIE_RETA") + 1352 .dwattr $C$DW$48, DW_AT_location[DW_OP_reg16] + 1353 + 1354 .dwendtag $C$DW$CU + 1355 + +No Assembly Errors, No Assembly Warnings diff --git a/CPE325/Lab1_Problem1/Debug/ccsObjs.opt b/CPE325/Lab1_Problem1/Debug/ccsObjs.opt new file mode 100644 index 0000000..c3038ce --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./P1a.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/Lab1_Problem1/Debug/for.d b/CPE325/Lab1_Problem1/Debug/for.d new file mode 100644 index 0000000..ae195ba --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/for.d @@ -0,0 +1,6 @@ +# FIXED + +for.obj: ../for.c + +../for.c: + diff --git a/CPE325/Lab1_Problem1/Debug/for.lst b/CPE325/Lab1_Problem1/Debug/for.lst new file mode 100644 index 0000000..7fbf6f0 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/for.lst @@ -0,0 +1,119 @@ +MSP430 Assembler PC v20.2.5 Sun Aug 22 14:01:15 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{D9BF6471-3FB4-4F61-BC55-D1489D24AE1E} PAGE 1 + + 1 ;****************************************************************************** + 2 ;* MSP430 G3 C/C++ Codegen PC v20.2.5.LTS * + 3 ;* Date/Time created: Sun Aug 22 14:01:15 2021 * + 4 ;****************************************************************************** + 5 .compiler_opts --abi=eabi --diag_wrap=off --hll_source=on --mem_model:code=small --mem_model:d + 6 + 7 $C$DW$CU .dwtag DW_TAG_compile_unit + 8 .dwattr $C$DW$CU, DW_AT_name("../for.c") + 9 .dwattr $C$DW$CU, DW_AT_producer("TI MSP430 G3 C/C++ Codegen PC v20.2.5.LTS Copyright (c) 2003 + 10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + 11 .dwattr $C$DW$CU, DW_AT_comp_dir("C:\CPE325_Workspace\Lab1_Problem1\Debug") + 12 ; C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\bin\acpia430.exe -@C:\\Users\\LIBRAR + 13 + 14 ;****************************************************************************** + 15 ;* BUILD ATTRIBUTES * + 16 ;****************************************************************************** + 17 .battr "TI", Tag_File, 1, Tag_LPM_INFO(1) + 18 .battr "TI", Tag_File, 1, Tag_PORTS_INIT_INFO("012345678901ABCDEFGHIJ0000000000000000000000000 + 19 .battr "TI", Tag_File, 1, Tag_LEA_INFO(1) + 20 .battr "TI", Tag_File, 1, Tag_HW_MPY32_INFO(1) + 21 .battr "TI", Tag_File, 1, Tag_HW_MPY_ISR_INFO(1) + 22 .battr "TI", Tag_File, 1, Tag_HW_MPY_INLINE_INFO(1) + 23 .battr "mspabi", Tag_File, 1, Tag_enum_size(3) + 24 + 25 ;****************************************************************************** + 26 ;* TYPE INFORMATION * + 27 ;****************************************************************************** + 28 $C$DW$T$2 .dwtag DW_TAG_unspecified_type + 29 .dwattr $C$DW$T$2, DW_AT_name("void") + 30 + 31 $C$DW$T$4 .dwtag DW_TAG_base_type + 32 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + 33 .dwattr $C$DW$T$4, DW_AT_name("bool") + 34 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01) + 35 + 36 $C$DW$T$5 .dwtag DW_TAG_base_type + 37 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char) + 38 .dwattr $C$DW$T$5, DW_AT_name("signed char") + 39 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01) + 40 + 41 $C$DW$T$6 .dwtag DW_TAG_base_type + 42 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char) + 43 .dwattr $C$DW$T$6, DW_AT_name("unsigned char") + 44 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01) + 45 + 46 $C$DW$T$7 .dwtag DW_TAG_base_type + 47 .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char) + 48 .dwattr $C$DW$T$7, DW_AT_name("wchar_t") + 49 .dwattr $C$DW$T$7, DW_AT_byte_size(0x02) + 50 + 51 $C$DW$T$8 .dwtag DW_TAG_base_type + 52 .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed) + 53 .dwattr $C$DW$T$8, DW_AT_name("short") + 54 .dwattr $C$DW$T$8, DW_AT_byte_size(0x02) + 55 + MSP430 Assembler PC v20.2.5 Sun Aug 22 14:01:15 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{D9BF6471-3FB4-4F61-BC55-D1489D24AE1E} PAGE 2 + + 56 $C$DW$T$9 .dwtag DW_TAG_base_type + 57 .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned) + 58 .dwattr $C$DW$T$9, DW_AT_name("unsigned short") + 59 .dwattr $C$DW$T$9, DW_AT_byte_size(0x02) + 60 + 61 $C$DW$T$10 .dwtag DW_TAG_base_type + 62 .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed) + 63 .dwattr $C$DW$T$10, DW_AT_name("int") + 64 .dwattr $C$DW$T$10, DW_AT_byte_size(0x02) + 65 + 66 $C$DW$T$11 .dwtag DW_TAG_base_type + 67 .dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned) + 68 .dwattr $C$DW$T$11, DW_AT_name("unsigned int") + 69 .dwattr $C$DW$T$11, DW_AT_byte_size(0x02) + 70 + 71 $C$DW$T$12 .dwtag DW_TAG_base_type + 72 .dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed) + 73 .dwattr $C$DW$T$12, DW_AT_name("long") + 74 .dwattr $C$DW$T$12, DW_AT_byte_size(0x04) + 75 + 76 $C$DW$T$13 .dwtag DW_TAG_base_type + 77 .dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned) + 78 .dwattr $C$DW$T$13, DW_AT_name("unsigned long") + 79 .dwattr $C$DW$T$13, DW_AT_byte_size(0x04) + 80 + 81 $C$DW$T$14 .dwtag DW_TAG_base_type + 82 .dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed) + 83 .dwattr $C$DW$T$14, DW_AT_name("long long") + 84 .dwattr $C$DW$T$14, DW_AT_byte_size(0x08) + 85 + 86 $C$DW$T$15 .dwtag DW_TAG_base_type + 87 .dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned) + 88 .dwattr $C$DW$T$15, DW_AT_name("unsigned long long") + 89 .dwattr $C$DW$T$15, DW_AT_byte_size(0x08) + 90 + 91 $C$DW$T$16 .dwtag DW_TAG_base_type + 92 .dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float) + 93 .dwattr $C$DW$T$16, DW_AT_name("float") + 94 .dwattr $C$DW$T$16, DW_AT_byte_size(0x04) + 95 + 96 $C$DW$T$17 .dwtag DW_TAG_base_type + 97 .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float) + 98 .dwattr $C$DW$T$17, DW_AT_name("double") + 99 .dwattr $C$DW$T$17, DW_AT_byte_size(0x08) + 100 + 101 $C$DW$T$18 .dwtag DW_TAG_base_type + 102 .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float) + 103 .dwattr $C$DW$T$18, DW_AT_name("long double") + 104 .dwattr $C$DW$T$18, DW_AT_byte_size(0x08) + 105 + 106 .dwendtag $C$DW$CU + 107 + +No Assembly Errors, No Assembly Warnings diff --git a/CPE325/Lab1_Problem1/Debug/makefile b/CPE325/Lab1_Problem1/Debug/makefile new file mode 100644 index 0000000..dc214f9 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/makefile @@ -0,0 +1,168 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./P1a.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab1_Problem1.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab1_Problem1.out" \ + +BIN_OUTPUTS += \ +Lab1_Problem1.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab1_Problem1.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab1_Problem1.out" + +# Tool invocations +Lab1_Problem1.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --advice:power=all --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing -z -m"Lab1_Problem1.map" --heap_size=300 --stack_size=160 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab1_Problem1_linkInfo.xml" --use_hw_mpy=F5 --rom_model -o "Lab1_Problem1.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab1_Problem1.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab1_Problem1.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "P1a.lst" + -$(RM) "P1a.obj" + -$(RM) "P1a.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab1_Problem1/Debug/objects.mk b/CPE325/Lab1_Problem1/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/Lab1_Problem1/Debug/sources.mk b/CPE325/Lab1_Problem1/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab1_Problem1/Debug/subdir_rules.mk b/CPE325/Lab1_Problem1/Debug/subdir_rules.mk new file mode 100644 index 0000000..fa9aff4 --- /dev/null +++ b/CPE325/Lab1_Problem1/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab1_Problem1" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430F5529__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --asm_listing --preproc_with_compile --preproc_dependency="$(basename $( +#include +int prod(int f, int s, int c, int p); + +int main() { + + //Intialize variables + int first = 4; + int second = 8; + int counter = 0; + int pr = 0; + int product = 0; + //Call loop + product =prod(first,second,counter,pr); + //Print output + printf ("%d times %d is %d\n", first,second,product); +} + +int prod(int f, int s, int c, int p){ + p =p+ f; //Add first number to product + c=c+1; //Increment counter by 1 + if (c!=s) p= prod(f,s,c,p); // If counter is not equal to the second number, + // call the function agian + return p; +} + diff --git a/CPE325/Lab1_Problem1/lnk_msp430f5529.cmd b/CPE325/Lab1_Problem1/lnk_msp430f5529.cmd new file mode 100755 index 0000000..d595380 --- /dev/null +++ b/CPE325/Lab1_Problem1/lnk_msp430f5529.cmd @@ -0,0 +1,251 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************************/ +/* lnk_msp430f5529.cmd - LINKER COMMAND FILE FOR LINKING MSP430F5529 PROGRAMS */ +/* */ +/* Usage: lnk430 -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/Lab1_Problem1/targetConfigs/MSP430F5529.ccxml b/CPE325/Lab1_Problem1/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/Lab1_Problem1/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab1_Problem1/targetConfigs/readme.txt b/CPE325/Lab1_Problem1/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab1_Problem1/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab4_Problem1/Debug/Lab4.map b/CPE325/Lab4_Problem1/Debug/Lab4.map new file mode 100644 index 0000000..985ed4e --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/Lab4.map @@ -0,0 +1,1760 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Sep 10 13:42:44 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "RESET" address: 0000441e + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 00000000 00002000 RWIX + FLASH 00004400 0000bb80 0000005a 0000bb26 RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000000 00000002 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.stack 0 00004400 00000000 + +.text 0 00004400 00000052 + 00004400 00000048 Lab04_D1.obj (.text) + 00004448 0000000a main.obj (.text) + +.text:_isr +* 0 00004452 00000008 + 00004452 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00004400 00000000 UNINITIALIZED + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +.reset 0 00000000 00000004 FAILED TO ALLOCATE +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + Lab04_D1.obj 72 0 0 + main.obj 10 0 0 + +--+------------------+------+---------+---------+ + Total: 82 0 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + isr_trap.asm.obj 8 0 0 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + +--+------------------+------+---------+---------+ + Total: 8 44 0 + + +--+------------------+------+---------+---------+ + Grand Total: 90 44 0 + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +0000441e RESET +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +00000902 USBCNF +00000903 USBCNF_H +00000902 USBCNF_L +0000093c USBCTL +0000093a USBFN +0000093b USBFN_H +0000093a USBFN_L +0000093f USBFUNADR +0000093d USBIE +00002378 USBIEP0BUF +000023c9 USBIEPBBAX_1 +000023d1 USBIEPBBAX_2 +000023d9 USBIEPBBAX_3 +000023e1 USBIEPBBAX_4 +000023e9 USBIEPBBAX_5 +000023f1 USBIEPBBAX_6 +000023f9 USBIEPBBAX_7 +000023cd USBIEPBBAY_1 +000023d5 USBIEPBBAY_2 +000023dd USBIEPBBAY_3 +000023e5 USBIEPBBAY_4 +000023ed USBIEPBBAY_5 +000023f5 USBIEPBBAY_6 +000023fd USBIEPBBAY_7 +000023ca USBIEPBCTX_1 +000023d2 USBIEPBCTX_2 +000023da USBIEPBCTX_3 +000023e2 USBIEPBCTX_4 +000023ea USBIEPBCTX_5 +000023f2 USBIEPBCTX_6 +000023fa USBIEPBCTX_7 +000023ce USBIEPBCTY_1 +000023d6 USBIEPBCTY_2 +000023de USBIEPBCTY_3 +000023e6 USBIEPBCTY_4 +000023ee USBIEPBCTY_5 +000023f6 USBIEPBCTY_6 +000023fe USBIEPBCTY_7 +00000920 USBIEPCNF_0 +000023c8 USBIEPCNF_1 +000023d0 USBIEPCNF_2 +000023d8 USBIEPCNF_3 +000023e0 USBIEPCNF_4 +000023e8 USBIEPCNF_5 +000023f0 USBIEPCNF_6 +000023f8 USBIEPCNF_7 +00000921 USBIEPCNT_0 +0000092e USBIEPIE +00000930 USBIEPIFG +000023cf USBIEPSIZXY_1 +000023d7 USBIEPSIZXY_2 +000023df USBIEPSIZXY_3 +000023e7 USBIEPSIZXY_4 +000023ef USBIEPSIZXY_5 +000023f7 USBIEPSIZXY_6 +000023ff USBIEPSIZXY_7 +0000093e USBIFG +00000900 USBKEYID +00000901 USBKEYID_H +00000900 USBKEYID_L +00000936 USBMAINT +00000937 USBMAINT_H +00000936 USBMAINT_L +00002370 USBOEP0BUF +00002389 USBOEPBBAX_1 +00002391 USBOEPBBAX_2 +00002399 USBOEPBBAX_3 +000023a1 USBOEPBBAX_4 +000023a9 USBOEPBBAX_5 +000023b1 USBOEPBBAX_6 +000023b9 USBOEPBBAX_7 +0000238d USBOEPBBAY_1 +00002395 USBOEPBBAY_2 +0000239d USBOEPBBAY_3 +000023a5 USBOEPBBAY_4 +000023ad USBOEPBBAY_5 +000023b5 USBOEPBBAY_6 +000023bd USBOEPBBAY_7 +0000238a USBOEPBCTX_1 +00002392 USBOEPBCTX_2 +0000239a USBOEPBCTX_3 +000023a2 USBOEPBCTX_4 +000023aa USBOEPBCTX_5 +000023b2 USBOEPBCTX_6 +000023ba USBOEPBCTX_7 +0000238e USBOEPBCTY_1 +00002396 USBOEPBCTY_2 +0000239e USBOEPBCTY_3 +000023a6 USBOEPBCTY_4 +000023ae USBOEPBCTY_5 +000023b6 USBOEPBCTY_6 +000023be USBOEPBCTY_7 +00000922 USBOEPCNF_0 +00002388 USBOEPCNF_1 +00002390 USBOEPCNF_2 +00002398 USBOEPCNF_3 +000023a0 USBOEPCNF_4 +000023a8 USBOEPCNF_5 +000023b0 USBOEPCNF_6 +000023b8 USBOEPCNF_7 +00000923 USBOEPCNT_0 +0000092f USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +00004400 __STACK_END +00000000 __STACK_SIZE +00004452 __TI_ISR_TRAP +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +00000000 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H +00000726 ADC12MEM3 +00000726 ADC12MEM3_L +00000727 ADC12MEM3_H +00000728 ADC12MEM4 +00000728 ADC12MEM4_L +00000729 ADC12MEM4_H +0000072a ADC12MEM5 +0000072a ADC12MEM5_L +0000072b ADC12MEM5_H +0000072c ADC12MEM6 +0000072c ADC12MEM6_L +0000072d ADC12MEM6_H +0000072e ADC12MEM7 +0000072e ADC12MEM7_L +0000072f ADC12MEM7_H +00000730 ADC12MEM8 +00000730 ADC12MEM8_L +00000731 ADC12MEM8_H +00000732 ADC12MEM9 +00000732 ADC12MEM9_L +00000733 ADC12MEM9_H +00000734 ADC12MEM10 +00000734 ADC12MEM10_L +00000735 ADC12MEM10_H +00000736 ADC12MEM11 +00000736 ADC12MEM11_L +00000737 ADC12MEM11_H +00000738 ADC12MEM12 +00000738 ADC12MEM12_L +00000739 ADC12MEM12_H +0000073a ADC12MEM13 +0000073a ADC12MEM13_L +0000073b ADC12MEM13_H +0000073c ADC12MEM14 +0000073c ADC12MEM14_L +0000073d ADC12MEM14_H +0000073e ADC12MEM15 +0000073e ADC12MEM15_L +0000073f ADC12MEM15_H +000008c0 CBCTL0 +000008c0 CBCTL0_L +000008c1 CBCTL0_H +000008c2 CBCTL1 +000008c2 CBCTL1_L +000008c3 CBCTL1_H +000008c4 CBCTL2 +000008c4 CBCTL2_L +000008c5 CBCTL2_H +000008c6 CBCTL3 +000008c6 CBCTL3_L +000008c7 CBCTL3_H +000008cc CBINT +000008cc CBINT_L +000008cd CBINT_H +000008ce CBIV +00000900 USBKEYID +00000900 USBKEYID_L +00000901 USBKEYID_H +00000902 USBCNF +00000902 USBCNF_L +00000903 USBCNF_H +00000904 USBPHYCTL +00000904 USBPHYCTL_L +00000905 USBPHYCTL_H +00000908 USBPWRCTL +00000908 USBPWRCTL_L +00000909 USBPWRCTL_H +00000910 USBPLLCTL +00000910 USBPLLCTL_L +00000911 USBPLLCTL_H +00000912 USBPLLDIVB +00000912 USBPLLDIVB_L +00000913 USBPLLDIVB_H +00000914 USBPLLIR +00000914 USBPLLIR_L +00000915 USBPLLIR_H +00000920 USBIEPCNF_0 +00000921 USBIEPCNT_0 +00000922 USBOEPCNF_0 +00000923 USBOEPCNT_0 +0000092e USBIEPIE +0000092f USBOEPIE +00000930 USBIEPIFG +00000931 USBOEPIFG +00000932 USBVECINT +00000932 USBVECINT_L +00000933 USBVECINT_H +00000936 USBMAINT +00000936 USBMAINT_L +00000937 USBMAINT_H +00000938 USBTSREG +00000938 USBTSREG_L +00000939 USBTSREG_H +0000093a USBFN +0000093a USBFN_L +0000093b USBFN_H +0000093c USBCTL +0000093d USBIE +0000093e USBIFG +0000093f USBFUNADR +00001c00 USBSTABUFF +0000236f USBTOPBUFF +00002370 USBOEP0BUF +00002378 USBIEP0BUF +00002380 USBSUBLK +00002388 USBOEPCNF_1 +00002389 USBOEPBBAX_1 +0000238a USBOEPBCTX_1 +0000238d USBOEPBBAY_1 +0000238e USBOEPBCTY_1 +0000238f USBOEPSIZXY_1 +00002390 USBOEPCNF_2 +00002391 USBOEPBBAX_2 +00002392 USBOEPBCTX_2 +00002395 USBOEPBBAY_2 +00002396 USBOEPBCTY_2 +00002397 USBOEPSIZXY_2 +00002398 USBOEPCNF_3 +00002399 USBOEPBBAX_3 +0000239a USBOEPBCTX_3 +0000239d USBOEPBBAY_3 +0000239e USBOEPBCTY_3 +0000239f USBOEPSIZXY_3 +000023a0 USBOEPCNF_4 +000023a1 USBOEPBBAX_4 +000023a2 USBOEPBCTX_4 +000023a5 USBOEPBBAY_4 +000023a6 USBOEPBCTY_4 +000023a7 USBOEPSIZXY_4 +000023a8 USBOEPCNF_5 +000023a9 USBOEPBBAX_5 +000023aa USBOEPBCTX_5 +000023ad USBOEPBBAY_5 +000023ae USBOEPBCTY_5 +000023af USBOEPSIZXY_5 +000023b0 USBOEPCNF_6 +000023b1 USBOEPBBAX_6 +000023b2 USBOEPBCTX_6 +000023b5 USBOEPBBAY_6 +000023b6 USBOEPBCTY_6 +000023b7 USBOEPSIZXY_6 +000023b8 USBOEPCNF_7 +000023b9 USBOEPBBAX_7 +000023ba USBOEPBCTX_7 +000023bd USBOEPBBAY_7 +000023be USBOEPBCTY_7 +000023bf USBOEPSIZXY_7 +000023c8 USBIEPCNF_1 +000023c9 USBIEPBBAX_1 +000023ca USBIEPBCTX_1 +000023cd USBIEPBBAY_1 +000023ce USBIEPBCTY_1 +000023cf USBIEPSIZXY_1 +000023d0 USBIEPCNF_2 +000023d1 USBIEPBBAX_2 +000023d2 USBIEPBCTX_2 +000023d5 USBIEPBBAY_2 +000023d6 USBIEPBCTY_2 +000023d7 USBIEPSIZXY_2 +000023d8 USBIEPCNF_3 +000023d9 USBIEPBBAX_3 +000023da USBIEPBCTX_3 +000023dd USBIEPBBAY_3 +000023de USBIEPBCTY_3 +000023df USBIEPSIZXY_3 +000023e0 USBIEPCNF_4 +000023e1 USBIEPBBAX_4 +000023e2 USBIEPBCTX_4 +000023e5 USBIEPBBAY_4 +000023e6 USBIEPBCTY_4 +000023e7 USBIEPSIZXY_4 +000023e8 USBIEPCNF_5 +000023e9 USBIEPBBAX_5 +000023ea USBIEPBCTX_5 +000023ed USBIEPBBAY_5 +000023ee USBIEPBCTY_5 +000023ef USBIEPSIZXY_5 +000023f0 USBIEPCNF_6 +000023f1 USBIEPBBAX_6 +000023f2 USBIEPBCTX_6 +000023f5 USBIEPBBAY_6 +000023f6 USBIEPBCTY_6 +000023f7 USBIEPSIZXY_6 +000023f8 USBIEPCNF_7 +000023f9 USBIEPBBAX_7 +000023fa USBIEPBCTX_7 +000023fd USBIEPBBAY_7 +000023fe USBIEPBCTY_7 +000023ff USBIEPSIZXY_7 +00004400 __STACK_END +0000441e RESET +00004452 __TI_ISR_TRAP +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[760 symbols] diff --git a/CPE325/Lab4_Problem1/Debug/Lab4_Problem1.map b/CPE325/Lab4_Problem1/Debug/Lab4_Problem1.map new file mode 100644 index 0000000..7e4dc9f --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/Lab4_Problem1.map @@ -0,0 +1,1763 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Sep 17 14:19:03 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "RESET" address: 00004400 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 00000022 00001fde RWIX + FLASH 00004400 0000bb80 00000056 0000bb2a RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00002400 00000022 + 00002400 00000022 main.obj (.data) + +.stack 0 00004400 00000000 + +.text 0 00004400 0000004e + 00004400 0000004e main.obj (.text) + +.text:_isr +* 0 0000444e 00000008 + 0000444e 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00004400 00000000 UNINITIALIZED + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 main.obj (.reset) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + main.obj 78 2 34 + +--+------------------+------+---------+---------+ + Total: 78 2 34 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + isr_trap.asm.obj 8 0 0 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + +--+------------------+------+---------+---------+ + Total: 8 44 0 + + +--+------------------+------+---------+---------+ + Grand Total: 86 46 34 + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +00004400 RESET +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +00000902 USBCNF +00000903 USBCNF_H +00000902 USBCNF_L +0000093c USBCTL +0000093a USBFN +0000093b USBFN_H +0000093a USBFN_L +0000093f USBFUNADR +0000093d USBIE +00002378 USBIEP0BUF +000023c9 USBIEPBBAX_1 +000023d1 USBIEPBBAX_2 +000023d9 USBIEPBBAX_3 +000023e1 USBIEPBBAX_4 +000023e9 USBIEPBBAX_5 +000023f1 USBIEPBBAX_6 +000023f9 USBIEPBBAX_7 +000023cd USBIEPBBAY_1 +000023d5 USBIEPBBAY_2 +000023dd USBIEPBBAY_3 +000023e5 USBIEPBBAY_4 +000023ed USBIEPBBAY_5 +000023f5 USBIEPBBAY_6 +000023fd USBIEPBBAY_7 +000023ca USBIEPBCTX_1 +000023d2 USBIEPBCTX_2 +000023da USBIEPBCTX_3 +000023e2 USBIEPBCTX_4 +000023ea USBIEPBCTX_5 +000023f2 USBIEPBCTX_6 +000023fa USBIEPBCTX_7 +000023ce USBIEPBCTY_1 +000023d6 USBIEPBCTY_2 +000023de USBIEPBCTY_3 +000023e6 USBIEPBCTY_4 +000023ee USBIEPBCTY_5 +000023f6 USBIEPBCTY_6 +000023fe USBIEPBCTY_7 +00000920 USBIEPCNF_0 +000023c8 USBIEPCNF_1 +000023d0 USBIEPCNF_2 +000023d8 USBIEPCNF_3 +000023e0 USBIEPCNF_4 +000023e8 USBIEPCNF_5 +000023f0 USBIEPCNF_6 +000023f8 USBIEPCNF_7 +00000921 USBIEPCNT_0 +0000092e USBIEPIE +00000930 USBIEPIFG +000023cf USBIEPSIZXY_1 +000023d7 USBIEPSIZXY_2 +000023df USBIEPSIZXY_3 +000023e7 USBIEPSIZXY_4 +000023ef USBIEPSIZXY_5 +000023f7 USBIEPSIZXY_6 +000023ff USBIEPSIZXY_7 +0000093e USBIFG +00000900 USBKEYID +00000901 USBKEYID_H +00000900 USBKEYID_L +00000936 USBMAINT +00000937 USBMAINT_H +00000936 USBMAINT_L +00002370 USBOEP0BUF +00002389 USBOEPBBAX_1 +00002391 USBOEPBBAX_2 +00002399 USBOEPBBAX_3 +000023a1 USBOEPBBAX_4 +000023a9 USBOEPBBAX_5 +000023b1 USBOEPBBAX_6 +000023b9 USBOEPBBAX_7 +0000238d USBOEPBBAY_1 +00002395 USBOEPBBAY_2 +0000239d USBOEPBBAY_3 +000023a5 USBOEPBBAY_4 +000023ad USBOEPBBAY_5 +000023b5 USBOEPBBAY_6 +000023bd USBOEPBBAY_7 +0000238a USBOEPBCTX_1 +00002392 USBOEPBCTX_2 +0000239a USBOEPBCTX_3 +000023a2 USBOEPBCTX_4 +000023aa USBOEPBCTX_5 +000023b2 USBOEPBCTX_6 +000023ba USBOEPBCTX_7 +0000238e USBOEPBCTY_1 +00002396 USBOEPBCTY_2 +0000239e USBOEPBCTY_3 +000023a6 USBOEPBCTY_4 +000023ae USBOEPBCTY_5 +000023b6 USBOEPBCTY_6 +000023be USBOEPBCTY_7 +00000922 USBOEPCNF_0 +00002388 USBOEPCNF_1 +00002390 USBOEPCNF_2 +00002398 USBOEPCNF_3 +000023a0 USBOEPCNF_4 +000023a8 USBOEPCNF_5 +000023b0 USBOEPCNF_6 +000023b8 USBOEPCNF_7 +00000923 USBOEPCNT_0 +0000092f USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +00004400 __STACK_END +00000000 __STACK_SIZE +0000444e __TI_ISR_TRAP +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +00000000 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 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ADC12MEM12 +00000738 ADC12MEM12_L +00000739 ADC12MEM12_H +0000073a ADC12MEM13 +0000073a ADC12MEM13_L +0000073b ADC12MEM13_H +0000073c ADC12MEM14 +0000073c ADC12MEM14_L +0000073d ADC12MEM14_H +0000073e ADC12MEM15 +0000073e ADC12MEM15_L +0000073f ADC12MEM15_H +000008c0 CBCTL0 +000008c0 CBCTL0_L +000008c1 CBCTL0_H +000008c2 CBCTL1 +000008c2 CBCTL1_L +000008c3 CBCTL1_H +000008c4 CBCTL2 +000008c4 CBCTL2_L +000008c5 CBCTL2_H +000008c6 CBCTL3 +000008c6 CBCTL3_L +000008c7 CBCTL3_H +000008cc CBINT +000008cc CBINT_L +000008cd CBINT_H +000008ce CBIV +00000900 USBKEYID +00000900 USBKEYID_L +00000901 USBKEYID_H +00000902 USBCNF +00000902 USBCNF_L +00000903 USBCNF_H +00000904 USBPHYCTL +00000904 USBPHYCTL_L +00000905 USBPHYCTL_H +00000908 USBPWRCTL +00000908 USBPWRCTL_L +00000909 USBPWRCTL_H +00000910 USBPLLCTL +00000910 USBPLLCTL_L +00000911 USBPLLCTL_H +00000912 USBPLLDIVB +00000912 USBPLLDIVB_L +00000913 USBPLLDIVB_H +00000914 USBPLLIR +00000914 USBPLLIR_L +00000915 USBPLLIR_H +00000920 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__TI_int61 +0000fffc __TI_int62 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[760 symbols] diff --git a/CPE325/Lab4_Problem1/Debug/Lab4_Problem1.out b/CPE325/Lab4_Problem1/Debug/Lab4_Problem1.out new file mode 100644 index 0000000..5f6f69d Binary files /dev/null and b/CPE325/Lab4_Problem1/Debug/Lab4_Problem1.out differ diff --git a/CPE325/Lab4_Problem1/Debug/Lab4_Problem1_linkInfo.xml b/CPE325/Lab4_Problem1/Debug/Lab4_Problem1_linkInfo.xml new file mode 100644 index 0000000..5b3f6ff --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/Lab4_Problem1_linkInfo.xml @@ -0,0 +1,5279 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x6144ea27 + 0x0 + Lab4_Problem1.out + + RESET +
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UCB1CTLW0_L + 0x620 + + + UCB1CTLW0_H + 0x621 + + + UCB1BRW + 0x626 + + + UCB1BRW_L + 0x626 + + + UCB1BRW_H + 0x627 + + + UCB1STAT + 0x62a + + + UCB1RXBUF + 0x62c + + + UCB1TXBUF + 0x62e + + + UCB1I2COA + 0x630 + + + UCB1I2COA_L + 0x630 + + + UCB1I2COA_H + 0x631 + + + UCB1I2CSA + 0x632 + + + UCB1I2CSA_L + 0x632 + + + UCB1I2CSA_H + 0x633 + + + UCB1ICTL + 0x63c + + + UCB1ICTL_L + 0x63c + + + UCB1ICTL_H + 0x63d + + + UCB1IV + 0x63e + + + WDTCTL + 0x15c + + + WDTCTL_L + 0x15c + + + WDTCTL_H + 0x15d + + + __STACK_SIZE + 0x0 + + + __STACK_END + 0x4400 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + RESET + 0x4400 + + + + __TI_int41 + 0xffd2 + + + + __TI_int42 + 0xffd4 + + + + __TI_int43 + 0xffd6 + + + + __TI_int44 + 0xffd8 + + + + __TI_int45 + 0xffda + + + + __TI_int46 + 0xffdc + + + + __TI_int47 + 0xffde + + + + __TI_int48 + 0xffe0 + + + + __TI_int49 + 0xffe2 + + + + __TI_int50 + 0xffe4 + + + + __TI_int51 + 0xffe6 + + + + __TI_int52 + 0xffe8 + + + + __TI_int53 + 0xffea + + + + __TI_int54 + 0xffec + + + + __TI_int55 + 0xffee + + + + __TI_int56 + 0xfff0 + + + + __TI_int57 + 0xfff2 + + + + __TI_int58 + 0xfff4 + + + + __TI_int59 + 0xfff6 + + + + __TI_int60 + 0xfff8 + + + + __TI_int61 + 0xfffa + + + + __TI_int62 + 0xfffc + + + + __TI_ISR_TRAP + 0x444e + + + + Link successful + diff --git a/CPE325/Lab4_Problem1/Debug/Lab4_linkInfo.xml b/CPE325/Lab4_Problem1/Debug/Lab4_linkInfo.xml new file mode 100644 index 0000000..b16e1f3 --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/Lab4_linkInfo.xml @@ -0,0 +1,5329 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x613ba724 + 0x2 + Lab4.out + + RESET +
0x441e
+ + + + .\ + object + Lab04_D1.obj + Lab04_D1.obj + + + .\ + object + main.obj + main.obj + + + object + <internal> + <internal> + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int41.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int42.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int43.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int44.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int45.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int46.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int47.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + 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USBIEPBCTY_6 + 0x23f6 + + + USBIEPBBAY_6 + 0x23f5 + + + USBIEPBCTX_6 + 0x23f2 + + + USBIEPBBAX_6 + 0x23f1 + + + USBIEPCNF_6 + 0x23f0 + + + USBIEPSIZXY_5 + 0x23ef + + + USBIEPBCTY_5 + 0x23ee + + + USBIEPBBAY_5 + 0x23ed + + + USBIEPBCTX_5 + 0x23ea + + + USBIEPBBAX_5 + 0x23e9 + + + USBIEPCNF_5 + 0x23e8 + + + USBIEPSIZXY_4 + 0x23e7 + + + USBIEPBCTY_4 + 0x23e6 + + + USBIEPBBAY_4 + 0x23e5 + + + USBIEPBCTX_4 + 0x23e2 + + + USBIEPBBAX_4 + 0x23e1 + + + USBIEPCNF_4 + 0x23e0 + + + USBIEPSIZXY_3 + 0x23df + + + USBIEPBCTY_3 + 0x23de + + + USBIEPBBAY_3 + 0x23dd + + + USBIEPBCTX_3 + 0x23da + + + USBIEPBBAX_3 + 0x23d9 + + + USBIEPCNF_3 + 0x23d8 + + + USBIEPSIZXY_2 + 0x23d7 + + + USBIEPBCTY_2 + 0x23d6 + + + USBIEPBBAY_2 + 0x23d5 + + + USBIEPBCTX_2 + 0x23d2 + + + USBIEPBBAX_2 + 0x23d1 + + + USBIEPCNF_2 + 0x23d0 + + + USBIEPSIZXY_1 + 0x23cf + + + USBIEPBCTY_1 + 0x23ce + + + USBIEPBBAY_1 + 0x23cd + + + USBIEPBCTX_1 + 0x23ca + + + USBIEPBBAX_1 + 0x23c9 + + + USBIEPCNF_1 + 0x23c8 + + + USBOEPSIZXY_7 + 0x23bf + + + USBOEPBCTY_7 + 0x23be + + + USBOEPBBAY_7 + 0x23bd + + + USBOEPBCTX_7 + 0x23ba + + + USBOEPBBAX_7 + 0x23b9 + + + USBOEPCNF_7 + 0x23b8 + + + USBOEPSIZXY_6 + 0x23b7 + + + USBOEPBCTY_6 + 0x23b6 + + + USBOEPBBAY_6 + 0x23b5 + + + USBOEPBCTX_6 + 0x23b2 + + + USBOEPBBAX_6 + 0x23b1 + + + USBOEPCNF_6 + 0x23b0 + + + USBOEPSIZXY_5 + 0x23af + + + USBOEPBCTY_5 + 0x23ae + + + USBOEPBBAY_5 + 0x23ad + + + USBOEPBCTX_5 + 0x23aa + + + USBOEPBBAX_5 + 0x23a9 + + + USBOEPCNF_5 + 0x23a8 + + + USBOEPSIZXY_4 + 0x23a7 + + + USBOEPBCTY_4 + 0x23a6 + + + USBOEPBBAY_4 + 0x23a5 + + + USBOEPBCTX_4 + 0x23a2 + + + USBOEPBBAX_4 + 0x23a1 + + + USBOEPCNF_4 + 0x23a0 + + + USBOEPSIZXY_3 + 0x239f + + + USBOEPBCTY_3 + 0x239e + + + USBOEPBBAY_3 + 0x239d + + + USBOEPBCTX_3 + 0x239a + + + USBOEPBBAX_3 + 0x2399 + + + USBOEPCNF_3 + 0x2398 + + + USBOEPSIZXY_2 + 0x2397 + + + USBOEPBCTY_2 + 0x2396 + + + USBOEPBBAY_2 + 0x2395 + + + USBOEPBCTX_2 + 0x2392 + + + USBOEPBBAX_2 + 0x2391 + + + USBOEPCNF_2 + 0x2390 + + + USBOEPSIZXY_1 + 0x238f + + + USBOEPBCTY_1 + 0x238e + + + USBOEPBBAY_1 + 0x238d + + + USBOEPBCTX_1 + 0x238a + + + USBOEPBBAX_1 + 0x2389 + + + USBOEPCNF_1 + 0x2388 + + + USBSUBLK + 0x2380 + + + USBIEP0BUF + 0x2378 + + + USBOEP0BUF + 0x2370 + + + USBTOPBUFF + 0x236f + + + USBSTABUFF + 0x1c00 + + + UCSCTL0 + 0x160 + + + UCSCTL0_L + 0x160 + + + UCSCTL0_H + 0x161 + + + UCSCTL1 + 0x162 + + + UCSCTL1_L + 0x162 + + + UCSCTL1_H + 0x163 + + + UCSCTL2 + 0x164 + + + UCSCTL2_L + 0x164 + + + UCSCTL2_H + 0x165 + + + UCSCTL3 + 0x166 + + + UCSCTL3_L + 0x166 + + + UCSCTL3_H + 0x167 + + + UCSCTL4 + 0x168 + + + UCSCTL4_L + 0x168 + + + UCSCTL4_H + 0x169 + + + UCSCTL5 + 0x16a + + + UCSCTL5_L + 0x16a + + + UCSCTL5_H + 0x16b + + + UCSCTL6 + 0x16c + + + UCSCTL6_L + 0x16c + + + UCSCTL6_H + 0x16d + + + UCSCTL7 + 0x16e + + + UCSCTL7_L + 0x16e + + + UCSCTL7_H + 0x16f + + + UCSCTL8 + 0x170 + + + UCSCTL8_L + 0x170 + + + UCSCTL8_H + 0x171 + + + UCA0CTLW0 + 0x5c0 + + + UCA0CTLW0_L + 0x5c0 + + + UCA0CTLW0_H + 0x5c1 + + + UCA0BRW + 0x5c6 + + + UCA0BRW_L + 0x5c6 + + + UCA0BRW_H + 0x5c7 + + + UCA0MCTL + 0x5c8 + + + UCA0STAT + 0x5ca + + + UCA0RXBUF + 0x5cc + + + UCA0TXBUF + 0x5ce + + + UCA0ABCTL + 0x5d0 + + + UCA0IRCTL + 0x5d2 + + + UCA0IRCTL_L + 0x5d2 + + + UCA0IRCTL_H + 0x5d3 + + + UCA0ICTL + 0x5dc + + + UCA0ICTL_L + 0x5dc + + + UCA0ICTL_H + 0x5dd + + + UCA0IV + 0x5de + + + UCB0CTLW0 + 0x5e0 + + + UCB0CTLW0_L + 0x5e0 + + + UCB0CTLW0_H + 0x5e1 + + + UCB0BRW + 0x5e6 + + + UCB0BRW_L + 0x5e6 + + + UCB0BRW_H + 0x5e7 + + + UCB0STAT + 0x5ea + + + UCB0RXBUF + 0x5ec + + + UCB0TXBUF + 0x5ee + + + UCB0I2COA + 0x5f0 + + + UCB0I2COA_L + 0x5f0 + + + UCB0I2COA_H + 0x5f1 + + + UCB0I2CSA + 0x5f2 + + + UCB0I2CSA_L + 0x5f2 + + + UCB0I2CSA_H + 0x5f3 + + + UCB0ICTL + 0x5fc + + + UCB0ICTL_L + 0x5fc + + + UCB0ICTL_H + 0x5fd + + + UCB0IV + 0x5fe + + + UCA1CTLW0 + 0x600 + + + UCA1CTLW0_L + 0x600 + + + UCA1CTLW0_H + 0x601 + + + UCA1BRW + 0x606 + + + UCA1BRW_L + 0x606 + + + UCA1BRW_H + 0x607 + + + UCA1MCTL + 0x608 + + + UCA1STAT + 0x60a + + + UCA1RXBUF + 0x60c + + + UCA1TXBUF + 0x60e + + + UCA1ABCTL + 0x610 + + + UCA1IRCTL + 0x612 + + + UCA1IRCTL_L + 0x612 + + + UCA1IRCTL_H + 0x613 + + + UCA1ICTL + 0x61c + + + UCA1ICTL_L + 0x61c + + + UCA1ICTL_H + 0x61d + + + UCA1IV + 0x61e + + + UCB1CTLW0 + 0x620 + + + UCB1CTLW0_L + 0x620 + + + UCB1CTLW0_H + 0x621 + + + UCB1BRW + 0x626 + + + UCB1BRW_L + 0x626 + + + UCB1BRW_H + 0x627 + + + UCB1STAT + 0x62a + + + UCB1RXBUF + 0x62c + + + UCB1TXBUF + 0x62e + + + UCB1I2COA + 0x630 + + + UCB1I2COA_L + 0x630 + + + UCB1I2COA_H + 0x631 + + + UCB1I2CSA + 0x632 + + + UCB1I2CSA_L + 0x632 + + + UCB1I2CSA_H + 0x633 + + + UCB1ICTL + 0x63c + + + UCB1ICTL_L + 0x63c + + + UCB1ICTL_H + 0x63d + + + UCB1IV + 0x63e + + + WDTCTL + 0x15c + + + WDTCTL_L + 0x15c + + + WDTCTL_H + 0x15d + + + __STACK_SIZE + 0x0 + + + __STACK_END + 0x4400 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + RESET + 0x441e + + + + __TI_int41 + 0xffd2 + + + + __TI_int42 + 0xffd4 + + + + __TI_int43 + 0xffd6 + + + + __TI_int44 + 0xffd8 + + + + __TI_int45 + 0xffda + + + + __TI_int46 + 0xffdc + + + + __TI_int47 + 0xffde + + + + __TI_int48 + 0xffe0 + + + + __TI_int49 + 0xffe2 + + + + __TI_int50 + 0xffe4 + + + + __TI_int51 + 0xffe6 + + + + __TI_int52 + 0xffe8 + + + + __TI_int53 + 0xffea + + + + __TI_int54 + 0xffec + + + + __TI_int55 + 0xffee + + + + __TI_int56 + 0xfff0 + + + + __TI_int57 + 0xfff2 + + + + __TI_int58 + 0xfff4 + + + + __TI_int59 + 0xfff6 + + + + __TI_int60 + 0xfff8 + + + + __TI_int61 + 0xfffa + + + + __TI_int62 + 0xfffc + + + + __TI_ISR_TRAP + 0x4452 + + + + Link errors: red sections failed placement,available memory ranges in purple + diff --git a/CPE325/Lab4_Problem1/Debug/ccsObjs.opt b/CPE325/Lab4_Problem1/Debug/ccsObjs.opt new file mode 100644 index 0000000..d254a20 --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./main.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/Lab4_Problem1/Debug/main.obj b/CPE325/Lab4_Problem1/Debug/main.obj new file mode 100644 index 0000000..a5b4f16 Binary files /dev/null and b/CPE325/Lab4_Problem1/Debug/main.obj differ diff --git a/CPE325/Lab4_Problem1/Debug/makefile b/CPE325/Lab4_Problem1/Debug/makefile new file mode 100644 index 0000000..ed3786e --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/makefile @@ -0,0 +1,167 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab4_Problem1.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab4_Problem1.out" \ + +BIN_OUTPUTS += \ +Lab4_Problem1.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab4_Problem1.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab4_Problem1.out" + +# Tool invocations +Lab4_Problem1.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --code_model=small --data_model=small --use_hw_mpy=F5 --advice:power="all" --define=__MSP430F5529__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 -z -m"Lab4_Problem1.map" --heap_size=0 --stack_size=0 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab4_Problem1_linkInfo.xml" --entry_point=RESET --use_hw_mpy=F5 -o "Lab4_Problem1.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab4_Problem1.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab4_Problem1.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "main.obj" + -$(RM) "main.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab4_Problem1/Debug/objects.mk b/CPE325/Lab4_Problem1/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/Lab4_Problem1/Debug/sources.mk b/CPE325/Lab4_Problem1/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab4_Problem1/Debug/subdir_rules.mk b/CPE325/Lab4_Problem1/Debug/subdir_rules.mk new file mode 100644 index 0000000..ddd4e56 --- /dev/null +++ b/CPE325/Lab4_Problem1/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --code_model=small --data_model=small --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab4_Problem1" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power="all" --define=__MSP430F5529__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/Lab4_Problem1/main.asm b/CPE325/Lab4_Problem1/main.asm new file mode 100644 index 0000000..564ca40 --- /dev/null +++ b/CPE325/Lab4_Problem1/main.asm @@ -0,0 +1,69 @@ +;------------------------------------------------------------------------------- +; MSP430 Assembler Code Template for use with TI Code Composer Studio +; +; +;------------------------------------------------------------------------------- + .cdecls C,LIST,"msp430.h" ; Include device header file + +;------------------------------------------------------------------------------- + .def RESET ; Export program entry-point to + ; make it known to linker. +;------------------------------------------------------------------------------- + .data +myStr: .cstring "!#$%&()*+,-./:;<=>?@[\\]^_`{|}~" ; Define cstring variable +symb_count: .int 0 ; counter variable + .text ; Assemble into program memory. + .retain ; Override ELF conditional linking + ; and retain current section. + .retainrefs ; And retain any sections that have + ; references to current section. + +;------------------------------------------------------------------------------- +RESET mov.w #__STACK_END,SP ; Initialize stackpointer +StopWDT mov.w #WDTPW|WDTHOLD,&WDTCTL ; Stop watchdog timer + + +;------------------------------------------------------------------------------- +; Main loop here +;------------------------------------------------------------------------------- +main: mov.w #myStr, R4 ; Move the starting address of myStr into register 4 + clr.b R5 ; Register 5 will serve as a counter +gnext: mov.b @R4+, R6 ; get a new character + cmp.b #0, R6 ; check for null character + jeq lend ; if null, go to end + cmp.b #97, R6 ; check if 'a' + jeq gnext ; if equal, get next character + jge range2 ; if greater or equal, jump to range2 + jl capitals ; if less than, jump to numbers label + +range2: cmp.b #123, R6 ; is it '{' char + jge incr ; if it is, jump to incr + jl gnext ; if less than, get next character + +capitals: cmp.b #91, R6 ; is it '[' + jge incr ; if it is or greater, jump to incr + cmp.b #65, R6 ; is it 'A' + jge gnext ; if equal or greater, get next character + cmp.b #58, R6 ; is it ';' + jge incr ; if greater or equal, jump to incr + cmp.b #48, R6 ; is it '0' + jge gnext ; if equal or greater, get next character +incr: inc.w R5 ; increment counter + jmp gnext ; get next character + +lend: mov.w R5,&P1OUT ; Write result in P1OUT (not visible on port pins) + bis.w #LPM4, SR ; LPM4 + nop ; Required only for debugger + +;------------------------------------------------------------------------------- +; Stack Pointer definition +;------------------------------------------------------------------------------- + .global __STACK_END + .sect .stack + +;------------------------------------------------------------------------------- +; Interrupt Vectors +;------------------------------------------------------------------------------- + .sect ".reset" ; MSP430 RESET Vector + .short RESET + diff --git a/CPE325/Lab4_Problem1/targetConfigs/MSP430F5529.ccxml b/CPE325/Lab4_Problem1/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/Lab4_Problem1/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab4_Problem1/targetConfigs/readme.txt b/CPE325/Lab4_Problem1/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab4_Problem1/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab4_Problem2/Debug/Lab4_Problem2.map b/CPE325/Lab4_Problem2/Debug/Lab4_Problem2.map new file mode 100644 index 0000000..b304da0 --- /dev/null +++ b/CPE325/Lab4_Problem2/Debug/Lab4_Problem2.map @@ -0,0 +1,1763 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Sep 17 14:25:58 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "RESET" address: 00004400 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOD 00001800 00000080 00000000 00000080 RWIX + INFOC 00001880 00000080 00000000 00000080 RWIX + INFOB 00001900 00000080 00000000 00000080 RWIX + INFOA 00001980 00000080 00000000 00000080 RWIX + USBRAM 00001c00 00000800 00000000 00000800 RWIX + RAM 00002400 00002000 00000004 00001ffc RWIX + FLASH 00004400 0000bb80 0000007c 0000bb04 RWIX + INT00 0000ff80 00000002 00000000 00000002 RWIX + INT01 0000ff82 00000002 00000000 00000002 RWIX + INT02 0000ff84 00000002 00000000 00000002 RWIX + INT03 0000ff86 00000002 00000000 00000002 RWIX + INT04 0000ff88 00000002 00000000 00000002 RWIX + INT05 0000ff8a 00000002 00000000 00000002 RWIX + INT06 0000ff8c 00000002 00000000 00000002 RWIX + INT07 0000ff8e 00000002 00000000 00000002 RWIX + INT08 0000ff90 00000002 00000000 00000002 RWIX + INT09 0000ff92 00000002 00000000 00000002 RWIX + INT10 0000ff94 00000002 00000000 00000002 RWIX + INT11 0000ff96 00000002 00000000 00000002 RWIX + INT12 0000ff98 00000002 00000000 00000002 RWIX + INT13 0000ff9a 00000002 00000000 00000002 RWIX + INT14 0000ff9c 00000002 00000000 00000002 RWIX + INT15 0000ff9e 00000002 00000000 00000002 RWIX + INT16 0000ffa0 00000002 00000000 00000002 RWIX + INT17 0000ffa2 00000002 00000000 00000002 RWIX + INT18 0000ffa4 00000002 00000000 00000002 RWIX + INT19 0000ffa6 00000002 00000000 00000002 RWIX + INT20 0000ffa8 00000002 00000000 00000002 RWIX + INT21 0000ffaa 00000002 00000000 00000002 RWIX + INT22 0000ffac 00000002 00000000 00000002 RWIX + INT23 0000ffae 00000002 00000000 00000002 RWIX + INT24 0000ffb0 00000002 00000000 00000002 RWIX + INT25 0000ffb2 00000002 00000000 00000002 RWIX + INT26 0000ffb4 00000002 00000000 00000002 RWIX + INT27 0000ffb6 00000002 00000000 00000002 RWIX + INT28 0000ffb8 00000002 00000000 00000002 RWIX + INT29 0000ffba 00000002 00000000 00000002 RWIX + INT30 0000ffbc 00000002 00000000 00000002 RWIX + INT31 0000ffbe 00000002 00000000 00000002 RWIX + INT32 0000ffc0 00000002 00000000 00000002 RWIX + INT33 0000ffc2 00000002 00000000 00000002 RWIX + INT34 0000ffc4 00000002 00000000 00000002 RWIX + INT35 0000ffc6 00000002 00000000 00000002 RWIX + INT36 0000ffc8 00000002 00000000 00000002 RWIX + INT37 0000ffca 00000002 00000000 00000002 RWIX + INT38 0000ffcc 00000002 00000000 00000002 RWIX + INT39 0000ffce 00000002 00000000 00000002 RWIX + INT40 0000ffd0 00000002 00000000 00000002 RWIX + INT41 0000ffd2 00000002 00000002 00000000 RWIX + INT42 0000ffd4 00000002 00000002 00000000 RWIX + INT43 0000ffd6 00000002 00000002 00000000 RWIX + INT44 0000ffd8 00000002 00000002 00000000 RWIX + INT45 0000ffda 00000002 00000002 00000000 RWIX + INT46 0000ffdc 00000002 00000002 00000000 RWIX + INT47 0000ffde 00000002 00000002 00000000 RWIX + INT48 0000ffe0 00000002 00000002 00000000 RWIX + INT49 0000ffe2 00000002 00000002 00000000 RWIX + INT50 0000ffe4 00000002 00000002 00000000 RWIX + INT51 0000ffe6 00000002 00000002 00000000 RWIX + INT52 0000ffe8 00000002 00000002 00000000 RWIX + INT53 0000ffea 00000002 00000002 00000000 RWIX + INT54 0000ffec 00000002 00000002 00000000 RWIX + INT55 0000ffee 00000002 00000002 00000000 RWIX + INT56 0000fff0 00000002 00000002 00000000 RWIX + INT57 0000fff2 00000002 00000002 00000000 RWIX + INT58 0000fff4 00000002 00000002 00000000 RWIX + INT59 0000fff6 00000002 00000002 00000000 RWIX + INT60 0000fff8 00000002 00000002 00000000 RWIX + INT61 0000fffa 00000002 00000002 00000000 RWIX + INT62 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 000143f8 00000000 000143f8 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00002400 00000004 + 00002400 00000004 main.obj (.data) + +.stack 0 00004400 00000000 + +.text 0 00004400 00000074 + 00004400 00000074 main.obj (.text) + +.text:_isr +* 0 00004474 00000008 + 00004474 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00004400 00000000 UNINITIALIZED + +.binit 0 00004400 00000000 + +.init_array +* 0 00004400 00000000 UNINITIALIZED + +RTC 0 0000ffd2 00000002 + 0000ffd2 00000002 rts430_eabi.lib : int41.asm.obj (.int41) + +PORT2 0 0000ffd4 00000002 + 0000ffd4 00000002 rts430_eabi.lib : int42.asm.obj (.int42) + +TIMER2_A1 +* 0 0000ffd6 00000002 + 0000ffd6 00000002 rts430_eabi.lib : int43.asm.obj (.int43) + +TIMER2_A0 +* 0 0000ffd8 00000002 + 0000ffd8 00000002 rts430_eabi.lib : int44.asm.obj (.int44) + +USCI_B1 0 0000ffda 00000002 + 0000ffda 00000002 rts430_eabi.lib : int45.asm.obj (.int45) + +USCI_A1 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int46.asm.obj (.int46) + +PORT1 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int47.asm.obj (.int47) + +TIMER1_A1 +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int48.asm.obj (.int48) + +TIMER1_A0 +* 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int49.asm.obj (.int49) + +DMA 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int50.asm.obj (.int50) + +USB_UBM 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int51.asm.obj (.int51) + +TIMER0_A1 +* 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430_eabi.lib : int52.asm.obj (.int52) + +TIMER0_A0 +* 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int53.asm.obj (.int53) + +ADC12 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int54.asm.obj (.int54) + +USCI_B0 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int55.asm.obj (.int55) + +USCI_A0 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int56.asm.obj (.int56) + +WDT 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int57.asm.obj (.int57) + +TIMER0_B1 +* 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int58.asm.obj (.int58) + +TIMER0_B0 +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int59.asm.obj (.int59) + +COMP_B 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int60.asm.obj (.int60) + +UNMI 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int61.asm.obj (.int61) + +SYSNMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int62.asm.obj (.int62) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 main.obj (.reset) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + main.obj 116 2 4 + +--+------------------+------+---------+---------+ + Total: 116 2 4 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + isr_trap.asm.obj 8 0 0 + int41.asm.obj 0 2 0 + int42.asm.obj 0 2 0 + int43.asm.obj 0 2 0 + int44.asm.obj 0 2 0 + int45.asm.obj 0 2 0 + int46.asm.obj 0 2 0 + int47.asm.obj 0 2 0 + int48.asm.obj 0 2 0 + int49.asm.obj 0 2 0 + int50.asm.obj 0 2 0 + int51.asm.obj 0 2 0 + int52.asm.obj 0 2 0 + int53.asm.obj 0 2 0 + int54.asm.obj 0 2 0 + int55.asm.obj 0 2 0 + int56.asm.obj 0 2 0 + int57.asm.obj 0 2 0 + int58.asm.obj 0 2 0 + int59.asm.obj 0 2 0 + int60.asm.obj 0 2 0 + int61.asm.obj 0 2 0 + int62.asm.obj 0 2 0 + +--+------------------+------+---------+---------+ + Total: 8 44 0 + + +--+------------------+------+---------+---------+ + Grand Total: 124 46 4 + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +000008c0 CBCTL0 +000008c1 CBCTL0_H +000008c0 CBCTL0_L +000008c2 CBCTL1 +000008c3 CBCTL1_H +000008c2 CBCTL1_L +000008c4 CBCTL2 +000008c5 CBCTL2_H +000008c4 CBCTL2_L +000008c6 CBCTL3 +000008c7 CBCTL3_H +000008c6 CBCTL3_L +000008cc CBINT +000008cd CBINT_H +000008cc CBINT_L +000008ce CBIV +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +00000510 DMA0CTL +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +000001e0 P4MAP01 +000001e1 P4MAP01_H +000001e0 P4MAP01_L +000001e2 P4MAP23 +000001e3 P4MAP23_H +000001e2 P4MAP23_L +000001e4 P4MAP45 +000001e5 P4MAP45_H +000001e4 P4MAP45_L +000001e6 P4MAP67 +000001e7 P4MAP67_H +000001e6 P4MAP67_L +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +000001c2 PMAPCTL +000001c3 PMAPCTL_H +000001c2 PMAPCTL_L +000001c0 PMAPKEYID +000001c1 PMAPKEYID_H +000001c0 PMAPKEYID_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +00004400 RESET +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000400 TA2CTL +00000420 TA2EX0 +0000042e TA2IV +00000410 TA2R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +00000902 USBCNF +00000903 USBCNF_H +00000902 USBCNF_L +0000093c USBCTL +0000093a USBFN +0000093b USBFN_H +0000093a USBFN_L +0000093f USBFUNADR +0000093d USBIE +00002378 USBIEP0BUF +000023c9 USBIEPBBAX_1 +000023d1 USBIEPBBAX_2 +000023d9 USBIEPBBAX_3 +000023e1 USBIEPBBAX_4 +000023e9 USBIEPBBAX_5 +000023f1 USBIEPBBAX_6 +000023f9 USBIEPBBAX_7 +000023cd USBIEPBBAY_1 +000023d5 USBIEPBBAY_2 +000023dd USBIEPBBAY_3 +000023e5 USBIEPBBAY_4 +000023ed USBIEPBBAY_5 +000023f5 USBIEPBBAY_6 +000023fd USBIEPBBAY_7 +000023ca USBIEPBCTX_1 +000023d2 USBIEPBCTX_2 +000023da USBIEPBCTX_3 +000023e2 USBIEPBCTX_4 +000023ea USBIEPBCTX_5 +000023f2 USBIEPBCTX_6 +000023fa USBIEPBCTX_7 +000023ce USBIEPBCTY_1 +000023d6 USBIEPBCTY_2 +000023de USBIEPBCTY_3 +000023e6 USBIEPBCTY_4 +000023ee USBIEPBCTY_5 +000023f6 USBIEPBCTY_6 +000023fe USBIEPBCTY_7 +00000920 USBIEPCNF_0 +000023c8 USBIEPCNF_1 +000023d0 USBIEPCNF_2 +000023d8 USBIEPCNF_3 +000023e0 USBIEPCNF_4 +000023e8 USBIEPCNF_5 +000023f0 USBIEPCNF_6 +000023f8 USBIEPCNF_7 +00000921 USBIEPCNT_0 +0000092e USBIEPIE +00000930 USBIEPIFG +000023cf USBIEPSIZXY_1 +000023d7 USBIEPSIZXY_2 +000023df USBIEPSIZXY_3 +000023e7 USBIEPSIZXY_4 +000023ef USBIEPSIZXY_5 +000023f7 USBIEPSIZXY_6 +000023ff USBIEPSIZXY_7 +0000093e USBIFG +00000900 USBKEYID +00000901 USBKEYID_H +00000900 USBKEYID_L +00000936 USBMAINT +00000937 USBMAINT_H +00000936 USBMAINT_L +00002370 USBOEP0BUF +00002389 USBOEPBBAX_1 +00002391 USBOEPBBAX_2 +00002399 USBOEPBBAX_3 +000023a1 USBOEPBBAX_4 +000023a9 USBOEPBBAX_5 +000023b1 USBOEPBBAX_6 +000023b9 USBOEPBBAX_7 +0000238d USBOEPBBAY_1 +00002395 USBOEPBBAY_2 +0000239d USBOEPBBAY_3 +000023a5 USBOEPBBAY_4 +000023ad USBOEPBBAY_5 +000023b5 USBOEPBBAY_6 +000023bd USBOEPBBAY_7 +0000238a USBOEPBCTX_1 +00002392 USBOEPBCTX_2 +0000239a USBOEPBCTX_3 +000023a2 USBOEPBCTX_4 +000023aa USBOEPBCTX_5 +000023b2 USBOEPBCTX_6 +000023ba USBOEPBCTX_7 +0000238e USBOEPBCTY_1 +00002396 USBOEPBCTY_2 +0000239e USBOEPBCTY_3 +000023a6 USBOEPBCTY_4 +000023ae USBOEPBCTY_5 +000023b6 USBOEPBCTY_6 +000023be USBOEPBCTY_7 +00000922 USBOEPCNF_0 +00002388 USBOEPCNF_1 +00002390 USBOEPCNF_2 +00002398 USBOEPCNF_3 +000023a0 USBOEPCNF_4 +000023a8 USBOEPCNF_5 +000023b0 USBOEPCNF_6 +000023b8 USBOEPCNF_7 +00000923 USBOEPCNT_0 +0000092f USBOEPIE +00000931 USBOEPIFG +0000238f USBOEPSIZXY_1 +00002397 USBOEPSIZXY_2 +0000239f USBOEPSIZXY_3 +000023a7 USBOEPSIZXY_4 +000023af USBOEPSIZXY_5 +000023b7 USBOEPSIZXY_6 +000023bf USBOEPSIZXY_7 +00000904 USBPHYCTL +00000905 USBPHYCTL_H +00000904 USBPHYCTL_L +00000910 USBPLLCTL +00000911 USBPLLCTL_H +00000910 USBPLLCTL_L +00000912 USBPLLDIVB +00000913 USBPLLDIVB_H +00000912 USBPLLDIVB_L +00000914 USBPLLIR +00000915 USBPLLIR_H +00000914 USBPLLIR_L +00000908 USBPWRCTL +00000909 USBPWRCTL_H +00000908 USBPWRCTL_L +00001c00 USBSTABUFF +00002380 USBSUBLK +0000236f USBTOPBUFF +00000938 USBTSREG +00000939 USBTSREG_H +00000938 USBTSREG_L +00000932 USBVECINT +00000933 USBVECINT_H +00000932 USBVECINT_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +00004400 __STACK_END +00000000 __STACK_SIZE +00004474 __TI_ISR_TRAP +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +00000000 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +000001c0 PMAPKEYID +000001c0 PMAPKEYID_L +000001c1 PMAPKEYID_H +000001c2 PMAPCTL +000001c2 PMAPCTL_L +000001c3 PMAPCTL_H +000001e0 P4MAP01 +000001e0 P4MAP01_L +000001e1 P4MAP01_H +000001e2 P4MAP23 +000001e2 P4MAP23_L +000001e3 P4MAP23_H +000001e4 P4MAP45 +000001e4 P4MAP45_L +000001e5 P4MAP45_H +000001e6 P4MAP67 +000001e6 P4MAP67_L +000001e7 P4MAP67_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +00000400 TA2CTL +00000402 TA2CCTL0 +00000404 TA2CCTL1 +00000406 TA2CCTL2 +00000410 TA2R +00000412 TA2CCR0 +00000414 TA2CCR1 +00000416 TA2CCR2 +00000420 TA2EX0 +0000042e TA2IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000502 DMACTL1 +00000504 DMACTL2 +00000506 DMACTL3 +00000508 DMACTL4 +0000050e DMAIV +00000510 DMA0CTL +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H +00000726 ADC12MEM3 +00000726 ADC12MEM3_L +00000727 ADC12MEM3_H +00000728 ADC12MEM4 +00000728 ADC12MEM4_L +00000729 ADC12MEM4_H +0000072a ADC12MEM5 +0000072a ADC12MEM5_L +0000072b ADC12MEM5_H +0000072c ADC12MEM6 +0000072c ADC12MEM6_L +0000072d ADC12MEM6_H +0000072e ADC12MEM7 +0000072e ADC12MEM7_L +0000072f ADC12MEM7_H +00000730 ADC12MEM8 +00000730 ADC12MEM8_L +00000731 ADC12MEM8_H +00000732 ADC12MEM9 +00000732 ADC12MEM9_L +00000733 ADC12MEM9_H +00000734 ADC12MEM10 +00000734 ADC12MEM10_L +00000735 ADC12MEM10_H +00000736 ADC12MEM11 +00000736 ADC12MEM11_L +00000737 ADC12MEM11_H +00000738 ADC12MEM12 +00000738 ADC12MEM12_L +00000739 ADC12MEM12_H +0000073a ADC12MEM13 +0000073a ADC12MEM13_L +0000073b ADC12MEM13_H +0000073c ADC12MEM14 +0000073c ADC12MEM14_L +0000073d ADC12MEM14_H +0000073e ADC12MEM15 +0000073e ADC12MEM15_L +0000073f ADC12MEM15_H +000008c0 CBCTL0 +000008c0 CBCTL0_L +000008c1 CBCTL0_H +000008c2 CBCTL1 +000008c2 CBCTL1_L +000008c3 CBCTL1_H +000008c4 CBCTL2 +000008c4 CBCTL2_L +000008c5 CBCTL2_H +000008c6 CBCTL3 +000008c6 CBCTL3_L +000008c7 CBCTL3_H +000008cc CBINT +000008cc CBINT_L +000008cd CBINT_H +000008ce CBIV +00000900 USBKEYID +00000900 USBKEYID_L +00000901 USBKEYID_H +00000902 USBCNF +00000902 USBCNF_L +00000903 USBCNF_H +00000904 USBPHYCTL +00000904 USBPHYCTL_L +00000905 USBPHYCTL_H +00000908 USBPWRCTL +00000908 USBPWRCTL_L +00000909 USBPWRCTL_H +00000910 USBPLLCTL +00000910 USBPLLCTL_L +00000911 USBPLLCTL_H +00000912 USBPLLDIVB +00000912 USBPLLDIVB_L +00000913 USBPLLDIVB_H +00000914 USBPLLIR +00000914 USBPLLIR_L +00000915 USBPLLIR_H +00000920 USBIEPCNF_0 +00000921 USBIEPCNT_0 +00000922 USBOEPCNF_0 +00000923 USBOEPCNT_0 +0000092e USBIEPIE +0000092f USBOEPIE +00000930 USBIEPIFG +00000931 USBOEPIFG +00000932 USBVECINT +00000932 USBVECINT_L +00000933 USBVECINT_H +00000936 USBMAINT +00000936 USBMAINT_L +00000937 USBMAINT_H +00000938 USBTSREG +00000938 USBTSREG_L +00000939 USBTSREG_H +0000093a USBFN +0000093a USBFN_L +0000093b USBFN_H +0000093c USBCTL +0000093d USBIE +0000093e USBIFG +0000093f USBFUNADR +00001c00 USBSTABUFF +0000236f USBTOPBUFF +00002370 USBOEP0BUF +00002378 USBIEP0BUF +00002380 USBSUBLK +00002388 USBOEPCNF_1 +00002389 USBOEPBBAX_1 +0000238a USBOEPBCTX_1 +0000238d USBOEPBBAY_1 +0000238e USBOEPBCTY_1 +0000238f USBOEPSIZXY_1 +00002390 USBOEPCNF_2 +00002391 USBOEPBBAX_2 +00002392 USBOEPBCTX_2 +00002395 USBOEPBBAY_2 +00002396 USBOEPBCTY_2 +00002397 USBOEPSIZXY_2 +00002398 USBOEPCNF_3 +00002399 USBOEPBBAX_3 +0000239a USBOEPBCTX_3 +0000239d USBOEPBBAY_3 +0000239e USBOEPBCTY_3 +0000239f USBOEPSIZXY_3 +000023a0 USBOEPCNF_4 +000023a1 USBOEPBBAX_4 +000023a2 USBOEPBCTX_4 +000023a5 USBOEPBBAY_4 +000023a6 USBOEPBCTY_4 +000023a7 USBOEPSIZXY_4 +000023a8 USBOEPCNF_5 +000023a9 USBOEPBBAX_5 +000023aa USBOEPBCTX_5 +000023ad USBOEPBBAY_5 +000023ae USBOEPBCTY_5 +000023af USBOEPSIZXY_5 +000023b0 USBOEPCNF_6 +000023b1 USBOEPBBAX_6 +000023b2 USBOEPBCTX_6 +000023b5 USBOEPBBAY_6 +000023b6 USBOEPBCTY_6 +000023b7 USBOEPSIZXY_6 +000023b8 USBOEPCNF_7 +000023b9 USBOEPBBAX_7 +000023ba USBOEPBCTX_7 +000023bd USBOEPBBAY_7 +000023be USBOEPBCTY_7 +000023bf USBOEPSIZXY_7 +000023c8 USBIEPCNF_1 +000023c9 USBIEPBBAX_1 +000023ca USBIEPBCTX_1 +000023cd USBIEPBBAY_1 +000023ce USBIEPBCTY_1 +000023cf USBIEPSIZXY_1 +000023d0 USBIEPCNF_2 +000023d1 USBIEPBBAX_2 +000023d2 USBIEPBCTX_2 +000023d5 USBIEPBBAY_2 +000023d6 USBIEPBCTY_2 +000023d7 USBIEPSIZXY_2 +000023d8 USBIEPCNF_3 +000023d9 USBIEPBBAX_3 +000023da USBIEPBCTX_3 +000023dd USBIEPBBAY_3 +000023de USBIEPBCTY_3 +000023df USBIEPSIZXY_3 +000023e0 USBIEPCNF_4 +000023e1 USBIEPBBAX_4 +000023e2 USBIEPBCTX_4 +000023e5 USBIEPBBAY_4 +000023e6 USBIEPBCTY_4 +000023e7 USBIEPSIZXY_4 +000023e8 USBIEPCNF_5 +000023e9 USBIEPBBAX_5 +000023ea USBIEPBCTX_5 +000023ed USBIEPBBAY_5 +000023ee USBIEPBCTY_5 +000023ef USBIEPSIZXY_5 +000023f0 USBIEPCNF_6 +000023f1 USBIEPBBAX_6 +000023f2 USBIEPBCTX_6 +000023f5 USBIEPBBAY_6 +000023f6 USBIEPBCTY_6 +000023f7 USBIEPSIZXY_6 +000023f8 USBIEPCNF_7 +000023f9 USBIEPBBAX_7 +000023fa USBIEPBCTX_7 +000023fd USBIEPBBAY_7 +000023fe USBIEPBCTY_7 +000023ff USBIEPSIZXY_7 +00004400 RESET +00004400 __STACK_END +00004474 __TI_ISR_TRAP +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[760 symbols] diff --git a/CPE325/Lab4_Problem2/Debug/Lab4_Problem2.out b/CPE325/Lab4_Problem2/Debug/Lab4_Problem2.out new file mode 100644 index 0000000..317301e Binary files /dev/null and b/CPE325/Lab4_Problem2/Debug/Lab4_Problem2.out differ diff --git a/CPE325/Lab4_Problem2/Debug/Lab4_Problem2_linkInfo.xml b/CPE325/Lab4_Problem2/Debug/Lab4_Problem2_linkInfo.xml new file mode 100644 index 0000000..e1ed397 --- /dev/null +++ b/CPE325/Lab4_Problem2/Debug/Lab4_Problem2_linkInfo.xml @@ -0,0 +1,5279 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x6144ebc6 + 0x0 + Lab4_Problem2.out + + RESET +
0x4400
+ + + + .\ + object + main.obj + main.obj + + + object + <internal> + <internal> + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int41.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int42.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int43.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int44.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int45.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int46.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int47.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int48.asm.obj + + + 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USBIEPCNF_5 + 0x23e8 + + + USBIEPSIZXY_4 + 0x23e7 + + + USBIEPBCTY_4 + 0x23e6 + + + USBIEPBBAY_4 + 0x23e5 + + + USBIEPBCTX_4 + 0x23e2 + + + USBIEPBBAX_4 + 0x23e1 + + + USBIEPCNF_4 + 0x23e0 + + + USBIEPSIZXY_3 + 0x23df + + + USBIEPBCTY_3 + 0x23de + + + USBIEPBBAY_3 + 0x23dd + + + USBIEPBCTX_3 + 0x23da + + + USBIEPBBAX_3 + 0x23d9 + + + USBIEPCNF_3 + 0x23d8 + + + USBIEPSIZXY_2 + 0x23d7 + + + USBIEPBCTY_2 + 0x23d6 + + + USBIEPBBAY_2 + 0x23d5 + + + USBIEPBCTX_2 + 0x23d2 + + + USBIEPBBAX_2 + 0x23d1 + + + USBIEPCNF_2 + 0x23d0 + + + USBIEPSIZXY_1 + 0x23cf + + + USBIEPBCTY_1 + 0x23ce + + + USBIEPBBAY_1 + 0x23cd + + + USBIEPBCTX_1 + 0x23ca + + + USBIEPBBAX_1 + 0x23c9 + + + USBIEPCNF_1 + 0x23c8 + + + USBOEPSIZXY_7 + 0x23bf + + + USBOEPBCTY_7 + 0x23be + + + USBOEPBBAY_7 + 0x23bd + + + USBOEPBCTX_7 + 0x23ba + + + USBOEPBBAX_7 + 0x23b9 + + + USBOEPCNF_7 + 0x23b8 + + + USBOEPSIZXY_6 + 0x23b7 + + + USBOEPBCTY_6 + 0x23b6 + + + USBOEPBBAY_6 + 0x23b5 + + + USBOEPBCTX_6 + 0x23b2 + + + USBOEPBBAX_6 + 0x23b1 + + + USBOEPCNF_6 + 0x23b0 + + + USBOEPSIZXY_5 + 0x23af + + + USBOEPBCTY_5 + 0x23ae + + + USBOEPBBAY_5 + 0x23ad + + + USBOEPBCTX_5 + 0x23aa + + + USBOEPBBAX_5 + 0x23a9 + + + USBOEPCNF_5 + 0x23a8 + + + USBOEPSIZXY_4 + 0x23a7 + + + USBOEPBCTY_4 + 0x23a6 + + + USBOEPBBAY_4 + 0x23a5 + + + USBOEPBCTX_4 + 0x23a2 + + + USBOEPBBAX_4 + 0x23a1 + + + USBOEPCNF_4 + 0x23a0 + + + USBOEPSIZXY_3 + 0x239f + + + USBOEPBCTY_3 + 0x239e + + + USBOEPBBAY_3 + 0x239d + + + USBOEPBCTX_3 + 0x239a + + + USBOEPBBAX_3 + 0x2399 + + + USBOEPCNF_3 + 0x2398 + + + USBOEPSIZXY_2 + 0x2397 + + + USBOEPBCTY_2 + 0x2396 + + + USBOEPBBAY_2 + 0x2395 + + + USBOEPBCTX_2 + 0x2392 + + + USBOEPBBAX_2 + 0x2391 + + + USBOEPCNF_2 + 0x2390 + + + USBOEPSIZXY_1 + 0x238f + + + USBOEPBCTY_1 + 0x238e + + + USBOEPBBAY_1 + 0x238d + + + USBOEPBCTX_1 + 0x238a + + + USBOEPBBAX_1 + 0x2389 + + + USBOEPCNF_1 + 0x2388 + + + USBSUBLK + 0x2380 + + + USBIEP0BUF + 0x2378 + + + USBOEP0BUF + 0x2370 + + + USBTOPBUFF + 0x236f + + + USBSTABUFF + 0x1c00 + + + UCSCTL0 + 0x160 + + + UCSCTL0_L + 0x160 + + + UCSCTL0_H + 0x161 + + + UCSCTL1 + 0x162 + + + UCSCTL1_L + 0x162 + + + UCSCTL1_H + 0x163 + + + UCSCTL2 + 0x164 + + + UCSCTL2_L + 0x164 + + + UCSCTL2_H + 0x165 + + + UCSCTL3 + 0x166 + + + UCSCTL3_L + 0x166 + + + UCSCTL3_H + 0x167 + + + UCSCTL4 + 0x168 + + + UCSCTL4_L + 0x168 + + + UCSCTL4_H + 0x169 + + + UCSCTL5 + 0x16a + + + UCSCTL5_L + 0x16a + + + UCSCTL5_H + 0x16b + + + UCSCTL6 + 0x16c + + + UCSCTL6_L + 0x16c + + + UCSCTL6_H + 0x16d + + + UCSCTL7 + 0x16e + + + UCSCTL7_L + 0x16e + + + UCSCTL7_H + 0x16f + + + UCSCTL8 + 0x170 + + + UCSCTL8_L + 0x170 + + + UCSCTL8_H + 0x171 + + + UCA0CTLW0 + 0x5c0 + + + UCA0CTLW0_L + 0x5c0 + + + UCA0CTLW0_H + 0x5c1 + + + UCA0BRW + 0x5c6 + + + UCA0BRW_L + 0x5c6 + + + UCA0BRW_H + 0x5c7 + + + UCA0MCTL + 0x5c8 + + + UCA0STAT + 0x5ca + + + UCA0RXBUF + 0x5cc + + + UCA0TXBUF + 0x5ce + + + UCA0ABCTL + 0x5d0 + + + UCA0IRCTL + 0x5d2 + + + UCA0IRCTL_L + 0x5d2 + + + UCA0IRCTL_H + 0x5d3 + + + UCA0ICTL + 0x5dc + + + UCA0ICTL_L + 0x5dc + + + UCA0ICTL_H + 0x5dd + + + UCA0IV + 0x5de + + + UCB0CTLW0 + 0x5e0 + + + UCB0CTLW0_L + 0x5e0 + + + UCB0CTLW0_H + 0x5e1 + + + UCB0BRW + 0x5e6 + + + UCB0BRW_L + 0x5e6 + + + UCB0BRW_H + 0x5e7 + + + UCB0STAT + 0x5ea + + + UCB0RXBUF + 0x5ec + + + UCB0TXBUF + 0x5ee + + + UCB0I2COA + 0x5f0 + + + UCB0I2COA_L + 0x5f0 + + + UCB0I2COA_H + 0x5f1 + + + UCB0I2CSA + 0x5f2 + + + UCB0I2CSA_L + 0x5f2 + + + UCB0I2CSA_H + 0x5f3 + + + UCB0ICTL + 0x5fc + + + UCB0ICTL_L + 0x5fc + + + UCB0ICTL_H + 0x5fd + + + UCB0IV + 0x5fe + + + UCA1CTLW0 + 0x600 + + + UCA1CTLW0_L + 0x600 + + + UCA1CTLW0_H + 0x601 + + + UCA1BRW + 0x606 + + + UCA1BRW_L + 0x606 + + + UCA1BRW_H + 0x607 + + + UCA1MCTL + 0x608 + + + UCA1STAT + 0x60a + + + UCA1RXBUF + 0x60c + + + UCA1TXBUF + 0x60e + + + UCA1ABCTL + 0x610 + + + UCA1IRCTL + 0x612 + + + UCA1IRCTL_L + 0x612 + + + UCA1IRCTL_H + 0x613 + + + UCA1ICTL + 0x61c + + + UCA1ICTL_L + 0x61c + + + UCA1ICTL_H + 0x61d + + + UCA1IV + 0x61e + + + UCB1CTLW0 + 0x620 + + + UCB1CTLW0_L + 0x620 + + + UCB1CTLW0_H + 0x621 + + + UCB1BRW + 0x626 + + + UCB1BRW_L + 0x626 + + + UCB1BRW_H + 0x627 + + + UCB1STAT + 0x62a + + + UCB1RXBUF + 0x62c + + + UCB1TXBUF + 0x62e + + + UCB1I2COA + 0x630 + + + UCB1I2COA_L + 0x630 + + + UCB1I2COA_H + 0x631 + + + UCB1I2CSA + 0x632 + + + UCB1I2CSA_L + 0x632 + + + UCB1I2CSA_H + 0x633 + + + UCB1ICTL + 0x63c + + + UCB1ICTL_L + 0x63c + + + UCB1ICTL_H + 0x63d + + + UCB1IV + 0x63e + + + WDTCTL + 0x15c + + + WDTCTL_L + 0x15c + + + WDTCTL_H + 0x15d + + + __STACK_SIZE + 0x0 + + + __STACK_END + 0x4400 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + RESET + 0x4400 + + + + __TI_int41 + 0xffd2 + + + + __TI_int42 + 0xffd4 + + + + __TI_int43 + 0xffd6 + + + + __TI_int44 + 0xffd8 + + + + __TI_int45 + 0xffda + + + + __TI_int46 + 0xffdc + + + + __TI_int47 + 0xffde + + + + __TI_int48 + 0xffe0 + + + + __TI_int49 + 0xffe2 + + + + __TI_int50 + 0xffe4 + + + + __TI_int51 + 0xffe6 + + + + __TI_int52 + 0xffe8 + + + + __TI_int53 + 0xffea + + + + __TI_int54 + 0xffec + + + + __TI_int55 + 0xffee + + + + __TI_int56 + 0xfff0 + + + + __TI_int57 + 0xfff2 + + + + __TI_int58 + 0xfff4 + + + + __TI_int59 + 0xfff6 + + + + __TI_int60 + 0xfff8 + + + + __TI_int61 + 0xfffa + + + + __TI_int62 + 0xfffc + + + + __TI_ISR_TRAP + 0x4474 + + + + Link successful + diff --git a/CPE325/Lab4_Problem2/Debug/ccsObjs.opt b/CPE325/Lab4_Problem2/Debug/ccsObjs.opt new file mode 100644 index 0000000..d254a20 --- /dev/null +++ b/CPE325/Lab4_Problem2/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./main.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/Lab4_Problem2/Debug/main.obj b/CPE325/Lab4_Problem2/Debug/main.obj new file mode 100644 index 0000000..803c43b Binary files /dev/null and b/CPE325/Lab4_Problem2/Debug/main.obj differ diff --git a/CPE325/Lab4_Problem2/Debug/makefile b/CPE325/Lab4_Problem2/Debug/makefile new file mode 100644 index 0000000..183161b --- /dev/null +++ b/CPE325/Lab4_Problem2/Debug/makefile @@ -0,0 +1,167 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab4_Problem2.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab4_Problem2.out" \ + +BIN_OUTPUTS += \ +Lab4_Problem2.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab4_Problem2.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab4_Problem2.out" + +# Tool invocations +Lab4_Problem2.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --code_model=small --data_model=small --use_hw_mpy=F5 --advice:power=all --define=__MSP430F5529__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 -z -m"Lab4_Problem2.map" --heap_size=0 --stack_size=0 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab4_Problem2_linkInfo.xml" --entry_point=RESET --use_hw_mpy=F5 -o "Lab4_Problem2.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab4_Problem2.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab4_Problem2.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "main.obj" + -$(RM) "main.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab4_Problem2/Debug/objects.mk b/CPE325/Lab4_Problem2/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/Lab4_Problem2/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/Lab4_Problem2/Debug/sources.mk b/CPE325/Lab4_Problem2/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab4_Problem2/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab4_Problem2/Debug/subdir_rules.mk b/CPE325/Lab4_Problem2/Debug/subdir_rules.mk new file mode 100644 index 0000000..a3c3fd0 --- /dev/null +++ b/CPE325/Lab4_Problem2/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --code_model=small --data_model=small --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab4_Problem2" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430F5529__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/Lab4_Problem2/main.asm b/CPE325/Lab4_Problem2/main.asm new file mode 100644 index 0000000..9debe15 --- /dev/null +++ b/CPE325/Lab4_Problem2/main.asm @@ -0,0 +1,87 @@ +;------------------------------------------------------------------------------- +; MSP430 Assembler Code Template for use with TI Code Composer Studio +; +; +;------------------------------------------------------------------------------- + .cdecls C,LIST,"msp430.h" ; Include device header file + +;------------------------------------------------------------------------------- + .def RESET ; Export program entry-point to + ; make it known to linker. + + .data +myStr: .cstring "6*8" ; define string +;------------------------------------------------------------------------------- + .text ; Assemble into program memory. + .retain ; Override ELF conditional linking + ; and retain current section. + .retainrefs ; And retain any sections that have + ; references to current section. + +;------------------------------------------------------------------------------- +RESET mov.w #__STACK_END,SP ; Initialize stackpointer +StopWDT mov.w #WDTPW|WDTHOLD,&WDTCTL ; Stop watchdog timer + + +;------------------------------------------------------------------------------- +; Main loop here +;------------------------------------------------------------------------------- +main: mov.w #myStr, R4 ; Move the starting address of myStr into register 4 + clr.b R5 ; Use R5 to hold the character + clr.b R6 ; use r6 for first number + clr.b R7 ; use R7 for second + mov.b #0, R3 ; use r3 as counter + mov.b @R4+, R5 ; get a new character + cmp.b #58, R5 ; check for ':' character + jge error ; if equal or greater, jump to error + cmp.b #48, R5 ; is it a '0' + jl error ; if less, jump to error + mov.b R4, R6 ; move first number into Register 6 + mov.b @R4+, R5 ; get a new character + cmp #'*', R5 ; is it '*' + jne error ; if not equal, jump to error + mov.b @R4+, R5 ; get next character + cmp.b #58, R5 ; check for ':' character + jge error ; if equal or greater, jump to error + cmp.b #48, R5 ; is it a '0' + jl error ; if less, jump to error + mov.b @R4+, R5 ; get next char + cmp.b #0, R5 ; is it NULL + jne error ; error if not + mov.b R4, R7 ; move next number to register 7 + cmp.b R7, R5 ; which is less + jge firstNum ; if first is greater jump to firstNum + jl secondNum ; less than, jump to secondNum + +firstNum: cmp R3, R5 ; comparing r3 to loop top + jz endOne ; when 0 end loop + dadd.b R7, R7 ; add bigger number to itself + dadd.b r3,r3 ; increment counter + jmp firstNum ; jump to firstNum + +secondNum: cmp R3, R7 ; comparing r3 to loop top + jz endTwo ; when 0 end loop + dadd.b R5, R5 ; add bigger number to itself + dadd.b r3,r3 ; increment counter + jmp secondNum ; jump to secondNum +error: mov #0xFF, &P2OUT ; move FF to P2OUT + jmp errorEnd + +endOne: mov.w R7,&P2OUT ; Write result in P1OUT (not visible on port pins) +endTwo: mov.w R5,&P2OUT ; Write result in P1OUT (not visible on port pins) +errorEnd: + bis.w #LPM4, SR ; LPM4 + nop ; Required only for debugger + +;------------------------------------------------------------------------------- +; Stack Pointer definition +;------------------------------------------------------------------------------- + .global __STACK_END + .sect .stack + +;------------------------------------------------------------------------------- +; Interrupt Vectors +;------------------------------------------------------------------------------- + .sect ".reset" ; MSP430 RESET Vector + .short RESET + diff --git a/CPE325/Lab4_Problem2/targetConfigs/MSP430F5529.ccxml b/CPE325/Lab4_Problem2/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/Lab4_Problem2/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab4_Problem2/targetConfigs/readme.txt b/CPE325/Lab4_Problem2/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab4_Problem2/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab5/Debug/ccsObjs.opt b/CPE325/Lab5/Debug/ccsObjs.opt new file mode 100644 index 0000000..d254a20 --- /dev/null +++ b/CPE325/Lab5/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./main.obj" "../lnk_msp430f5529.cmd" -llibmath.a -llibc.a \ No newline at end of file diff --git a/CPE325/Lab5/Debug/makefile b/CPE325/Lab5/Debug/makefile new file mode 100644 index 0000000..beb74a4 --- /dev/null +++ b/CPE325/Lab5/Debug/makefile @@ -0,0 +1,167 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"../lnk_msp430f5529.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibmath.a \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab5.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab5.out" \ + +BIN_OUTPUTS += \ +Lab5.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab5.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab5.out" + +# Tool invocations +Lab5.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --code_model=small --data_model=small --use_hw_mpy=F5 --advice:power=all --define=__MSP430F5529__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 -z -m"Lab5.map" --heap_size=0 --stack_size=0 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab5_linkInfo.xml" --entry_point=RESET --use_hw_mpy=F5 -o "Lab5.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab5.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab5.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "main.obj" + -$(RM) "main.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab5/Debug/objects.mk b/CPE325/Lab5/Debug/objects.mk new file mode 100644 index 0000000..0b4f51f --- /dev/null +++ b/CPE325/Lab5/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibmath.a -llibc.a + diff --git a/CPE325/Lab5/Debug/sources.mk b/CPE325/Lab5/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab5/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab5/Debug/subdir_rules.mk b/CPE325/Lab5/Debug/subdir_rules.mk new file mode 100644 index 0000000..b9be351 --- /dev/null +++ b/CPE325/Lab5/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --code_model=small --data_model=small --use_hw_mpy=F5 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab5" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430F5529__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x2400, length = 0x2000 + USBRAM : origin = 0x1C00, length = 0x0800 + INFOA : origin = 0x1980, length = 0x0080 + INFOB : origin = 0x1900, length = 0x0080 + INFOC : origin = 0x1880, length = 0x0080 + INFOD : origin = 0x1800, length = 0x0080 + FLASH : origin = 0x4400, length = 0xBB80 + FLASH2 : origin = 0x10000,length = 0x143F8 /* Boundaries changed to fix CPU47 */ + INT00 : origin = 0xFF80, length = 0x0002 + INT01 : origin = 0xFF82, length = 0x0002 + INT02 : origin = 0xFF84, length = 0x0002 + INT03 : origin = 0xFF86, length = 0x0002 + INT04 : origin = 0xFF88, length = 0x0002 + INT05 : origin = 0xFF8A, length = 0x0002 + INT06 : origin = 0xFF8C, length = 0x0002 + INT07 : origin = 0xFF8E, length = 0x0002 + INT08 : origin = 0xFF90, length = 0x0002 + INT09 : origin = 0xFF92, length = 0x0002 + INT10 : origin = 0xFF94, length = 0x0002 + INT11 : origin = 0xFF96, length = 0x0002 + INT12 : origin = 0xFF98, length = 0x0002 + INT13 : origin = 0xFF9A, length = 0x0002 + INT14 : origin = 0xFF9C, length = 0x0002 + INT15 : origin = 0xFF9E, length = 0x0002 + INT16 : origin = 0xFFA0, length = 0x0002 + INT17 : origin = 0xFFA2, length = 0x0002 + INT18 : origin = 0xFFA4, length = 0x0002 + INT19 : origin = 0xFFA6, length = 0x0002 + INT20 : origin = 0xFFA8, length = 0x0002 + INT21 : origin = 0xFFAA, length = 0x0002 + INT22 : origin = 0xFFAC, length = 0x0002 + INT23 : origin = 0xFFAE, length = 0x0002 + INT24 : origin = 0xFFB0, length = 0x0002 + INT25 : origin = 0xFFB2, length = 0x0002 + INT26 : origin = 0xFFB4, length = 0x0002 + INT27 : origin = 0xFFB6, length = 0x0002 + INT28 : origin = 0xFFB8, length = 0x0002 + INT29 : origin = 0xFFBA, length = 0x0002 + INT30 : origin = 0xFFBC, length = 0x0002 + INT31 : origin = 0xFFBE, length = 0x0002 + INT32 : origin = 0xFFC0, length = 0x0002 + INT33 : origin = 0xFFC2, length = 0x0002 + INT34 : origin = 0xFFC4, length = 0x0002 + INT35 : origin = 0xFFC6, length = 0x0002 + INT36 : origin = 0xFFC8, length = 0x0002 + INT37 : origin = 0xFFCA, length = 0x0002 + INT38 : origin = 0xFFCC, length = 0x0002 + INT39 : origin = 0xFFCE, length = 0x0002 + INT40 : origin = 0xFFD0, length = 0x0002 + INT41 : origin = 0xFFD2, length = 0x0002 + INT42 : origin = 0xFFD4, length = 0x0002 + INT43 : origin = 0xFFD6, length = 0x0002 + INT44 : origin = 0xFFD8, length = 0x0002 + INT45 : origin = 0xFFDA, length = 0x0002 + INT46 : origin = 0xFFDC, length = 0x0002 + INT47 : origin = 0xFFDE, length = 0x0002 + INT48 : origin = 0xFFE0, length = 0x0002 + INT49 : origin = 0xFFE2, length = 0x0002 + INT50 : origin = 0xFFE4, length = 0x0002 + INT51 : origin = 0xFFE6, length = 0x0002 + INT52 : origin = 0xFFE8, length = 0x0002 + INT53 : origin = 0xFFEA, length = 0x0002 + INT54 : origin = 0xFFEC, length = 0x0002 + INT55 : origin = 0xFFEE, length = 0x0002 + INT56 : origin = 0xFFF0, length = 0x0002 + INT57 : origin = 0xFFF2, length = 0x0002 + INT58 : origin = 0xFFF4, length = 0x0002 + INT59 : origin = 0xFFF6, length = 0x0002 + INT60 : origin = 0xFFF8, length = 0x0002 + INT61 : origin = 0xFFFA, length = 0x0002 + INT62 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + .int14 : {} > INT14 + .int15 : {} > INT15 + .int16 : {} > INT16 + .int17 : {} > INT17 + .int18 : {} > INT18 + .int19 : {} > INT19 + .int20 : {} > INT20 + .int21 : {} > INT21 + .int22 : {} > INT22 + .int23 : {} > INT23 + .int24 : {} > INT24 + .int25 : {} > INT25 + .int26 : {} > INT26 + .int27 : {} > INT27 + .int28 : {} > INT28 + .int29 : {} > INT29 + .int30 : {} > INT30 + .int31 : {} > INT31 + .int32 : {} > INT32 + .int33 : {} > INT33 + .int34 : {} > INT34 + .int35 : {} > INT35 + .int36 : {} > INT36 + .int37 : {} > INT37 + .int38 : {} > INT38 + .int39 : {} > INT39 + .int40 : {} > INT40 + RTC : { * ( .int41 ) } > INT41 type = VECT_INIT + PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT + TIMER2_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT + TIMER2_A0 : { * ( .int44 ) } > INT44 type = VECT_INIT + USCI_B1 : { * ( .int45 ) } > INT45 type = VECT_INIT + USCI_A1 : { * ( .int46 ) } > INT46 type = VECT_INIT + PORT1 : { * ( .int47 ) } > INT47 type = VECT_INIT + TIMER1_A1 : { * ( .int48 ) } > INT48 type = VECT_INIT + TIMER1_A0 : { * ( .int49 ) } > INT49 type = VECT_INIT + DMA : { * ( .int50 ) } > INT50 type = VECT_INIT + USB_UBM : { * ( .int51 ) } > INT51 type = VECT_INIT + TIMER0_A1 : { * ( .int52 ) } > INT52 type = VECT_INIT + TIMER0_A0 : { * ( .int53 ) } > INT53 type = VECT_INIT + ADC12 : { * ( .int54 ) } > INT54 type = VECT_INIT + USCI_B0 : { * ( .int55 ) } > INT55 type = VECT_INIT + USCI_A0 : { * ( .int56 ) } > INT56 type = VECT_INIT + WDT : { * ( .int57 ) } > INT57 type = VECT_INIT + TIMER0_B1 : { * ( .int58 ) } > INT58 type = VECT_INIT + TIMER0_B0 : { * ( .int59 ) } > INT59 type = VECT_INIT + COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT + UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT + SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430f5529.cmd + diff --git a/CPE325/Lab5/main.asm b/CPE325/Lab5/main.asm new file mode 100644 index 0000000..03e4f9e --- /dev/null +++ b/CPE325/Lab5/main.asm @@ -0,0 +1,76 @@ +;------------------------------------------------------------------------------- +; MSP430 Assembler Code Template for use with TI Code Composer Studio +; +; +;------------------------------------------------------------------------------- + .cdecls C,LIST,"msp430.h" ; Include device header file + +;------------------------------------------------------------------------------- + .def RESET ; Export program entry-point to + ; make it known to linker. + .data +arr: .int "-25", "5", "22", "8", "-6", "14" +arrSize .int "6" +;------------------------------------------------------------------------------- + .text ; Assemble into program memory. + .retain ; Override ELF conditional linking + ; and retain current section. + .retainrefs ; And retain any sections that have + ; references to current section. + +;------------------------------------------------------------------------------- +RESET mov.w #__STACK_END,SP ; Initialize stackpointer +StopWDT mov.w #WDTPW|WDTHOLD,&WDTCTL ; Stop watchdog timer + + +;------------------------------------------------------------------------------- +; Main loop here +;------------------------------------------------------------------------------- +main: push #arr ; Move the starting address of arr onto the stack + push #arraySize ; Push the arraySize onto the stack + call #SW_Mult + mov.w @SP, #6 + + + + + + +SW_Mult: push R7 ; save r7, the sum + push R6 ; save R6, array size + push r4 ; save r4, pointer to array + mov.w 10(SP), R6 ; retreive array size + mov.w 12(SP, R7 ; retreive starting address + clr.w r8 + clr.w r9 + addIndex: mov.w @r4+, r5 ; increment byte counter + jmp comp + +comp: cmp #0, r5 + clr.w r8 ; clear result + jl ext +sum2 cmp #16, r10 + jz step2 + ; sxt r5 ; sign-extend value + +ext: sxt r5 ; sign-extend value + jmp sum2 +step2: add + + + + + +;------------------------------------------------------------------------------- +; Stack Pointer definition +;------------------------------------------------------------------------------- + .global __STACK_END + .sect .stack + + +;------------------------------------------------------------------------------- +; Interrupt Vectors +;------------------------------------------------------------------------------- + .sect ".reset" ; MSP430 RESET Vector + .short RESET + diff --git a/CPE325/Lab5/targetConfigs/MSP430F5529.ccxml b/CPE325/Lab5/targetConfigs/MSP430F5529.ccxml new file mode 100644 index 0000000..965ea95 --- /dev/null +++ b/CPE325/Lab5/targetConfigs/MSP430F5529.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab5/targetConfigs/readme.txt b/CPE325/Lab5/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab5/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab6_Problem1/Debug/Lab6_Problem1.map b/CPE325/Lab6_Problem1/Debug/Lab6_Problem1.map new file mode 100644 index 0000000..bc9a6b1 --- /dev/null +++ b/CPE325/Lab6_Problem1/Debug/Lab6_Problem1.map @@ -0,0 +1,726 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Fri Oct 1 15:16:30 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "RESET" address: 00003100 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOB 00001000 00000080 00000000 00000080 RWIX + INFOA 00001080 00000080 00000000 00000080 RWIX + RAM 00001100 00002000 00000000 00002000 RWIX + FLASH 00003100 0000cebe 00000088 0000ce36 RWIX + BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff + INT00 0000ffc0 00000002 00000000 00000002 RWIX + INT01 0000ffc2 00000002 00000000 00000002 RWIX + INT02 0000ffc4 00000002 00000000 00000002 RWIX + INT03 0000ffc6 00000002 00000000 00000002 RWIX + INT04 0000ffc8 00000002 00000000 00000002 RWIX + INT05 0000ffca 00000002 00000000 00000002 RWIX + INT06 0000ffcc 00000002 00000000 00000002 RWIX + INT07 0000ffce 00000002 00000000 00000002 RWIX + INT08 0000ffd0 00000002 00000000 00000002 RWIX + INT09 0000ffd2 00000002 00000000 00000002 RWIX + INT10 0000ffd4 00000002 00000000 00000002 RWIX + INT11 0000ffd6 00000002 00000000 00000002 RWIX + INT12 0000ffd8 00000002 00000000 00000002 RWIX + INT13 0000ffda 00000002 00000000 00000002 RWIX + INT14 0000ffdc 00000002 00000002 00000000 RWIX + INT15 0000ffde 00000002 00000002 00000000 RWIX + INT16 0000ffe0 00000002 00000002 00000000 RWIX + INT17 0000ffe2 00000002 00000002 00000000 RWIX + INT18 0000ffe4 00000002 00000002 00000000 RWIX + INT19 0000ffe6 00000002 00000002 00000000 RWIX + INT20 0000ffe8 00000002 00000002 00000000 RWIX + INT21 0000ffea 00000002 00000002 00000000 RWIX + INT22 0000ffec 00000002 00000002 00000000 RWIX + INT23 0000ffee 00000002 00000002 00000000 RWIX + INT24 0000fff0 00000002 00000002 00000000 RWIX + INT25 0000fff2 00000002 00000002 00000000 RWIX + INT26 0000fff4 00000002 00000002 00000000 RWIX + INT27 0000fff6 00000002 00000002 00000000 RWIX + INT28 0000fff8 00000002 00000002 00000000 RWIX + INT29 0000fffa 00000002 00000002 00000000 RWIX + INT30 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 00010000 00000000 00010000 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.stack 0 00003100 00000000 + +.text 0 00003100 00000080 + 00003100 00000080 main.obj (.text) + +.text:_isr +* 0 00003180 00000008 + 00003180 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00003100 00000000 UNINITIALIZED + +.binit 0 00003100 00000000 + +.init_array +* 0 00003100 00000000 UNINITIALIZED + +DAC12 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int14.asm.obj (.int14) + +DMA 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int15.asm.obj (.int15) + +BASICTIMER +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int16.asm.obj (.int16) + +PORT2 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int17.asm.obj (.int17) + +USART1TX 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int18.asm.obj (.int18) + +USART1RX 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int19.asm.obj (.int19) + +PORT1 0 0000ffe8 00000002 + 0000ffe8 00000002 main.obj (.int20) + +TIMERA1 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int21.asm.obj (.int21) + +TIMERA0 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int22.asm.obj (.int22) + +ADC12 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int23.asm.obj (.int23) + +USCIAB0TX +* 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int24.asm.obj (.int24) + +USCIAB0RX +* 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int25.asm.obj (.int25) + +WDT 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int26.asm.obj (.int26) + +COMPARATORA +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int27.asm.obj (.int27) + +TIMERB1 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int28.asm.obj (.int28) + +TIMERB0 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int29.asm.obj (.int29) + +NMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int30.asm.obj (.int30) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 main.obj (.reset) + +$fill000 0 0000ffbe 00000002 + 0000ffbe 00000002 --HOLE-- [fill = ffff] + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + main.obj 128 4 0 + +--+------------------+------+---------+---------+ + Total: 128 4 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + isr_trap.asm.obj 8 0 0 + int14.asm.obj 0 2 0 + int15.asm.obj 0 2 0 + int16.asm.obj 0 2 0 + int17.asm.obj 0 2 0 + int18.asm.obj 0 2 0 + int19.asm.obj 0 2 0 + int21.asm.obj 0 2 0 + int22.asm.obj 0 2 0 + int23.asm.obj 0 2 0 + int24.asm.obj 0 2 0 + int25.asm.obj 0 2 0 + int26.asm.obj 0 2 0 + int27.asm.obj 0 2 0 + int28.asm.obj 0 2 0 + int29.asm.obj 0 2 0 + int30.asm.obj 0 2 0 + +--+------------------+------+---------+---------+ + Total: 8 32 0 + + +--+------------------+------+---------+---------+ + Grand Total: 136 36 0 + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a6 ADC12IE +000001a4 ADC12IFG +000001a8 ADC12IV +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +00000040 BTCTL +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +000001c0 DAC12_0CTL +000001c8 DAC12_0DAT +000001c2 DAC12_1CTL +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d6 DMA0DA +000001d6 DMA0DAL +000001d2 DMA0SA +000001d2 DMA0SAL +000001da DMA0SZ +000001dc DMA1CTL +000001e2 DMA1DA +000001e2 DMA1DAL +000001de DMA1SA +000001de DMA1SAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ee DMA2DA +000001ee DMA2DAL +000001ea DMA2SA +000001ea DMA2SAL +000001f2 DMA2SZ +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000090 LCDACTL +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +00000091 LCDM1 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +00000092 LCDM2 +000000a4 LCDM20 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +00000134 MAC +00000136 MACS +00000005 ME2 +00000130 MPY +00000132 MPYS +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000138 OP2 +0000000d P10DIR +00000009 P10IN +0000000b P10OUT +0000000f P10SEL +00000022 P1DIR +00000025 P1IE +00000024 P1IES +00000023 P1IFG +00000020 P1IN +00000021 P1OUT +00000026 P1SEL +0000002a P2DIR +0000002d P2IE +0000002c P2IES +0000002b P2IFG +00000028 P2IN +00000029 P2OUT +0000002e P2SEL +0000001a P3DIR +00000018 P3IN +00000019 P3OUT +0000001b P3SEL +0000001e P4DIR +0000001c P4IN +0000001d P4OUT +0000001f P4SEL +00000032 P5DIR +00000030 P5IN +00000031 P5OUT +00000033 P5SEL +00000036 P6DIR +00000034 P6IN +00000035 P6OUT +00000037 P6SEL +0000003c P7DIR +00000038 P7IN +0000003a P7OUT +0000003e P7SEL +0000003d P8DIR +00000039 P8IN +0000003b P8OUT +0000003f P8SEL +0000000c P9DIR +00000008 P9IN +0000000a P9OUT +0000000e P9SEL +0000003c PADIR +00000038 PAIN +0000003a PAOUT +0000003e PASEL +0000000c PBDIR +00000008 PBIN +0000000a PBOUT +0000000e PBSEL +00003100 RESET +0000013c RESHI +0000013a RESLO +00000041 RTCCTL +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +00000042 RTCNT1 +00000043 RTCNT2 +00000044 RTCNT3 +00000045 RTCNT4 +00000042 RTCTIM0 +00000044 RTCTIM1 +00000040 RTCTL +0000004e RTCYEAR +0000004f RTCYEARH +0000004e RTCYEARL +00000050 SCFI0 +00000051 SCFI1 +00000052 SCFQCTL +0000013e SUMEXT +00000056 SVSCTL +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000160 TACTL +0000012e TAIV +00000170 TAR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000180 TBCTL +0000011e TBIV +00000190 TBR +0000007c U1BR0 +0000007d U1BR1 +00000078 U1CTL +0000007b U1MCTL +0000007a U1RCTL +0000007e U1RXBUF +00000079 U1TCTL +0000007f U1TXBUF +0000005d UCA0ABCTL +00000062 UCA0BR0 +00000063 UCA0BR1 +00000060 UCA0CTL0 +00000061 UCA0CTL1 +0000005f UCA0IRRCTL +0000005e UCA0IRTCTL +00000064 UCA0MCTL +00000066 UCA0RXBUF +00000065 UCA0STAT +00000067 UCA0TXBUF +0000006a UCB0BR0 +0000006b UCB0BR1 +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006c UCB0I2CIE +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000006e UCB0RXBUF +0000006d UCB0STAT +0000006f UCB0TXBUF +00000120 WDTCTL +00003100 __STACK_END +00000000 __STACK_SIZE +00003180 __TI_ISR_TRAP +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 __TI_int20 +0000ffea __TI_int21 +0000ffec __TI_int22 +0000ffee __TI_int23 +0000fff0 __TI_int24 +0000fff2 __TI_int25 +0000fff4 __TI_int26 +0000fff6 __TI_int27 +0000fff8 __TI_int28 +0000fffa __TI_int29 +0000fffc __TI_int30 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +00000000 IE1 +00000000 __STACK_SIZE +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000005 ME2 +00000008 P9IN +00000008 PBIN +00000009 P10IN +0000000a P9OUT +0000000a PBOUT +0000000b P10OUT +0000000c P9DIR +0000000c PBDIR +0000000d P10DIR +0000000e P9SEL +0000000e PBSEL +0000000f P10SEL +00000018 P3IN +00000019 P3OUT +0000001a P3DIR +0000001b P3SEL +0000001c P4IN +0000001d P4OUT +0000001e P4DIR +0000001f P4SEL +00000020 P1IN +00000021 P1OUT +00000022 P1DIR +00000023 P1IFG +00000024 P1IES +00000025 P1IE +00000026 P1SEL +00000028 P2IN +00000029 P2OUT +0000002a P2DIR +0000002b P2IFG +0000002c P2IES +0000002d P2IE +0000002e P2SEL +00000030 P5IN +00000031 P5OUT +00000032 P5DIR +00000033 P5SEL +00000034 P6IN +00000035 P6OUT +00000036 P6DIR +00000037 P6SEL +00000038 P7IN +00000038 PAIN +00000039 P8IN +0000003a P7OUT +0000003a PAOUT +0000003b P8OUT +0000003c P7DIR +0000003c PADIR +0000003d P8DIR +0000003e P7SEL +0000003e PASEL +0000003f P8SEL +00000040 BTCTL +00000040 RTCTL +00000041 RTCCTL +00000042 RTCNT1 +00000042 RTCTIM0 +00000043 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files /dev/null and b/CPE325/Lab6_Problem1/Debug/Lab6_Problem1.out differ diff --git a/CPE325/Lab6_Problem1/Debug/Lab6_Problem1_linkInfo.xml b/CPE325/Lab6_Problem1/Debug/Lab6_Problem1_linkInfo.xml new file mode 100644 index 0000000..16d58cf --- /dev/null +++ b/CPE325/Lab6_Problem1/Debug/Lab6_Problem1_linkInfo.xml @@ -0,0 +1,2610 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x61576c9e + 0x0 + Lab6_Problem1.out + + RESET +
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+ + + DMA1CTL + 0x1dc + + + DMA2CTL + 0x1e8 + + + DMA0SA + 0x1d2 + + + DMA0SAL + 0x1d2 + + + DMA0DA + 0x1d6 + + + DMA0DAL + 0x1d6 + + + DMA0SZ + 0x1da + + + DMA1SA + 0x1de + + + DMA1SAL + 0x1de + + + DMA1DA + 0x1e2 + + + DMA1DAL + 0x1e2 + + + DMA1SZ + 0x1e6 + + + DMA2SA + 0x1ea + + + DMA2SAL + 0x1ea + + + DMA2DA + 0x1ee + + + DMA2DAL + 0x1ee + + + DMA2SZ + 0x1f2 + + + FCTL1 + 0x128 + + + FCTL2 + 0x12a + + + FCTL3 + 0x12c + + + SCFI0 + 0x50 + + + SCFI1 + 0x51 + + + SCFQCTL + 0x52 + + + FLL_CTL0 + 0x53 + + + FLL_CTL1 + 0x54 + + + LCDACTL + 0x90 + + + LCDAPCTL0 + 0xac + + + LCDAPCTL1 + 0xad + + + LCDAVCTL0 + 0xae + + + LCDAVCTL1 + 0xaf + + + LCDM1 + 0x91 + + + LCDM2 + 0x92 + + + LCDM3 + 0x93 + + + LCDM4 + 0x94 + + + LCDM5 + 0x95 + + + LCDM6 + 0x96 + + + LCDM7 + 0x97 + + + LCDM8 + 0x98 + + + LCDM9 + 0x99 + + + LCDM10 + 0x9a + + + LCDM11 + 0x9b + + + LCDM12 + 0x9c + + + LCDM13 + 0x9d + + + LCDM14 + 0x9e + + + LCDM15 + 0x9f + + + LCDM16 + 0xa0 + + + LCDM17 + 0xa1 + + + LCDM18 + 0xa2 + + + LCDM19 + 0xa3 + + + LCDM20 + 0xa4 + + + MPY + 0x130 + + + MPYS + 0x132 + + + MAC + 0x134 + + + MACS + 0x136 + + + OP2 + 0x138 + + + RESLO + 0x13a + + + RESHI + 0x13c + + + SUMEXT + 0x13e + + + OA0CTL0 + 0xc0 + + + OA0CTL1 + 0xc1 + + + OA1CTL0 + 0xc2 + + + OA1CTL1 + 0xc3 + + + OA2CTL0 + 0xc4 + + + OA2CTL1 + 0xc5 + + + P1IN + 0x20 + + + P1OUT + 0x21 + + + P1DIR + 0x22 + + + P1IFG + 0x23 + + + P1IES + 0x24 + + + P1IE + 0x25 + + + P1SEL + 0x26 + + + P2IN + 0x28 + + + P2OUT + 0x29 + + + P2DIR + 0x2a + + + P2IFG + 0x2b + + + P2IES + 0x2c + + + P2IE + 0x2d + + + P2SEL + 0x2e + + + P3IN + 0x18 + + + P3OUT + 0x19 + + + P3DIR + 0x1a + + + P3SEL + 0x1b + + + P4IN + 0x1c + + + P4OUT + 0x1d + + + P4DIR + 0x1e + + + P4SEL + 0x1f + + + P5IN + 0x30 + + + P5OUT + 0x31 + + + P5DIR + 0x32 + + + P5SEL + 0x33 + + + P6IN + 0x34 + + + P6OUT + 0x35 + + + P6DIR + 0x36 + + + P6SEL + 0x37 + + + P7IN + 0x38 + + + P7OUT + 0x3a + + + P7DIR + 0x3c + + + P7SEL + 0x3e + + + P8IN + 0x39 + + + P8OUT + 0x3b + + + P8DIR + 0x3d + + + P8SEL + 0x3f + + + PAIN + 0x38 + + + PAOUT + 0x3a + + + PADIR + 0x3c + + + PASEL + 0x3e + + + P9IN + 0x8 + + + P9OUT + 0xa + + + P9DIR + 0xc + + + P9SEL + 0xe + + + P10IN + 0x9 + + + P10OUT + 0xb + + + P10DIR + 0xd + + + P10SEL + 0xf + + + PBIN + 0x8 + + + PBOUT + 0xa + + + PBDIR + 0xc + + + PBSEL + 0xe + + + SVSCTL + 0x56 + + + TAIV + 0x12e + + + TACTL + 0x160 + + + TACCTL0 + 0x162 + + + TACCTL1 + 0x164 + + + TACCTL2 + 0x166 + + + TAR + 0x170 + + + TACCR0 + 0x172 + + + TACCR1 + 0x174 + + + TACCR2 + 0x176 + + + TBIV + 0x11e + + + TBCTL + 0x180 + + + TBCCTL0 + 0x182 + + + TBCCTL1 + 0x184 + + + TBCCTL2 + 0x186 + + + TBCCTL3 + 0x188 + + + TBCCTL4 + 0x18a + + + TBCCTL5 + 0x18c + + + TBCCTL6 + 0x18e + + + TBR + 0x190 + + + TBCCR0 + 0x192 + + + TBCCR1 + 0x194 + + + TBCCR2 + 0x196 + + + TBCCR3 + 0x198 + + + TBCCR4 + 0x19a + + + TBCCR5 + 0x19c + + + TBCCR6 + 0x19e + + + UCA0CTL0 + 0x60 + + + UCA0CTL1 + 0x61 + + + UCA0BR0 + 0x62 + + + UCA0BR1 + 0x63 + + + UCA0MCTL + 0x64 + + + UCA0STAT + 0x65 + + + UCA0RXBUF + 0x66 + + + UCA0TXBUF + 0x67 + + + UCA0ABCTL + 0x5d + + + UCA0IRTCTL + 0x5e + + + UCA0IRRCTL + 0x5f + + + UCB0CTL0 + 0x68 + + + UCB0CTL1 + 0x69 + + + UCB0BR0 + 0x6a + + + UCB0BR1 + 0x6b + + + UCB0I2CIE + 0x6c + + + UCB0STAT + 0x6d + + + UCB0RXBUF + 0x6e + + + UCB0TXBUF + 0x6f + + + UCB0I2COA + 0x118 + + + UCB0I2CSA + 0x11a + + + U1CTL + 0x78 + + + U1TCTL + 0x79 + + + U1RCTL + 0x7a + + + U1MCTL + 0x7b + + + U1BR0 + 0x7c + + + U1BR1 + 0x7d + + + U1RXBUF + 0x7e + + + U1TXBUF + 0x7f + + + WDTCTL + 0x120 + + + __STACK_SIZE + 0x0 + + + __STACK_END + 0x3100 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + RESET + 0x3100 + + + + __TI_int20 + 0xffe8 + + + + __TI_int14 + 0xffdc + + + + __TI_int15 + 0xffde + + + + __TI_int16 + 0xffe0 + + + + __TI_int17 + 0xffe2 + + + + __TI_int18 + 0xffe4 + + + + __TI_int19 + 0xffe6 + + + + __TI_int21 + 0xffea + + + + __TI_int22 + 0xffec + + + + __TI_int23 + 0xffee + + + + __TI_int24 + 0xfff0 + + + + __TI_int25 + 0xfff2 + + + + __TI_int26 + 0xfff4 + + + + __TI_int27 + 0xfff6 + + + + __TI_int28 + 0xfff8 + + + + __TI_int29 + 0xfffa + + + + __TI_int30 + 0xfffc + + + + __TI_ISR_TRAP + 0x3180 + + + + Link successful + diff --git a/CPE325/Lab6_Problem1/Debug/ccsObjs.opt b/CPE325/Lab6_Problem1/Debug/ccsObjs.opt new file mode 100644 index 0000000..2f36690 --- /dev/null +++ b/CPE325/Lab6_Problem1/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./main.obj" "../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/Lab6_Problem1/Debug/main.obj b/CPE325/Lab6_Problem1/Debug/main.obj new file mode 100644 index 0000000..702410e Binary files /dev/null and b/CPE325/Lab6_Problem1/Debug/main.obj differ diff --git a/CPE325/Lab6_Problem1/Debug/makefile b/CPE325/Lab6_Problem1/Debug/makefile new file mode 100644 index 0000000..4b9d62d --- /dev/null +++ b/CPE325/Lab6_Problem1/Debug/makefile @@ -0,0 +1,166 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab6_Problem1.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab6_Problem1.out" \ + +BIN_OUTPUTS += \ +Lab6_Problem1.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab6_Problem1.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab6_Problem1.out" + +# Tool invocations +Lab6_Problem1.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --code_model=small --data_model=small --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"Lab6_Problem1.map" --heap_size=0 --stack_size=0 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab6_Problem1_linkInfo.xml" --entry_point=RESET --use_hw_mpy=16 -o "Lab6_Problem1.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab6_Problem1.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab6_Problem1.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "main.obj" + -$(RM) "main.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab6_Problem1/Debug/objects.mk b/CPE325/Lab6_Problem1/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/Lab6_Problem1/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/Lab6_Problem1/Debug/sources.mk b/CPE325/Lab6_Problem1/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab6_Problem1/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab6_Problem1/Debug/subdir_rules.mk b/CPE325/Lab6_Problem1/Debug/subdir_rules.mk new file mode 100644 index 0000000..9f14dde --- /dev/null +++ b/CPE325/Lab6_Problem1/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --code_model=small --data_model=small --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab6_Problem1" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --preproc_with_compile --preproc_dependency="$(basename $(LED1(GREEN) +; | P2.1|-->LED2(YELLOW) +; +; Author: Aleksandar Milenkovic, milenkovic@computer.org +; Date: September 14, 2018 +;------------------------------------------------------------------------------- + .cdecls C,LIST,"msp430.h" ; Include device header file + +;------------------------------------------------------------------------------- + .def RESET ; Export program entry-point to + ; make it known to linker. +;------------------------------------------------------------------------------- + .text ; Assemble into program memory. + .retain ; Override ELF conditional linking + ; and retain current section. + .retainrefs ; And retain any sections that have + ; references to current section. + +;------------------------------------------------------------------------------- +RESET: mov.w #__STACK_END,SP ; Initialize stack pointer +StopWDT: mov.w #WDTPW|WDTHOLD,&WDTCTL ; Stop watchdog timer +Setup: bis.b #0x06,&P2DIR ; Set P2.2 and P2.1 to output + ; direction (0000_0110) + bic.b #0x04,&P2OUT ; Set P2OUT to 0x0000_0100 (LEDS off) +InfLoop: mov.w #0xFFFF, R5 ; Software delay (65,535*16cc/2^20 ~ 1s) +SWDelay1: nop ; 1cc (total delay is 16 cc) + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + dec.w R5 ; 1cc + jnz SWDelay1 ; 2cc + xor.b #0x06, P2OUT ; toggle LEDs + jmp InfLoop ; goto InfLoop + +;------------------------------------------------------------------------------- +; Stack Pointer definition +;------------------------------------------------------------------------------- + .global __STACK_END + .sect .stack + +;------------------------------------------------------------------------------- +; Interrupt Vectors +;------------------------------------------------------------------------------- + .sect ".reset" ; MSP430 RESET Vector + .short RESET + diff --git a/CPE325/Lab6_Problem1/Lab6_D2.asm b/CPE325/Lab6_Problem1/Lab6_D2.asm new file mode 100644 index 0000000..6f5054b --- /dev/null +++ b/CPE325/Lab6_Problem1/Lab6_D2.asm @@ -0,0 +1,80 @@ +;------------------------------------------------------------------------------- +; File: Lab6_D2.asm +; Description: The program demonstrates Press/Release using SW1 and LED1. +; LED1 is initialized off. +; When SW1 press is detected, a software delay of 20 ms +; is used to implement debouncing. The switch is checked +; again, and if on, LED1 is turned on until SW1 is released. +; +; Clocks: ACLK = 32.768kHz, MCLK = SMCLK = default DCO = 2^20=1,048,576 Hz +; Platform: TI Experimenter's Board +; +; MSP430xG461x +; ----------------- +; /|\| | +; | | | +; --|RST | +; | P2.2|-->LED1(GREEN) +; | P1.0|<--SW1 +; +; Author: Aleksandar Milenkovic, milenkovic@computer.org +; Date: September 14, 2018 +;------------------------------------------------------------------------------- + + .cdecls C,LIST,"msp430.h" ; Include device header file + +;------------------------------------------------------------------------------- + .def RESET ; Export program entry-point to + ; make it known to linker. +;------------------------------------------------------------------------------- + .text ; Assemble into program memory. + .retain ; Override ELF conditional linking + ; and retain current section. + .retainrefs ; And retain any sections that have + ; references to current section. + +;------------------------------------------------------------------------------- +RESET: mov.w #__STACK_END,SP ; Initialize stack pointer +StopWDT: mov.w #WDTPW|WDTHOLD,&WDTCTL ; Stop watchdog timer +;------------------------------------------------------------------------------- +SetupP2: + bis.b #004h, &P2DIR ; Set P2.2 to output + ; direction (0000_0100) + bic.b #004h, &P2OUT ; Set P2OUT to 0x0000_0100 (ensure + ; LED1 is off) +ChkSW1: bit.b #01h, &P1IN ; Check if SW1 is pressed + ; (0000_0001 on P1IN) + jnz ChkSW1 ; If not zero, SW is not pressed + ; loop and check again +Debounce: + mov.w #2000, R15 ; Set to (2000 * 10 cc = 20,000 cc) +SWD20ms: dec.w R15 ; Decrement R15 + nop + nop + nop + nop + nop + nop + nop + jnz SWD20ms ; Delay over? + bit.b #00000001b, &P1IN ; Verify SW1 is still pressed + jnz ChkSW1 ; If not, wait for SW1 press + +LEDon: bis.b #004h, &P2OUT ; Turn on LED1 +SW1wait: bit.b #001h, &P1IN ; Test SW1 + jz SW1wait ; Wait until SW1 is released + bic.b #004, &P2OUT ; Turn off LED1 + jmp ChkSW1 ; Loop to beginning + +;------------------------------------------------------------------------------- +; Stack Pointer definition +;------------------------------------------------------------------------------- + .global __STACK_END + .sect .stack + +;------------------------------------------------------------------------------- +; Interrupt Vectors +;------------------------------------------------------------------------------- + .sect ".reset" ; MSP430 RESET Vector + .short RESET + .end diff --git a/CPE325/Lab6_Problem1/lnk_msp430fg4618.cmd b/CPE325/Lab6_Problem1/lnk_msp430fg4618.cmd new file mode 100755 index 0000000..557b664 --- /dev/null +++ b/CPE325/Lab6_Problem1/lnk_msp430fg4618.cmd @@ -0,0 +1,184 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************************/ +/* lnk_msp430fg4618.cmd - LINKER COMMAND FILE FOR LINKING MSP430FG4618 PROGRAMS */ +/* */ +/* Usage: lnk430 -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/Lab6_Problem1/main.asm b/CPE325/Lab6_Problem1/main.asm new file mode 100644 index 0000000..11977b9 --- /dev/null +++ b/CPE325/Lab6_Problem1/main.asm @@ -0,0 +1,94 @@ +;------------------------------------------------------------------------------- +; MSP430 Assembler Code Template for use with TI Code Composer Studio +; +; +;------------------------------------------------------------------------------- + .cdecls C,LIST,"msp430.h" ; Include device header file + +;------------------------------------------------------------------------------- + .def RESET ; Export program entry-point to + ; make it known to linker. +;------------------------------------------------------------------------------- + .text ; Assemble into program memory. + .retain ; Override ELF conditional linking + ; and retain current section. + .retainrefs ; And retain any sections that have + ; references to current section. + +;------------------------------------------------------------------------------- +RESET mov.w #__STACK_END,SP ; Initialize stackpointer +StopWDT mov.w #WDTPW|WDTHOLD,&WDTCTL ; Stop watchdog timer + + +;------------------------------------------------------------------------------- +; Main loop here +;------------------------------------------------------------------------------- +Setup: + bis.b #004h, &P2DIR ; Set P2.2 to output + ; direction (0000_0100) + bic.b #004h, &P2OUT ; Set P2OUT to 0x0000_0100 (ensure + ; LED1 is off) + bis.b #002h, &P2DIR ; Set P2.1 to output + ; direction (0000_0010) + bic.b #002h, &P2OUT ; Set P2OUT to 0x0000_0010 (ensure + ; LED1 is off) + + bis.w #GIE, SR ; Enable Global Interrupts + bis.b #001h, &P1IE ; Enable Port 1 interrupt from bit 0 + bis.b #001h, &P1IES ; Set interrupt to call from hi to low + bic.b #001h, &P1IFG ; Clear interrupt flag + ;mov.w #0, R8 ; Counter for inner loop + bic.b #0x04,&P2OUT ; Set P2OUT to 0x0000_0100 (LEDS off) +InfLoop: mov.w #0xFFFF, R5 ; Software delay (65,535*16cc/2^20 ~ 1s) + mov.w #0, R8 ; Counter for inner loop +Iter: +SWDelay1: nop ; 1cc (total delay is 16 cc) + nop + nop + nop + nop + nop + nop + nop + nop + nop + dec.w R5 ; 1cc + jnz SWDelay1 ; 2cc + inc.b R8 ; 3cc + cmp #2, R8 ; 4cc + jnz Iter ; jump to Iter + xor.b #0x02, P2OUT ; toggle LED 2 + jmp InfLoop ; goto InfLoop + +SW1_ISR: bic.b #001h, &P1IFG ; Clear interrupt flag +ChkSw1: bit.b #01h, &P1IN ; Check if SW1 is pressed + ; (0000_0001 on P1IN) + jnz LExit ; If not zero, SW is not pressed + ; loop and check again +Debounce: mov.w #2000, R15 ; Set to (2000 * 10 cc ) +SWD20ms: dec.w R15 ; Decrement R15 + nop + nop + nop + nop + nop + nop + nop + jnz SWD20ms ; Delay over? + bit.b #00000001b,&P1IN ; Verify SW1 is still pressed + jnz LExit ; If not, wait for SW1 press +LEDon: xor.b #0x04,P2OUT ; Turn on LED1 +LExit: reti ; Return from interrupt +;------------------------------------------------------------------------------- +; Stack Pointer definition +;------------------------------------------------------------------------------- + .global __STACK_END + .sect .stack +;------------------------------------------------------------------------------- +; Interrupt Vectors +;------------------------------------------------------------------------------- + .sect ".reset" ; MSP430 RESET Vector + .short RESET + .sect ".int20" ; + .short SW1_ISR ; set SW1 Interupt service routine + .end diff --git a/CPE325/Lab6_Problem1/targetConfigs/MSP430FG4618.ccxml b/CPE325/Lab6_Problem1/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/Lab6_Problem1/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab6_Problem1/targetConfigs/readme.txt b/CPE325/Lab6_Problem1/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab6_Problem1/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab6_Problem2/Debug/Lab6_Problem2.map b/CPE325/Lab6_Problem2/Debug/Lab6_Problem2.map new file mode 100644 index 0000000..7975eb6 --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/Lab6_Problem2.map @@ -0,0 +1,750 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Thu Dec 2 20:38:06 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noinit_noargs" address: 000031b0 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOB 00001000 00000080 00000000 00000080 RWIX + INFOA 00001080 00000080 00000000 00000080 RWIX + RAM 00001100 00002000 00000050 00001fb0 RWIX + FLASH 00003100 0000cebe 000000d6 0000cde8 RWIX + BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff + INT00 0000ffc0 00000002 00000000 00000002 RWIX + INT01 0000ffc2 00000002 00000000 00000002 RWIX + INT02 0000ffc4 00000002 00000000 00000002 RWIX + INT03 0000ffc6 00000002 00000000 00000002 RWIX + INT04 0000ffc8 00000002 00000000 00000002 RWIX + INT05 0000ffca 00000002 00000000 00000002 RWIX + INT06 0000ffcc 00000002 00000000 00000002 RWIX + INT07 0000ffce 00000002 00000000 00000002 RWIX + INT08 0000ffd0 00000002 00000000 00000002 RWIX + INT09 0000ffd2 00000002 00000000 00000002 RWIX + INT10 0000ffd4 00000002 00000000 00000002 RWIX + INT11 0000ffd6 00000002 00000000 00000002 RWIX + INT12 0000ffd8 00000002 00000000 00000002 RWIX + INT13 0000ffda 00000002 00000000 00000002 RWIX + INT14 0000ffdc 00000002 00000002 00000000 RWIX + INT15 0000ffde 00000002 00000002 00000000 RWIX + INT16 0000ffe0 00000002 00000002 00000000 RWIX + INT17 0000ffe2 00000002 00000002 00000000 RWIX + INT18 0000ffe4 00000002 00000002 00000000 RWIX + INT19 0000ffe6 00000002 00000002 00000000 RWIX + INT20 0000ffe8 00000002 00000002 00000000 RWIX + INT21 0000ffea 00000002 00000002 00000000 RWIX + INT22 0000ffec 00000002 00000002 00000000 RWIX + INT23 0000ffee 00000002 00000002 00000000 RWIX + INT24 0000fff0 00000002 00000002 00000000 RWIX + INT25 0000fff2 00000002 00000002 00000000 RWIX + INT26 0000fff4 00000002 00000002 00000000 RWIX + INT27 0000fff6 00000002 00000002 00000000 RWIX + INT28 0000fff8 00000002 00000002 00000000 RWIX + INT29 0000fffa 00000002 00000002 00000000 RWIX + INT30 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 00010000 00000000 00010000 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.stack 0 000030b0 00000050 UNINITIALIZED + 000030b0 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 000030b2 0000004e --HOLE-- + +.text 0 00003100 000000ce + 00003100 0000005c main.obj (.text:main) + 0000315c 00000054 main.obj (.text:Port1_ISR) + 000031b0 00000014 rts430_eabi.lib : boot.c.obj (.text:_c_int00_noinit_noargs) + 000031c4 00000006 : exit.c.obj (.text:abort) + 000031ca 00000004 : pre_init.c.obj (.text:_system_pre_init) + +.text:_isr +* 0 000031ce 00000008 + 000031ce 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00003100 00000000 UNINITIALIZED + +.binit 0 00003100 00000000 + +.init_array +* 0 00003100 00000000 UNINITIALIZED + +DAC12 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int14.asm.obj (.int14) + +DMA 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int15.asm.obj (.int15) + +BASICTIMER +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int16.asm.obj (.int16) + +PORT2 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int17.asm.obj (.int17) + +USART1TX 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int18.asm.obj (.int18) + +USART1RX 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int19.asm.obj (.int19) + +PORT1 0 0000ffe8 00000002 + 0000ffe8 00000002 main.obj (.int20) + +TIMERA1 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int21.asm.obj (.int21) + +TIMERA0 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int22.asm.obj (.int22) + +ADC12 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int23.asm.obj (.int23) + +USCIAB0TX +* 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int24.asm.obj (.int24) + +USCIAB0RX +* 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int25.asm.obj (.int25) + +WDT 0 0000fff4 00000002 + 0000fff4 00000002 rts430_eabi.lib : int26.asm.obj (.int26) + +COMPARATORA +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int27.asm.obj (.int27) + +TIMERB1 0 0000fff8 00000002 + 0000fff8 00000002 rts430_eabi.lib : int28.asm.obj (.int28) + +TIMERB0 0 0000fffa 00000002 + 0000fffa 00000002 rts430_eabi.lib : int29.asm.obj (.int29) + +NMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int30.asm.obj (.int30) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +$fill000 0 0000ffbe 00000002 + 0000ffbe 00000002 --HOLE-- [fill = ffff] + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + main.obj 176 2 0 + +--+------------------+------+---------+---------+ + Total: 176 2 0 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + boot.c.obj 20 2 0 + isr_trap.asm.obj 8 0 0 + exit.c.obj 6 0 0 + pre_init.c.obj 4 0 0 + int14.asm.obj 0 2 0 + int15.asm.obj 0 2 0 + int16.asm.obj 0 2 0 + int17.asm.obj 0 2 0 + int18.asm.obj 0 2 0 + int19.asm.obj 0 2 0 + int21.asm.obj 0 2 0 + int22.asm.obj 0 2 0 + int23.asm.obj 0 2 0 + int24.asm.obj 0 2 0 + int25.asm.obj 0 2 0 + int26.asm.obj 0 2 0 + int27.asm.obj 0 2 0 + int28.asm.obj 0 2 0 + int29.asm.obj 0 2 0 + int30.asm.obj 0 2 0 + +--+------------------+------+---------+---------+ + Total: 38 34 0 + + Stack: 0 0 80 + +--+------------------+------+---------+---------+ + Grand Total: 214 36 80 + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a6 ADC12IE +000001a4 ADC12IFG +000001a8 ADC12IV +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +00000040 BTCTL +000031c4 C$$EXIT +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +000001c0 DAC12_0CTL +000001c8 DAC12_0DAT +000001c2 DAC12_1CTL +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d6 DMA0DA +000001d6 DMA0DAL +000001d2 DMA0SA +000001d2 DMA0SAL +000001da DMA0SZ +000001dc DMA1CTL +000001e2 DMA1DA +000001e2 DMA1DAL +000001de DMA1SA +000001de DMA1SAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ee DMA2DA +000001ee DMA2DAL +000001ea DMA2SA +000001ea DMA2SAL +000001f2 DMA2SZ +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000090 LCDACTL +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +00000091 LCDM1 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +00000092 LCDM2 +000000a4 LCDM20 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +00000134 MAC +00000136 MACS +00000005 ME2 +00000130 MPY +00000132 MPYS +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000138 OP2 +0000000d P10DIR +00000009 P10IN +0000000b P10OUT +0000000f P10SEL +00000022 P1DIR +00000025 P1IE +00000024 P1IES +00000023 P1IFG +00000020 P1IN +00000021 P1OUT +00000026 P1SEL +0000002a P2DIR +0000002d P2IE +0000002c P2IES +0000002b P2IFG +00000028 P2IN +00000029 P2OUT +0000002e P2SEL +0000001a P3DIR +00000018 P3IN +00000019 P3OUT +0000001b P3SEL +0000001e P4DIR +0000001c P4IN +0000001d P4OUT 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TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000180 TBCTL +0000011e TBIV +00000190 TBR +0000007c U1BR0 +0000007d U1BR1 +00000078 U1CTL +0000007b U1MCTL +0000007a U1RCTL +0000007e U1RXBUF +00000079 U1TCTL +0000007f U1TXBUF +0000005d UCA0ABCTL +00000062 UCA0BR0 +00000063 UCA0BR1 +00000060 UCA0CTL0 +00000061 UCA0CTL1 +0000005f UCA0IRRCTL +0000005e UCA0IRTCTL +00000064 UCA0MCTL +00000066 UCA0RXBUF +00000065 UCA0STAT +00000067 UCA0TXBUF +0000006a UCB0BR0 +0000006b UCB0BR1 +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006c UCB0I2CIE +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000006e UCB0RXBUF +0000006d UCB0STAT +0000006f UCB0TXBUF +00000120 WDTCTL +00003100 __STACK_END +00000050 __STACK_SIZE +000031ce __TI_ISR_TRAP +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 __TI_int20 +0000ffea __TI_int21 +0000ffec __TI_int22 +0000ffee __TI_int23 +0000fff0 __TI_int24 +0000fff2 __TI_int25 +0000fff4 __TI_int26 +0000fff6 __TI_int27 +0000fff8 __TI_int28 +0000fffa __TI_int29 +0000fffc __TI_int30 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ +000031b0 _c_int00_noinit_noargs +0000fffe _reset_vector +000030b0 _stack +000031ca _system_pre_init +000031c4 abort +00003100 main + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000005 ME2 +00000008 P9IN +00000008 PBIN +00000009 P10IN +0000000a P9OUT +0000000a PBOUT +0000000b P10OUT +0000000c P9DIR +0000000c PBDIR +0000000d P10DIR +0000000e P9SEL +0000000e PBSEL +0000000f P10SEL +00000018 P3IN +00000019 P3OUT +0000001a P3DIR +0000001b P3SEL +0000001c P4IN +0000001d P4OUT +0000001e P4DIR +0000001f P4SEL +00000020 P1IN +00000021 P1OUT +00000022 P1DIR +00000023 P1IFG +00000024 P1IES +00000025 P1IE +00000026 P1SEL +00000028 P2IN +00000029 P2OUT +0000002a P2DIR +0000002b P2IFG +0000002c P2IES +0000002d P2IE +0000002e P2SEL +00000030 P5IN +00000031 P5OUT +00000032 P5DIR +00000033 P5SEL +00000034 P6IN +00000035 P6OUT +00000036 P6DIR +00000037 P6SEL +00000038 P7IN +00000038 PAIN +00000039 P8IN +0000003a P7OUT +0000003a PAOUT +0000003b P8OUT +0000003c P7DIR +0000003c PADIR +0000003d P8DIR +0000003e P7SEL +0000003e PASEL +0000003f P8SEL +00000040 BTCTL +00000040 RTCTL +00000041 RTCCTL +00000042 RTCNT1 +00000042 RTCTIM0 +00000043 RTCNT2 +00000044 RTCNT3 +00000044 RTCTIM1 +00000045 RTCNT4 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +0000004e RTCYEAR +0000004e RTCYEARL +0000004f RTCYEARH +00000050 SCFI0 +00000050 __STACK_SIZE +00000051 SCFI1 +00000052 SCFQCTL +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000056 SVSCTL +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +0000005d UCA0ABCTL +0000005e UCA0IRTCTL +0000005f UCA0IRRCTL +00000060 UCA0CTL0 +00000061 UCA0CTL1 +00000062 UCA0BR0 +00000063 UCA0BR1 +00000064 UCA0MCTL +00000065 UCA0STAT +00000066 UCA0RXBUF +00000067 UCA0TXBUF +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006a UCB0BR0 +0000006b UCB0BR1 +0000006c UCB0I2CIE +0000006d UCB0STAT +0000006e UCB0RXBUF +0000006f UCB0TXBUF +00000078 U1CTL +00000079 U1TCTL +0000007a U1RCTL +0000007b U1MCTL +0000007c U1BR0 +0000007d U1BR1 +0000007e U1RXBUF +0000007f U1TXBUF +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000090 LCDACTL +00000091 LCDM1 +00000092 LCDM2 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +000000a4 LCDM20 +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000011e TBIV +00000120 WDTCTL +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +0000012e TAIV +00000130 MPY +00000132 MPYS +00000134 MAC +00000136 MACS +00000138 OP2 +0000013a RESLO +0000013c RESHI +0000013e SUMEXT +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000160 TACTL +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000170 TAR +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000180 TBCTL +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000190 TBR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a4 ADC12IFG +000001a6 ADC12IE +000001a8 ADC12IV +000001c0 DAC12_0CTL +000001c2 DAC12_1CTL +000001c8 DAC12_0DAT +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d2 DMA0SA +000001d2 DMA0SAL +000001d6 DMA0DA +000001d6 DMA0DAL +000001da DMA0SZ +000001dc DMA1CTL +000001de DMA1SA +000001de DMA1SAL +000001e2 DMA1DA +000001e2 DMA1DAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ea DMA2SA +000001ea DMA2SAL +000001ee DMA2DA +000001ee DMA2DAL +000001f2 DMA2SZ +000030b0 _stack +00003100 __STACK_END +00003100 main +0000315c Port1_ISR +000031b0 _c_int00_noinit_noargs +000031c4 C$$EXIT +000031c4 abort +000031ca _system_pre_init +000031ce __TI_ISR_TRAP +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 __TI_int20 +0000ffea __TI_int21 +0000ffec __TI_int22 +0000ffee __TI_int23 +0000fff0 __TI_int24 +0000fff2 __TI_int25 +0000fff4 __TI_int26 +0000fff6 __TI_int27 +0000fff8 __TI_int28 +0000fffa __TI_int29 +0000fffc __TI_int30 +0000fffe _reset_vector +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[278 symbols] diff --git a/CPE325/Lab6_Problem2/Debug/Lab6_Problem2.out b/CPE325/Lab6_Problem2/Debug/Lab6_Problem2.out new file mode 100644 index 0000000..96223c1 Binary files /dev/null and b/CPE325/Lab6_Problem2/Debug/Lab6_Problem2.out differ diff --git a/CPE325/Lab6_Problem2/Debug/Lab6_Problem2_linkInfo.xml b/CPE325/Lab6_Problem2/Debug/Lab6_Problem2_linkInfo.xml new file mode 100644 index 0000000..77e1b6b --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/Lab6_Problem2_linkInfo.xml @@ -0,0 +1,3083 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x61a9830e + 0x0 + Lab6_Problem2.out + + _c_int00_noinit_noargs +
0x31b0
+ + + + .\ + object + main.obj + main.obj + + + object + <internal> + <internal> + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int14.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int15.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int16.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int17.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int18.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int19.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int21.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int22.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int23.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int24.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int25.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int26.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int27.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int28.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int29.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + int30.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + isr_trap.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + mult16_hw.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + mult1632_hw.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + mult32_hw.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + mult3264_hw.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + mult64_hw.asm.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + boot.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + autoinit.c.obj + + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\ + archive + rts430_eabi.lib + copy_zero_init.c.obj + + + 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0x5d + + + UCA0IRTCTL + 0x5e + + + UCA0IRRCTL + 0x5f + + + UCB0CTL0 + 0x68 + + + UCB0CTL1 + 0x69 + + + UCB0BR0 + 0x6a + + + UCB0BR1 + 0x6b + + + UCB0I2CIE + 0x6c + + + UCB0STAT + 0x6d + + + UCB0RXBUF + 0x6e + + + UCB0TXBUF + 0x6f + + + UCB0I2COA + 0x118 + + + UCB0I2CSA + 0x11a + + + U1CTL + 0x78 + + + U1TCTL + 0x79 + + + U1RCTL + 0x7a + + + U1MCTL + 0x7b + + + U1BR0 + 0x7c + + + U1BR1 + 0x7d + + + U1RXBUF + 0x7e + + + U1TXBUF + 0x7f + + + WDTCTL + 0x120 + + + __STACK_SIZE + 0x50 + + + __STACK_END + 0x3100 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + __TI_int20 + 0xffe8 + + + + Port1_ISR + 0x315c + + + + main + 0x3100 + + + + __TI_int14 + 0xffdc + + + + __TI_int15 + 0xffde + + + + __TI_int16 + 0xffe0 + + + + __TI_int17 + 0xffe2 + + + + __TI_int18 + 0xffe4 + + + + __TI_int19 + 0xffe6 + + + + __TI_int21 + 0xffea + + + + __TI_int22 + 0xffec + + + + __TI_int23 + 0xffee + + + + __TI_int24 + 0xfff0 + + + + __TI_int25 + 0xfff2 + + + + __TI_int26 + 0xfff4 + + + + __TI_int27 + 0xfff6 + + + + __TI_int28 + 0xfff8 + + + + __TI_int29 + 0xfffa + + + + __TI_int30 + 0xfffc + + + + __TI_ISR_TRAP + 0x31ce + + + + _c_int00_noinit_noargs + 0x31b0 + + + + _stack + 0x30b0 + + + + _reset_vector + 0xfffe + + + + _system_pre_init + 0x31ca + + + + C$$EXIT + 0x31c4 + + + + abort + 0x31c4 + + + + Link successful + diff --git a/CPE325/Lab6_Problem2/Debug/ccsObjs.opt b/CPE325/Lab6_Problem2/Debug/ccsObjs.opt new file mode 100644 index 0000000..2f36690 --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./main.obj" "../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/Lab6_Problem2/Debug/main.d b/CPE325/Lab6_Problem2/Debug/main.d new file mode 100644 index 0000000..15f98dd --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/main.d @@ -0,0 +1,21 @@ +# FIXED + +main.obj: ../main.c +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h + +../main.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + diff --git a/CPE325/Lab6_Problem2/Debug/main.lst b/CPE325/Lab6_Problem2/Debug/main.lst new file mode 100644 index 0000000..b881034 --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/main.lst @@ -0,0 +1,614 @@ +MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 1 + + 1 ;****************************************************************************** + 2 ;* MSP430 G3 C/C++ Codegen PC v20.2.5.LTS * + 3 ;* Date/Time created: Thu Dec 2 20:38:06 2021 * + 4 ;****************************************************************************** + 5 .compiler_opts --abi=eabi --diag_wrap=off --hll_source=on --mem_model:code=small --mem_model:d + 6 + 7 $C$DW$CU .dwtag DW_TAG_compile_unit + 8 .dwattr $C$DW$CU, DW_AT_name("../main.c") + 9 .dwattr $C$DW$CU, DW_AT_producer("TI MSP430 G3 C/C++ Codegen PC v20.2.5.LTS Copyright (c) 2003 + 10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + 11 .dwattr $C$DW$CU, DW_AT_comp_dir("C:\CPE325_Workspace\Lab6_Problem2\Debug") + 12 ; Interrupt vector table mappings + 13 000000 .intvec ".int20", Port1_ISR + 000000 + 14 $C$DW$1 .dwtag DW_TAG_variable + 15 .dwattr $C$DW$1, DW_AT_name("SCFI0") + 16 .dwattr $C$DW$1, DW_AT_TI_symbol_name("SCFI0") + 17 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$23) + 18 .dwattr $C$DW$1, DW_AT_declaration + 19 .dwattr $C$DW$1, DW_AT_external + 20 .dwattr $C$DW$1, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 21 .dwattr $C$DW$1, DW_AT_decl_line(0x331) + 22 .dwattr $C$DW$1, DW_AT_decl_column(0x01) + 23 + 24 $C$DW$2 .dwtag DW_TAG_variable + 25 .dwattr $C$DW$2, DW_AT_name("SCFQCTL") + 26 .dwattr $C$DW$2, DW_AT_TI_symbol_name("SCFQCTL") + 27 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$23) + 28 .dwattr $C$DW$2, DW_AT_declaration + 29 .dwattr $C$DW$2, DW_AT_external + 30 .dwattr $C$DW$2, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 31 .dwattr $C$DW$2, DW_AT_decl_line(0x33f) + 32 .dwattr $C$DW$2, DW_AT_decl_column(0x01) + 33 + 34 $C$DW$3 .dwtag DW_TAG_variable + 35 .dwattr $C$DW$3, DW_AT_name("FLL_CTL0") + 36 .dwattr $C$DW$3, DW_AT_TI_symbol_name("FLL_CTL0") + 37 .dwattr $C$DW$3, DW_AT_type(*$C$DW$T$23) + 38 .dwattr $C$DW$3, DW_AT_declaration + 39 .dwattr $C$DW$3, DW_AT_external + 40 .dwattr $C$DW$3, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 41 .dwattr $C$DW$3, DW_AT_decl_line(0x34b) + 42 .dwattr $C$DW$3, DW_AT_decl_column(0x01) + 43 + 44 $C$DW$4 .dwtag DW_TAG_variable + 45 .dwattr $C$DW$4, DW_AT_name("P1IFG") + 46 .dwattr $C$DW$4, DW_AT_TI_symbol_name("P1IFG") + 47 .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$23) + 48 .dwattr $C$DW$4, DW_AT_declaration + 49 .dwattr $C$DW$4, DW_AT_external + 50 .dwattr $C$DW$4, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 51 .dwattr $C$DW$4, DW_AT_decl_line(0x450) + 52 .dwattr $C$DW$4, DW_AT_decl_column(0x01) + 53 + 54 $C$DW$5 .dwtag DW_TAG_variable + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 2 + + 55 .dwattr $C$DW$5, DW_AT_name("P1IES") + 56 .dwattr $C$DW$5, DW_AT_TI_symbol_name("P1IES") + 57 .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$23) + 58 .dwattr $C$DW$5, DW_AT_declaration + 59 .dwattr $C$DW$5, DW_AT_external + 60 .dwattr $C$DW$5, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 61 .dwattr $C$DW$5, DW_AT_decl_line(0x451) + 62 .dwattr $C$DW$5, DW_AT_decl_column(0x01) + 63 + 64 $C$DW$6 .dwtag DW_TAG_variable + 65 .dwattr $C$DW$6, DW_AT_name("P1IE") + 66 .dwattr $C$DW$6, DW_AT_TI_symbol_name("P1IE") + 67 .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$23) + 68 .dwattr $C$DW$6, DW_AT_declaration + 69 .dwattr $C$DW$6, DW_AT_external + 70 .dwattr $C$DW$6, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 71 .dwattr $C$DW$6, DW_AT_decl_line(0x452) + 72 .dwattr $C$DW$6, DW_AT_decl_column(0x01) + 73 + 74 $C$DW$7 .dwtag DW_TAG_variable + 75 .dwattr $C$DW$7, DW_AT_name("P2OUT") + 76 .dwattr $C$DW$7, DW_AT_TI_symbol_name("P2OUT") + 77 .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$23) + 78 .dwattr $C$DW$7, DW_AT_declaration + 79 .dwattr $C$DW$7, DW_AT_external + 80 .dwattr $C$DW$7, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 81 .dwattr $C$DW$7, DW_AT_decl_line(0x456) + 82 .dwattr $C$DW$7, DW_AT_decl_column(0x01) + 83 + 84 $C$DW$8 .dwtag DW_TAG_variable + 85 .dwattr $C$DW$8, DW_AT_name("P2DIR") + 86 .dwattr $C$DW$8, DW_AT_TI_symbol_name("P2DIR") + 87 .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$23) + 88 .dwattr $C$DW$8, DW_AT_declaration + 89 .dwattr $C$DW$8, DW_AT_external + 90 .dwattr $C$DW$8, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 91 .dwattr $C$DW$8, DW_AT_decl_line(0x457) + 92 .dwattr $C$DW$8, DW_AT_decl_column(0x01) + 93 + 94 $C$DW$9 .dwtag DW_TAG_variable + 95 .dwattr $C$DW$9, DW_AT_name("WDTCTL") + 96 .dwattr $C$DW$9, DW_AT_TI_symbol_name("WDTCTL") + 97 .dwattr $C$DW$9, DW_AT_type(*$C$DW$T$25) + 98 .dwattr $C$DW$9, DW_AT_declaration + 99 .dwattr $C$DW$9, DW_AT_external + 100 .dwattr $C$DW$9, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h") + 101 .dwattr $C$DW$9, DW_AT_decl_line(0x6df) + 102 .dwattr $C$DW$9, DW_AT_decl_column(0x01) + 103 + 104 ; C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\bin\acpia430.exe -@C:\\Users\\LIBRAR + 105 000000 .sect ".text:main" + 106 .clink + 107 .global main + 108 + 109 $C$DW$10 .dwtag DW_TAG_subprogram + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 3 + + 110 .dwattr $C$DW$10, DW_AT_name("main") + 111 .dwattr $C$DW$10, DW_AT_low_pc(main) + 112 .dwattr $C$DW$10, DW_AT_high_pc(0x00) + 113 .dwattr $C$DW$10, DW_AT_TI_symbol_name("main") + 114 .dwattr $C$DW$10, DW_AT_external + 115 .dwattr $C$DW$10, DW_AT_type(*$C$DW$T$10) + 116 .dwattr $C$DW$10, DW_AT_TI_begin_file("../main.c") + 117 .dwattr $C$DW$10, DW_AT_TI_begin_line(0x0b) + 118 .dwattr $C$DW$10, DW_AT_TI_begin_column(0x05) + 119 .dwattr $C$DW$10, DW_AT_decl_file("../main.c") + 120 .dwattr $C$DW$10, DW_AT_decl_line(0x0b) + 121 .dwattr $C$DW$10, DW_AT_decl_column(0x05) + 122 .dwattr $C$DW$10, DW_AT_TI_max_frame_size(0x02) + 123 .dwpsn file "../main.c",line 12,column 1,is_stmt,address main,isa 0 + 124 + 125 .dwfde $C$DW$CIE, main + 126 + 127 ;***************************************************************************** + 128 ;* FUNCTION NAME: main * + 129 ;* * + 130 ;* Regs Modified : SP,SR * + 131 ;* Regs Used : SP,SR * + 132 ;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte * + 133 ;***************************************************************************** + 134 000000 main: + 135 ;* --------------------------------------------------------------------------* + 136 .dwcfi cfa_offset, 2 + 137 .dwcfi save_reg_to_mem, 16, -2 + 138 .dwpsn file "../main.c",line 13,column 2,is_stmt,isa 0 + 139 000000 40B2 MOV.W #23168,&WDTCTL+0 ; [] |13| + 000002 5A80 + 000004 0000! + 140 .dwpsn file "../main.c",line 14,column 2,is_stmt,isa 0 + 141 000006 D2E2 OR.B #4,&P2DIR+0 ; [] |14| + 000008 0000! + 142 .dwpsn file "../main.c",line 15,column 2,is_stmt,isa 0 + 143 00000a 43C2 MOV.B #0,&P2OUT+0 ; [] |15| + 00000c 0000! + 144 .dwpsn file "../main.c",line 16,column 2,is_stmt,isa 0 + 145 00000e D232 EINT ; [] |16| + 146 .dwpsn file "../main.c",line 17,column 2,is_stmt,isa 0 + 147 000010 D3D2 OR.B #1,&P1IE+0 ; [] |17| + 000012 0000! + 148 .dwpsn file "../main.c",line 18,column 2,is_stmt,isa 0 + 149 000014 D3E2 OR.B #2,&P1IE+0 ; [] |18| + 000016 0000! + 150 .dwpsn file "../main.c",line 19,column 2,is_stmt,isa 0 + 151 000018 D3D2 OR.B #1,&P1IES+0 ; [] |19| + 00001a 0000! + 152 .dwpsn file "../main.c",line 20,column 2,is_stmt,isa 0 + 153 00001c C3D2 BIC.B #1,&P1IFG+0 ; [] |20| + 00001e 0000! + 154 .dwpsn file "../main.c",line 21,column 2,is_stmt,isa 0 + 155 000020 D3E2 OR.B #2,&P1IES+0 ; [] |21| + 000022 0000! + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 4 + + 156 .dwpsn file "../main.c",line 22,column 2,is_stmt,isa 0 + 157 000024 C3E2 BIC.B #2,&P1IFG+0 ; [] |22| + 000026 0000! + 158 .dwpsn file "../main.c",line 23,column 2,is_stmt,isa 0 + 159 000028 D0F2 OR.B #176,&FLL_CTL0+0 ; [] |23| + 00002a 00B0 + 00002c 0000! + 160 .dwpsn file "../main.c",line 24,column 5,is_stmt,isa 0 + 161 00002e D0F2 OR.B #80,&SCFI0+0 ; [] |24| + 000030 0050 + 000032 0000! + 162 .dwpsn file "../main.c",line 25,column 5,is_stmt,isa 0 + 163 000034 40F2 MOV.B #63,&SCFQCTL+0 ; [] |25| + 000036 003F + 000038 0000! + 164 .dwpsn file "../main.c",line 26,column 8,is_stmt,isa 0 + 165 ;* --------------------------------------------------------------------------* + 166 ;* BEGIN LOOP $C$L1 + 167 ;* + 168 ;* Loop source line : 26 + 169 ;* Loop closing brace source line : 29 + 170 ;* Known Minimum Trip Count : 1 + 171 ;* Known Maximum Trip Count : 4294967295 + 172 ;* Known Max Trip Count Factor : 1 + 173 ;* --------------------------------------------------------------------------* + 174 00003a $C$L1: + 175 .dwpsn file "../main.c",line 27,column 6,is_stmt,isa 0 + 176 ; Begin 1048576 cycle delay + 177 .newblock + 178 00003a 120D PUSH r13 + 179 00003c 120E PUSH r14 + 180 00003e 403D MOV.W #16380, r13 + 000040 3FFC + 181 000042 403E MOV.W #3, r14 + 000044 0003 + 182 000046 831D $1: SUB.W #1, r13 + 183 000048 730E SUBC.W #0, r14 + 184 00004a 23FD JNE $1 + 185 00004c 930D TST.W r13 + 186 00004e 23FB JNE $1 + 187 000050 413E POP r14 + 188 000052 413D POP r13 + 189 000054 3C00 JMP ($ + 2) + 190 ; End 1048576 cycle delay ; [] |27| + 191 .dwpsn file "../main.c",line 28,column 6,is_stmt,isa 0 + 192 000056 E2E2 XOR.B #4,&P2OUT+0 ; [] |28| + 000058 0000! + 193 .dwpsn file "../main.c",line 26,column 8,is_stmt,isa 0 + 194 00005a 3FEF JMP $C$L1 ; [] |26| + 195 ; [] |26| + 196 ;* --------------------------------------------------------------------------* + 197 .dwattr $C$DW$10, DW_AT_TI_end_file("../main.c") + 198 .dwattr $C$DW$10, DW_AT_TI_end_line(0x1e) + 199 .dwattr $C$DW$10, DW_AT_TI_end_column(0x01) + 200 .dwendentry + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 5 + + 201 .dwendtag $C$DW$10 + 202 + 203 000000 .sect ".text:Port1_ISR" + 204 .clink + 205 .global Port1_ISR + 206 + 207 $C$DW$11 .dwtag DW_TAG_subprogram + 208 .dwattr $C$DW$11, DW_AT_name("Port1_ISR") + 209 .dwattr $C$DW$11, DW_AT_low_pc(Port1_ISR) + 210 .dwattr $C$DW$11, DW_AT_high_pc(0x00) + 211 .dwattr $C$DW$11, DW_AT_TI_symbol_name("Port1_ISR") + 212 .dwattr $C$DW$11, DW_AT_external + 213 .dwattr $C$DW$11, DW_AT_TI_begin_file("../main.c") + 214 .dwattr $C$DW$11, DW_AT_TI_begin_line(0x21) + 215 .dwattr $C$DW$11, DW_AT_TI_begin_column(0x12) + 216 .dwattr $C$DW$11, DW_AT_decl_file("../main.c") + 217 .dwattr $C$DW$11, DW_AT_decl_line(0x21) + 218 .dwattr $C$DW$11, DW_AT_decl_column(0x12) + 219 .dwattr $C$DW$11, DW_AT_TI_interrupt + 220 .dwattr $C$DW$11, DW_AT_TI_max_frame_size(0x02) + 221 .dwpsn file "../main.c",line 33,column 35,is_stmt,address Port1_ISR,isa 0 + 222 + 223 .dwfde $C$DW$CIE, Port1_ISR + 224 + 225 ;***************************************************************************** + 226 ;* FUNCTION NAME: Port1_ISR * + 227 ;* * + 228 ;* Regs Modified : SP,SR * + 229 ;* Regs Used : SP,SR * + 230 ;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte * + 231 ;***************************************************************************** + 232 000000 Port1_ISR: + 233 ;* --------------------------------------------------------------------------* + 234 .dwcfi cfa_offset, 2 + 235 .dwcfi save_reg_to_mem, 16, -2 + 236 .dwpsn file "../main.c",line 34,column 5,is_stmt,isa 0 + 237 000000 B3D2 BIT.B #1,&P1IFG+0 ; [] |34| + 000002 0000! + 238 000004 2412 JEQ $C$L2 ; [] |34| + 239 ; [] |34| + 240 ;* --------------------------------------------------------------------------* + 241 .dwpsn file "../main.c",line 36,column 11,is_stmt,isa 0 + 242 000006 D0F2 OR.B #176,&FLL_CTL0+0 ; [] |36| + 000008 00B0 + 00000a 0000! + 243 .dwpsn file "../main.c",line 37,column 11,is_stmt,isa 0 + 244 00000c D0F2 OR.B #80,&SCFI0+0 ; [] |37| + 00000e 0050 + 000010 0000! + 245 .dwpsn file "../main.c",line 38,column 11,is_stmt,isa 0 + 246 000012 40F2 MOV.B #127,&SCFQCTL+0 ; [] |38| + 000014 007F + 000016 0000! + 247 .dwpsn file "../main.c",line 39,column 11,is_stmt,isa 0 + 248 000018 D3D2 OR.B #1,&P1IES+0 ; [] |39| + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 6 + + 00001a 0000! + 249 .dwpsn file "../main.c",line 40,column 11,is_stmt,isa 0 + 250 00001c C3D2 BIC.B #1,&P1IFG+0 ; [] |40| + 00001e 0000! + 251 .dwpsn file "../main.c",line 41,column 11,is_stmt,isa 0 + 252 000020 D3E2 OR.B #2,&P1IES+0 ; [] |41| + 000022 0000! + 253 .dwpsn file "../main.c",line 42,column 11,is_stmt,isa 0 + 254 000024 C3E2 BIC.B #2,&P1IFG+0 ; [] |42| + 000026 0000! + 255 000028 3C14 JMP $C$L3 ; [] + 256 ; [] + 257 ;* --------------------------------------------------------------------------* + 258 00002a $C$L2: + 259 .dwpsn file "../main.c",line 44,column 10,is_stmt,isa 0 + 260 00002a B3E2 BIT.B #2,&P1IFG+0 ; [] |44| + 00002c 0000! + 261 00002e 2411 JEQ $C$L3 ; [] |44| + 262 ; [] |44| + 263 ;* --------------------------------------------------------------------------* + 264 .dwpsn file "../main.c",line 46,column 11,is_stmt,isa 0 + 265 000030 D0F2 OR.B #176,&FLL_CTL0+0 ; [] |46| + 000032 00B0 + 000034 0000! + 266 .dwpsn file "../main.c",line 47,column 11,is_stmt,isa 0 + 267 000036 D0F2 OR.B #80,&SCFI0+0 ; [] |47| + 000038 0050 + 00003a 0000! + 268 .dwpsn file "../main.c",line 48,column 11,is_stmt,isa 0 + 269 00003c 40F2 MOV.B #31,&SCFQCTL+0 ; [] |48| + 00003e 001F + 000040 0000! + 270 .dwpsn file "../main.c",line 49,column 11,is_stmt,isa 0 + 271 000042 D3D2 OR.B #1,&P1IES+0 ; [] |49| + 000044 0000! + 272 .dwpsn file "../main.c",line 50,column 11,is_stmt,isa 0 + 273 000046 C3D2 BIC.B #1,&P1IFG+0 ; [] |50| + 000048 0000! + 274 .dwpsn file "../main.c",line 51,column 11,is_stmt,isa 0 + 275 00004a D3E2 OR.B #2,&P1IES+0 ; [] |51| + 00004c 0000! + 276 .dwpsn file "../main.c",line 52,column 11,is_stmt,isa 0 + 277 00004e C3E2 BIC.B #2,&P1IFG+0 ; [] |52| + 000050 0000! + 278 .dwpsn file "../main.c",line 54,column 1,is_stmt,isa 0 + 279 ;* --------------------------------------------------------------------------* + 280 $C$L3: + 281 $C$DW$12 .dwtag DW_TAG_TI_branch + 282 .dwattr $C$DW$12, DW_AT_low_pc(0x00) + 283 .dwattr $C$DW$12, DW_AT_TI_return + 284 + 285 000052 1300 RETI ; [] + 286 ; [] + 287 .dwattr $C$DW$11, DW_AT_TI_end_file("../main.c") + 288 .dwattr $C$DW$11, DW_AT_TI_end_line(0x36) + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 7 + + 289 .dwattr $C$DW$11, DW_AT_TI_end_column(0x01) + 290 .dwendentry + 291 .dwendtag $C$DW$11 + 292 + 293 ;***************************************************************************** + 294 ;* UNDEFINED EXTERNAL REFERENCES * + 295 ;***************************************************************************** + 296 .global SCFI0 + 297 .global SCFQCTL + 298 .global FLL_CTL0 + 299 .global P1IFG + 300 .global P1IES + 301 .global P1IE + 302 .global P2OUT + 303 .global P2DIR + 304 .global WDTCTL + 305 + 306 ;****************************************************************************** + 307 ;* BUILD ATTRIBUTES * + 308 ;****************************************************************************** + 309 .battr "TI", Tag_File, 1, Tag_LPM_INFO(1) + 310 .battr "TI", Tag_File, 1, Tag_PORTS_INIT_INFO("012345678901ABCDEFGHIJ0111111111101100000000001 + 311 .battr "TI", Tag_File, 1, Tag_LEA_INFO(1) + 312 .battr "TI", Tag_File, 1, Tag_HW_MPY32_INFO(1) + 313 .battr "TI", Tag_File, 1, Tag_HW_MPY_ISR_INFO(1) + 314 .battr "TI", Tag_File, 1, Tag_HW_MPY_INLINE_INFO(1) + 315 .battr "mspabi", Tag_File, 1, Tag_enum_size(3) + 316 + 317 ;****************************************************************************** + 318 ;* TYPE INFORMATION * + 319 ;****************************************************************************** + 320 $C$DW$T$2 .dwtag DW_TAG_unspecified_type + 321 .dwattr $C$DW$T$2, DW_AT_name("void") + 322 + 323 + 324 $C$DW$T$20 .dwtag DW_TAG_subroutine_type + 325 .dwattr $C$DW$T$20, DW_AT_language(DW_LANG_C) + 326 .dwendtag $C$DW$T$20 + 327 + 328 $C$DW$T$21 .dwtag DW_TAG_pointer_type + 329 .dwattr $C$DW$T$21, DW_AT_type(*$C$DW$T$20) + 330 .dwattr $C$DW$T$21, DW_AT_address_class(0x10) + 331 + 332 $C$DW$T$22 .dwtag DW_TAG_typedef + 333 .dwattr $C$DW$T$22, DW_AT_name("__SFR_FARPTR") + 334 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$21) + 335 .dwattr $C$DW$T$22, DW_AT_language(DW_LANG_C) + 336 .dwattr $C$DW$T$22, DW_AT_decl_file("C:\ti\ccs1040\ccs\ccs_base\msp430\include\msp430fg4618.h" + 337 .dwattr $C$DW$T$22, DW_AT_decl_line(0x4d) + 338 .dwattr $C$DW$T$22, DW_AT_decl_column(0x11) + 339 + 340 $C$DW$T$4 .dwtag DW_TAG_base_type + 341 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + 342 .dwattr $C$DW$T$4, DW_AT_name("bool") + 343 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01) + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 8 + + 344 + 345 $C$DW$T$5 .dwtag DW_TAG_base_type + 346 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char) + 347 .dwattr $C$DW$T$5, DW_AT_name("signed char") + 348 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01) + 349 + 350 $C$DW$T$6 .dwtag DW_TAG_base_type + 351 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char) + 352 .dwattr $C$DW$T$6, DW_AT_name("unsigned char") + 353 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01) + 354 + 355 $C$DW$T$23 .dwtag DW_TAG_volatile_type + 356 .dwattr $C$DW$T$23, DW_AT_type(*$C$DW$T$6) + 357 + 358 $C$DW$T$7 .dwtag DW_TAG_base_type + 359 .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char) + 360 .dwattr $C$DW$T$7, DW_AT_name("wchar_t") + 361 .dwattr $C$DW$T$7, DW_AT_byte_size(0x02) + 362 + 363 $C$DW$T$8 .dwtag DW_TAG_base_type + 364 .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed) + 365 .dwattr $C$DW$T$8, DW_AT_name("short") + 366 .dwattr $C$DW$T$8, DW_AT_byte_size(0x02) + 367 + 368 $C$DW$T$9 .dwtag DW_TAG_base_type + 369 .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned) + 370 .dwattr $C$DW$T$9, DW_AT_name("unsigned short") + 371 .dwattr $C$DW$T$9, DW_AT_byte_size(0x02) + 372 + 373 $C$DW$T$10 .dwtag DW_TAG_base_type + 374 .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed) + 375 .dwattr $C$DW$T$10, DW_AT_name("int") + 376 .dwattr $C$DW$T$10, DW_AT_byte_size(0x02) + 377 + 378 $C$DW$T$11 .dwtag DW_TAG_base_type + 379 .dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned) + 380 .dwattr $C$DW$T$11, DW_AT_name("unsigned int") + 381 .dwattr $C$DW$T$11, DW_AT_byte_size(0x02) + 382 + 383 $C$DW$T$25 .dwtag DW_TAG_volatile_type + 384 .dwattr $C$DW$T$25, DW_AT_type(*$C$DW$T$11) + 385 + 386 $C$DW$T$12 .dwtag DW_TAG_base_type + 387 .dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed) + 388 .dwattr $C$DW$T$12, DW_AT_name("long") + 389 .dwattr $C$DW$T$12, DW_AT_byte_size(0x04) + 390 + 391 $C$DW$T$13 .dwtag DW_TAG_base_type + 392 .dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned) + 393 .dwattr $C$DW$T$13, DW_AT_name("unsigned long") + 394 .dwattr $C$DW$T$13, DW_AT_byte_size(0x04) + 395 + 396 $C$DW$T$14 .dwtag DW_TAG_base_type + 397 .dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed) + 398 .dwattr $C$DW$T$14, DW_AT_name("long long") + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 9 + + 399 .dwattr $C$DW$T$14, DW_AT_byte_size(0x08) + 400 + 401 $C$DW$T$15 .dwtag DW_TAG_base_type + 402 .dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned) + 403 .dwattr $C$DW$T$15, DW_AT_name("unsigned long long") + 404 .dwattr $C$DW$T$15, DW_AT_byte_size(0x08) + 405 + 406 $C$DW$T$16 .dwtag DW_TAG_base_type + 407 .dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float) + 408 .dwattr $C$DW$T$16, DW_AT_name("float") + 409 .dwattr $C$DW$T$16, DW_AT_byte_size(0x04) + 410 + 411 $C$DW$T$17 .dwtag DW_TAG_base_type + 412 .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float) + 413 .dwattr $C$DW$T$17, DW_AT_name("double") + 414 .dwattr $C$DW$T$17, DW_AT_byte_size(0x08) + 415 + 416 $C$DW$T$18 .dwtag DW_TAG_base_type + 417 .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float) + 418 .dwattr $C$DW$T$18, DW_AT_name("long double") + 419 .dwattr $C$DW$T$18, DW_AT_byte_size(0x08) + 420 + 421 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C) + 422 + 423 ;*************************************************************** + 424 ;* DWARF CIE ENTRIES * + 425 ;*************************************************************** + 426 + 427 $C$DW$CIE .dwcie 16 + 428 .dwcfi cfa_register, 1 + 429 .dwcfi cfa_offset, 0 + 430 .dwcfi same_value, 0 + 431 .dwcfi same_value, 1 + 432 .dwcfi same_value, 3 + 433 .dwcfi same_value, 4 + 434 .dwcfi same_value, 5 + 435 .dwcfi same_value, 6 + 436 .dwcfi same_value, 7 + 437 .dwcfi same_value, 8 + 438 .dwcfi same_value, 9 + 439 .dwcfi same_value, 10 + 440 .dwendentry + 441 + 442 ;*************************************************************** + 443 ;* DWARF REGISTER MAP * + 444 ;*************************************************************** + 445 + 446 $C$DW$13 .dwtag DW_TAG_TI_assign_register + 447 .dwattr $C$DW$13, DW_AT_name("PC") + 448 .dwattr $C$DW$13, DW_AT_location[DW_OP_reg0] + 449 + 450 $C$DW$14 .dwtag DW_TAG_TI_assign_register + 451 .dwattr $C$DW$14, DW_AT_name("SP") + 452 .dwattr $C$DW$14, DW_AT_location[DW_OP_reg1] + 453 + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 10 + + 454 $C$DW$15 .dwtag DW_TAG_TI_assign_register + 455 .dwattr $C$DW$15, DW_AT_name("SR") + 456 .dwattr $C$DW$15, DW_AT_location[DW_OP_reg2] + 457 + 458 $C$DW$16 .dwtag DW_TAG_TI_assign_register + 459 .dwattr $C$DW$16, DW_AT_name("CG") + 460 .dwattr $C$DW$16, DW_AT_location[DW_OP_reg3] + 461 + 462 $C$DW$17 .dwtag DW_TAG_TI_assign_register + 463 .dwattr $C$DW$17, DW_AT_name("r4") + 464 .dwattr $C$DW$17, DW_AT_location[DW_OP_reg4] + 465 + 466 $C$DW$18 .dwtag DW_TAG_TI_assign_register + 467 .dwattr $C$DW$18, DW_AT_name("r5") + 468 .dwattr $C$DW$18, DW_AT_location[DW_OP_reg5] + 469 + 470 $C$DW$19 .dwtag DW_TAG_TI_assign_register + 471 .dwattr $C$DW$19, DW_AT_name("r6") + 472 .dwattr $C$DW$19, DW_AT_location[DW_OP_reg6] + 473 + 474 $C$DW$20 .dwtag DW_TAG_TI_assign_register + 475 .dwattr $C$DW$20, DW_AT_name("r7") + 476 .dwattr $C$DW$20, DW_AT_location[DW_OP_reg7] + 477 + 478 $C$DW$21 .dwtag DW_TAG_TI_assign_register + 479 .dwattr $C$DW$21, DW_AT_name("r8") + 480 .dwattr $C$DW$21, DW_AT_location[DW_OP_reg8] + 481 + 482 $C$DW$22 .dwtag DW_TAG_TI_assign_register + 483 .dwattr $C$DW$22, DW_AT_name("r9") + 484 .dwattr $C$DW$22, DW_AT_location[DW_OP_reg9] + 485 + 486 $C$DW$23 .dwtag DW_TAG_TI_assign_register + 487 .dwattr $C$DW$23, DW_AT_name("r10") + 488 .dwattr $C$DW$23, DW_AT_location[DW_OP_reg10] + 489 + 490 $C$DW$24 .dwtag DW_TAG_TI_assign_register + 491 .dwattr $C$DW$24, DW_AT_name("r11") + 492 .dwattr $C$DW$24, DW_AT_location[DW_OP_reg11] + 493 + 494 $C$DW$25 .dwtag DW_TAG_TI_assign_register + 495 .dwattr $C$DW$25, DW_AT_name("r12") + 496 .dwattr $C$DW$25, DW_AT_location[DW_OP_reg12] + 497 + 498 $C$DW$26 .dwtag DW_TAG_TI_assign_register + 499 .dwattr $C$DW$26, DW_AT_name("r13") + 500 .dwattr $C$DW$26, DW_AT_location[DW_OP_reg13] + 501 + 502 $C$DW$27 .dwtag DW_TAG_TI_assign_register + 503 .dwattr $C$DW$27, DW_AT_name("r14") + 504 .dwattr $C$DW$27, DW_AT_location[DW_OP_reg14] + 505 + 506 $C$DW$28 .dwtag DW_TAG_TI_assign_register + 507 .dwattr $C$DW$28, DW_AT_name("r15") + 508 .dwattr $C$DW$28, DW_AT_location[DW_OP_reg15] + MSP430 Assembler PC v20.2.5 Thu Dec 2 20:38:06 2021 + +Copyright (c) 2003-2018 Texas Instruments Incorporated +C:\Users\LIBRAR~1\AppData\Local\Temp\{B3212681-677C-4407-B7A6-59626703CBB1} PAGE 11 + + 509 + 510 $C$DW$29 .dwtag DW_TAG_TI_assign_register + 511 .dwattr $C$DW$29, DW_AT_name("CIE_RETA") + 512 .dwattr $C$DW$29, DW_AT_location[DW_OP_reg16] + 513 + 514 .dwendtag $C$DW$CU + 515 + +No Assembly Errors, No Assembly Warnings diff --git a/CPE325/Lab6_Problem2/Debug/main.obj b/CPE325/Lab6_Problem2/Debug/main.obj new file mode 100644 index 0000000..cd5eb64 Binary files /dev/null and b/CPE325/Lab6_Problem2/Debug/main.obj differ diff --git a/CPE325/Lab6_Problem2/Debug/makefile b/CPE325/Lab6_Problem2/Debug/makefile new file mode 100644 index 0000000..f7021c4 --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/makefile @@ -0,0 +1,167 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab6_Problem2.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab6_Problem2.out" \ + +BIN_OUTPUTS += \ +Lab6_Problem2.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab6_Problem2.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab6_Problem2.out" + +# Tool invocations +Lab6_Problem2.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --asm_listing -z -m"Lab6_Problem2.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab6_Problem2_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "Lab6_Problem2.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab6_Problem2.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab6_Problem2.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "main.lst" + -$(RM) "main.obj" + -$(RM) "main.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab6_Problem2/Debug/objects.mk b/CPE325/Lab6_Problem2/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/Lab6_Problem2/Debug/sources.mk b/CPE325/Lab6_Problem2/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab6_Problem2/Debug/subdir_rules.mk b/CPE325/Lab6_Problem2/Debug/subdir_rules.mk new file mode 100644 index 0000000..746d0fb --- /dev/null +++ b/CPE325/Lab6_Problem2/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small -Ooff --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab6_Problem2" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=full --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --asm_listing --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/Lab6_Problem2/main.c b/CPE325/Lab6_Problem2/main.c new file mode 100644 index 0000000..706eedf --- /dev/null +++ b/CPE325/Lab6_Problem2/main.c @@ -0,0 +1,54 @@ +/* --------------------------------------------------------------------------------------- + * + * + * + * + */ + +#include +#define SW1_PRESSED ((BIT0&P1IFG)==0) // SW1 Status +#define SW2_PRESSED ((BIT1&P1IFG)==0) // SW2 Status +int main(void) +{ + WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer + P2DIR |= BIT2; // Set LED1 as output + P2OUT = 0x00; // clear LED1 status + _EINT(); // enable interrupts + P1IE |= BIT0; // P1.0 interrupt enabled + P1IE |= BIT1; // P1.1 interrupt enabled + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared + FLL_CTL0 |= DCOPLUS + XCAP18PF; // DCO+ set, freq = xtal x D x N+1 + SCFI0 |= FN_4 + FLLD_2; // DCO range control, multiplier D + SCFQCTL = 63; // (61+1) x 32768 x 2 = 4.19 MHz + while(1){ + _delay_cycles(1048576); // Delay + P2OUT ^= BIT2; // LED1 is turned ON + } +} +// Port 1 interrupt service routine +#pragma vector = PORT1_VECTOR +__interrupt void Port1_ISR (void) { + if(!SW1_PRESSED) { + //SW1pressed = 1; + FLL_CTL0 |= DCOPLUS + XCAP18PF; // DCO+ set, freq = xtal x D x N+1 + SCFI0 |= FN_4 + FLLD_2; // DCO range control, multiplier D + SCFQCTL = 127; // (127+1) x 32768 x 2 = 8.39 MHz + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared + } + else if(!SW2_PRESSED) { + //SW1pressed = 0; + FLL_CTL0 |= DCOPLUS + XCAP18PF; // DCO+ set, freq = xtal x D x N+1 + SCFI0 |= FN_4 + FLLD_2; // DCO range control, multiplier D + SCFQCTL = 31; // (31+1) x 32768 x 2 = 2.10 MHz + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared + } +} diff --git a/CPE325/Lab6_Problem2/targetConfigs/MSP430FG4618.ccxml b/CPE325/Lab6_Problem2/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/Lab6_Problem2/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab6_Problem2/targetConfigs/readme.txt b/CPE325/Lab6_Problem2/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab6_Problem2/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab7_P1/Debug/Lab7_P1.map b/CPE325/Lab7_P1/Debug/Lab7_P1.map new file mode 100644 index 0000000..5b64db8 --- /dev/null +++ b/CPE325/Lab7_P1/Debug/Lab7_P1.map @@ -0,0 +1,890 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Thu Dec 2 20:38:08 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 000032f8 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOB 00001000 00000080 00000000 00000080 RWIX + INFOA 00001080 00000080 00000000 00000080 RWIX + RAM 00001100 00002000 00000052 00001fae RWIX + FLASH 00003100 0000cebe 0000027e 0000cc40 RWIX + BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff + INT00 0000ffc0 00000002 00000000 00000002 RWIX + INT01 0000ffc2 00000002 00000000 00000002 RWIX + INT02 0000ffc4 00000002 00000000 00000002 RWIX + INT03 0000ffc6 00000002 00000000 00000002 RWIX + INT04 0000ffc8 00000002 00000000 00000002 RWIX + INT05 0000ffca 00000002 00000000 00000002 RWIX + INT06 0000ffcc 00000002 00000000 00000002 RWIX + INT07 0000ffce 00000002 00000000 00000002 RWIX + INT08 0000ffd0 00000002 00000000 00000002 RWIX + INT09 0000ffd2 00000002 00000000 00000002 RWIX + INT10 0000ffd4 00000002 00000000 00000002 RWIX + INT11 0000ffd6 00000002 00000000 00000002 RWIX + INT12 0000ffd8 00000002 00000000 00000002 RWIX + INT13 0000ffda 00000002 00000000 00000002 RWIX + INT14 0000ffdc 00000002 00000002 00000000 RWIX + INT15 0000ffde 00000002 00000002 00000000 RWIX + INT16 0000ffe0 00000002 00000002 00000000 RWIX + INT17 0000ffe2 00000002 00000002 00000000 RWIX + INT18 0000ffe4 00000002 00000002 00000000 RWIX + INT19 0000ffe6 00000002 00000002 00000000 RWIX + INT20 0000ffe8 00000002 00000002 00000000 RWIX + INT21 0000ffea 00000002 00000002 00000000 RWIX + INT22 0000ffec 00000002 00000002 00000000 RWIX + INT23 0000ffee 00000002 00000002 00000000 RWIX + INT24 0000fff0 00000002 00000002 00000000 RWIX + INT25 0000fff2 00000002 00000002 00000000 RWIX + INT26 0000fff4 00000002 00000002 00000000 RWIX + INT27 0000fff6 00000002 00000002 00000000 RWIX + INT28 0000fff8 00000002 00000002 00000000 RWIX + INT29 0000fffa 00000002 00000002 00000000 RWIX + INT30 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 00010000 00000000 00010000 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00001100 00000002 UNINITIALIZED + 00001100 00000002 Lab7_Part1.obj (.data) + +.stack 0 000030b0 00000050 UNINITIALIZED + 000030b0 00000002 rts430_eabi.lib : boot.c.obj (.stack) + 000030b2 0000004e --HOLE-- + +.text 0 00003100 00000268 + 00003100 0000007c rts430_eabi.lib : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 0000317c 00000062 Lab7_Part1.obj (.text:main) + 000031de 00000058 rts430_eabi.lib : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 00003236 0000004c : lsr16.asm.obj (.text) + 00003282 0000002c Lab7_Part1.obj (.text:Port1_ISR) + 000032ae 0000002c rts430_eabi.lib : lsl16.asm.obj (.text) + 000032da 0000001e Lab7_Part1.obj (.text:watchdog_timer) + 000032f8 0000001c rts430_eabi.lib : boot.c.obj (.text:_c_int00_noargs) + 00003314 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00003326 00000012 : memcpy.c.obj (.text:memcpy) + 00003338 00000010 : epilog.asm.obj (.text) + 00003348 0000000a Lab7_Part1.obj (.text:timerISR2) + 00003352 0000000a Lab7_Part1.obj (.text:timerISR) + 0000335c 00000006 rts430_eabi.lib : exit.c.obj (.text:abort) + 00003362 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00003366 00000002 : startup.c.obj (.text:_system_post_cinit) + +.text:_isr +* 0 00003368 00000008 + 00003368 00000008 rts430_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 00003370 0000000e + 00003370 00000006 (.cinit..data.load) [load image] + 00003376 00000004 (__TI_handler_table) + 0000337a 00000004 (__TI_cinit_table) + +.binit 0 00003100 00000000 + +.init_array +* 0 00003100 00000000 UNINITIALIZED + +DAC12 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430_eabi.lib : int14.asm.obj (.int14) + +DMA 0 0000ffde 00000002 + 0000ffde 00000002 rts430_eabi.lib : int15.asm.obj (.int15) + +BASICTIMER +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430_eabi.lib : int16.asm.obj (.int16) + +PORT2 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430_eabi.lib : int17.asm.obj (.int17) + +USART1TX 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430_eabi.lib : int18.asm.obj (.int18) + +USART1RX 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430_eabi.lib : int19.asm.obj (.int19) + +PORT1 0 0000ffe8 00000002 + 0000ffe8 00000002 Lab7_Part1.obj (.int20) + +TIMERA1 0 0000ffea 00000002 + 0000ffea 00000002 rts430_eabi.lib : int21.asm.obj (.int21) + +TIMERA0 0 0000ffec 00000002 + 0000ffec 00000002 rts430_eabi.lib : int22.asm.obj (.int22) + +ADC12 0 0000ffee 00000002 + 0000ffee 00000002 rts430_eabi.lib : int23.asm.obj (.int23) + +USCIAB0TX +* 0 0000fff0 00000002 + 0000fff0 00000002 rts430_eabi.lib : int24.asm.obj (.int24) + +USCIAB0RX +* 0 0000fff2 00000002 + 0000fff2 00000002 rts430_eabi.lib : int25.asm.obj (.int25) + +WDT 0 0000fff4 00000002 + 0000fff4 00000002 Lab7_Part1.obj (.int26) + +COMPARATORA +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430_eabi.lib : int27.asm.obj (.int27) + +TIMERB1 0 0000fff8 00000002 + 0000fff8 00000002 Lab7_Part1.obj (.int28) + +TIMERB0 0 0000fffa 00000002 + 0000fffa 00000002 Lab7_Part1.obj (.int29) + +NMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430_eabi.lib : int30.asm.obj (.int30) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430_eabi.lib : boot.c.obj (.reset) + +$fill000 0 0000ffbe 00000002 + 0000ffbe 00000002 --HOLE-- [fill = ffff] + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + Lab7_Part1.obj 192 8 2 + +--+----------------------------+------+---------+---------+ + Total: 192 8 2 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430_eabi.lib + copy_decompress_lzss.c.obj 124 0 0 + autoinit.c.obj 88 0 0 + lsr16.asm.obj 76 0 0 + lsl16.asm.obj 44 0 0 + boot.c.obj 28 2 0 + copy_decompress_none.c.obj 18 0 0 + memcpy.c.obj 18 0 0 + epilog.asm.obj 16 0 0 + isr_trap.asm.obj 8 0 0 + exit.c.obj 6 0 0 + pre_init.c.obj 4 0 0 + int14.asm.obj 0 2 0 + int15.asm.obj 0 2 0 + int16.asm.obj 0 2 0 + int17.asm.obj 0 2 0 + int18.asm.obj 0 2 0 + int19.asm.obj 0 2 0 + int21.asm.obj 0 2 0 + int22.asm.obj 0 2 0 + int23.asm.obj 0 2 0 + int24.asm.obj 0 2 0 + int25.asm.obj 0 2 0 + int27.asm.obj 0 2 0 + int30.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+------+---------+---------+ + Total: 432 28 0 + + Stack: 0 0 80 + Linker Generated: 0 14 0 + +--+----------------------------+------+---------+---------+ + Grand Total: 624 50 82 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 0000337a records: 1, size/record: 4, table size: 4 + .data: load addr=00003370, load size=00000006 bytes, run addr=00001100, run size=00000002 bytes, compression=copy + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 00003376 records: 2, size/record: 2, table size: 4 + index: 0, handler: __TI_decompress_lzss + index: 1, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a6 ADC12IE +000001a4 ADC12IFG +000001a8 ADC12IV +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +00000040 BTCTL +0000335c C$$EXIT +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +000001c0 DAC12_0CTL +000001c8 DAC12_0DAT +000001c2 DAC12_1CTL +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d6 DMA0DA +000001d6 DMA0DAL +000001d2 DMA0SA +000001d2 DMA0SAL +000001da DMA0SZ +000001dc DMA1CTL +000001e2 DMA1DA +000001e2 DMA1DAL +000001de DMA1SA +000001de DMA1SAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ee DMA2DA +000001ee DMA2DAL +000001ea DMA2SA +000001ea DMA2SAL +000001f2 DMA2SZ +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000090 LCDACTL +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +00000091 LCDM1 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +00000092 LCDM2 +000000a4 LCDM20 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +00000134 MAC +00000136 MACS +00000005 ME2 +00000130 MPY +00000132 MPYS +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000138 OP2 +0000000d P10DIR +00000009 P10IN +0000000b P10OUT +0000000f P10SEL +00000022 P1DIR +00000025 P1IE +00000024 P1IES +00000023 P1IFG +00000020 P1IN +00000021 P1OUT +00000026 P1SEL +0000002a P2DIR +0000002d P2IE +0000002c P2IES +0000002b P2IFG +00000028 P2IN +00000029 P2OUT +0000002e P2SEL +0000001a P3DIR +00000018 P3IN +00000019 P3OUT +0000001b P3SEL +0000001e P4DIR +0000001c P4IN +0000001d P4OUT +0000001f P4SEL +00000032 P5DIR +00000030 P5IN +00000031 P5OUT +00000033 P5SEL +00000036 P6DIR +00000034 P6IN +00000035 P6OUT +00000037 P6SEL +0000003c P7DIR +00000038 P7IN +0000003a P7OUT +0000003e P7SEL +0000003d P8DIR +00000039 P8IN +0000003b P8OUT +0000003f P8SEL +0000000c P9DIR +00000008 P9IN +0000000a P9OUT +0000000e P9SEL +0000003c PADIR +00000038 PAIN +0000003a PAOUT +0000003e PASEL +0000000c PBDIR +00000008 PBIN +0000000a PBOUT +0000000e PBSEL +00003282 Port1_ISR +0000013c RESHI +0000013a RESLO +00000041 RTCCTL +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +00000042 RTCNT1 +00000043 RTCNT2 +00000044 RTCNT3 +00000045 RTCNT4 +00000042 RTCTIM0 +00000044 RTCTIM1 +00000040 RTCTL +0000004e RTCYEAR +0000004f RTCYEARH +0000004e RTCYEARL +00000050 SCFI0 +00000051 SCFI1 +00000052 SCFQCTL +0000013e SUMEXT +00000056 SVSCTL +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000160 TACTL +0000012e TAIV +00000170 TAR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000180 TBCTL +0000011e TBIV +00000190 TBR +0000007c U1BR0 +0000007d U1BR1 +00000078 U1CTL +0000007b U1MCTL +0000007a U1RCTL +0000007e U1RXBUF +00000079 U1TCTL +0000007f U1TXBUF +0000005d UCA0ABCTL +00000062 UCA0BR0 +00000063 UCA0BR1 +00000060 UCA0CTL0 +00000061 UCA0CTL1 +0000005f UCA0IRRCTL +0000005e UCA0IRTCTL +00000064 UCA0MCTL +00000066 UCA0RXBUF +00000065 UCA0STAT +00000067 UCA0TXBUF +0000006a UCB0BR0 +0000006b UCB0BR1 +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006c UCB0I2CIE +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000006e UCB0RXBUF +0000006d UCB0STAT +0000006f UCB0TXBUF +00001100 Up +00000120 WDTCTL +00003100 __STACK_END +00000050 __STACK_SIZE +0000337a __TI_CINIT_Base +0000337e __TI_CINIT_Limit +00003376 __TI_Handler_Table_Base +0000337a __TI_Handler_Table_Limit +00003368 __TI_ISR_TRAP +000031de __TI_auto_init_nobinit_nopinit_hold_wdt +00003100 __TI_decompress_lzss +00003314 __TI_decompress_none +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 __TI_int20 +0000ffea __TI_int21 +0000ffec __TI_int22 +0000ffee __TI_int23 +0000fff0 __TI_int24 +0000fff2 __TI_int25 +0000fff4 __TI_int26 +0000fff6 __TI_int27 +0000fff8 __TI_int28 +0000fffa __TI_int29 +0000fffc __TI_int30 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ +00003344 __mspabi_func_epilog_1 +00003342 __mspabi_func_epilog_2 +00003340 __mspabi_func_epilog_3 +0000333e __mspabi_func_epilog_4 +0000333c __mspabi_func_epilog_5 +0000333a __mspabi_func_epilog_6 +00003338 __mspabi_func_epilog_7 +000032ae __mspabi_slli +000032d6 __mspabi_slli_1 +000032c4 __mspabi_slli_10 +000032c2 __mspabi_slli_11 +000032c0 __mspabi_slli_12 +000032be __mspabi_slli_13 +000032bc __mspabi_slli_14 +000032ba __mspabi_slli_15 +000032d4 __mspabi_slli_2 +000032d2 __mspabi_slli_3 +000032d0 __mspabi_slli_4 +000032ce __mspabi_slli_5 +000032cc __mspabi_slli_6 +000032ca __mspabi_slli_7 +000032c8 __mspabi_slli_8 +000032c6 __mspabi_slli_9 +00003236 __mspabi_srli +0000327c __mspabi_srli_1 +00003258 __mspabi_srli_10 +00003254 __mspabi_srli_11 +00003250 __mspabi_srli_12 +0000324c __mspabi_srli_13 +00003248 __mspabi_srli_14 +00003244 __mspabi_srli_15 +00003278 __mspabi_srli_2 +00003274 __mspabi_srli_3 +00003270 __mspabi_srli_4 +0000326c __mspabi_srli_5 +00003268 __mspabi_srli_6 +00003264 __mspabi_srli_7 +00003260 __mspabi_srli_8 +0000325c __mspabi_srli_9 +000032f8 _c_int00_noargs +0000fffe _reset_vector +000030b0 _stack +00003366 _system_post_cinit +00003362 _system_pre_init +0000335c abort +0000317c main +00003326 memcpy +00003352 timerISR +00003348 timerISR2 +000032da watchdog_timer + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +address name +------- ---- +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000005 ME2 +00000008 P9IN +00000008 PBIN +00000009 P10IN +0000000a P9OUT +0000000a PBOUT +0000000b P10OUT +0000000c P9DIR +0000000c PBDIR +0000000d P10DIR +0000000e P9SEL +0000000e PBSEL +0000000f P10SEL +00000018 P3IN +00000019 P3OUT +0000001a P3DIR +0000001b P3SEL +0000001c P4IN +0000001d P4OUT +0000001e P4DIR +0000001f P4SEL +00000020 P1IN +00000021 P1OUT +00000022 P1DIR +00000023 P1IFG +00000024 P1IES +00000025 P1IE +00000026 P1SEL +00000028 P2IN +00000029 P2OUT +0000002a P2DIR +0000002b P2IFG +0000002c P2IES +0000002d P2IE +0000002e P2SEL +00000030 P5IN +00000031 P5OUT +00000032 P5DIR +00000033 P5SEL +00000034 P6IN +00000035 P6OUT +00000036 P6DIR +00000037 P6SEL +00000038 P7IN +00000038 PAIN +00000039 P8IN +0000003a P7OUT +0000003a PAOUT +0000003b P8OUT +0000003c P7DIR +0000003c PADIR +0000003d P8DIR +0000003e P7SEL +0000003e PASEL +0000003f P8SEL +00000040 BTCTL +00000040 RTCTL +00000041 RTCCTL +00000042 RTCNT1 +00000042 RTCTIM0 +00000043 RTCNT2 +00000044 RTCNT3 +00000044 RTCTIM1 +00000045 RTCNT4 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +0000004e RTCYEAR +0000004e RTCYEARL +0000004f RTCYEARH +00000050 SCFI0 +00000050 __STACK_SIZE +00000051 SCFI1 +00000052 SCFQCTL +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000056 SVSCTL +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +0000005d UCA0ABCTL +0000005e UCA0IRTCTL +0000005f UCA0IRRCTL +00000060 UCA0CTL0 +00000061 UCA0CTL1 +00000062 UCA0BR0 +00000063 UCA0BR1 +00000064 UCA0MCTL +00000065 UCA0STAT +00000066 UCA0RXBUF +00000067 UCA0TXBUF +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006a UCB0BR0 +0000006b UCB0BR1 +0000006c UCB0I2CIE +0000006d UCB0STAT +0000006e UCB0RXBUF +0000006f UCB0TXBUF +00000078 U1CTL +00000079 U1TCTL +0000007a U1RCTL +0000007b U1MCTL +0000007c U1BR0 +0000007d U1BR1 +0000007e U1RXBUF +0000007f U1TXBUF +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000090 LCDACTL +00000091 LCDM1 +00000092 LCDM2 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +000000a4 LCDM20 +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000011e TBIV +00000120 WDTCTL +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +0000012e TAIV +00000130 MPY +00000132 MPYS +00000134 MAC +00000136 MACS +00000138 OP2 +0000013a RESLO +0000013c RESHI +0000013e SUMEXT +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000160 TACTL +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000170 TAR +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000180 TBCTL +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000190 TBR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a4 ADC12IFG +000001a6 ADC12IE +000001a8 ADC12IV +000001c0 DAC12_0CTL +000001c2 DAC12_1CTL +000001c8 DAC12_0DAT +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d2 DMA0SA +000001d2 DMA0SAL +000001d6 DMA0DA +000001d6 DMA0DAL +000001da DMA0SZ +000001dc DMA1CTL +000001de DMA1SA +000001de DMA1SAL +000001e2 DMA1DA +000001e2 DMA1DAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ea DMA2SA +000001ea DMA2SAL +000001ee DMA2DA +000001ee DMA2DAL +000001f2 DMA2SZ +00001100 Up +000030b0 _stack +00003100 __STACK_END +00003100 __TI_decompress_lzss +0000317c main +000031de __TI_auto_init_nobinit_nopinit_hold_wdt +00003236 __mspabi_srli +00003244 __mspabi_srli_15 +00003248 __mspabi_srli_14 +0000324c __mspabi_srli_13 +00003250 __mspabi_srli_12 +00003254 __mspabi_srli_11 +00003258 __mspabi_srli_10 +0000325c __mspabi_srli_9 +00003260 __mspabi_srli_8 +00003264 __mspabi_srli_7 +00003268 __mspabi_srli_6 +0000326c __mspabi_srli_5 +00003270 __mspabi_srli_4 +00003274 __mspabi_srli_3 +00003278 __mspabi_srli_2 +0000327c __mspabi_srli_1 +00003282 Port1_ISR +000032ae __mspabi_slli +000032ba __mspabi_slli_15 +000032bc __mspabi_slli_14 +000032be __mspabi_slli_13 +000032c0 __mspabi_slli_12 +000032c2 __mspabi_slli_11 +000032c4 __mspabi_slli_10 +000032c6 __mspabi_slli_9 +000032c8 __mspabi_slli_8 +000032ca __mspabi_slli_7 +000032cc __mspabi_slli_6 +000032ce __mspabi_slli_5 +000032d0 __mspabi_slli_4 +000032d2 __mspabi_slli_3 +000032d4 __mspabi_slli_2 +000032d6 __mspabi_slli_1 +000032da watchdog_timer +000032f8 _c_int00_noargs +00003314 __TI_decompress_none +00003326 memcpy +00003338 __mspabi_func_epilog_7 +0000333a __mspabi_func_epilog_6 +0000333c __mspabi_func_epilog_5 +0000333e __mspabi_func_epilog_4 +00003340 __mspabi_func_epilog_3 +00003342 __mspabi_func_epilog_2 +00003344 __mspabi_func_epilog_1 +00003348 timerISR2 +00003352 timerISR +0000335c C$$EXIT +0000335c abort +00003362 _system_pre_init +00003366 _system_post_cinit +00003368 __TI_ISR_TRAP +00003376 __TI_Handler_Table_Base +0000337a __TI_CINIT_Base +0000337a __TI_Handler_Table_Limit +0000337e __TI_CINIT_Limit +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 __TI_int20 +0000ffea __TI_int21 +0000ffec __TI_int22 +0000ffee __TI_int23 +0000fff0 __TI_int24 +0000fff2 __TI_int25 +0000fff4 __TI_int26 +0000fff6 __TI_int27 +0000fff8 __TI_int28 +0000fffa __TI_int29 +0000fffc __TI_int30 +0000fffe _reset_vector +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ + +[330 symbols] diff --git a/CPE325/Lab7_P1/Debug/Lab7_P1.out b/CPE325/Lab7_P1/Debug/Lab7_P1.out new file mode 100644 index 0000000..5ca7537 Binary files /dev/null and b/CPE325/Lab7_P1/Debug/Lab7_P1.out differ diff --git a/CPE325/Lab7_P1/Debug/Lab7_P1_linkInfo.xml b/CPE325/Lab7_P1/Debug/Lab7_P1_linkInfo.xml new file mode 100644 index 0000000..553d835 --- /dev/null +++ b/CPE325/Lab7_P1/Debug/Lab7_P1_linkInfo.xml @@ -0,0 +1,4515 @@ + + + MSP430 Linker PC v20.2.5.LTS + Copyright (c) 2003-2018 Texas Instruments Incorporated + 0x61a98310 + 0x0 + Lab7_P1.out + + _c_int00_noargs +
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__TI_int17 + 0xffe2 + + + + __TI_int18 + 0xffe4 + + + + __TI_int19 + 0xffe6 + + + + __TI_int21 + 0xffea + + + + __TI_int22 + 0xffec + + + + __TI_int23 + 0xffee + + + + __TI_int24 + 0xfff0 + + + + __TI_int25 + 0xfff2 + + + + __TI_int27 + 0xfff6 + + + + __TI_int30 + 0xfffc + + + + __TI_ISR_TRAP + 0x3368 + + + + _stack + 0x30b0 + + + + _c_int00_noargs + 0x32f8 + + + + _reset_vector + 0xfffe + + + + __TI_auto_init_nobinit_nopinit_hold_wdt + 0x31de + + + + _system_pre_init + 0x3362 + + + + _system_post_cinit + 0x3366 + + + + __TI_decompress_none + 0x3314 + + + + __TI_decompress_lzss + 0x3100 + + + + C$$EXIT + 0x335c + + + + abort + 0x335c + + + + memcpy + 0x3326 + + + + __mspabi_func_epilog_2 + 0x3342 + + + + __mspabi_func_epilog_3 + 0x3340 + + + + __mspabi_func_epilog_1 + 0x3344 + + + + __mspabi_func_epilog_6 + 0x333a + + + + __mspabi_func_epilog_7 + 0x3338 + + + + __mspabi_func_epilog_4 + 0x333e + + + + __mspabi_func_epilog_5 + 0x333c + + + + __mspabi_slli + 0x32ae + + + + __mspabi_slli_9 + 0x32c6 + + + + __mspabi_slli_8 + 0x32c8 + + + + __mspabi_slli_7 + 0x32ca + + + + __mspabi_slli_6 + 0x32cc + + + + __mspabi_slli_5 + 0x32ce + + + + __mspabi_slli_4 + 0x32d0 + + + + __mspabi_slli_3 + 0x32d2 + + + + __mspabi_slli_2 + 0x32d4 + + + + __mspabi_slli_1 + 0x32d6 + + + + __mspabi_slli_15 + 0x32ba + + + + __mspabi_slli_14 + 0x32bc + + + + __mspabi_slli_13 + 0x32be + + + + __mspabi_slli_12 + 0x32c0 + + + + __mspabi_slli_11 + 0x32c2 + + + + __mspabi_slli_10 + 0x32c4 + + + + __mspabi_srli_8 + 0x3260 + + + + __mspabi_srli_9 + 0x325c + + + + __mspabi_srli_6 + 0x3268 + + + + __mspabi_srli_7 + 0x3264 + + + + __mspabi_srli_4 + 0x3270 + + + + __mspabi_srli_5 + 0x326c + + + + __mspabi_srli_2 + 0x3278 + + + + __mspabi_srli_3 + 0x3274 + + + + __mspabi_srli_1 + 0x327c + + + + __mspabi_srli + 0x3236 + + + + __mspabi_srli_15 + 0x3244 + + + + __mspabi_srli_14 + 0x3248 + + + + __mspabi_srli_13 + 0x324c + + + + __mspabi_srli_12 + 0x3250 + + + + __mspabi_srli_11 + 0x3254 + + + + __mspabi_srli_10 + 0x3258 + + + + Link successful + diff --git a/CPE325/Lab7_P1/Debug/Lab7_Part1.d b/CPE325/Lab7_P1/Debug/Lab7_Part1.d new file mode 100644 index 0000000..4d4000d --- /dev/null +++ b/CPE325/Lab7_P1/Debug/Lab7_Part1.d @@ -0,0 +1,21 @@ +# FIXED + +Lab7_Part1.obj: ../Lab7_Part1.c +Lab7_Part1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +Lab7_Part1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h +Lab7_Part1.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +Lab7_Part1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +Lab7_Part1.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h + +../Lab7_Part1.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + diff --git a/CPE325/Lab7_P1/Debug/Lab7_Part1.obj b/CPE325/Lab7_P1/Debug/Lab7_Part1.obj new file mode 100644 index 0000000..6e66ac0 Binary files /dev/null and b/CPE325/Lab7_P1/Debug/Lab7_Part1.obj differ diff --git a/CPE325/Lab7_P1/Debug/ccsObjs.opt b/CPE325/Lab7_P1/Debug/ccsObjs.opt new file mode 100644 index 0000000..2fc5ac6 --- /dev/null +++ b/CPE325/Lab7_P1/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./Lab7_Part1.obj" "../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/Lab7_P1/Debug/main.d b/CPE325/Lab7_P1/Debug/main.d new file mode 100644 index 0000000..15f98dd --- /dev/null +++ b/CPE325/Lab7_P1/Debug/main.d @@ -0,0 +1,21 @@ +# FIXED + +main.obj: ../main.c +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h + +../main.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + diff --git a/CPE325/Lab7_P1/Debug/main.obj b/CPE325/Lab7_P1/Debug/main.obj new file mode 100644 index 0000000..dd9e6d6 Binary files /dev/null and b/CPE325/Lab7_P1/Debug/main.obj differ diff --git a/CPE325/Lab7_P1/Debug/makefile b/CPE325/Lab7_P1/Debug/makefile new file mode 100644 index 0000000..0965624 --- /dev/null +++ b/CPE325/Lab7_P1/Debug/makefile @@ -0,0 +1,166 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./Lab7_Part1.obj" \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab7_P1.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab7_P1.out" \ + +BIN_OUTPUTS += \ +Lab7_P1.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab7_P1.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab7_P1.out" + +# Tool invocations +Lab7_P1.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"Lab7_P1.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab7_P1_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "Lab7_P1.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab7_P1.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab7_P1.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "Lab7_Part1.obj" + -$(RM) "Lab7_Part1.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab7_P1/Debug/objects.mk b/CPE325/Lab7_P1/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/Lab7_P1/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/Lab7_P1/Debug/sources.mk b/CPE325/Lab7_P1/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab7_P1/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab7_P1/Debug/subdir_rules.mk b/CPE325/Lab7_P1/Debug/subdir_rules.mk new file mode 100644 index 0000000..2ce64c7 --- /dev/null +++ b/CPE325/Lab7_P1/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmsp --data_model=small --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab7_P1" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --preproc_with_compile --preproc_dependency="$(basename $( +#define SW1_PRESSED ((BIT0&P1IFG)==0) // SW1 Status +#define SW2_PRESSED ((BIT1&P1IFG)==0) // SW2 Status + +int Up =1; + +int main(void) +{ + WDTCTL = WDT_MDLY_8; // 8 ms interval + _EINT(); // Enable interrupts + IE1 |= WDTIE; // Enable WDT interrupt + P2DIR |= (BIT1 + BIT2); // P2.1 and P2.2 set up as output + P2SEL &= ~BIT1; // Clear P2.1 + P2OUT |= BIT1; // Turn on LED2 + P2OUT &= ~BIT2; // Turn Off LED1 + P2SEL |= BIT2; // P2.2 special function (TB0 output) + TB0CTL = TBSSEL_2 | MC_1; // Upmode + TB0CCTL1 |= (OUTMOD_2 + CCIE); // TB1 output is in Up mode and Interrupt + TB0CCTL0 = CCIE; // TB0 count triggers interrupt + TB0CCR0 = 750; // Set TB0 (and maximum) count value + TB0CCR1 = Up; // Set TB1 count value + P1IE |= BIT0; // P1.0 interrupt enabled + P1IE |= BIT1; // P1.1 interrupt enabled + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared + _BIS_SR(LPM0_bits + GIE); // Enter Low Power Mode 0 +} + +#pragma vector = TIMERB0_VECTOR +__interrupt void timerISR(void) +{ + P2OUT |= BIT1; // Turn off LED2 + TB0CCTL0 &= ~CCIFG; // Clear interrupt flag +} + +#pragma vector = TIMERB1_VECTOR +__interrupt void timerISR2(void) +{ + P2OUT &= ~BIT1; // Toggle LED2 + TB0CCTL1 &= ~CCIFG; // Clear interrupt flag +} + +// Watchdog Timer interrupt service routine +#pragma vector=WDT_VECTOR +__interrupt void watchdog_timer(void) +{ + TB0CCR1 += Up; // Up=1, CCR1 will increase; Up = -1 CCR1 will decrease + if(TB0CCR1 == 750){ // If CCR1 is upper-bound, Up becomes -1 + Up = -1; + } + if(TB0CCR1 ==0 ){ // If CCR1 is upper-bound, Up becomes 1 + Up = 1; + } +} + +// Port 1 interrupt service routine +#pragma vector = PORT1_VECTOR +__interrupt void Port1_ISR (void) { + if(!SW1_PRESSED) + WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer + else if(!SW2_PRESSED) + WDTCTL = WDT_MDLY_8; // 8 ms interval + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared +} + diff --git a/CPE325/Lab7_P1/lnk_msp430fg4618.cmd b/CPE325/Lab7_P1/lnk_msp430fg4618.cmd new file mode 100755 index 0000000..557b664 --- /dev/null +++ b/CPE325/Lab7_P1/lnk_msp430fg4618.cmd @@ -0,0 +1,184 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************************/ +/* lnk_msp430fg4618.cmd - LINKER COMMAND FILE FOR LINKING MSP430FG4618 PROGRAMS */ +/* */ +/* Usage: lnk430 -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/Lab7_P1/main.c b/CPE325/Lab7_P1/main.c new file mode 100644 index 0000000..6ba1091 --- /dev/null +++ b/CPE325/Lab7_P1/main.c @@ -0,0 +1,81 @@ +/*------------------------------------------------------------------------------ + * File: p1.c + * Function: Prints out variables according to their Data Type with the size and the ranges of the variables + * Description: + * Input: None + * Output: " + * Author(s): Noah Woodlee + * Lab Section: 09 + * Date: Nov 1, 2021 + *----------------------------------------------------------------------------*/ + +#include +#define SW1_PRESSED ((BIT0&P1IFG)==0) // SW1 Status +#define SW2_PRESSED ((BIT1&P1IFG)==0) // SW2 Status + +int Up =1; + +int main(void) +{ + WDTCTL = WDT_MDLY_8; // 8 ms interval + _EINT(); // Enable interrupts + IE1 |= WDTIE; // Enable WDT interrupt + P2DIR |= (BIT1 + BIT2); // P2.1 and P2.2 set up as output + P2SEL &= ~BIT1; // Clear P2.1 + P2OUT |= BIT1; // Turn on LED2 + P2OUT &= ~BIT2; // Turn Off LED1 + P2SEL |= BIT2; // P2.2 special function (TB0 output) + TB0CTL = TBSSEL_2 | MC_1; // Upmode + TB0CCTL1 |= (OUTMOD_2 + CCIE); // TB1 output is in Up mode and Interrupt + TB0CCTL0 = CCIE; // TB0 count triggers interrupt + TB0CCR0 = 750; // Set TB0 (and maximum) count value + TB0CCR1 = Up; // Set TB1 count value + P1IE |= BIT0; // P1.0 interrupt enabled + P1IE |= BIT1; // P1.1 interrupt enabled + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared + _BIS_SR(LPM0_bits + GIE); // Enter Low Power Mode 3 +} + +#pragma vector = TIMERB0_VECTOR +__interrupt void timerISR(void) +{ + P2OUT |= BIT1; // Turn off LED2 + TB0CCTL0 &= ~CCIFG; // Clear interrupt flag +} + +#pragma vector = TIMERB1_VECTOR +__interrupt void timerISR2(void) +{ + P2OUT &= ~BIT1; // Toggle LED2 + TB0CCTL1 &= ~CCIFG; // Clear interrupt flag +} + +// Watchdog Timer interrupt service routine +#pragma vector=WDT_VECTOR +__interrupt void watchdog_timer(void) +{ + TB0CCR1 += Up; // Up=1, CCR1 will increase; Up = -1 CCR1 will decrease + if(TB0CCR1 == 750){ // If CCR1 is upper-bound, Up becomes -1 + Up = -1; + } + if(TB0CCR1 ==0 ){ // If CCR1 is upper-bound, Up becomes 1 + Up = 1; + } +} + +// Port 1 interrupt service routine +#pragma vector = PORT1_VECTOR +__interrupt void Port1_ISR (void) { + if(!SW1_PRESSED) + WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer + } + else if(!SW2_PRESSED) WDTCTL = WDT_MDLY_8; // 8 ms interval + P1IES |= BIT0; // P1.0 hi/low edge + P1IFG &= ~BIT0; // P1.0 IFG cleared + P1IES |= BIT1; // P1.1 hi/low edge + P1IFG &= ~BIT1; // P1.1 IFG cleared +} + diff --git a/CPE325/Lab7_P1/targetConfigs/MSP430FG4618.ccxml b/CPE325/Lab7_P1/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/Lab7_P1/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab7_P1/targetConfigs/readme.txt b/CPE325/Lab7_P1/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab7_P1/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE325/Lab7_P2/Debug/Lab7_P2.map b/CPE325/Lab7_P2/Debug/Lab7_P2.map new file mode 100644 index 0000000..905ffd8 --- /dev/null +++ b/CPE325/Lab7_P2/Debug/Lab7_P2.map @@ -0,0 +1,802 @@ +****************************************************************************** + MSP430 Linker PC v20.2.5 +****************************************************************************** +>> Linked Thu Dec 2 20:38:09 2021 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00003176 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + SFR 00000000 00000010 00000000 00000010 RWIX + PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX + PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX + INFOB 00001000 00000080 00000000 00000080 RWIX + INFOA 00001080 00000080 00000000 00000080 RWIX + RAM 00001100 00002000 0000005a 00001fa6 RWIX + FLASH 00003100 0000cebe 000000ba 0000ce04 RWIX + BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff + INT00 0000ffc0 00000002 00000000 00000002 RWIX + INT01 0000ffc2 00000002 00000000 00000002 RWIX + INT02 0000ffc4 00000002 00000000 00000002 RWIX + INT03 0000ffc6 00000002 00000000 00000002 RWIX + INT04 0000ffc8 00000002 00000000 00000002 RWIX + INT05 0000ffca 00000002 00000000 00000002 RWIX + INT06 0000ffcc 00000002 00000000 00000002 RWIX + INT07 0000ffce 00000002 00000000 00000002 RWIX + INT08 0000ffd0 00000002 00000000 00000002 RWIX + INT09 0000ffd2 00000002 00000000 00000002 RWIX + INT10 0000ffd4 00000002 00000000 00000002 RWIX + INT11 0000ffd6 00000002 00000000 00000002 RWIX + INT12 0000ffd8 00000002 00000000 00000002 RWIX + INT13 0000ffda 00000002 00000000 00000002 RWIX + INT14 0000ffdc 00000002 00000002 00000000 RWIX + INT15 0000ffde 00000002 00000002 00000000 RWIX + INT16 0000ffe0 00000002 00000002 00000000 RWIX + INT17 0000ffe2 00000002 00000002 00000000 RWIX + INT18 0000ffe4 00000002 00000002 00000000 RWIX + INT19 0000ffe6 00000002 00000002 00000000 RWIX + INT20 0000ffe8 00000002 00000002 00000000 RWIX + INT21 0000ffea 00000002 00000002 00000000 RWIX + INT22 0000ffec 00000002 00000002 00000000 RWIX + INT23 0000ffee 00000002 00000002 00000000 RWIX + INT24 0000fff0 00000002 00000002 00000000 RWIX + INT25 0000fff2 00000002 00000002 00000000 RWIX + INT26 0000fff4 00000002 00000002 00000000 RWIX + INT27 0000fff6 00000002 00000002 00000000 RWIX + INT28 0000fff8 00000002 00000002 00000000 RWIX + INT29 0000fffa 00000002 00000002 00000000 RWIX + INT30 0000fffc 00000002 00000002 00000000 RWIX + RESET 0000fffe 00000002 00000002 00000000 RWIX + FLASH2 00010000 00010000 00000144 0000febc RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.data 0 00001100 0000000a UNINITIALIZED + 00001100 00000008 main.obj (.data:freq) + 00001108 00000002 main.obj (.data) + +.stack 0 000030b0 00000050 UNINITIALIZED + 000030b0 00000004 rts430x_lc_rd_eabi.lib : boot.c.obj (.stack) + 000030b4 0000004c --HOLE-- + +.text:_isr +* 0 00003100 0000009a + 00003100 00000076 main.obj (.text:_isr:watchdog_timer) + 00003176 0000001c rts430x_lc_rd_eabi.lib : boot.c.obj (.text:_isr:_c_int00_noargs) + 00003192 00000008 : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + +.cinit 0 0000319a 00000020 + 0000319a 0000000f (.cinit..data.load) [load image, compression = lzss] + 000031a9 00000001 --HOLE-- [fill = 0] + 000031aa 00000008 (__TI_handler_table) + 000031b2 00000008 (__TI_cinit_table) + +.binit 0 00003100 00000000 + +.init_array +* 0 00003100 00000000 UNINITIALIZED + +$fill000 0 0000ffbe 00000002 + 0000ffbe 00000002 --HOLE-- [fill = ffff] + +DAC12 0 0000ffdc 00000002 + 0000ffdc 00000002 rts430x_lc_rd_eabi.lib : int14.asm.obj (.int14) + +DMA 0 0000ffde 00000002 + 0000ffde 00000002 rts430x_lc_rd_eabi.lib : int15.asm.obj (.int15) + +BASICTIMER +* 0 0000ffe0 00000002 + 0000ffe0 00000002 rts430x_lc_rd_eabi.lib : int16.asm.obj (.int16) + +PORT2 0 0000ffe2 00000002 + 0000ffe2 00000002 rts430x_lc_rd_eabi.lib : int17.asm.obj (.int17) + +USART1TX 0 0000ffe4 00000002 + 0000ffe4 00000002 rts430x_lc_rd_eabi.lib : int18.asm.obj (.int18) + +USART1RX 0 0000ffe6 00000002 + 0000ffe6 00000002 rts430x_lc_rd_eabi.lib : int19.asm.obj (.int19) + +PORT1 0 0000ffe8 00000002 + 0000ffe8 00000002 rts430x_lc_rd_eabi.lib : int20.asm.obj (.int20) + +TIMERA1 0 0000ffea 00000002 + 0000ffea 00000002 rts430x_lc_rd_eabi.lib : int21.asm.obj (.int21) + +TIMERA0 0 0000ffec 00000002 + 0000ffec 00000002 rts430x_lc_rd_eabi.lib : int22.asm.obj (.int22) + +ADC12 0 0000ffee 00000002 + 0000ffee 00000002 rts430x_lc_rd_eabi.lib : int23.asm.obj (.int23) + +USCIAB0TX +* 0 0000fff0 00000002 + 0000fff0 00000002 rts430x_lc_rd_eabi.lib : int24.asm.obj (.int24) + +USCIAB0RX +* 0 0000fff2 00000002 + 0000fff2 00000002 rts430x_lc_rd_eabi.lib : int25.asm.obj (.int25) + +WDT 0 0000fff4 00000002 + 0000fff4 00000002 main.obj (.int26) + +COMPARATORA +* 0 0000fff6 00000002 + 0000fff6 00000002 rts430x_lc_rd_eabi.lib : int27.asm.obj (.int27) + +TIMERB1 0 0000fff8 00000002 + 0000fff8 00000002 rts430x_lc_rd_eabi.lib : int28.asm.obj (.int28) + +TIMERB0 0 0000fffa 00000002 + 0000fffa 00000002 rts430x_lc_rd_eabi.lib : int29.asm.obj (.int29) + +NMI 0 0000fffc 00000002 + 0000fffc 00000002 rts430x_lc_rd_eabi.lib : int30.asm.obj (.int30) + +.reset 0 0000fffe 00000002 + 0000fffe 00000002 rts430x_lc_rd_eabi.lib : boot.c.obj (.reset) + +.text 0 00010000 00000144 + 00010000 00000076 rts430x_lc_rd_eabi.lib : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) + 00010076 00000054 : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) + 000100ca 00000048 main.obj (.text:main) + 00010112 00000014 rts430x_lc_rd_eabi.lib : memcpy.c.obj (.text:memcpy) + 00010126 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) + 00010138 00000006 : exit.c.obj (.text:abort) + 0001013e 00000004 : pre_init.c.obj (.text:_system_pre_init) + 00010142 00000002 : startup.c.obj (.text:_system_post_cinit) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + main.obj 190 2 10 + +--+----------------------------+------+---------+---------+ + Total: 190 2 10 + + C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430x_lc_rd_eabi.lib + copy_decompress_lzss.c.obj 118 0 0 + autoinit.c.obj 84 0 0 + boot.c.obj 28 2 0 + memcpy.c.obj 20 0 0 + copy_decompress_none.c.obj 18 0 0 + isr_trap.asm.obj 8 0 0 + exit.c.obj 6 0 0 + pre_init.c.obj 4 0 0 + int14.asm.obj 0 2 0 + int15.asm.obj 0 2 0 + int16.asm.obj 0 2 0 + int17.asm.obj 0 2 0 + int18.asm.obj 0 2 0 + int19.asm.obj 0 2 0 + int20.asm.obj 0 2 0 + int21.asm.obj 0 2 0 + int22.asm.obj 0 2 0 + int23.asm.obj 0 2 0 + int24.asm.obj 0 2 0 + int25.asm.obj 0 2 0 + int27.asm.obj 0 2 0 + int28.asm.obj 0 2 0 + int29.asm.obj 0 2 0 + int30.asm.obj 0 2 0 + startup.c.obj 2 0 0 + +--+----------------------------+------+---------+---------+ + Total: 288 34 0 + + Stack: 0 0 80 + Linker Generated: 0 31 0 + +--+----------------------------+------+---------+---------+ + Grand Total: 478 67 90 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 000031b2 records: 1, size/record: 8, table size: 8 + .data: load addr=0000319a, load size=0000000f bytes, run addr=00001100, run size=0000000a bytes, compression=lzss + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 000031aa records: 2, size/record: 4, table size: 8 + index: 0, handler: __TI_decompress_lzss + index: 1, handler: __TI_decompress_none + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +000001a0 ADC12CTL0 +000001a2 ADC12CTL1 +000001a6 ADC12IE +000001a4 ADC12IFG +000001a8 ADC12IV +00000080 ADC12MCTL0 +00000081 ADC12MCTL1 +0000008a ADC12MCTL10 +0000008b ADC12MCTL11 +0000008c ADC12MCTL12 +0000008d ADC12MCTL13 +0000008e ADC12MCTL14 +0000008f ADC12MCTL15 +00000082 ADC12MCTL2 +00000083 ADC12MCTL3 +00000084 ADC12MCTL4 +00000085 ADC12MCTL5 +00000086 ADC12MCTL6 +00000087 ADC12MCTL7 +00000088 ADC12MCTL8 +00000089 ADC12MCTL9 +00000140 ADC12MEM0 +00000142 ADC12MEM1 +00000154 ADC12MEM10 +00000156 ADC12MEM11 +00000158 ADC12MEM12 +0000015a ADC12MEM13 +0000015c ADC12MEM14 +0000015e ADC12MEM15 +00000144 ADC12MEM2 +00000146 ADC12MEM3 +00000148 ADC12MEM4 +0000014a ADC12MEM5 +0000014c ADC12MEM6 +0000014e ADC12MEM7 +00000150 ADC12MEM8 +00000152 ADC12MEM9 +00000046 BTCNT1 +00000046 BTCNT12 +00000047 BTCNT2 +00000040 BTCTL +00010138 C$$EXIT +00000059 CACTL1 +0000005a CACTL2 +0000005b CAPD +000001c0 DAC12_0CTL +000001c8 DAC12_0DAT +000001c2 DAC12_1CTL +000001ca DAC12_1DAT +000001d0 DMA0CTL +000001d6 DMA0DA +000001d6 DMA0DAL +000001d2 DMA0SA +000001d2 DMA0SAL +000001da DMA0SZ +000001dc DMA1CTL +000001e2 DMA1DA +000001e2 DMA1DAL +000001de DMA1SA +000001de DMA1SAL +000001e6 DMA1SZ +000001e8 DMA2CTL +000001ee DMA2DA +000001ee DMA2DAL +000001ea DMA2SA +000001ea DMA2SAL +000001f2 DMA2SZ +00000122 DMACTL0 +00000124 DMACTL1 +00000126 DMAIV +00000128 FCTL1 +0000012a FCTL2 +0000012c FCTL3 +00000053 FLL_CTL0 +00000054 FLL_CTL1 +00000000 IE1 +00000001 IE2 +00000002 IFG1 +00000003 IFG2 +00000090 LCDACTL +000000ac LCDAPCTL0 +000000ad LCDAPCTL1 +000000ae LCDAVCTL0 +000000af LCDAVCTL1 +00000091 LCDM1 +0000009a LCDM10 +0000009b LCDM11 +0000009c LCDM12 +0000009d LCDM13 +0000009e LCDM14 +0000009f LCDM15 +000000a0 LCDM16 +000000a1 LCDM17 +000000a2 LCDM18 +000000a3 LCDM19 +00000092 LCDM2 +000000a4 LCDM20 +00000093 LCDM3 +00000094 LCDM4 +00000095 LCDM5 +00000096 LCDM6 +00000097 LCDM7 +00000098 LCDM8 +00000099 LCDM9 +00000134 MAC +00000136 MACS +00000005 ME2 +00000130 MPY +00000132 MPYS +000000c0 OA0CTL0 +000000c1 OA0CTL1 +000000c2 OA1CTL0 +000000c3 OA1CTL1 +000000c4 OA2CTL0 +000000c5 OA2CTL1 +00000138 OP2 +0000000d P10DIR +00000009 P10IN +0000000b P10OUT +0000000f P10SEL +00000022 P1DIR +00000025 P1IE +00000024 P1IES +00000023 P1IFG +00000020 P1IN +00000021 P1OUT +00000026 P1SEL +0000002a P2DIR +0000002d P2IE +0000002c P2IES +0000002b P2IFG +00000028 P2IN +00000029 P2OUT +0000002e P2SEL +0000001a P3DIR +00000018 P3IN +00000019 P3OUT +0000001b P3SEL +0000001e P4DIR +0000001c P4IN +0000001d P4OUT +0000001f P4SEL +00000032 P5DIR +00000030 P5IN +00000031 P5OUT +00000033 P5SEL +00000036 P6DIR +00000034 P6IN +00000035 P6OUT +00000037 P6SEL +0000003c P7DIR +00000038 P7IN +0000003a P7OUT +0000003e P7SEL +0000003d P8DIR +00000039 P8IN +0000003b P8OUT +0000003f P8SEL +0000000c P9DIR +00000008 P9IN +0000000a P9OUT +0000000e P9SEL +0000003c PADIR +00000038 PAIN +0000003a PAOUT +0000003e PASEL +0000000c PBDIR +00000008 PBIN +0000000a PBOUT +0000000e PBSEL +0000013c RESHI +0000013a RESLO +00000041 RTCCTL +0000004c RTCDATE +0000004c RTCDAY +0000004d RTCMON +00000042 RTCNT1 +00000043 RTCNT2 +00000044 RTCNT3 +00000045 RTCNT4 +00000042 RTCTIM0 +00000044 RTCTIM1 +00000040 RTCTL +0000004e RTCYEAR +0000004f RTCYEARH +0000004e RTCYEARL +00000050 SCFI0 +00000051 SCFI1 +00000052 SCFQCTL +0000013e SUMEXT +00000056 SVSCTL +00000172 TACCR0 +00000174 TACCR1 +00000176 TACCR2 +00000162 TACCTL0 +00000164 TACCTL1 +00000166 TACCTL2 +00000160 TACTL +0000012e TAIV +00000170 TAR +00000192 TBCCR0 +00000194 TBCCR1 +00000196 TBCCR2 +00000198 TBCCR3 +0000019a TBCCR4 +0000019c TBCCR5 +0000019e TBCCR6 +00000182 TBCCTL0 +00000184 TBCCTL1 +00000186 TBCCTL2 +00000188 TBCCTL3 +0000018a TBCCTL4 +0000018c TBCCTL5 +0000018e TBCCTL6 +00000180 TBCTL +0000011e TBIV +00000190 TBR +0000007c U1BR0 +0000007d U1BR1 +00000078 U1CTL +0000007b U1MCTL +0000007a U1RCTL +0000007e U1RXBUF +00000079 U1TCTL +0000007f U1TXBUF +0000005d UCA0ABCTL +00000062 UCA0BR0 +00000063 UCA0BR1 +00000060 UCA0CTL0 +00000061 UCA0CTL1 +0000005f UCA0IRRCTL +0000005e UCA0IRTCTL +00000064 UCA0MCTL +00000066 UCA0RXBUF +00000065 UCA0STAT +00000067 UCA0TXBUF +0000006a UCB0BR0 +0000006b UCB0BR1 +00000068 UCB0CTL0 +00000069 UCB0CTL1 +0000006c UCB0I2CIE +00000118 UCB0I2COA +0000011a UCB0I2CSA +0000006e UCB0RXBUF +0000006d UCB0STAT +0000006f UCB0TXBUF +00000120 WDTCTL +00003100 __STACK_END +00000050 __STACK_SIZE +000031b2 __TI_CINIT_Base +000031ba __TI_CINIT_Limit +000031aa __TI_Handler_Table_Base +000031b2 __TI_Handler_Table_Limit +00003192 __TI_ISR_TRAP +00010076 __TI_auto_init_nobinit_nopinit_hold_wdt +00010000 __TI_decompress_lzss +00010126 __TI_decompress_none +0000ffdc __TI_int14 +0000ffde __TI_int15 +0000ffe0 __TI_int16 +0000ffe2 __TI_int17 +0000ffe4 __TI_int18 +0000ffe6 __TI_int19 +0000ffe8 __TI_int20 +0000ffea __TI_int21 +0000ffec __TI_int22 +0000ffee __TI_int23 +0000fff0 __TI_int24 +0000fff2 __TI_int25 +0000fff4 __TI_int26 +0000fff6 __TI_int27 +0000fff8 __TI_int28 +0000fffa __TI_int29 +0000fffc __TI_int30 +ffffffff __TI_pprof_out_hndl +ffffffff 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__TI_prof_data_size + 0xffffffff + + + __TI_int26 + 0xfff4 + + + + freq + 0x1100 + + + + watchdog_timer + 0x3100 + + + + main + 0x100ca + + + + __TI_int14 + 0xffdc + + + + __TI_int15 + 0xffde + + + + __TI_int16 + 0xffe0 + + + + __TI_int17 + 0xffe2 + + + + __TI_int18 + 0xffe4 + + + + __TI_int19 + 0xffe6 + + + + __TI_int20 + 0xffe8 + + + + __TI_int21 + 0xffea + + + + __TI_int22 + 0xffec + + + + __TI_int23 + 0xffee + + + + __TI_int24 + 0xfff0 + + + + __TI_int25 + 0xfff2 + + + + __TI_int27 + 0xfff6 + + + + __TI_int28 + 0xfff8 + + + + __TI_int29 + 0xfffa + + + + __TI_int30 + 0xfffc + + + + __TI_ISR_TRAP + 0x3192 + + + + _stack + 0x30b0 + + + + _c_int00_noargs + 0x3176 + + + + _reset_vector + 0xfffe + + + + __TI_auto_init_nobinit_nopinit_hold_wdt + 0x10076 + + + + _system_pre_init + 0x1013e + + + + _system_post_cinit + 0x10142 + + + + __TI_decompress_none + 0x10126 + + + + __TI_decompress_lzss + 0x10000 + + + + C$$EXIT + 0x10138 + + + + abort + 0x10138 + + + + memcpy + 0x10112 + + + + Link successful + diff --git a/CPE325/Lab7_P2/Debug/ccsObjs.opt b/CPE325/Lab7_P2/Debug/ccsObjs.opt new file mode 100644 index 0000000..2f36690 --- /dev/null +++ b/CPE325/Lab7_P2/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./main.obj" "../lnk_msp430fg4618.cmd" -llibc.a \ No newline at end of file diff --git a/CPE325/Lab7_P2/Debug/main.d b/CPE325/Lab7_P2/Debug/main.d new file mode 100644 index 0000000..15f98dd --- /dev/null +++ b/CPE325/Lab7_P2/Debug/main.d @@ -0,0 +1,21 @@ +# FIXED + +main.obj: ../main.c +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h +main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h +main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h + +../main.c: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h: + +C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h: + +C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h: + diff --git a/CPE325/Lab7_P2/Debug/main.obj b/CPE325/Lab7_P2/Debug/main.obj new file mode 100644 index 0000000..114001c Binary files /dev/null and b/CPE325/Lab7_P2/Debug/main.obj differ diff --git a/CPE325/Lab7_P2/Debug/makefile b/CPE325/Lab7_P2/Debug/makefile new file mode 100644 index 0000000..810f98d --- /dev/null +++ b/CPE325/Lab7_P2/Debug/makefile @@ -0,0 +1,166 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"../lnk_msp430fg4618.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +Lab7_P2.out \ + +EXE_OUTPUTS__QUOTED += \ +"Lab7_P2.out" \ + +BIN_OUTPUTS += \ +Lab7_P2.hex \ + +BIN_OUTPUTS__QUOTED += \ +"Lab7_P2.hex" \ + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "Lab7_P2.out" + +# Tool invocations +Lab7_P2.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) + @echo 'Building target: "$@"' + @echo 'Invoking: MSP430 Linker' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"Lab7_P2.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab7_P2_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "Lab7_P2.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +Lab7_P2.hex: $(EXE_OUTPUTS) + @echo 'Building secondary target: "$@"' + @echo 'Invoking: MSP430 Hex Utility' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab7_P2.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building secondary target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) + -$(RM) "main.obj" + -$(RM) "main.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/CPE325/Lab7_P2/Debug/objects.mk b/CPE325/Lab7_P2/Debug/objects.mk new file mode 100644 index 0000000..9ca4b12 --- /dev/null +++ b/CPE325/Lab7_P2/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/CPE325/Lab7_P2/Debug/sources.mk b/CPE325/Lab7_P2/Debug/sources.mk new file mode 100644 index 0000000..fb4f5d4 --- /dev/null +++ b/CPE325/Lab7_P2/Debug/sources.mk @@ -0,0 +1,115 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/CPE325/Lab7_P2/Debug/subdir_rules.mk b/CPE325/Lab7_P2/Debug/subdir_rules.mk new file mode 100644 index 0000000..6ab1087 --- /dev/null +++ b/CPE325/Lab7_P2/Debug/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: MSP430 Compiler' + "C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab7_P2" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --preproc_with_compile --preproc_dependency="$(basename $( -o -m lnk.cmd */ +/* cl430 -z -o -m lnk.cmd */ +/* */ +/*----------------------------------------------------------------------------*/ +/* These linker options are for command line linking only. For IDE linking, */ +/* you should set your linker options in Project Properties */ +/* -c LINK USING C CONVENTIONS */ +/* -stack 0x0100 SOFTWARE STACK SIZE */ +/* -heap 0x0100 HEAP AREA SIZE */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Version: 1.211 */ +/*----------------------------------------------------------------------------*/ + +/****************************************************************************/ +/* Specify the system memory map */ +/****************************************************************************/ + +MEMORY +{ + SFR : origin = 0x0000, length = 0x0010 + PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0 + PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100 + RAM : origin = 0x1100, length = 0x2000 + INFOA : origin = 0x1080, length = 0x0080 + INFOB : origin = 0x1000, length = 0x0080 + FLASH : origin = 0x3100, length = 0xCEBE + FLASH2 : origin = 0x10000,length = 0x10000 + BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF + INT00 : origin = 0xFFC0, length = 0x0002 + INT01 : origin = 0xFFC2, length = 0x0002 + INT02 : origin = 0xFFC4, length = 0x0002 + INT03 : origin = 0xFFC6, length = 0x0002 + INT04 : origin = 0xFFC8, length = 0x0002 + INT05 : origin = 0xFFCA, length = 0x0002 + INT06 : origin = 0xFFCC, length = 0x0002 + INT07 : origin = 0xFFCE, length = 0x0002 + INT08 : origin = 0xFFD0, length = 0x0002 + INT09 : origin = 0xFFD2, length = 0x0002 + INT10 : origin = 0xFFD4, length = 0x0002 + INT11 : origin = 0xFFD6, length = 0x0002 + INT12 : origin = 0xFFD8, length = 0x0002 + INT13 : origin = 0xFFDA, length = 0x0002 + INT14 : origin = 0xFFDC, length = 0x0002 + INT15 : origin = 0xFFDE, length = 0x0002 + INT16 : origin = 0xFFE0, length = 0x0002 + INT17 : origin = 0xFFE2, length = 0x0002 + INT18 : origin = 0xFFE4, length = 0x0002 + INT19 : origin = 0xFFE6, length = 0x0002 + INT20 : origin = 0xFFE8, length = 0x0002 + INT21 : origin = 0xFFEA, length = 0x0002 + INT22 : origin = 0xFFEC, length = 0x0002 + INT23 : origin = 0xFFEE, length = 0x0002 + INT24 : origin = 0xFFF0, length = 0x0002 + INT25 : origin = 0xFFF2, length = 0x0002 + INT26 : origin = 0xFFF4, length = 0x0002 + INT27 : origin = 0xFFF6, length = 0x0002 + INT28 : origin = 0xFFF8, length = 0x0002 + INT29 : origin = 0xFFFA, length = 0x0002 + INT30 : origin = 0xFFFC, length = 0x0002 + RESET : origin = 0xFFFE, length = 0x0002 +} + +/****************************************************************************/ +/* Specify the sections allocation into memory */ +/****************************************************************************/ + +SECTIONS +{ + .bss : {} > RAM /* Global & static vars */ + .data : {} > RAM /* Global & static vars */ + .TI.noinit : {} > RAM /* For #pragma noinit */ + .sysmem : {} > RAM /* Dynamic memory allocation area */ + .stack : {} > RAM (HIGH) /* Software system stack */ + +#ifndef __LARGE_CODE_MODEL__ + .text : {} > FLASH /* Code */ +#else + .text : {} >> FLASH2 | FLASH /* Code */ +#endif + .text:_isr : {} > FLASH /* ISR Code space */ + .cinit : {} > FLASH /* Initialization tables */ +#ifndef __LARGE_DATA_MODEL__ + .const : {} > FLASH /* Constant data */ +#else + .const : {} >> FLASH | FLASH2 /* Constant data */ +#endif + .bslsignature : {} > BSLSIGNATURE /* BSL Signature */ + .cio : {} > RAM /* C I/O Buffer */ + + .pinit : {} > FLASH /* C++ Constructor tables */ + .binit : {} > FLASH /* Boot-time Initialization tables */ + .init_array : {} > FLASH /* C++ Constructor tables */ + .mspabi.exidx : {} > FLASH /* C++ Constructor tables */ + .mspabi.extab : {} > FLASH /* C++ Constructor tables */ +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #ifndef __LARGE_CODE_MODEL__ + .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT) + #else + .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT) + #endif + #endif +#endif + + .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */ + .infoB : {} > INFOB + + /* MSP430 Interrupt vectors */ + .int00 : {} > INT00 + .int01 : {} > INT01 + .int02 : {} > INT02 + .int03 : {} > INT03 + .int04 : {} > INT04 + .int05 : {} > INT05 + .int06 : {} > INT06 + .int07 : {} > INT07 + .int08 : {} > INT08 + .int09 : {} > INT09 + .int10 : {} > INT10 + .int11 : {} > INT11 + .int12 : {} > INT12 + .int13 : {} > INT13 + DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT + DMA : { * ( .int15 ) } > INT15 type = VECT_INIT + BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT + PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT + USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT + USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT + PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT + TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT + TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT + ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT + USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT + USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT + WDT : { * ( .int26 ) } > INT26 type = VECT_INIT + COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT + TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT + TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT + NMI : { * ( .int30 ) } > INT30 type = VECT_INIT + .reset : {} > RESET /* MSP430 Reset vector */ +} + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +-l msp430fg4618.cmd + diff --git a/CPE325/Lab7_P2/main.c b/CPE325/Lab7_P2/main.c new file mode 100644 index 0000000..8a37c29 --- /dev/null +++ b/CPE325/Lab7_P2/main.c @@ -0,0 +1,58 @@ +#include + + +/** + * main.c + */ + +int freq[4] = {0, 128, 256, 512}; // off, 1KHz, 2 KHz, 4 Khz +int main(void) +{ + WDTCTL = WDT_ADLY_1000; // 1 s interval + _EINT(); // Enable interrupts + IE1 |= WDTIE; // Enable WDT interrupt + P2SEL |= BIT2; // P2.2 special function (TB0 output) + P2SEL &= ~BIT1; // Clear P2.1 + P2OUT &= ~(BIT1+BIT2); // Turn Off LED1 + TB0CTL = TBSSEL_1 + MC_1; // Upmode + P3SEL |= 0x20; // P3.5 as special function + P3DIR |= 0x20; // P3.5 as digital output + TB0CCTL4 = OUTMOD_4; // TB4 output is in toggle mode + TB0CCTL0 = freq[0]; + _BIS_SR(LPM3_bits + GIE); // Enter Low Power Mode 3 +} + + +// Watchdog Timer interrupt service routine +#pragma vector=WDT_VECTOR +__interrupt void watchdog_timer(void) +{ + static int i =0; + i++; + + if(i == 1){ + TB0CCTL0= freq[0]; // f = 4 MHz + P2OUT &=~ BIT1; // Turn on LED2 + P2OUT &= ~BIT2; // Turn Off LED1 + } + else if(i == 2){ + TB0CCTL0= freq[2]; // f = 2 MHz + P2OUT &= BIT1; // Turn on LED2 + P2OUT |= BIT2; // Turn Off LED1 + } + else if(i == 3){ + TB0CCTL0= freq[3]; // f = 4 MHz + P2OUT |= BIT1; // Turn on LED2 + P2OUT |= BIT2; // Turn Off LED1 + } + else if(i == 4){ + TB0CCTL0= freq[1]; // f = 4 MHz + P2OUT &=~ BIT1; // Turn on LED2 + P2OUT &= ~BIT2; // Turn Off LED1 + } + else if(i == 5){ + TB0CCTL0= freq[3]; // f = 4 MHz + P2OUT &=~ BIT1; // Turn on LED2 + P2OUT |= BIT2; // Turn Off LED1 + } +} diff --git a/CPE325/Lab7_P2/targetConfigs/MSP430FG4618.ccxml b/CPE325/Lab7_P2/targetConfigs/MSP430FG4618.ccxml new file mode 100644 index 0000000..ac89209 --- /dev/null +++ b/CPE325/Lab7_P2/targetConfigs/MSP430FG4618.ccxml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/CPE325/Lab7_P2/targetConfigs/readme.txt b/CPE325/Lab7_P2/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/CPE325/Lab7_P2/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/CPE348/.vscode/launch.json b/CPE348/.vscode/launch.json new file mode 100644 index 0000000..c13fbd7 --- /dev/null +++ b/CPE348/.vscode/launch.json @@ -0,0 +1,30 @@ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + { + "version": "0.2.0", + "configurations": [ + { + "name": "gcc - Build and debug active file", + "type": "cppdbg", + "request": "launch", + "program": "${fileDirname}/${fileBasenameNoExtension}", + "args": [], + "stopAtEntry": false, + "cwd": "${fileDirname}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ], + "preLaunchTask": "C/C++: g++ build active file", + "miDebuggerPath": "/usr/bin/gdb" + }, + ] + } + \ No newline at end of file diff --git a/CPE348/.vscode/settings.json b/CPE348/.vscode/settings.json new file mode 100644 index 0000000..ede20b4 --- /dev/null +++ b/CPE348/.vscode/settings.json @@ -0,0 +1,36 @@ +{ + "files.associations": { + "fstream": "cpp", + "cmath": "cpp", + "array": "cpp", + "*.tcc": "cpp", + "cctype": "cpp", + "clocale": "cpp", + "cstdarg": "cpp", + "cstdint": "cpp", + "cstdio": "cpp", + "cstdlib": "cpp", + "cwchar": "cpp", + "cwctype": "cpp", + "unordered_map": "cpp", + "vector": "cpp", + "exception": "cpp", + "functional": "cpp", + "initializer_list": "cpp", + "iosfwd": "cpp", + "iostream": "cpp", + "istream": "cpp", + "limits": "cpp", + "new": "cpp", + "ostream": "cpp", + "numeric": "cpp", + "sstream": "cpp", + "stdexcept": "cpp", + "streambuf": "cpp", + "tuple": "cpp", + "type_traits": "cpp", + "utility": "cpp", + "typeinfo": "cpp", + "iomanip": "cpp" + } +} \ No newline at end of file diff --git a/CPE348/.vscode/tasks.json b/CPE348/.vscode/tasks.json new file mode 100644 index 0000000..a471831 --- /dev/null +++ b/CPE348/.vscode/tasks.json @@ -0,0 +1,29 @@ +{ + "tasks": [ + { + "type": "cppbuild", + "label": "C/C++: g++ build active file", + "command": "/usr/bin/g++", + "args": [ + "-fdiagnostics-color=always", + "-g", + "-std=c++11", + "${file}", + "-o", + "${fileDirname}/${fileBasenameNoExtension}" + ], + "options": { + "cwd": "${fileDirname}" + }, + "problemMatcher": [ + "$gcc" + ], + "group": { + "kind": "build", + "isDefault": true + }, + "detail": "Task generated by Debugger." + } + ], + "version": "2.0.0" +} \ No newline at end of file diff --git a/CPE348/ExponentialBackoff.jpg b/CPE348/ExponentialBackoff.jpg new file mode 100644 index 0000000..c492786 Binary files /dev/null and b/CPE348/ExponentialBackoff.jpg differ diff --git a/CPE348/HW4/HW4.code-workspace b/CPE348/HW4/HW4.code-workspace new file mode 100644 index 0000000..70bc36b --- /dev/null +++ b/CPE348/HW4/HW4.code-workspace @@ -0,0 +1,43 @@ +{ + "folders": [ + { + "path": ".." + } + ], + "settings": { + "files.associations": { + "fstream": "cpp", + "cmath": "cpp", + "array": "cpp", + "*.tcc": "cpp", + "cctype": "cpp", + "clocale": "cpp", + "cstdarg": "cpp", + "cstdint": "cpp", + "cstdio": "cpp", + "cstdlib": "cpp", + "cwchar": "cpp", + "cwctype": "cpp", + "unordered_map": "cpp", + "vector": "cpp", + "exception": "cpp", + "functional": "cpp", + "initializer_list": "cpp", + "iosfwd": "cpp", + "iostream": "cpp", + "istream": "cpp", + "limits": "cpp", + "new": "cpp", + "ostream": "cpp", + "numeric": "cpp", + "sstream": "cpp", + "stdexcept": "cpp", + "streambuf": "cpp", + "tuple": "cpp", + "type_traits": "cpp", + "utility": "cpp", + "typeinfo": "cpp", + "iomanip": "cpp" + } + } +} \ No newline at end of file diff --git a/CPE348/HW4/P3A.txt b/CPE348/HW4/P3A.txt new file mode 100644 index 0000000..5f8dc25 --- /dev/null +++ b/CPE348/HW4/P3A.txt @@ -0,0 +1,21 @@ +Iteration # SampleRTT EstimatedRTT Deviation Difference Timeout +0 - 4.0000 0.5000 - - +1 1.0000 3.6250 0.8125 -3.0000 6.8750 +2 1.0000 3.2969 1.0391 -2.6250 7.4531 +3 1.0000 3.0098 1.1963 -2.2969 7.7949 +4 1.0000 2.7585 1.2980 -2.0098 7.9504 +5 1.0000 2.5387 1.3555 -1.7585 7.9609 +6 1.0000 2.3464 1.3784 -1.5387 7.8602 +7 1.0000 2.1781 1.3744 -1.3464 7.6758 +8 1.0000 2.0308 1.3499 -1.1781 7.4304 +9 1.0000 1.9020 1.3100 -1.0308 7.1420 +10 1.0000 1.7892 1.2590 -0.9020 6.8252 +11 1.0000 1.6906 1.2003 -0.7892 6.4917 +12 1.0000 1.6043 1.1366 -0.6906 6.1505 +13 1.0000 1.5287 1.0700 -0.6043 5.8088 +14 1.0000 1.4626 1.0024 -0.5287 5.4721 +15 1.0000 1.4048 0.9349 -0.4626 5.1444 +16 1.0000 1.3542 0.8686 -0.4048 4.8287 +17 1.0000 1.3099 0.8043 -0.3542 4.5273 +18 1.0000 1.2712 0.7425 -0.3099 4.2413 +19 1.0000 1.2373 0.6836 -0.2712 3.9717 diff --git a/CPE348/HW4/P3B.txt b/CPE348/HW4/P3B.txt new file mode 100644 index 0000000..e212337 --- /dev/null +++ b/CPE348/HW4/P3B.txt @@ -0,0 +1,22 @@ +Iteration # SampleRTT EstimatedRTT Deviation Difference Timeout +0 - 4.0000 1.5000 - - +1 1.0000 3.6250 1.6875 -3.0000 10.3750 +2 1.0000 3.2969 1.8047 -2.6250 10.5156 +3 1.0000 3.0098 1.8662 -2.2969 10.4746 +4 1.0000 2.7585 1.8842 -2.0098 10.2952 +5 1.0000 2.5387 1.8685 -1.7585 10.0125 +6 1.0000 2.3464 1.8272 -1.5387 9.6553 +7 1.0000 2.1781 1.7671 -1.3464 9.2466 +8 1.0000 2.0308 1.6935 -1.1781 8.8048 +9 1.0000 1.9020 1.6107 -1.0308 8.3446 +10 1.0000 1.7892 1.5221 -0.9020 7.8775 +11 1.0000 1.6906 1.4305 -0.7892 7.4125 +12 1.0000 1.6043 1.3380 -0.6906 6.9562 +13 1.0000 1.5287 1.2463 -0.6043 6.5138 +14 1.0000 1.4626 1.1566 -0.5287 6.0889 +15 1.0000 1.4048 1.0698 -0.4626 5.6841 +16 1.0000 1.3542 0.9867 -0.4048 5.3010 +17 1.0000 1.3099 0.9076 -0.3542 4.9405 +18 1.0000 1.2712 0.8329 -0.3099 4.6029 +19 1.0000 1.2373 0.7627 -0.2712 4.2881 +20 1.0000 1.2076 0.6970 -0.2373 3.9958 diff --git a/CPE348/HW4/P3C.txt b/CPE348/HW4/P3C.txt new file mode 100644 index 0000000..1ee1dc4 --- /dev/null +++ b/CPE348/HW4/P3C.txt @@ -0,0 +1,12 @@ +Iteration # SampleRTT EstimatedRTT Deviation Difference Timeout +0 - 4.0000 0.5000 - - +1 1.0000 3.2500 1.1250 -3.0000 7.7500 +2 1.0000 2.6875 1.4062 -2.2500 8.3125 +3 1.0000 2.2656 1.4766 -1.6875 8.1719 +4 1.0000 1.9492 1.4238 -1.2656 7.6445 +5 1.0000 1.7119 1.3052 -0.9492 6.9326 +6 1.0000 1.5339 1.1569 -0.7119 6.1614 +7 1.0000 1.4005 1.0011 -0.5339 5.4050 +8 1.0000 1.3003 0.8510 -0.4005 4.7042 +9 1.0000 1.2253 0.7133 -0.3003 4.0785 +10 1.0000 1.1689 0.5913 -0.2253 3.5341 diff --git a/CPE348/HW4/P4A.txt b/CPE348/HW4/P4A.txt new file mode 100644 index 0000000..9781598 --- /dev/null +++ b/CPE348/HW4/P4A.txt @@ -0,0 +1,31 @@ +Iteration # SampleRTT EstimatedRTT TimeOut +1 1.0000 1.2500 2.5000 +2 1.0000 1.1250 2.2500 +3 1.0000 1.0625 2.1250 +4 1.0000 1.0312 2.0625 +5 1.0000 1.0156 2.0312 +6 5.0000 3.0078 6.0156 +7 1.0000 2.0039 4.0078 +8 1.0000 1.5020 3.0039 +9 1.0000 1.2510 2.5020 +10 1.0000 1.1255 2.2510 +11 1.0000 1.0627 2.1255 +12 5.0000 3.0314 6.0627 +13 1.0000 2.0157 4.0314 +14 1.0000 1.5078 3.0157 +15 1.0000 1.2539 2.5078 +16 1.0000 1.1270 2.2539 +17 1.0000 1.0635 2.1270 +18 5.0000 3.0317 6.0635 +19 1.0000 2.0159 4.0317 +20 1.0000 1.5079 3.0159 +21 1.0000 1.2540 2.5079 +22 1.0000 1.1270 2.2540 +23 1.0000 1.0635 2.1270 +24 5.0000 3.0317 6.0635 +25 1.0000 2.0159 4.0317 +26 1.0000 1.5079 3.0159 +27 1.0000 1.2540 2.5079 +28 1.0000 1.1270 2.2540 +29 1.0000 1.0635 2.1270 +30 5.0000 3.0317 6.0635 diff --git a/CPE348/HW4/P4B.txt b/CPE348/HW4/P4B.txt new file mode 100644 index 0000000..9de4d7e --- /dev/null +++ b/CPE348/HW4/P4B.txt @@ -0,0 +1,31 @@ +Iteration # SampleRTT EstimatedRTT TimeOut +1 1.0000 1.4000 2.8000 +2 1.0000 1.3200 2.6400 +3 1.0000 1.2560 2.5120 +4 1.0000 1.2048 2.4096 +5 1.0000 1.1638 2.3277 +6 5.0000 1.9311 3.8621 +7 1.0000 1.7449 3.4897 +8 1.0000 1.5959 3.1918 +9 1.0000 1.4767 2.9534 +10 1.0000 1.3814 2.7627 +11 1.0000 1.3051 2.6102 +12 5.0000 2.0441 4.0882 +13 1.0000 1.8353 3.6705 +14 1.0000 1.6682 3.3364 +15 1.0000 1.5346 3.0691 +16 1.0000 1.4277 2.8553 +17 1.0000 1.3421 2.6842 +18 5.0000 2.0737 4.1474 +19 1.0000 1.8590 3.7179 +20 1.0000 1.6872 3.3743 +21 1.0000 1.5497 3.0995 +22 1.0000 1.4398 2.8796 +23 1.0000 1.3518 2.7037 +24 5.0000 2.0815 4.1629 +25 1.0000 1.8652 3.7303 +26 1.0000 1.6921 3.3843 +27 1.0000 1.5537 3.1074 +28 1.0000 1.4430 2.8859 +29 1.0000 1.3544 2.7087 +30 5.0000 2.0835 4.1670 diff --git a/CPE348/HW4/P4C.txt b/CPE348/HW4/P4C.txt new file mode 100644 index 0000000..88ba029 --- /dev/null +++ b/CPE348/HW4/P4C.txt @@ -0,0 +1,31 @@ +Iteration # SampleRTT EstimatedRTT TimeOut +1 1.0000 1.4500 2.9000 +2 1.0000 1.4050 2.8100 +3 1.0000 1.3645 2.7290 +4 1.0000 1.3280 2.6561 +5 1.0000 1.2952 2.5905 +6 5.0000 1.6657 3.3314 +7 1.0000 1.5991 3.1983 +8 1.0000 1.5392 3.0785 +9 1.0000 1.4853 2.9706 +10 1.0000 1.4368 2.8736 +11 1.0000 1.3931 2.7862 +12 5.0000 1.7538 3.5076 +13 1.0000 1.6784 3.3568 +14 1.0000 1.6106 3.2211 +15 1.0000 1.5495 3.0990 +16 1.0000 1.4946 2.9891 +17 1.0000 1.4451 2.8902 +18 5.0000 1.8006 3.6012 +19 1.0000 1.7205 3.4411 +20 1.0000 1.6485 3.2970 +21 1.0000 1.5836 3.1673 +22 1.0000 1.5253 3.0505 +23 1.0000 1.4727 2.9455 +24 5.0000 1.8255 3.6509 +25 1.0000 1.7429 3.4858 +26 1.0000 1.6686 3.3373 +27 1.0000 1.6018 3.2035 +28 1.0000 1.5416 3.0832 +29 1.0000 1.4874 2.9749 +30 5.0000 1.8387 3.6774 diff --git a/CPE348/HW4/p3 b/CPE348/HW4/p3 new file mode 100755 index 0000000..59bcff5 Binary files /dev/null and b/CPE348/HW4/p3 differ diff --git a/CPE348/HW4/p3-back b/CPE348/HW4/p3-back new file mode 100755 index 0000000..6b0a22a Binary files /dev/null and b/CPE348/HW4/p3-back differ diff --git a/CPE348/HW4/p3-back.cpp b/CPE348/HW4/p3-back.cpp new file mode 100644 index 0000000..c10976e --- /dev/null +++ b/CPE348/HW4/p3-back.cpp @@ -0,0 +1,64 @@ +#include +#include +#include +#include + +#define MAX_ARRAY_SIZE 1000 + +using namespace std; + +void calculations(float deltaVal, float deviationVal, string outputFileName); + +int main(int argc, char const *argv[]) +{ + // calculate part a + calculations(0.125, 0.500, "P3A.txt"); + calculations(0.125, 1.500, "P3B.txt"); + calculations(0.25, 0.500, "P3C.txt"); + +} + +void calculations(float deltaVal, float deviationVal, string outputFileName) +{ + ofstream outputFile; + outputFile.open(outputFileName.c_str()); + // difference = sampleRTT - estimatedRTT + // estimatedRTT = estimatedRTT + (delta * difference) + // deviation = deviation + delta(|difference| - deviation) + // timeOut = mu * estimatedRTT + (phi * deviation) + + float delta = 0.0, mu = 0.0, phi = 0.0; // + float difference[MAX_ARRAY_SIZE], estimatedRTT[MAX_ARRAY_SIZE], sampleRTT; + float deviation[MAX_ARRAY_SIZE], timeOut = 0.0, tmpDeviation = 0.0, tmpestimateRTT = 0.0; + // Values for Jacobson/Karels Algorithim + delta = deltaVal; + mu = 1.0; + phi = 4.0; + + // do-while loop + int i = 0; + outputFile << "Iteration #\t\tSampleRTT\t\tEstimatedRTT\t\t Deviation\t\tDifference\t\tTimeout\n"; + do + { + // initial values + if (i == 0) + { + outputFile << fixed << setprecision(4); + estimatedRTT[0] = 4.000; + deviation[0] = deviationVal; + outputFile << i << "\t\t\t\t - \t\t\t\t\t" << estimatedRTT[0] << "\t\t\t\t" << deviation[0] << "\t\t\t - \t\t\t - \n"; + i++; + } + sampleRTT = 1.0000; + difference[i] = sampleRTT - estimatedRTT[i-1]; + // calculate estimatedRTT again + estimatedRTT[i] = estimatedRTT[i-1] + (delta * difference[i]); + deviation[i] = deviation[i-1] + delta*(fabs(difference[i]) - deviation[i-1]); + timeOut = mu * estimatedRTT[i] + (phi * deviation[i]); + // "Iteration #\t\tSampleRTT\t\tEstimatedRTT\t\tDeviation\t\tTimeout\n" + outputFile << i << "\t\t\t\t" << setw(5) << setfill(' ') << sampleRTT << setw(10) << setfill(' ') << "\t\t" << estimatedRTT[i] << setw(8) << setfill(' ') << + "\t\t" << deviation[i] << setw(3) << setfill(' ') << "\t\t" << difference[i] << setw(8) << setfill(' ') << "\t" << timeOut << endl; + i++; + } while (timeOut > 4.0); + outputFile.close(); +} \ No newline at end of file diff --git a/CPE348/HW4/p3.cpp b/CPE348/HW4/p3.cpp new file mode 100644 index 0000000..729c41f --- /dev/null +++ b/CPE348/HW4/p3.cpp @@ -0,0 +1,63 @@ +#include +#include +#include +#include + +#define MAX_ARRAY_SIZE 1000 + +using namespace std; + +void calculations(float deltaVal, float deviationVal, string outputFileName); + +int main(int argc, char const *argv[]) +{ + // calculate part a + calculations(0.125, 0.500, "P3A.txt"); + calculations(0.125, 1.500, "P3B.txt"); + calculations(0.25, 0.500, "P3C.txt"); + +} + +void calculations(float deltaVal, float deviationVal, string outputFileName) +{ + ofstream outputFile; + outputFile.open(outputFileName.c_str()); + // difference = sampleRTT - estimatedRTT + // estimatedRTT = estimatedRTT + (delta * difference) + // deviation = deviation + delta(|difference| - deviation) + // timeOut = mu * estimatedRTT + (phi * deviation) + + float delta = 0.0, mu = 0.0, phi = 0.0; // + float difference = 0.0, estimatedRTT = 0.0, sampleRTT = 0.0; + float deviation = 0.0, timeOut = 0.0, tmpDeviation = 0.0, tmpestimateRTT = 0.0; + // Values for Jacobson/Karels Algorithim + delta = deltaVal; + mu = 1.0; + phi = 4.0; + + // do-while loop + int i = 0; + outputFile << "Iteration #\t\tSampleRTT\t\tEstimatedRTT\t\t Deviation\t\tDifference\t\tTimeout\n"; + do + { + // initial values + if (i == 0) + { + outputFile << fixed << setprecision(4); + estimatedRTT = 4.000; + deviation = deviationVal; + outputFile << i << "\t\t\t\t - \t\t\t\t\t" << estimatedRTT << "\t\t\t\t" << deviation << "\t\t\t - \t\t\t - \n"; + i++; + } + sampleRTT = 1.0000; + difference = sampleRTT - estimatedRTT; + // calculate estimatedRTT again + estimatedRTT = estimatedRTT + (delta * difference); + deviation = deviation + delta*(fabs(difference) - deviation); + timeOut = mu * estimatedRTT + (phi * deviation); + outputFile << i << "\t\t\t\t" << setw(5) << setfill(' ') << sampleRTT << setw(10) << setfill(' ') << "\t\t" << estimatedRTT << setw(8) << setfill(' ') << + "\t\t" << deviation << setw(3) << setfill(' ') << "\t\t" << difference << setw(8) << setfill(' ') << "\t" << timeOut << endl; + i++; + } while (timeOut > 4.0); + outputFile.close(); +} \ No newline at end of file diff --git a/CPE348/HW4/p4 b/CPE348/HW4/p4 new file mode 100755 index 0000000..ab197d2 Binary files /dev/null and b/CPE348/HW4/p4 differ diff --git a/CPE348/HW4/p4.cpp b/CPE348/HW4/p4.cpp new file mode 100644 index 0000000..25796c1 --- /dev/null +++ b/CPE348/HW4/p4.cpp @@ -0,0 +1,42 @@ +#include +#include +#include +#include + +using namespace std; + +void calculations(float alphaVal, string outputFileName); + +int main(int argc, char const *argv[]) +{ + // calculate part a + calculations(0.5, "P4A.txt"); + calculations(0.8, "P4B.txt"); + calculations(0.9, "P4C.txt"); + +} + +void calculations(float alphaVal, string outputFileName) +{ + ofstream outputFile; + outputFile.open(outputFileName.c_str()); + float alpha = alphaVal; + outputFile << fixed << setprecision(4); + float estimatedRTT = 1.50, sampleRTT = 0.0; + float timeOut = 0.0; + outputFile << "Iteration #\t\tSampleRTT\t\tEstimatedRTT\t\tTimeOut\n"; + for (int i = 1; i < 31; i++) + { + if((i % 6)==0) + { + sampleRTT = 5.0; + } + else sampleRTT = 1.0; + estimatedRTT = alpha * estimatedRTT + (1 - alpha) * sampleRTT; + timeOut = 2 * estimatedRTT; + outputFile << i << "\t\t\t\t" << setw(5) << setfill(' ') << sampleRTT << setw(10) << setfill(' ') + << "\t\t" << estimatedRTT << setw(16) << setfill(' ') << timeOut << endl; + } + + outputFile.close(); +} \ No newline at end of file diff --git a/CPE348/HW4/test.cpp b/CPE348/HW4/test.cpp new file mode 100644 index 0000000..15ad953 --- /dev/null +++ b/CPE348/HW4/test.cpp @@ -0,0 +1,8 @@ +const char* byteToBitString (value) { + char output[9]; + output[8] = 0; + for (int i = 0; i < 8; ++i) { + output[7 - i] = (value & (1 << i)) ? '1' : '0'; + } + return output; +} \ No newline at end of file diff --git a/CPE348/IP Checksum.pdf b/CPE348/IP Checksum.pdf new file mode 100644 index 0000000..e2a64de Binary files /dev/null and b/CPE348/IP Checksum.pdf differ diff --git a/CPE348/IP Checksum.xlsm b/CPE348/IP Checksum.xlsm new file mode 100644 index 0000000..9c84a81 Binary files /dev/null and b/CPE348/IP Checksum.xlsm differ diff --git a/CPE348/IP Checksum.xlsx b/CPE348/IP Checksum.xlsx new file mode 100644 index 0000000..eea3649 Binary files /dev/null and b/CPE348/IP Checksum.xlsx differ diff --git a/CPE348/Project2/.vscode/launch.json b/CPE348/Project2/.vscode/launch.json new file mode 100644 index 0000000..1bb985a --- /dev/null +++ b/CPE348/Project2/.vscode/launch.json @@ -0,0 +1,34 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "g++ - Build and debug active file", + "type": "cppdbg", + "request": "launch", + "program": "${fileDirname}/${fileBasenameNoExtension}", + "args": [], + "stopAtEntry": false, + "cwd": "${fileDirname}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + }, + { + "description": "Set Disassembly Flavor to Intel", + "text": "-gdb-set disassembly-flavor intel", + "ignoreFailures": true + } + ], + "preLaunchTask": "C/C++: g++ build active file", + "miDebuggerPath": "/usr/bin/gdb" + } + ] +} \ No newline at end of file diff --git a/CPE348/Project2/.vscode/tasks.json b/CPE348/Project2/.vscode/tasks.json new file mode 100644 index 0000000..a471831 --- /dev/null +++ b/CPE348/Project2/.vscode/tasks.json @@ -0,0 +1,29 @@ +{ + "tasks": [ + { + "type": "cppbuild", + "label": "C/C++: g++ build active file", + "command": "/usr/bin/g++", + "args": [ + "-fdiagnostics-color=always", + "-g", + "-std=c++11", + "${file}", + "-o", + "${fileDirname}/${fileBasenameNoExtension}" + ], + "options": { + "cwd": "${fileDirname}" + }, + "problemMatcher": [ + "$gcc" + ], + "group": { + "kind": "build", + "isDefault": true + }, + "detail": "Task generated by Debugger." + } + ], + "version": "2.0.0" +} \ No newline at end of file diff --git a/CPE348/Project2/ExponentialBackoff.jpg b/CPE348/Project2/ExponentialBackoff.jpg new file mode 100644 index 0000000..3211b2b Binary files /dev/null and b/CPE348/Project2/ExponentialBackoff.jpg differ diff --git a/CPE348/Project2/Project2_part1_rn.txt b/CPE348/Project2/Project2_part1_rn.txt new file mode 100644 index 0000000..bca638b --- /dev/null +++ b/CPE348/Project2/Project2_part1_rn.txt @@ -0,0 +1,200 @@ +16482 +28905 +26183 +22666 +9664 +26342 +1587 +12704 +4094 +23596 +9459 +3914 +29436 +12112 +14330 +1337 +3107 +31257 +15633 +29246 +25721 +26178 +20807 +20408 +19472 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+9500 +9762 +478 +3913 +1100 +12008 +32163 +8179 +15032 +30478 +15352 +17807 +23017 +5160 +14847 +16964 +22019 +10170 +30275 +19251 +11880 +11958 +10471 +30650 +21152 +3723 diff --git a/CPE348/Project2/Project_2.doc b/CPE348/Project2/Project_2.doc new file mode 100644 index 0000000..34e7e92 Binary files /dev/null and b/CPE348/Project2/Project_2.doc differ diff --git a/CPE348/Project2/Project_2.pdf b/CPE348/Project2/Project_2.pdf new file mode 100644 index 0000000..083d44f Binary files /dev/null and b/CPE348/Project2/Project_2.pdf differ diff --git a/CPE348/Project2/output.txt b/CPE348/Project2/output.txt new file mode 100644 index 0000000..c496cf7 Binary files /dev/null and b/CPE348/Project2/output.txt differ diff --git a/CPE348/Project2/project2Pt1a b/CPE348/Project2/project2Pt1a new file mode 100755 index 0000000..f385d2f Binary files /dev/null and b/CPE348/Project2/project2Pt1a differ diff --git a/CPE348/Project2/project2Pt1a.cpp b/CPE348/Project2/project2Pt1a.cpp new file mode 100644 index 0000000..8b85496 --- /dev/null +++ b/CPE348/Project2/project2Pt1a.cpp @@ -0,0 +1,405 @@ +#include +#include +#include +#include +#include +#include + + +#define MAX_COLLISIONS 10 +#define MAX_STATIONS 6 + +using namespace std; +struct timeSlot { + int timeOfTransmission; // time slot + int totalCollisions; + // stations A; + bool collided, transmitted; +}; + +struct stations { + int arrivalTimeSlot; // time slot + int collisions; + int backoff; + timeSlot A; +}; + +// function that generates the +// range of backoff slots +//int rangeOfBackoff(int k); + +std::random_device rand_dev; + std::mt19937 generator(rand_dev()); + //std::uniform_int_distribution distr(0, k); +int rangeOfBackoff(); +int array[200]; +int arrayIndex; +int main() +{ + bool didNotCollide, end; + int collisionArray[MAX_COLLISIONS]; + int timeArray[MAX_COLLISIONS]; + + int k; + // file with numbers + string file = "Project2_part1_rn.txt"; + ifstream inputFile; + inputFile.open(file.c_str()); + bool transmitted; + + int timeIndex = 0; + int modOperand; + struct stations st[6]; + int timeSlot=0, numFromFile; + const int timeInterval = 512; // time interval in micro seconds + + // strings for precise code + string check="Checking time slot: "; + string collisionsStr = " collisions: "; + string backing = ": backing off to slot "; + string dashes = "--------------------------------------------------\n"; + string stationStr = "\tStation "; + // define variables + int n, totalCollisions,i; + struct timeSlot t[MAX_COLLISIONS]; + + + //int modOperand = pow(2,st[i].collisions); + + // k * timeInterval + // begining at t = 0, all stations collide + + while (timeSlot < 10) + { + if (timeSlot==0) + { + cout << dashes << check << timeSlot << endl; + for (int i = 0; i < MAX_STATIONS; i++) + { + t[i].totalCollisions++; + t[i].timeOfTransmission = i; + st[i].arrivalTimeSlot=0; // Arrival Time slot + //k= pow(2,st[i].collisions); + st[i].collisions = 1; + k=1; + uniform_int_distribution distr(0, k); + int o = distr(generator); + st[i].backoff = o; + if (o==0) + { + st[i].arrivalTimeSlot=1; + t[i].timeOfTransmission=1; + timeArray[1]++; + } + else + { + timeArray[2]++; + st[i].arrivalTimeSlot = 2; + } + cout << "\tStation " << i << backing << st[i].arrivalTimeSlot << collisionsStr << st[i].collisions << endl; + } + + cout << dashes << endl; + timeSlot++; + + } + else + { + for (int comp = 0; comp < 6; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + // timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>=timeSlot){ + //cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + //cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + + + } + for (int i = 0; i < MAX_COLLISIONS; i++) + { + //cout << dashes << check << timeSlot << endl; + for (int stationCount = 0; stationCount < MAX_STATIONS; stationCount++) + { + t[stationCount].transmitted=true; + if (stationCount==0) + { + for (int comp = 0; comp < 6; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + //timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>timeSlot){ + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + + + } + for (int i = 0; i < 6; i++) + { + // cout << "TimeArray\t"<> numFromFile; + //array[arrayIndex] = numFromFile; + //arrayIndex++; + modOperand = pow(2,st[stationCount].collisions); + modOperand--; + k = numFromFile % modOperand; + uniform_int_distribution distr(0, k); + int o = distr(generator); + st[stationCount].backoff = o; + st[stationCount].arrivalTimeSlot = st[stationCount].arrivalTimeSlot+st[stationCount].backoff; + timeArray[st[stationCount].arrivalTimeSlot]++; + if (timeArray[st[stationCount].arrivalTimeSlot]>1) + { + t[st[stationCount].arrivalTimeSlot].collided=false; + + } + + cout << "\tStation " << stationCount << backing << st[stationCount].arrivalTimeSlot << collisionsStr << st[stationCount].collisions << endl; + } + else if (t[timeSlot].totalCollisions==1 && t[timeSlot].transmitted && st[stationCount].arrivalTimeSlot==timeSlot) + { + //t[timeSlot].transmitted=true; + cout << stationStr << stationCount << " Success! " << endl << dashes << endl; + cout << "End of program\n"; + end = true; + } + else //if (st[stationCount].arrivalTimeSlot != timeSlot && t[timeSlot].totalCollisions<1 && !t[timeSlot].transmitted) + { + if (timeArray[timeSlot]==0) + { + if(stationCount==5) + cout << " NO ATTEMPTS\n"; + } + } + + + if (end) break; + + + + + + if(stationCount==5) + { + cout << dashes << endl; + // if (t[timeSlot].totalCollisions==0) + // { + // cout << " NO ATTEMPTS\n"; + // } + + timeSlot++; + for (int comp = 0; comp < 6; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + //timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if ((t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>=timeSlot) && t[st[comp].arrivalTimeSlot].totalCollisions>1) + { + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + + + } + } + + + } + if (end) break; + + /* if (t[timeSlot].totalCollisions<2 && t[timeSlot].) + // { + cout << dashes << check << timeSlot << endl << stationStr << stationCount << " Success! " << endl + << dashes; + } */ + // if(transmitted==true) cout << dashes << endl; + + } + //timeSlot++; + if (timeSlot==9) + { + break; + } + if (end) break; + } + if (end) break; + + } +} + + + +int rangeOfBackoff() +{ +} \ No newline at end of file diff --git a/CPE348/Project2/project2Pt1a.cpp.bak b/CPE348/Project2/project2Pt1a.cpp.bak new file mode 100644 index 0000000..aa5094e --- /dev/null +++ b/CPE348/Project2/project2Pt1a.cpp.bak @@ -0,0 +1,421 @@ +#include +#include +#include +#include +#include +#include +#include + + +#define MAX_COLLISIONS 9 +#define MAX_STATIONS 6 + +using namespace std; +struct timeSlot { + int timeOfTransmission; // time slot + int totalCollisions; + // stations A; + bool collided, transmitted; +}; + +struct stations { + int arrivalTimeSlot; // time slot + int collisions; + int backoff; + timeSlot A; +}; + +bool areSame(int a[],int n) +{ + unordered_map m;//hash map to store the frequency of every + //element + + for(int i=0;i distr(0, k); +int rangeOfBackoff(); +int array[200]; +int arrayIndex; +int main() +{ + bool didNotCollide, end; + int collisionArray[MAX_COLLISIONS]; + int timeArray[MAX_COLLISIONS]; + + int k; + // file with numbers + string file = "Project2_part1_rn.txt"; + ifstream inputFile; + inputFile.open(file.c_str()); + // while (inputFile) //Read in array + // { + // if (inputFile.eof()) + // { + // break; + // } + + // for (int i = 0; i < 200; i++) + // { + // inputFile >> array[i]; + // } + // } + + int timeIndex = 0; + int modOperand; + struct stations st[6]; + int timeSlot=0, numFromFile; + const int timeInterval = 512; // time interval in micro seconds + + // strings for precise code + string check="Checking time slot: "; + string collisionsStr = " collisions: "; + string backing = ": backing off to slot "; + string dashes = "--------------------------------------------------\n"; + string stationStr = "\tStation "; + // define variables + int n, totalCollisions,i; + struct timeSlot t[MAX_COLLISIONS]; + + + //int modOperand = pow(2,st[i].collisions); + + // k * timeInterval + // begining at t = 0, all stations collide + + while (timeSlot < 10) + { + if (timeSlot==0) + { + cout << dashes << check << timeSlot << endl; + for (int i = 0; i < MAX_STATIONS; i++) + { + t[i].totalCollisions++; + t[i].timeOfTransmission = i; + st[i].arrivalTimeSlot=0; // Arrival Time slot + //k= pow(2,st[i].collisions); + st[i].collisions = 1; + k=1; + uniform_int_distribution distr(0, k); + int o = distr(generator); + st[i].backoff = o; + if (o==0) + { + st[i].arrivalTimeSlot=1; + t[i].timeOfTransmission=1; + } + else st[i].arrivalTimeSlot = 2; + + cout << "\tStation " << i << backing << st[i].arrivalTimeSlot << collisionsStr << st[i].collisions << endl; + } + + cout << dashes << endl; + timeSlot++; + + } + else + { + for (int comp = 0; comp < 6; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + // timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>=timeSlot){ + //cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + //cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + + + } + for (int i = 0; i < MAX_COLLISIONS; i++) + { + //cout << dashes << check << timeSlot << endl; + for (int stationCount = 0; stationCount < MAX_STATIONS; stationCount++) + { + t[stationCount].transmitted=true; + if (stationCount==0) + { + for (int comp = 0; comp < 6; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + //timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>timeSlot){ + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + + + } + for (int i = 0; i < 6; i++) + { + // cout << "TimeArray\t"<> numFromFile; + //array[arrayIndex] = numFromFile; + //arrayIndex++; + modOperand = pow(2,st[stationCount].collisions); + modOperand--; + k = numFromFile % modOperand; + uniform_int_distribution distr(0, k); + int o = distr(generator); + st[stationCount].backoff = o; + st[stationCount].arrivalTimeSlot = st[stationCount].arrivalTimeSlot+st[stationCount].backoff; + timeArray[st[stationCount].arrivalTimeSlot]++; + if (timeArray[st[stationCount].arrivalTimeSlot]>1) + { + t[st[stationCount].arrivalTimeSlot].collided=false; + + } + + cout << "\tStation " << stationCount << backing << st[stationCount].arrivalTimeSlot << collisionsStr << st[stationCount].collisions << endl; + } + else if (t[timeSlot].totalCollisions==1 && t[timeSlot].transmitted && st[stationCount].arrivalTimeSlot==timeSlot) + { + //t[timeSlot].transmitted=true; + cout << stationStr << stationCount << " Success! " << endl << dashes << endl; + cout << "End of program\n"; + end = true; + } + else //if (st[stationCount].arrivalTimeSlot != timeSlot && t[timeSlot].totalCollisions<1 && !t[timeSlot].transmitted) + { + if (t[timeSlot].totalCollisions==0) + { + if(stationCount==5) + cout << " NO ATTEMPTS\n"; + } + } + + + if (end) break; + + + + + + if(stationCount==5) + { + if (t[timeSlot].totalCollisions==0) + { + cout << " NO ATTEMPTS\n"; + } + + timeSlot++; + for (int comp = 0; comp < 6; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + //timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if ((t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>=timeSlot) && t[st[comp].arrivalTimeSlot].totalCollisions>1) + { + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + + + } + cout << dashes << endl; + } + + + } + if (end) break; + + /* if (t[timeSlot].totalCollisions<2 && t[timeSlot].) + // { + cout << dashes << check << timeSlot << endl << stationStr << stationCount << " Success! " << endl + << dashes; + } */ + } + //timeSlot++; + if (timeSlot==9) + { + break; + } + if (end) break; + } + if (end) break; + + } +} + + + +int rangeOfBackoff() +{ +} \ No newline at end of file diff --git a/CPE348/Project2/project2Pt1b b/CPE348/Project2/project2Pt1b new file mode 100755 index 0000000..4686fe7 Binary files /dev/null and b/CPE348/Project2/project2Pt1b differ diff --git a/CPE348/Project2/project2Pt1b.cpp b/CPE348/Project2/project2Pt1b.cpp new file mode 100644 index 0000000..7fec5fe --- /dev/null +++ b/CPE348/Project2/project2Pt1b.cpp @@ -0,0 +1,229 @@ +#include +#include +#include +#include +#include +#include + + +#define MAX_COLLISIONS 100000 +#define MAX_STATIONS 6 + +using namespace std; +struct timeSlot { + int timeOfTransmission; // time slot + int totalCollisions; + // stations A; + bool collided, transmitted; +}; + +struct stations { + int arrivalTimeSlot; // time slot + int collisions; + int backoff; + timeSlot A; +}; + +// function that generates the +// range of backoff slots +//int rangeOfBackoff(int k); + +std::random_device rand_dev; + std::mt19937 generator(rand_dev()); + //std::uniform_int_distribution distr(0, k); +int main() +{ + bool didNotCollide, end; + int collisionArray[MAX_COLLISIONS]; + int timeArray[MAX_COLLISIONS]; + int transmissions =0; + int k = 0; + // file with numbers + string file = "Project2_part1_rn.txt"; + ifstream inputFile; + inputFile.open(file.c_str()); + bool transmitted; + + int timeIndex = 0; + int modOperand; + struct stations st[6]; + int timeSlot=0, numFromFile; + const int timeInterval = 512; // time interval in micro seconds + + // strings for precise code + string check="Checking time slot: "; + string collisionsStr = " collisions: "; + string backing = ": backing off to slot "; + string dashes = "--------------------------------------------------\n"; + string stationStr = "\tStation "; + // define variables + int n, totalCollisions,i; + struct timeSlot t[MAX_COLLISIONS]; + + + //int modOperand = pow(2,st[i].collisions); + + // k * timeInterval + // begining at t = 0, all stations collide + + while (timeSlot < MAX_COLLISIONS) + { + if (timeSlot==0) + { + + cout << dashes << check << timeSlot << endl; + // add total collisions to station time + for (int i = 0; i < MAX_STATIONS; i++) + { + t[i].totalCollisions++; + t[i].timeOfTransmission = i; + st[i].arrivalTimeSlot=0; // Arrival Time slot + //k= pow(2,st[i].collisions); + st[i].collisions = 1; + k=1; + uniform_int_distribution distr(0, k); + int o = distr(generator); + st[i].backoff = o; + if (o==0) + { + + st[i].arrivalTimeSlot=1; + t[i].timeOfTransmission=1; + timeArray[1]++; + } + else + { + //t[2].totalCollisions++; + timeArray[2]++; + st[i].arrivalTimeSlot = 2; + } + cout << "\tStation " << i << backing << st[i].arrivalTimeSlot << collisionsStr << st[i].collisions << endl; + t[st[i].arrivalTimeSlot].totalCollisions++; + } + + cout << dashes << endl; + timeSlot++; + + } + else + { + for (int i = 0; i < MAX_COLLISIONS; i++) + { + //cout << dashes << check << timeSlot << endl; + for (int stationCount = 0; stationCount < MAX_STATIONS; stationCount++) + { + t[stationCount].transmitted=true; + if (stationCount==0) + { + cout << dashes << check << timeSlot << endl; + } + transmitted==false; + if(timeArray[timeSlot]==1 && t[timeSlot].totalCollisions<=2 && st[stationCount].arrivalTimeSlot==timeSlot)//st[stationCount].arrivalTimeSlot==timeSlot && t[timeSlot].totalCollisions==0 && !t[timeSlot].collided) + { + t[timeSlot].transmitted=true; + cout << stationStr << stationCount << " Success! "; + + + transmissions++; + if (transmissions>1 && transmissions != 6) + { + cout << "\t\t<=== Project1b Solution\n"; + } + else if (transmissions==6) + { + cout << "\t\t<=== Project1b Solution\n" << dashes << endl; + end = true; + break; + } + else + { + cout << "\t\t<=== Project1a Solution\n"; + } + + + transmitted=true; + + } + else if (st[stationCount].arrivalTimeSlot==timeSlot && timeArray[timeSlot]>1) + { + // if (t[timeSlot].totalCollisions==1 && timeArray[timeSlot]==1 && t[timeSlot].totalCollisions==0) + // { + // // t[timeSlot].transmitted=true; + // cout << stationStr << stationCount << " Success! " << endl; + // cout << "End of program\n"; + // end = true; + // } + if (end) break; + + st[stationCount].arrivalTimeSlot++; + st[stationCount].collisions++; + inputFile >> numFromFile; + //array[arrayIndex] = numFromFile; + //arrayIndex++; + modOperand = pow(2,st[stationCount].collisions); + modOperand--; + k = numFromFile % modOperand; + //uniform_int_distribution distr(0, k); + // int o = distr(generator); + st[stationCount].backoff = k; + st[stationCount].arrivalTimeSlot = st[stationCount].arrivalTimeSlot+st[stationCount].backoff; + timeArray[st[stationCount].arrivalTimeSlot]++; + if (timeArray[st[stationCount].arrivalTimeSlot]<=1) + { + t[st[stationCount].arrivalTimeSlot].collided=false; + + } + else + t[st[stationCount].arrivalTimeSlot].collided=false; + + cout << "\tStation " << stationCount << backing << st[stationCount].arrivalTimeSlot << collisionsStr << st[stationCount].collisions << endl; + t[st[stationCount].arrivalTimeSlot].totalCollisions++; + } + else if (t[timeSlot].totalCollisions==1 && t[timeSlot].transmitted && st[stationCount].arrivalTimeSlot==timeSlot) + { + //t[timeSlot].transmitted=true; + cout << stationStr << stationCount << " Success! " << endl << dashes << endl; + cout << "End of program\n"; + end = true; + } + else //if (st[stationCount].arrivalTimeSlot != timeSlot && t[timeSlot].totalCollisions<1 && !t[timeSlot].transmitted) + { + if (timeArray[timeSlot]==0) + { + if(stationCount==5) + cout << " NO ATTEMPTS\n"; + } + } + + + if (end) break; + + + + + + if(stationCount==5) + { + cout << dashes << endl; + timeSlot++; + } + + + } + if (end) break; + + /* if (t[timeSlot].totalCollisions<2 && t[timeSlot].) + // { + cout << dashes << check << timeSlot << endl << stationStr << stationCount << " Success! " << endl + << dashes; + } */ + // if(transmitted==true) cout << dashes << endl; + + } + if (end) break; + } + + } +} + + diff --git a/CPE348/Project2/project2Pt1c b/CPE348/Project2/project2Pt1c new file mode 100755 index 0000000..50deb83 Binary files /dev/null and b/CPE348/Project2/project2Pt1c differ diff --git a/CPE348/Project2/project2Pt1c.cpp b/CPE348/Project2/project2Pt1c.cpp new file mode 100644 index 0000000..5d2c00d --- /dev/null +++ b/CPE348/Project2/project2Pt1c.cpp @@ -0,0 +1,390 @@ +#include +#include +#include +#include +#include +#include + +#define MAX_COLLISIONS 10000 +#define MAX_STATIONS 5 + +using namespace std; +struct timeSlot { + int timeOfTransmission; // time slot + int totalCollisions; + // stations A; + bool collided, transmitted; +}; + +struct stations { + int arrivalTimeSlot; // time slot + int collisions; + int backoff; + timeSlot A; +}; + + +// function that generates the +// range of backoff slots +//int rangeOfBackoff(int k); + +std::random_device rand_dev; + std::mt19937 generator(rand_dev()); + //std::uniform_int_distribution distr(0, k); + +int main() +{ + bool didNotCollide, end; + int collisionArray[MAX_COLLISIONS]; + int timeArray[MAX_COLLISIONS]; + + int k; + // file with numbers + string file = "Project2_part1_rn.txt"; + ifstream inputFile; + inputFile.open(file.c_str()); + bool transmitted; + int totalTransmitted = 0; + int timeIndex = 0; + int modOperand =0; + struct stations st[6]; + int timeSlot=0, numFromFile = 0; + const int timeInterval = 512; // time interval in micro seconds + + // strings for precise code + string check="Checking time slot: "; + string collisionsStr = " collisions: "; + string backing = ": backing off to slot "; + string dashes = "--------------------------------------------------\n"; + string stationStr = "\tStation "; + // define variables + int n, totalCollisions,i; + struct timeSlot t[MAX_COLLISIONS]; + + + //int modOperand = pow(2,st[i].collisions); + + // k * timeInterval + // begining at t = 0, all stations collide + + while (1) + { + if (timeSlot==0) + { + cout << dashes << check << timeSlot << endl; + for (int i = 0; i < MAX_STATIONS; i++) + { + t[i].totalCollisions++; + t[i].timeOfTransmission = i; + st[i].arrivalTimeSlot=0; // Arrival Time slot + //k= pow(2,st[i].collisions); + st[i].collisions = 1; + k=1; + uniform_int_distribution distr(0, k); + int o = distr(generator); + st[i].backoff = o; + if (o==0) + { + st[i].arrivalTimeSlot=1; + t[i].timeOfTransmission=1; + timeArray[1]++; + } + else + { + timeArray[2]++; + st[i].arrivalTimeSlot = 2; + } + cout << "\tStation " << i << backing << st[i].arrivalTimeSlot << collisionsStr << st[i].collisions << endl; + } + + cout << dashes << endl; + timeSlot++; + + } + else + { + for (int comp = 0; comp < 5; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + // timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + else if (t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>=timeSlot){ + //cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + //cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + + + } + for (int i = 0; i < MAX_COLLISIONS; i++) + { + //cout << dashes << check << timeSlot << endl; + for (int stationCount = 0; stationCount < MAX_STATIONS; stationCount++) + { + t[stationCount].transmitted=true; + if (stationCount==0) + { + for (int comp = 0; comp < MAX_STATIONS; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + //timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>timeSlot){ + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + + + } + for (int i = 0; i < 6; i++) + { + // cout << "TimeArray\t"<> numFromFile; + //array[arrayIndex] = numFromFile; + //arrayIndex++; + modOperand = pow(2,st[stationCount].collisions); + modOperand--; + k = numFromFile % modOperand; + uniform_int_distribution distr(0, k); + int o = distr(generator); + st[stationCount].backoff = o; + st[stationCount].arrivalTimeSlot = st[stationCount].arrivalTimeSlot+st[stationCount].backoff; + timeArray[st[stationCount].arrivalTimeSlot]++; + if (timeArray[st[stationCount].arrivalTimeSlot]>1) + { + t[st[stationCount].arrivalTimeSlot].collided=false; + + } + st[stationCount].A.transmitted=false; + cout << "\tStation " << stationCount << backing << st[stationCount].arrivalTimeSlot << collisionsStr << st[stationCount].collisions << endl; + if (stationCount==MAX_STATIONS-1 && st[MAX_STATIONS-1].arrivalTimeSlot==timeSlot) + { + cout << dashes << endl; + } + + } + else if (t[timeSlot].totalCollisions==1 && t[timeSlot].transmitted && st[stationCount].arrivalTimeSlot==timeSlot) + { + // //t[timeSlot].transmitted=true; + // cout << stationStr << stationCount << " Success! " << endl << dashes << endl; + // cout << "End of program\n"; + // end = true; + } + else //if (st[stationCount].arrivalTimeSlot != timeSlot && t[timeSlot].totalCollisions<1 && !t[timeSlot].transmitted) + { + if (timeArray[timeSlot]==0) + { + if(stationCount==4) + cout << " NO ATTEMPTS\n"; + } + } + + + if (end) break; + + + + + + if(stationCount == MAX_STATIONS-1) + { + //if(st[stationCount].A.transmitted==false) cout << dashes << endl; + timeSlot++; + for (int comp = 0; comp < 5; comp++) + { + if (st[comp].arrivalTimeSlot==st[comp+1].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+1].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+1].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+2].arrivalTimeSlot && st[comp].arrivalTimeSlot>=timeSlot && st[comp+2].arrivalTimeSlot>=timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+2].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+3].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+3].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+3].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + //timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+4].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+4].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+4].arrivalTimeSlot].collided=true; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // timeArray[st[comp].arrivalTimeSlot]++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if (st[comp].arrivalTimeSlot==st[comp+5].arrivalTimeSlot && st[comp].arrivalTimeSlot>timeSlot && st[comp+5].arrivalTimeSlot>timeSlot) + { + t[st[comp].arrivalTimeSlot].collided=true; + t[st[comp+5].arrivalTimeSlot].collided=true; + //timeArray[st[comp].arrivalTimeSlot]++; + t[st[comp].arrivalTimeSlot].totalCollisions++; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\ttrue" << endl; + } + if ((t[st[comp].arrivalTimeSlot].collided=true || st[comp].arrivalTimeSlot>=timeSlot) && t[st[comp].arrivalTimeSlot].totalCollisions>1) + { + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tcontinue" << endl; + + continue; + } + else + { + + t[st[comp].arrivalTimeSlot].collided=false; + // cout << comp << "\t" << st[comp].arrivalTimeSlot << "\tfalse" << endl; + + } + } + if (st[MAX_STATIONS-1].A.transmitted==false) + { + cout << dashes < +#include +#include +#include +#include + + +#define MAX_TIME 100000 +#define MAX_STATIONS 6 + +using namespace std; +struct timeSlot { + int timeOfTransmission; // time slot + int totalCollisions; + // stations A; + bool collided, transmitted; +}; + +struct stations { + int arrivalTimeSlot; // time slot + int collisions; + int backoff; + timeSlot A; +}; + +int main() +{ + bool end; + int timeArray[MAX_TIME]; + int transmissions =0; + int k = 0; + // file with numbers + string file = "Project2_part1_rn.txt"; + ifstream inputFile; + inputFile.open(file.c_str()); + int modOperand = 0; + struct stations st[6]; + int timeSlot=0, numFromFile = 0; + const double timeInterval = 51.2; // time interval in micro seconds + + // strings for precise code + string check="Checking time slot: "; + string collisionsStr = " collisions: "; + string backing = ": backing off to slot "; + string dashes = "--------------------------------------------------\n"; + string stationStr = "\tStation "; + // define variables + struct timeSlot t[MAX_TIME]; + + + //int modOperand = pow(2,st[stationCount].collisions); + + // k * timeInterval + // begining at t = 0, all stations collide + + +for (int i = 0; i < MAX_TIME; i++) +{ + //cout << dashes << check << timeSlot << endl; + for (int stationCount = 0; stationCount < MAX_STATIONS; stationCount++) + { + t[stationCount].transmitted=true; + if (stationCount==0) + { + cout << dashes << check << timeSlot << endl; + } + // no station has collided and will transmit + if(timeArray[timeSlot]==1 && t[timeSlot].totalCollisions<=2 && st[stationCount].arrivalTimeSlot==timeSlot)//st[stationCount].arrivalTimeSlot==timeSlot && t[timeSlot].totalCollisions==0 && !t[timeSlot].collided) + { + t[timeSlot].transmitted=true; + + + transmissions++; + if (transmissions==1) + { + //cout << stationStr << stationCount << " Success! "; + cout << "Station " << stationCount << " has successfully transmitted\n" << + "in slot number " << timeSlot << " which is " << timeInterval*timeSlot << " micro seconds"; + cout << "\t\t<====\tSolution Part1a and Partb \n"; + } + else if (transmissions==6) + { + //cout << stationStr << stationCount << " Success! "; + cout << "Station " << stationCount << " has successfully transmitted\n" << + "in slot number " << timeSlot << " which is " << timeInterval*timeSlot << " micro seconds"; + cout << "\t\t<====\tSolution Part1b \n" << dashes << endl; + end = true; + break; + } + else + { + //cout << stationStr << stationCount << " Success! "; + cout << "Station " << stationCount << " has successfully transmitted\n" << + "in slot number " << timeSlot << " which is " << timeInterval*timeSlot << " micro seconds"; + cout << "\t\t<==== \tSolution Part1b\n"; + } + } + // Two or more stations have collided + else if (st[stationCount].arrivalTimeSlot==timeSlot || timeSlot==0) + { + // initialize values to zero + if (timeSlot==0) + { + st[stationCount].arrivalTimeSlot = 0; + st[stationCount].backoff = 0; + st[stationCount].collisions = 0; + } + st[stationCount].arrivalTimeSlot++; + st[stationCount].collisions++; + inputFile >> numFromFile; + modOperand = pow(2,st[stationCount].collisions); + k = numFromFile % modOperand; + st[stationCount].backoff = k; + st[stationCount].arrivalTimeSlot = st[stationCount].arrivalTimeSlot+st[stationCount].backoff; + timeArray[st[stationCount].arrivalTimeSlot]++; + cout << "\tStation " << stationCount << backing << st[stationCount].arrivalTimeSlot << collisionsStr << st[stationCount].collisions << endl; + t[st[stationCount].arrivalTimeSlot].totalCollisions++; + } + else + { + if (timeArray[timeSlot]==0) + { + if(stationCount==5) + cout << " NO ATTEMPTS\n"; + } + } + + + if (end) break; + if(stationCount==5) + { + cout << dashes << endl; + timeSlot++; + } + + + } + if (end) break; +} + +} \ No newline at end of file diff --git a/CPE348/Project2/project2PtC b/CPE348/Project2/project2PtC new file mode 100755 index 0000000..8064c4f Binary files /dev/null and b/CPE348/Project2/project2PtC differ diff --git a/CPE348/Project2/project2PtC.cpp b/CPE348/Project2/project2PtC.cpp new file mode 100644 index 0000000..4cc4280 --- /dev/null +++ b/CPE348/Project2/project2PtC.cpp @@ -0,0 +1,140 @@ +#include +#include +#include +#include +#include + + +#define MAX_TIME 100000 +#define MAX_STATIONS 5 + +using namespace std; +struct timeSlot { + int timeOfTransmission; // time slot + int totalCollisions; + // stations A; + bool collided, transmitted; +}; + +struct stations { + int arrivalTimeSlot; // time slot + int collisions; + int packetsTransmitted; + int backoff; + timeSlot A; +}; + +int main() +{ + bool end = false; + int timeArray[MAX_TIME]; + int k = 0; + // file with numbers + string file = "Project2_part1_rn.txt"; + ifstream inputFile; + inputFile.open(file.c_str()); + int firstTransmissions = 0; + int modOperand = 0; + struct stations st[6]; + int timeSlot=0, numFromFile =0; + const double timeInterval = 51.2; // time interval in micro seconds + + // strings for precise code + string check="Checking time slot: "; + string collisionsStr = " collisions: "; + string backing = ": backing off to slot "; + string dashes = "--------------------------------------------------\n"; + string stationStr = "\tStation "; + // define variables + struct timeSlot t[MAX_TIME]; + + + //int modOperand = pow(2,st[stationCount].collisions); + + // k * timeInterval + // begining at t = 0, all stations collide + + +for (int i = 0; i < MAX_TIME; i++) +{ + //cout << dashes << check << timeSlot << endl; + for (int stationCount = 0; stationCount < MAX_STATIONS; stationCount++) + { + if (stationCount==0) + { + //cout << dashes << check << timeSlot << endl; + } + // station is going to transmit + if(timeArray[timeSlot]==1 && st[stationCount].arrivalTimeSlot==timeSlot)//st[stationCount].arrivalTimeSlot==timeSlot && t[timeSlot].totalCollisions==0 && !t[timeSlot].collided) + { + t[timeSlot].transmitted=true; + + st[stationCount].packetsTransmitted++; + if (st[stationCount].packetsTransmitted==1) + { + firstTransmissions++; + } + + // the last station transmits + if (firstTransmissions == 5 && st[stationCount].packetsTransmitted == 1) + { + cout << "\n****************************************************\n" << "Part1c: \n"; + cout << "****************************************************\n"; + cout << check << timeSlot << endl; + cout << "Station " << stationCount << " has successfully transmitted\n" << + "in slot number " << timeSlot << " which is " << timeInterval*timeSlot << " micro seconds\n"; + end = true; + break; + } + st[stationCount].arrivalTimeSlot=st[stationCount].arrivalTimeSlot+3; + timeArray[st[stationCount].arrivalTimeSlot]++; + //t[st[stationCount].arrivalTimeSlot].totalCollisions++; + st[stationCount].collisions=0; + // cout << stationStr << stationCount << " Success! \n"; + } + // Two or more stations have collided + else if (st[stationCount].arrivalTimeSlot==timeSlot || timeSlot==0) + { + // initialize values to zero + if (timeSlot==0) + { + st[stationCount].arrivalTimeSlot = 0; + st[stationCount].backoff = 0; + st[stationCount].collisions = 0; + st[stationCount].packetsTransmitted = 0; + } + + st[stationCount].arrivalTimeSlot++; + st[stationCount].collisions++; + inputFile >> numFromFile; + modOperand = pow(2,st[stationCount].collisions); + k = numFromFile % modOperand; + st[stationCount].backoff = k; + st[stationCount].arrivalTimeSlot = st[stationCount].arrivalTimeSlot+st[stationCount].backoff; + timeArray[st[stationCount].arrivalTimeSlot]++; + // cout << "\tStation " << stationCount << backing << st[stationCount].arrivalTimeSlot << collisionsStr << st[stationCount].collisions << endl; + t[st[stationCount].arrivalTimeSlot].totalCollisions++; + } + else + { + if (timeArray[timeSlot]==0) + { + + // cout << " NO ATTEMPTS\n"; + } + } + + + if (end) break; + if(stationCount==4) + { + //cout << dashes << endl; + timeSlot++; + } + + + } + if (end) break; +} + +} \ No newline at end of file diff --git a/CPE348/Project2/submission sample.txt b/CPE348/Project2/submission sample.txt new file mode 100644 index 0000000..f2c62dd --- /dev/null +++ b/CPE348/Project2/submission sample.txt @@ -0,0 +1,70 @@ +-------------------------------------------------- +Checking time slot: 0 + station 0: backing off to slot 1 collisions: 1 + station 1: backing off to slot 2 collisions: 1 + station 2: backing off to slot 2 collisions: 1 + station 3: backing off to slot 1 collisions: 1 + station 4: backing off to slot 1 collisions: 1 +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 1 + station 0: backing off to slot 4 collisions: 2 + station 3: backing off to slot 5 collisions: 2 + station 4: backing off to slot 2 collisions: 2 +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 2 + station 1: backing off to slot 5 collisions: 2 + station 2: backing off to slot 3 collisions: 2 + station 4: backing off to slot 6 collisions: 3 +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 3 + station 2: success! <========= Solution Part1b +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 4 + station 0: success! <========= Solution Part1a & Part1b +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 5 + station 1: backing off to slot 2 collisions: 3 + station 3: backing off to slot 3 collisions: 3 +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 6 + station 4: success! <========= Solution Part1b +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 7 + NO ATTEMPTS +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 8 + station 1: success! <========= Solution Part1b +-------------------------------------------------- + +-------------------------------------------------- +Checking time slot: 9 + station 3: success! <========= Solution Part1b +-------------------------------------------------- + + + +**************************************************** +Par1c: +**************************************************** +Checking time slot: 135 +Station 3 has successfully transmitted +in slot number 135 which is 6,912 micro seconds + + + diff --git a/CPE348/Project2/t b/CPE348/Project2/t new file mode 100755 index 0000000..695009f Binary files /dev/null and b/CPE348/Project2/t differ diff --git a/CPE348/Project2/t.cpp b/CPE348/Project2/t.cpp new file mode 100644 index 0000000..0be5b38 --- /dev/null +++ b/CPE348/Project2/t.cpp @@ -0,0 +1,14 @@ +#include +#include + +int main(int argc, char const *argv[]) +{ + const int range_from = 0; +const int range_to = 1; +std::random_device rand_dev; +std::mt19937 generator(rand_dev()); +std::uniform_int_distribution distr(range_from, range_to); + +std::cout << distr(generator) << '\n'; + return 0; +} diff --git a/CPE348/Project3/Project3_wireshark.docx b/CPE348/Project3/Project3_wireshark.docx new file mode 100644 index 0000000..884814c Binary files /dev/null and b/CPE348/Project3/Project3_wireshark.docx differ diff --git a/CPE348/Project3/packets.c b/CPE348/Project3/packets.c new file mode 100644 index 0000000..171b316 --- /dev/null +++ b/CPE348/Project3/packets.c @@ -0,0 +1,9 @@ +"4","0.026477","192.168.1.102","128.119.245.12","TCP","619","1161 → 80 [PSH, ACK] Seq=1 Ack=1 Win=17520 Len=565" +"5","0.041737","192.168.1.102","128.119.245.12","TCP","1514","1161 → 80 [PSH, ACK] Seq=566 Ack=1 Win=17520 Len=1460" +"6","0.053937","128.119.245.12","192.168.1.102","TCP","60","80 → 1161 [ACK] Seq=1 Ack=566 Win=6780 Len=0" +"7","0.054026","192.168.1.102","128.119.245.12","TCP","1514","1161 → 80 [ACK] Seq=2026 Ack=1 Win=17520 Len=1460" +"8","0.054690","192.168.1.102","128.119.245.12","TCP","1514","1161 → 80 [ACK] Seq=3486 Ack=1 Win=17520 Len=1460" +"9","0.077294","128.119.245.12","192.168.1.102","TCP","60","80 → 1161 [ACK] Seq=1 Ack=2026 Win=8760 Len=0" +"10","0.077405","192.168.1.102","128.119.245.12","TCP","1514","1161 → 80 [ACK] Seq=4946 Ack=1 Win=17520 Len=1460" +"11","0.078157","192.168.1.102","128.119.245.12","TCP","1514","1161 → 80 [ACK] Seq=6406 Ack=1 Win=17520 Len=1460" +"12","0.124085","128.119.245.12","192.168.1.102","TCP","60","80 → 1161 [ACK] Seq=1 Ack=3486 Win=11680 Len=0" diff --git a/CPE348/Project3/packets.csv b/CPE348/Project3/packets.csv new file mode 100644 index 0000000..13d474b --- /dev/null +++ b/CPE348/Project3/packets.csv @@ -0,0 +1,14 @@ +4,0.026477,192.168.1.102,128.119.245.12,TCP,619,"1161 → 80 [PSH, ACK] Seq=1 Ack=1 Win=17520 Len=565",,,,,,, +5,0.041737,192.168.1.102,128.119.245.12,TCP,1514,"1161 → 80 [PSH, ACK] Seq=566 Ack=1 Win=17520 Len=1460",,,,,,, +6,0.053937,128.119.245.12,192.168.1.102,TCP,60,80 → 1161 [ACK] Seq=1 Ack=566 Win=6780 Len=0,,,,Segment,RTT,Estimated RTT,alpha +7,0.054026,192.168.1.102,128.119.245.12,TCP,1514,1161 → 80 [ACK] Seq=2026 Ack=1 Win=17520 Len=1460,,,,1,0.02746,0.02746,0.125 +8,0.05469,192.168.1.102,128.119.245.12,TCP,1514,1161 → 80 [ACK] Seq=3486 Ack=1 Win=17520 Len=1460,,,,2,0.035557,0.034544875,0.125 +9,0.077294,128.119.245.12,192.168.1.102,TCP,60,80 → 1161 [ACK] Seq=1 Ack=2026 Win=8760 Len=0,,,,3,0.070059,0.065619734,0.125 +10,0.077405,192.168.1.102,128.119.245.12,TCP,1514,1161 → 80 [ACK] Seq=4946 Ack=1 Win=17520 Len=1460,,,,4,0.114428,0.108326967,0.125 +11,0.078157,192.168.1.102,128.119.245.12,TCP,1514,1161 → 80 [ACK] Seq=6406 Ack=1 Win=17520 Len=1460,,,,5,0.139894,0.135948121,0.125 +12,0.124085,128.119.245.12,192.168.1.102,TCP,60,80 → 1161 [ACK] Seq=1 Ack=3486 Win=11680 Len=0,,,,6,0.189645,0.18293289,0.125 +13,0.124185,192.168.1.102,128.119.245.12,TCP,1201,"1161 → 80 [PSH, ACK] Seq=7866 Ack=1 Win=17520 Len=1147",,,,,,, +14,0.169118,128.119.245.12,192.168.1.102,TCP,60,80 → 1161 [ACK] Seq=1 Ack=4946 Win=14600 Len=0,,,,,,, +15,0.217299,128.119.245.12,192.168.1.102,TCP,60,80 → 1161 [ACK] Seq=1 Ack=6406 Win=17520 Len=0,,,,,,, +16,0.267802,128.119.245.12,192.168.1.102,TCP,60,80 → 1161 [ACK] Seq=1 Ack=7866 Win=20440 Len=0,,,,,,, +17,0.304807,128.119.245.12,192.168.1.102,TCP,60,80 → 1161 [ACK] Seq=1 Ack=9013 Win=23360 Len=0,,,,,,, diff --git a/CPE348/Project3/packets.pdf b/CPE348/Project3/packets.pdf new file mode 100644 index 0000000..f6b3f94 Binary files /dev/null and b/CPE348/Project3/packets.pdf differ diff --git a/CPE348/Project3/packets.txt b/CPE348/Project3/packets.txt new file mode 100644 index 0000000..c834bb4 --- /dev/null +++ b/CPE348/Project3/packets.txt @@ -0,0 +1,428 @@ +|Time | 192.168.1.102 | Intel_52:2b:23 | LinksysG_da:af:73 | 192.168.1.1 | +| | | 128.119.245.12 | | Broadcast | | 192.168.1.100 | | 199.2.53.206 | +|0.000000 | 1161 → 80 [SYN] Seq= | | | | | | |TCP: 1161 → 80 [SYN] Seq=0 Win=16384 Len=0 MSS=1460 SACK_PERM=1 +| |(1161) ------------------> (80) | | | | | | | +|0.023172 | 80 → 1161 [SYN, ACK] | | | | | | |TCP: 80 → 1161 [SYN, ACK] Seq=0 Ack=1 Win=5840 Len=0 MSS=1460 SACK_PERM=1 +| |(1161) <------------------ (80) | | | | | | | +|0.023265 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=1 Ack=1 Win=17520 Len=0 +| |(1161) ------------------> (80) | | | | | | | +|0.026477 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=1 Ack=1 Win=17520 Len=565 +| |(1161) ------------------> (80) | | | | | | | +|0.041737 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=566 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.053937 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=566 Win=6780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.054026 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=2026 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.054690 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=3486 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.077294 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=2026 Win=8760 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.077405 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=4946 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.078157 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=6406 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.124085 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=3486 Win=11680 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.124185 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=7866 Ack=1 Win=17520 Len=1147 +| |(1161) ------------------> (80) | | | | | | | +|0.169118 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=4946 Win=14600 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.217299 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=6406 Win=17520 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.267802 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=7866 Win=20440 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.304807 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=9013 Win=23360 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.305040 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=9013 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.305813 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=10473 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.306692 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=11933 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.307571 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=13393 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.308699 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=14853 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.309553 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=16313 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|0.356437 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=10473 Win=26280 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.400164 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=11933 Win=29200 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.448613 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=13393 Win=32120 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.500029 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=14853 Win=35040 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.545052 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=16313 Win=37960 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.576417 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=17205 Win=37960 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.576671 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=17205 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.577385 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=18665 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.578329 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=20125 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.579195 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=21585 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.580149 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=23045 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.581074 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=24505 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|0.626496 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=18665 Win=40880 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.672796 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=20125 Win=43800 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.730684 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=21585 Win=46720 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.772990 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=23045 Win=49640 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.820622 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=24505 Win=52560 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.853186 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=25397 Win=52560 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.853405 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=25397 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.854076 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=26857 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.855036 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=28317 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.855878 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=29777 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.856802 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=31237 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|0.857683 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=32697 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|0.899423 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=26857 Win=55480 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.949545 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=28317 Win=58400 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|0.994715 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=29777 Win=61320 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.039820 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=31237 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.117097 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=33589 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.117333 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=33589 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.118133 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=35049 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.119029 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=36509 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.119858 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=37969 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.120902 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=39429 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.121891 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=40889 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|1.200421 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=35049 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.265026 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=37969 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.362074 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=40889 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.389886 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=41781 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.390110 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=41781 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.390824 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=43241 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.391683 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=44701 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.392594 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=46161 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.393390 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=47621 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.394202 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=49081 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|1.488313 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=44701 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.584980 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=47621 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.661513 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=49973 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.661734 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=49973 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.662474 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=51433 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.663315 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=52893 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.664198 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=54353 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.665254 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=55813 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.666151 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=57273 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|1.758227 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=52893 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.860063 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=55813 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.930880 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=58165 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|1.931099 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=58165 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.931879 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=59625 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.932757 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=61085 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.933636 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=62545 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.934770 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=64005 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|1.935586 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=65465 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|2.029069 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=61085 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.126682 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=64005 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.203195 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=66357 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.203411 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=66357 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.204125 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=67817 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.204962 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=69277 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.205836 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=70737 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.206824 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=72197 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.207746 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=73657 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|2.311413 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=69277 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.404228 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=72197 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.476576 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=74549 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.476801 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=74549 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.477515 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=76009 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.478415 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=77469 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.479341 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=78929 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.480356 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=80389 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.481218 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=81849 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|2.576633 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=77469 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.672045 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=80389 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.747257 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=82741 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.747468 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=82741 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.748321 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=84201 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.749246 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=85661 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.750126 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=87121 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.751237 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=88581 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|2.752049 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=90041 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|2.847009 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=85661 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|2.944420 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=88581 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.020822 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=90933 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.021036 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=90933 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.021748 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=92393 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.022626 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=93853 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.023492 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=95313 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.024734 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=96773 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.025618 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=98233 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|3.117302 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=93853 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.216127 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=96773 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.291672 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=99125 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.291881 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=99125 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.292657 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=100585 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.293613 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=102045 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.294487 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=103505 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.295806 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=104965 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.296698 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=106425 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|3.388926 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=102045 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.485275 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=104965 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.562531 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=107317 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.562737 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=107317 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.563561 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=108777 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.564458 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=110237 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.565426 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=111697 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.566442 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=113157 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.567324 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=114617 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|3.660330 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=110237 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.768417 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=113157 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.840483 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=115509 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|3.840697 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=115509 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.841410 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=116969 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.842307 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=118429 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.843230 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=119889 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.844008 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=121349 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|3.844820 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=122809 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|3.936967 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=118429 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.031145 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=121349 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.107455 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=123701 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.107686 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=123701 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.108476 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=125161 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.109329 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=126621 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.110217 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=128081 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.111334 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=129541 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.112209 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=131001 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|4.205521 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=126621 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.300300 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=129541 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.379826 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=131893 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.380034 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=131893 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.380741 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=133353 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.381618 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=134813 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.382478 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=136273 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.383659 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=137733 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.384548 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=139193 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|4.476833 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=134813 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.575928 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=137733 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.648167 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=140085 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.648386 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=140085 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.649100 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=141545 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.649993 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=143005 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.650926 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=144465 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.651858 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=145925 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.652735 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=147385 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|4.747988 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=143005 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.844598 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=145925 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.920051 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=148277 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|4.920310 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=148277 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.921025 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=149737 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.921916 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=151197 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.922820 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=152657 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.923863 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=154117 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|4.924667 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=155577 Ack=1 Win=17520 Len=892 +| |(1161) ------------------> (80) | | | | | | | +|5.019189 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=151197 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|5.104175 | | | Who has 192.168.1.1? | | | | |ARP: Who has 192.168.1.1? Tell 192.168.1.100 +| | | |(0) ------------------> (0) | | | | | +|5.105060 | | | 192.168.1.1 is at 00:06:25:da:af:73 | | | |ARP: 192.168.1.1 is at 00:06:25:da:af:73 +| | | |(0) <-------------------------------------- (0) | | | | +|5.106121 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|5.125019 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=154117 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|5.197286 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=156469 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|5.197508 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=156469 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|5.198388 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=157929 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|5.199275 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=159389 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|5.200252 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=160849 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|5.201150 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=162309 Ack=1 Win=17520 Len=1460 +| |(1161) ------------------> (80) | | | | | | | +|5.202024 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=163769 Ack=1 Win=17520 Len=272 +| |(1161) ------------------> (80) | | | | | | | +|5.297257 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=159389 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|5.297341 | 1161 → 80 [PSH, ACK] | | | | | | |TCP: 1161 → 80 [PSH, ACK] Seq=164041 Ack=1 Win=17520 Len=50 +| |(1161) ------------------> (80) | | | | | | | +|5.389471 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=162309 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|5.447887 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=164041 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|5.455830 | 80 → 1161 [ACK] Seq= | | | | | | |TCP: 80 → 1161 [ACK] Seq=1 Ack=164091 Win=62780 Len=0 +| |(1161) <------------------ (80) | | | | | | | +|5.461175 | 80 → 1161 [PSH, ACK] | | | | | | |TCP: 80 → 1161 [PSH, ACK] Seq=1 Ack=164091 Win=62780 Len=730 +| |(1161) <------------------ (80) | | | | | | | +|5.598090 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|5.599082 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|5.651141 | 1161 → 80 [ACK] Seq= | | | | | | |TCP: 1161 → 80 [ACK] Seq=164091 Ack=731 Win=16790 Len=0 +| |(1161) ------------------> (80) | | | | | | | +|6.101044 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|6.102069 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|6.600152 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|6.601063 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|7.102852 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|7.103780 | | | | | | M-SEARCH * HTTP/1.1 | |SSDP: M-SEARCH * HTTP/1.1 +| | | | | | |(44265) ------------------> (1900) | | +|7.595557 | 1162 → 631 [SYN] Seq=0 Win=16384 Len=0 MSS=1460 SACK_PERM=1 | | | | |TCP: 1162 → 631 [SYN] Seq=0 Win=16384 Len=0 MSS=1460 SACK_PERM=1 +| |(1162) ------------------------------------------------------------------------------------------------------------------------------------------> (631) | diff --git a/CPE348/Project3/tcp-trace b/CPE348/Project3/tcp-trace new file mode 100644 index 0000000..1f92706 Binary files /dev/null and b/CPE348/Project3/tcp-trace differ diff --git a/CPE348/Project3/~$oject3_wireshark.docx b/CPE348/Project3/~$oject3_wireshark.docx new file mode 100644 index 0000000..f85161d Binary files /dev/null and b/CPE348/Project3/~$oject3_wireshark.docx differ diff --git a/CPE348/Project3/~WRL0003.tmp b/CPE348/Project3/~WRL0003.tmp new file mode 100644 index 0000000..36791c9 Binary files /dev/null and b/CPE348/Project3/~WRL0003.tmp differ diff --git a/CPE348/Project3/~WRL0089.tmp b/CPE348/Project3/~WRL0089.tmp new file mode 100644 index 0000000..caa145f Binary files /dev/null and b/CPE348/Project3/~WRL0089.tmp differ diff --git a/CPE348/Project3/~WRL0134.tmp b/CPE348/Project3/~WRL0134.tmp new file mode 100644 index 0000000..7949ade Binary files /dev/null and b/CPE348/Project3/~WRL0134.tmp differ diff --git a/CPE348/Project_1_CRC.doc b/CPE348/Project_1_CRC.doc new file mode 100644 index 0000000..2800261 Binary files /dev/null and b/CPE348/Project_1_CRC.doc differ diff --git a/CPE435/.vscode/c_cpp_properties.json b/CPE435/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..abc0bea --- /dev/null +++ b/CPE435/.vscode/c_cpp_properties.json @@ -0,0 +1,16 @@ +{ + "configurations": [ + { + "name": "linux-gcc-x64", + "includePath": [ + "${workspaceFolder}/**" + ], + "compilerPath": "gcc", + "cStandard": "${default}", + "cppStandard": "${default}", + "intelliSenseMode": "linux-gcc-x64", + "compilerArgs": [] + } + ], + "version": 4 +} \ No newline at end of file diff --git a/CPE435/.vscode/extensions.json b/CPE435/.vscode/extensions.json new file mode 100644 index 0000000..5a9a397 --- /dev/null +++ b/CPE435/.vscode/extensions.json @@ -0,0 +1,5 @@ +{ + "recommendations": [ + "ms-vscode.cpptools" + ] +} \ No newline at end of file diff --git a/CPE435/.vscode/launch.json b/CPE435/.vscode/launch.json new file mode 100644 index 0000000..38a951f --- /dev/null +++ b/CPE435/.vscode/launch.json @@ -0,0 +1,49 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "gcc - Build and debug active file", + "type": "cppdbg", + "request": "launch", + "program": "${fileDirname}/${fileBasenameNoExtension}", + "args": [], + "stopAtEntry": false, + "cwd": "${fileDirname}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ], + "preLaunchTask": "C/C++: g++ build active file", + "miDebuggerPath": "/usr/bin/gdb" + }, + { + "name": "C/C++ Runner: Debug Session", + "type": "cppdbg", + "request": "launch", + "args": [ + "" + ], + "stopAtEntry": false, + "cwd": "/home/student/anw0044/CPE435Lab_SP22/Lab6", + "environment": [], + "program": "/home/student/anw0044/CPE435Lab_SP22/Lab6/build/Debug/outDebug", + "internalConsoleOptions": "openOnSessionStart", + "MIMode": "gdb", + "miDebuggerPath": "/usr/bin/gdb", + "externalConsole": false, + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + } + ] +} \ No newline at end of file diff --git a/CPE435/.vscode/settings.json b/CPE435/.vscode/settings.json new file mode 100644 index 0000000..72a7d00 --- /dev/null +++ b/CPE435/.vscode/settings.json @@ -0,0 +1,38 @@ +{ + "files.associations": { + "ostream": "cpp", + "iostream": "cpp", + "wait.h": "c", + "stdio.h": "c", + "*.tcc": "cpp" + }, + "cmake.configureOnOpen": false, + "C_Cpp_Runner.cCompilerPath": "gcc", + "C_Cpp_Runner.cppCompilerPath": "/usr/bin/g++", + "C_Cpp_Runner.debuggerPath": "/usr/bin/gdb", + "C_Cpp_Runner.cStandard": "", + "C_Cpp_Runner.cppStandard": "", + "C_Cpp_Runner.msvcBatchPath": "", + "C_Cpp_Runner.warnings": [ + "-Wall", + "-Wextra", + "-Wpedantic" + ], + "C_Cpp_Runner.enableWarnings": true, + "C_Cpp_Runner.warningsAsError": false, + "C_Cpp_Runner.compilerArgs": [], + "C_Cpp_Runner.linkerArgs": [], + "C_Cpp_Runner.includePaths": [], + "C_Cpp_Runner.includeSearch": [ + "*", + "**/*" + ], + "C_Cpp_Runner.excludeSearch": [ + "**/build", + "**/build/**", + "**/.*", + "**/.*/**", + "**/.vscode", + "**/.vscode/**" + ] +} \ No newline at end of file diff --git a/CPE435/.vscode/tasks.json b/CPE435/.vscode/tasks.json new file mode 100644 index 0000000..b1b70af --- /dev/null +++ b/CPE435/.vscode/tasks.json @@ -0,0 +1,26 @@ +{ + "tasks": [ + { + "type": "cppbuild", + "label": "C/C++: g++ build active file", + "command": "/usr/bin/gcc", + "args": [ + "-lm", + "-fdiagnostics-color=always", + "-g", + "${file}", + "-o", + "${fileDirname}/${fileBasenameNoExtension}" + ], + "options": { + "cwd": "${fileDirname}" + }, + "problemMatcher": [ + "$gcc" + ], + "group": "build", + "detail": "compiler: /usr/bin/gcc" + }, + + ] +} \ No newline at end of file diff --git a/CPE435/Lab1/Lab01.pdf b/CPE435/Lab1/Lab01.pdf new file mode 100644 index 0000000..eec4aed Binary files /dev/null and b/CPE435/Lab1/Lab01.pdf differ diff --git a/CPE435/Lab1/Lab01_Study_Material.pdf b/CPE435/Lab1/Lab01_Study_Material.pdf new file mode 100644 index 0000000..4d3ec83 Binary files /dev/null and b/CPE435/Lab1/Lab01_Study_Material.pdf differ diff --git a/CPE435/Lab1/demo_1 b/CPE435/Lab1/demo_1 new file mode 100755 index 0000000..971ad2b Binary files /dev/null and b/CPE435/Lab1/demo_1 differ diff --git a/CPE435/Lab1/demo_1.cpp b/CPE435/Lab1/demo_1.cpp new file mode 100644 index 0000000..a80ba35 --- /dev/null +++ b/CPE435/Lab1/demo_1.cpp @@ -0,0 +1,19 @@ +using namespace std; +#include +#include +#include +#include +int main(int argc, char * argv[]) +{ + pid_t c_pid; + cout << "The pid of the parent is " << getpid() << endl; + c_pid = fork(); + if (c_pid == 0 ) /* we are the child */ + { + cout << "I am the child, my parents pid was " << getppid() << endl; + exit(0); + } + cout << "I am the parent, the child's pid is " << c_pid << endl; + + exit(0); +} diff --git a/CPE435/Lab1/demo_2 b/CPE435/Lab1/demo_2 new file mode 100755 index 0000000..4278308 Binary files /dev/null and b/CPE435/Lab1/demo_2 differ diff --git a/CPE435/Lab1/demo_2.cpp b/CPE435/Lab1/demo_2.cpp new file mode 100644 index 0000000..2b6d20b --- /dev/null +++ b/CPE435/Lab1/demo_2.cpp @@ -0,0 +1,17 @@ +/* This program illustrates the use of fork */ + +#include +#include +#include +using namespace std; + +int main() +{ + int x; + x = 0; + fork(); + x++; + // This should be printed twice, once by the parent and once by the child + cout << "I am process "<< getpid() << " and my x is " << x << endl; + return 0; +} diff --git a/CPE435/Lab1/demo_3 b/CPE435/Lab1/demo_3 new file mode 100755 index 0000000..bb4d88c Binary files /dev/null and b/CPE435/Lab1/demo_3 differ diff --git a/CPE435/Lab1/demo_3.cpp b/CPE435/Lab1/demo_3.cpp new file mode 100644 index 0000000..6e1c823 --- /dev/null +++ b/CPE435/Lab1/demo_3.cpp @@ -0,0 +1,18 @@ +/* This program illustrates multiple fork operations */ + +#include +#include +#include +#include + +using namespace std; + +int main() +{ + printf("I am the Parent\n"); + fork(); + printf("This is printed by both parent and child\n"); + fork(); + printf("This will be printed 4 times\n"); + return 0; +} diff --git a/CPE435/Lab1/demo_4 b/CPE435/Lab1/demo_4 new file mode 100755 index 0000000..7921517 Binary files /dev/null and b/CPE435/Lab1/demo_4 differ diff --git a/CPE435/Lab1/demo_4.cpp b/CPE435/Lab1/demo_4.cpp new file mode 100644 index 0000000..89b37f7 --- /dev/null +++ b/CPE435/Lab1/demo_4.cpp @@ -0,0 +1,25 @@ +/* This program illustrates the death of the parent process before the child is terminated. */ +/* The child process is now considered an orphan process since the parent is dead. */ + +#include +#include +#include + +int main() +{ + int pid; + pid = fork(); + if (pid == 0) + { + printf("I am the child, my ID is %d\n", getpid()); + printf("I am the child, my parent is %d\n", getppid()); + printf("The child will now sleep for 10 seconds\n"); + sleep(10); + printf("I am the same child with ID %d, but my parent Id is %d\n", getpid(), getppid()); + } + else + { + printf("I am the parent with ID %d. My parent is %d and my child is %d\n", getpid(), getppid(), pid); + sleep(5); + } +} diff --git a/CPE435/Lab1/lab1 b/CPE435/Lab1/lab1 new file mode 100755 index 0000000..3188573 Binary files /dev/null and b/CPE435/Lab1/lab1 differ diff --git a/CPE435/Lab1/lab1.cpp b/CPE435/Lab1/lab1.cpp new file mode 100644 index 0000000..4125efd --- /dev/null +++ b/CPE435/Lab1/lab1.cpp @@ -0,0 +1,20 @@ +using namespace std; +#include +#include +#include +#include +int main(int argc, char * argv[]) +{ + pid_t x; + cout << "The pid of the parent is " << getpid() << endl; + for(int i=0; i<10; i++){ + x = fork(); + if (x == 0 ) /* we are the child */ + { + cout << "Id: " << getpid() << "\tX: x "<< endl; + exit(0); + } + // cout << "I am the parent, the child's pid is " << x << endl; + } + exit(0); +} diff --git a/CPE435/Lab1/lab1Questions.txt b/CPE435/Lab1/lab1Questions.txt new file mode 100644 index 0000000..a5c6c13 --- /dev/null +++ b/CPE435/Lab1/lab1Questions.txt @@ -0,0 +1,3 @@ +Question 1: The processes' PIDs are different each time the program is run, and both processes differ by 1. +2: Four are running. +3: \ No newline at end of file diff --git a/CPE435/Lab10/Lab10.pdf b/CPE435/Lab10/Lab10.pdf new file mode 100644 index 0000000..1303aa8 Binary files /dev/null and b/CPE435/Lab10/Lab10.pdf differ diff --git a/CPE435/Lab10/UFTP_v3_transfer.pcapng b/CPE435/Lab10/UFTP_v3_transfer.pcapng new file mode 100644 index 0000000..95556cf Binary files /dev/null and b/CPE435/Lab10/UFTP_v3_transfer.pcapng differ diff --git a/CPE435/Lab10/apache_pb.png b/CPE435/Lab10/apache_pb.png new file mode 100644 index 0000000..eb99a8c Binary files /dev/null and b/CPE435/Lab10/apache_pb.png differ diff --git a/CPE435/Lab10/lab10Capture.pcap b/CPE435/Lab10/lab10Capture.pcap new file mode 100644 index 0000000..32928af Binary files /dev/null and b/CPE435/Lab10/lab10Capture.pcap differ diff --git a/CPE435/Lab10/lab10CaptureOpenOffice.pcap b/CPE435/Lab10/lab10CaptureOpenOffice.pcap new file mode 100644 index 0000000..b911c61 Binary files /dev/null and b/CPE435/Lab10/lab10CaptureOpenOffice.pcap differ diff --git a/CPE435/Lab10/lab10CaptureUAH.pcap b/CPE435/Lab10/lab10CaptureUAH.pcap new file mode 100644 index 0000000..5e2a24a Binary files /dev/null and b/CPE435/Lab10/lab10CaptureUAH.pcap differ diff --git a/CPE435/Lab10/mysql-ssl-larger.pcapng b/CPE435/Lab10/mysql-ssl-larger.pcapng new file mode 100644 index 0000000..657a8a9 Binary files /dev/null and b/CPE435/Lab10/mysql-ssl-larger.pcapng differ diff --git a/CPE435/Lab10/mysql_complete.pcap b/CPE435/Lab10/mysql_complete.pcap new file mode 100644 index 0000000..bfc4d79 Binary files /dev/null and b/CPE435/Lab10/mysql_complete.pcap differ diff --git a/CPE435/Lab10/openlogo-25.html b/CPE435/Lab10/openlogo-25.html new file mode 100644 index 0000000..df81b0c --- /dev/null +++ b/CPE435/Lab10/openlogo-25.html @@ -0,0 +1,7 @@ + + +404 Not Found + +

Not Found

+

The requested URL /icons/debian/openlogo-25.jpg was not found on this server.

+ diff --git a/CPE435/Lab10/rsasnakeoil2.README b/CPE435/Lab10/rsasnakeoil2.README new file mode 100644 index 0000000..a7c4c59 --- /dev/null +++ b/CPE435/Lab10/rsasnakeoil2.README @@ -0,0 +1,6 @@ +(05/31/07: Updated to use proper delimiter and specify protocol) + +In preferences for SSL set RSA Keylist to: + UNIX/Linux: 127.0.0.1,443,http,/path/to/snakeoil2.key + Windows: 127.0.0.1,443,http,c:\path\to\snakeoil2.key + diff --git a/CPE435/Lab10/rsasnakeoil2.cap b/CPE435/Lab10/rsasnakeoil2.cap new file mode 100644 index 0000000..a1c6bd4 Binary files /dev/null and b/CPE435/Lab10/rsasnakeoil2.cap differ diff --git a/CPE435/Lab10/rsasnakeoil2.key b/CPE435/Lab10/rsasnakeoil2.key new file mode 100644 index 0000000..b064354 --- /dev/null +++ b/CPE435/Lab10/rsasnakeoil2.key @@ -0,0 +1,19 @@ +-----BEGIN RSA PRIVATE KEY----- +MIICWwIBAAKBgQCkblMUCt4s42BVmvJCpq9HEi8Xzvq63E5jVjS5unNLeEQ9xmxp +pCWzYQKdCQQ/cj3YJ9OwWkV3tzbkJiPMEriu3qe2OoI8fCRZCviWQ4ujKTY/kX9d +xyOUKX8Kzgq9jZsvGReq1Y7sZqI36z9XUzzyqrt5GUuQfqejmf6ETInwPQIDAQAB +AoGAedqEWKsBIPTTtDziYYBTDnEsUxGA/685rCX7ZtQEkx4qPDlqqBMMGVW/8Q34 +hugrap+BIgSTzHcLB6I4DwiksUpR08x0hf0oxqqjMo0KykhZDfUUfxR85JHUrFZM +GznurVhfSBXX4Il9Tgc/RPzD32FZ6gaz9sFumJh0LKKadeECQQDWOfP6+nIAvmyH +aRINErBSlK+xv2mZ4jEKvROIQmrpyNyoOStYLG/DRPlEzAIA6oQnowGgS6gwaibg +g7yVTgBpAkEAxH6dcwhIDRTILvtUdKSWB6vdhtXFGdebaU4cuUOW2kWwPpyIj4XN +D+rezwfptmeOr34DCA/QKCI/BWkbFDG2tQJAVAH971nvAuOp46AMeBvwETJFg8qw +Oqw81x02X6TMEEm4Xi+tE7K5UTXnGld2Ia3VjUWbCaUhm3rFLB39Af/IoQJAUn/G +o5GKjtN26SLk5sRjqXzjWcVPJ/Z6bdA6Bx71q1cvFFqsi3XmDxTRz6LG4arBIbWK +mEvrXa5jP2ZN1EC7MQJAYTfwPZ8/4x/USmA4vx9FKdADdDoZnA9ZSwezWaqa44My +bJ0SY/WmNU+Z4ldVIkcevwwwcxqLF399hjrXWhzlBQ== +-----END RSA PRIVATE KEY----- + + + + diff --git a/CPE435/Lab10/snakeoil2_070531.tar b/CPE435/Lab10/snakeoil2_070531.tar new file mode 100644 index 0000000..ad90c27 Binary files /dev/null and b/CPE435/Lab10/snakeoil2_070531.tar differ diff --git a/CPE435/Lab10/snakeoil2_070531.tgz b/CPE435/Lab10/snakeoil2_070531.tgz new file mode 100644 index 0000000..e04e270 Binary files /dev/null and b/CPE435/Lab10/snakeoil2_070531.tgz differ diff --git a/CPE435/Lab10/telnet-cooked.pcap b/CPE435/Lab10/telnet-cooked.pcap new file mode 100644 index 0000000..34515d4 Binary files /dev/null and b/CPE435/Lab10/telnet-cooked.pcap differ diff --git a/CPE435/Lab10/telnet-raw.pcap b/CPE435/Lab10/telnet-raw.pcap new file mode 100644 index 0000000..fcef276 Binary files /dev/null and b/CPE435/Lab10/telnet-raw.pcap differ diff --git a/CPE435/Lab10/why_edu.png b/CPE435/Lab10/why_edu.png new file mode 100644 index 0000000..4535084 Binary files /dev/null and b/CPE435/Lab10/why_edu.png differ diff --git a/CPE435/Lab10/why_sme.png b/CPE435/Lab10/why_sme.png new file mode 100644 index 0000000..007f85b Binary files /dev/null and b/CPE435/Lab10/why_sme.png differ diff --git a/CPE435/Lab11/Lab11_Part 2.pdf b/CPE435/Lab11/Lab11_Part 2.pdf new file mode 100644 index 0000000..3aadd4e Binary files /dev/null and b/CPE435/Lab11/Lab11_Part 2.pdf differ diff --git a/CPE435/Lab11/Lab11_Part1.pdf b/CPE435/Lab11/Lab11_Part1.pdf new file mode 100644 index 0000000..16825f5 Binary files /dev/null and b/CPE435/Lab11/Lab11_Part1.pdf differ diff --git a/CPE435/Lab12/Lab12.pdf b/CPE435/Lab12/Lab12.pdf new file mode 100644 index 0000000..5a60a6d Binary files /dev/null and b/CPE435/Lab12/Lab12.pdf differ diff --git a/CPE435/Lab12/test.c b/CPE435/Lab12/test.c new file mode 100644 index 0000000..7d8af4c --- /dev/null +++ b/CPE435/Lab12/test.c @@ -0,0 +1,14 @@ +volatile unsigned int * const UART0DR = (unsigned int *)0x101f1000; + // UART0 is the terminal running at 0x101f1000 + // UART0DR is the register used to transmit and receive bytes + +void print_uart0(const char *s) { + while(*s != '\0') { /* Loop until end of string */ + *UART0DR = (unsigned int)(*s); /* Transmit char */ + s++; /* Next char */ + } +} + +void c_entry() { + print_uart0("Hello world!\n"); +} \ No newline at end of file diff --git a/CPE435/Lab13/Lab13.pdf b/CPE435/Lab13/Lab13.pdf new file mode 100644 index 0000000..5e859f5 Binary files /dev/null and b/CPE435/Lab13/Lab13.pdf differ diff --git a/CPE435/Lab2/1642876381.png b/CPE435/Lab2/1642876381.png new file mode 100644 index 0000000..e35a9b9 Binary files /dev/null and b/CPE435/Lab2/1642876381.png differ diff --git a/CPE435/Lab2/1642889504.png b/CPE435/Lab2/1642889504.png new file mode 100644 index 0000000..9494502 Binary files /dev/null and b/CPE435/Lab2/1642889504.png differ diff --git a/CPE435/Lab2/1642890159.png b/CPE435/Lab2/1642890159.png new file mode 100644 index 0000000..12b8ae9 Binary files /dev/null and b/CPE435/Lab2/1642890159.png differ diff --git a/CPE435/Lab2/1642890503.png b/CPE435/Lab2/1642890503.png new file mode 100644 index 0000000..bd7ca1d Binary files /dev/null and b/CPE435/Lab2/1642890503.png differ diff --git a/CPE435/Lab2/1642892271.png b/CPE435/Lab2/1642892271.png new file mode 100644 index 0000000..143e6fa Binary files /dev/null and b/CPE435/Lab2/1642892271.png differ diff --git a/CPE435/Lab2/Lab02.pdf b/CPE435/Lab2/Lab02.pdf new file mode 100644 index 0000000..4c2c3a6 Binary files /dev/null and b/CPE435/Lab2/Lab02.pdf differ diff --git a/CPE435/Lab2/Lab02_ex1Output.png b/CPE435/Lab2/Lab02_ex1Output.png new file mode 100644 index 0000000..0fc3f71 Binary files /dev/null and b/CPE435/Lab2/Lab02_ex1Output.png differ diff --git a/CPE435/Lab2/Lab2_ex1Output.png b/CPE435/Lab2/Lab2_ex1Output.png new file mode 100644 index 0000000..0fc3f71 Binary files /dev/null and b/CPE435/Lab2/Lab2_ex1Output.png differ diff --git a/CPE435/Lab2/Lab2_ex3Output.png b/CPE435/Lab2/Lab2_ex3Output.png new file mode 100644 index 0000000..e35a9b9 Binary files /dev/null and b/CPE435/Lab2/Lab2_ex3Output.png differ diff --git a/CPE435/Lab2/Lab2_ex4Output.png b/CPE435/Lab2/Lab2_ex4Output.png new file mode 100644 index 0000000..9494502 Binary files /dev/null and b/CPE435/Lab2/Lab2_ex4Output.png differ diff --git a/CPE435/Lab2/Report 2.pdf b/CPE435/Lab2/Report 2.pdf new file mode 100644 index 0000000..a1aedd8 Binary files /dev/null and b/CPE435/Lab2/Report 2.pdf differ diff --git a/CPE435/Lab2/a.out b/CPE435/Lab2/a.out new file mode 100755 index 0000000..c942e8a Binary files /dev/null and b/CPE435/Lab2/a.out differ diff --git a/CPE435/Lab2/lab2_ex1 b/CPE435/Lab2/lab2_ex1 new file mode 100755 index 0000000..f7c7ccf Binary files /dev/null and b/CPE435/Lab2/lab2_ex1 differ diff --git a/CPE435/Lab2/lab2_ex1.cpp b/CPE435/Lab2/lab2_ex1.cpp new file mode 100644 index 0000000..846fcbb --- /dev/null +++ b/CPE435/Lab2/lab2_ex1.cpp @@ -0,0 +1,23 @@ +using namespace std; +#include +#include +#include +#include +#include + +int main(int argc, char * argv[]) +{ + int val = 0; + int pid; + pid = fork(); + if (pid == 0 ) /* we are the child */ + { + val=+2; + cout << "Id: " << getpid() << "\tVal: " << val << endl; + } + else //(getpid > 0) // we are the parent + { + val=+5; + cout << "Id: " << getpid() << "\tVal: " << val << endl; + } +} diff --git a/CPE435/Lab2/lab2_ex2 b/CPE435/Lab2/lab2_ex2 new file mode 100755 index 0000000..59e25d5 Binary files /dev/null and b/CPE435/Lab2/lab2_ex2 differ diff --git a/CPE435/Lab2/lab2_ex2.cpp b/CPE435/Lab2/lab2_ex2.cpp new file mode 100644 index 0000000..bfa1dc5 --- /dev/null +++ b/CPE435/Lab2/lab2_ex2.cpp @@ -0,0 +1,61 @@ +using namespace std; +#include +#include +#include +#include +#include + +void mult(int x, int y, int id); + +void sub(int x, int y, int id); + +void add(int x, int y, int id); + +int main(int argc, char * argv[]) +{ + int pid; + cout << "Parent's PID: " << getpid() << endl; + pid = fork(); + if (pid == 0 ) // child1 + { + int pidChild2; + sub(4, 5, getpid()); + + // child1 subtracts numbers + pidChild2 = fork(); // child2 + if (pidChild2 == 0) + { + add(4, 5, getpid()); + exit(0); + } + else // child1 + { + wait(0); + mult(4, 5, getpid()); + exit(0); + } + } + else // parent of both + { + wait(0); + } +} + +void mult(int x, int y, int id) +{ + cout << "4*5 = " << x*y << endl; + cout << "Child1's ID: " << id << endl; +} + +void sub(int x, int y, int id) +{ + cout << "4-5 = " << x-y << endl; + cout << "Child1's ID: " << id << endl; +} + + +void add(int x, int y, int id) +{ + cout << "4+5 = " << x+y << endl; + cout << "Child2's ID: " << id << endl; +} diff --git a/CPE435/Lab2/lab2_ex3 b/CPE435/Lab2/lab2_ex3 new file mode 100755 index 0000000..366e818 Binary files /dev/null and b/CPE435/Lab2/lab2_ex3 differ diff --git a/CPE435/Lab2/lab2_ex3.cpp b/CPE435/Lab2/lab2_ex3.cpp new file mode 100644 index 0000000..374023d --- /dev/null +++ b/CPE435/Lab2/lab2_ex3.cpp @@ -0,0 +1,28 @@ +using namespace std; +#include +#include +#include +#include +int main(int argc, char * argv[]) +{ + int proc; + int x; + cout << "Please enter a number of processes to spawn: "; + cin >> proc; + if((proc % 2) != 0) + { + cout << "Odd number entered. Please enter an even number. Exiting now." << endl; + return(0); + } + + for(int i=0; i +#include +#include +#include +int main(int argc, char * argv[]) +{ + +} diff --git a/CPE435/Lab2/lab2_ex4_orphan b/CPE435/Lab2/lab2_ex4_orphan new file mode 100755 index 0000000..b0b4b18 Binary files /dev/null and b/CPE435/Lab2/lab2_ex4_orphan differ diff --git a/CPE435/Lab2/lab2_ex4_orphan.cpp b/CPE435/Lab2/lab2_ex4_orphan.cpp new file mode 100644 index 0000000..ae75ff4 --- /dev/null +++ b/CPE435/Lab2/lab2_ex4_orphan.cpp @@ -0,0 +1,22 @@ +using namespace std; +#include +#include +#include +#include +#include +int main(int argc, char * argv[]) +{ + int pid; + pid = fork(); + if (pid == 0) { + printf("I am the child, my process id is %d\n",getpid( )); + printf("the child’s parent process id is %d\n",getppid( )); + sleep(20); + printf("I am the child, my process id is %d\n",getpid( )); + printf("I am the child, parent's process id is %d\n",getppid( )); + } else + { + printf("I am the parent, my process id is %d\n",getpid( )); + printf("the parents parent process id is %d\n",getppid( )); + } +} diff --git a/CPE435/Lab2/lab2_ex4_sleeping b/CPE435/Lab2/lab2_ex4_sleeping new file mode 100755 index 0000000..c942e8a Binary files /dev/null and b/CPE435/Lab2/lab2_ex4_sleeping differ diff --git a/CPE435/Lab2/lab2_ex4_sleeping.cpp b/CPE435/Lab2/lab2_ex4_sleeping.cpp new file mode 100644 index 0000000..2a2997b --- /dev/null +++ b/CPE435/Lab2/lab2_ex4_sleeping.cpp @@ -0,0 +1,11 @@ +using namespace std; +#include +#include +#include +#include +#include +int main(int argc, char * argv[]) +{ + sleep(50); + printf("Hello World"); +} diff --git a/CPE435/Lab2/lab2_ex4_zombie b/CPE435/Lab2/lab2_ex4_zombie new file mode 100755 index 0000000..db97d23 Binary files /dev/null and b/CPE435/Lab2/lab2_ex4_zombie differ diff --git a/CPE435/Lab2/lab2_ex4_zombie.cpp b/CPE435/Lab2/lab2_ex4_zombie.cpp new file mode 100644 index 0000000..29958d7 --- /dev/null +++ b/CPE435/Lab2/lab2_ex4_zombie.cpp @@ -0,0 +1,14 @@ +using namespace std; +#include +#include +#include +#include +#include +int main(int argc, char * argv[]) +{ + if (fork ( ) > 0) + { + printf("parent\n"); + sleep(50); + } +} diff --git a/CPE435/Lab2/out b/CPE435/Lab2/out new file mode 100755 index 0000000..b0b4b18 Binary files /dev/null and b/CPE435/Lab2/out differ diff --git a/CPE435/Lab2/sleeping.png b/CPE435/Lab2/sleeping.png new file mode 100644 index 0000000..143e6fa Binary files /dev/null and b/CPE435/Lab2/sleeping.png differ diff --git a/CPE435/Lab2/zombie.png b/CPE435/Lab2/zombie.png new file mode 100644 index 0000000..12b8ae9 Binary files /dev/null and b/CPE435/Lab2/zombie.png differ diff --git a/CPE435/Lab3/Lab03.pdf b/CPE435/Lab3/Lab03.pdf new file mode 100644 index 0000000..8f8eaab Binary files /dev/null and b/CPE435/Lab3/Lab03.pdf differ diff --git a/CPE435/Lab3/Study_Lab03.pdf b/CPE435/Lab3/Study_Lab03.pdf new file mode 100644 index 0000000..d12475d Binary files /dev/null and b/CPE435/Lab3/Study_Lab03.pdf differ diff --git a/CPE435/Lab3/Study_Lab03.pptx b/CPE435/Lab3/Study_Lab03.pptx new file mode 100644 index 0000000..72dfe39 Binary files /dev/null and b/CPE435/Lab3/Study_Lab03.pptx differ diff --git a/CPE435/Lab3/a.txt b/CPE435/Lab3/a.txt new file mode 100644 index 0000000..8bd328b --- /dev/null +++ b/CPE435/Lab3/a.txt @@ -0,0 +1,26 @@ +total 1.2M +drwx------ 2 anw0044 student 4.0K Feb 8 20:59 . +drwx------ 7 anw0044 student 4.0K Feb 1 16:17 .. +-rw------- 1 anw0044 student 0 Feb 8 21:00 a.txt +-rw------- 1 anw0044 student 189 Feb 8 20:17 a.txt + +-rwx------ 1 anw0044 student 8.3K Feb 6 21:55 demo1 +-rw------- 1 anw0044 student 1.6K Feb 7 19:31 demo1.c +-rwx------ 1 anw0044 student 9.8K Feb 8 09:12 demo2 +-rw------- 1 anw0044 student 1.3K Feb 8 09:12 demo2.c +-rwx------ 1 anw0044 student 8.6K Feb 6 21:56 demo3 +-rw------- 1 anw0044 student 1.7K Feb 7 19:31 demo3.c +-rwx------ 1 anw0044 student 8.4K Feb 7 01:09 demo4 +-rw------- 1 anw0044 student 1.7K Feb 8 01:15 demo4.c +-rwx------ 1 anw0044 student 8.5K Feb 6 21:56 demo5 +-rw------- 1 anw0044 student 1.3K Feb 7 19:31 demo5.c +-rwx------ 1 anw0044 student 8.4K Feb 8 02:17 example2 +-rw------- 1 anw0044 student 271 Jan 27 16:19 example2.c +-rwx------ 1 anw0044 student 8.5K Feb 8 02:17 example3 +-rw------- 1 anw0044 student 536 Jan 27 16:19 example3.c +-rw------- 1 anw0044 student 121K Jan 27 16:19 Lab03.pdf +-rwx------ 1 anw0044 student 17K Feb 8 20:59 shell +-rw------- 1 anw0044 student 7.4K Feb 8 20:58 shell.c +-rw------- 1 anw0044 student 417K Jan 27 16:19 Study_Lab03.pdf +-rw------- 1 anw0044 student 482K Jan 27 16:19 Study_Lab03.pptx +-rw------- 1 anw0044 student 94 Feb 8 09:12 test.txt diff --git a/CPE435/Lab3/demo1 b/CPE435/Lab3/demo1 new file mode 100755 index 0000000..edf4270 Binary files /dev/null and b/CPE435/Lab3/demo1 differ diff --git a/CPE435/Lab3/demo1.c b/CPE435/Lab3/demo1.c new file mode 100644 index 0000000..6686700 --- /dev/null +++ b/CPE435/Lab3/demo1.c @@ -0,0 +1,44 @@ +/* +Written By: Prawar Poudel +This program is intended to showcase the use of strtok() function +Please study about the strtok function first and compare the three outputs that you will receive here +*/ +#include +#include +#include +int main(int argc,char* argv[]) +{ + printf("Demo Number 1\n"); + printf("================\n"); + char myString[100] = "i,want to break,this string using, both,comma and space"; + //following is the temporary string that I want to keep my char[] read from breaking the above char[] myString + //following breaks based on space character + char *temp; + temp = strtok(myString," "); //include inside "" + while(temp!=NULL) + { + printf("%s\n",temp); + temp = strtok(NULL," "); //include inside "" + } + //following breaks based on comma character + printf("\n\nDemo Number 2\n"); + printf("================\n"); + strcpy(myString,"i,want to break,this string using, both,comma and space"); + temp = strtok(myString,","); //include , inside "" + while(temp!=NULL) + { + printf("%s\n",temp); + temp = strtok(NULL,","); //include , inside "" + } + //following breaks based on space or comma character + printf("\n\nDemo Number 3\n"); + printf("================\n"); + strcpy(myString,"i,want to break,this string using, both,comma and space"); + temp = strtok(myString,", "); //include both space and , inside "" while(temp!=NULL) + while(temp!=NULL) + { + printf("%s\n",temp); + temp = strtok(NULL,", "); //include both space and , inside "" + } + return 0; +} diff --git a/CPE435/Lab3/demo2 b/CPE435/Lab3/demo2 new file mode 100755 index 0000000..b4a3636 Binary files /dev/null and b/CPE435/Lab3/demo2 differ diff --git a/CPE435/Lab3/demo2.c b/CPE435/Lab3/demo2.c new file mode 100644 index 0000000..8c41d41 --- /dev/null +++ b/CPE435/Lab3/demo2.c @@ -0,0 +1,33 @@ +/* +Written By: Prawar Poudel +This program is supposed to demonstrate the execution of dup2() function +Please read the manual page first before jumping to run this program +*/ +#include +#include +#include +#include +#include +int main() +{ + printf("You would expect this to go to your stdout, and it does\n"); + //we will create a file using open function + char myFileName[] = "test.txt"; + //lets open the file by the name of test.txt + int myDescriptor = open(myFileName,O_CREAT|O_RDWR|O_TRUNC,0644); + int id; + //creating a child that redirects the stdout to test.txt + // you can use similar functionality for '>' operator + if((id=fork())==0) + { + //lets call dup2 so that out stdout (second argument) is now copied to (points to) test.txt (first argument) + // what this essentially means is that anything that you send to stdout will be sent to myDescriptor + dup2(myDescriptor,1); //1 is stdout, 0 is stdin and 2 is stderr + printf("You would expect this to go to your stdout, but since we called dup2, this will go to test.txt"); + close(myDescriptor); + exit(0); + }else + wait(0); + printf("This is also printed to the console\n"); + return 0; +} diff --git a/CPE435/Lab3/demo3 b/CPE435/Lab3/demo3 new file mode 100755 index 0000000..ff2137c Binary files /dev/null and b/CPE435/Lab3/demo3 differ diff --git a/CPE435/Lab3/demo3.c b/CPE435/Lab3/demo3.c new file mode 100644 index 0000000..2d834f9 --- /dev/null +++ b/CPE435/Lab3/demo3.c @@ -0,0 +1,49 @@ +/* +Written By: Prawar Poudel +This program demonstrates the use of pipe() function in C +Please man pipe and have understanding before going through this code +Pipe passes information from one process to another, similar to water-pipes there is a read-end and a write-end of pipe +*/ +#include +#include +#include +#include +#include +int main() +{ + int myPipingDescriptors[2]; + if(pipe(myPipingDescriptors)==-1) + { + printf("Error in calling the piping function\n"); + exit(0); + } + //at this point two pipe ends are created + // one is the read end and other is write end + // [0] will be the read end, [1] will be the write end + //now lets fork two process where one will make use of the read end and other will make + // use of write end + // they can communicate this way through the pipe + int id; + if((id=fork())==0) + { + dup2(myPipingDescriptors[1],1); //second argument 1 is stdout + close(myPipingDescriptors[0]); //read end is unused to lets close it + //this following statement will not be printed since we have copied the stdout to write end of pipe + printf("I am child, and sending this message.\n"); + exit(0); + }else if (id>0) + { + wait(0); + char myRead[100]; + //basically what's written to the write-end of pipe stays there until we read the read-end of pipe + read(myPipingDescriptors[0],myRead,37); + printf("I am parent. I read following statement\n\t%s\n",myRead); close(myPipingDescriptors[1]); + }else + { + printf("Failed to fork so terminating the process\n"); + exit(-1); + } + close(myPipingDescriptors[0]); + close(myPipingDescriptors[1]); + return 0; +} diff --git a/CPE435/Lab3/demo4 b/CPE435/Lab3/demo4 new file mode 100755 index 0000000..e9df5b6 Binary files /dev/null and b/CPE435/Lab3/demo4 differ diff --git a/CPE435/Lab3/demo4.c b/CPE435/Lab3/demo4.c new file mode 100644 index 0000000..dcebf18 --- /dev/null +++ b/CPE435/Lab3/demo4.c @@ -0,0 +1,46 @@ +/* +Written By: Prawar Poudel +execvp runs a program that you pass as argument +Please study about the execvp function before going to run this program +After you understand the things, please run and watch them +Please make sure that execvp has the right executable provided +*/ +#include +#include +#include +#include +int main() +{ + char myArgument[100]; + //you can change the content of myArgument using any user typed input using gets() + strcpy(myArgument,"date"); + //execvp expects the arguments to be provided as char[][] + //so please make sure you understand strtok before coming here + //we will use strtok() to break the sequence of command and argument in myArgument to convert to char[][] + char* myBrokenArgs[10]; //this will hold the values after we tokenize + printf("Starting tokenization...\n"); + myBrokenArgs[0] = strtok(myArgument," "); + int counter = 0; + while(myBrokenArgs[counter]!=NULL) + { + counter+=1; + myBrokenArgs[counter] = strtok(NULL," "); + } + myBrokenArgs[counter] = NULL; + printf("\ttokenization complete....\n\nNow executing using execvp\n"); + printf("Following will be the output of execvp\n"); + printf("=======================================\n"); + int id; + //I will spawn a child that will run my execvp command + if((id=fork())==0) + execvp(myBrokenArgs[0],myBrokenArgs); + else if(id<0) + printf("Failed to make child...\n"); + else + { + //parent shall wait until the child is killed + wait(0); + printf("=======================================\n"); printf("Completed execution\n"); + } + return 0; +} diff --git a/CPE435/Lab3/demo5 b/CPE435/Lab3/demo5 new file mode 100755 index 0000000..6ebf0d4 Binary files /dev/null and b/CPE435/Lab3/demo5 differ diff --git a/CPE435/Lab3/demo5.c b/CPE435/Lab3/demo5.c new file mode 100644 index 0000000..b6702f0 --- /dev/null +++ b/CPE435/Lab3/demo5.c @@ -0,0 +1,57 @@ +/* + program runs "ls | sort" command using 2 child processes + + dup2 is used to duplicate an old file descriptor into a new one + normal file descriptor table + + 0 [ standard input ] + 1 [ standard output ] + 2 [ standard error ] + + pipe is used to communicate between child processes + unused ends of the pipe should be closed if unused + in that process + + + +*/ +#include +#include +#include +#include +#include + +int main() +{ + int fds[2]; + pipe(fds); + // Child 1 will duplicate downstream into stdin + if(fork() == 0) + { + dup2(fds[0], 0); // normally 0 is for stdin + // will now read to fds[0] + // end of pipe + close(fds[1]); // close other end of pipe + execlp("sort", "sort", 0); + //execlp("wc", "wc", "-l", 0); // Note the first argument is the command + // After it are the arguments including + // original command + } + // Child2 duplicates upstream into stdout + else if (fork() == 0) + { + dup2(fds[1], 1); // normally 1 is for stdout + // will now write to fds[1] + // end of pipe + close(fds[0]); // close other end of pipe + execlp("ls", "ls", 0); + } + // Parent + else + { + close(fds[0]); + close(fds[1]); + wait(0); + wait(0); + } +} diff --git a/CPE435/Lab3/example2 b/CPE435/Lab3/example2 new file mode 100755 index 0000000..6aa712d Binary files /dev/null and b/CPE435/Lab3/example2 differ diff --git a/CPE435/Lab3/example2.c b/CPE435/Lab3/example2.c new file mode 100644 index 0000000..64d8ea5 --- /dev/null +++ b/CPE435/Lab3/example2.c @@ -0,0 +1,14 @@ +#include +#include +#include +#include + +int main() +{ + char *cmd[] = {"who", "ls", "date"}; + int i; + printf("0=who, 1=ls, 2=date :"); + scanf("%d", &i); + execlp(cmd[i], cmd[i], 0); + printf("command not found\n"); /*exec failed*/ +} diff --git a/CPE435/Lab3/example3 b/CPE435/Lab3/example3 new file mode 100755 index 0000000..b50fe0c Binary files /dev/null and b/CPE435/Lab3/example3 differ diff --git a/CPE435/Lab3/example3.c b/CPE435/Lab3/example3.c new file mode 100644 index 0000000..13d3f82 --- /dev/null +++ b/CPE435/Lab3/example3.c @@ -0,0 +1,28 @@ +#include +#include +#include +#include +#include + +int main() +{ + char *cmd[] = {"who", "ls", "date", "notacommand"}; + int i; + while(1) + { + printf("0=who, 1=ls, 2=date, 3=notacommand :"); + scanf("%d", &i); + if(fork() == 0) + { + execlp(cmd[i], cmd[i], 0); // If execlp runs correctly, control + // is transfer to the new program + printf("command not found\n"); // exec failed + exit(1); + } + else + { + // Parent waits for child process to complete + wait(0); + } + } +} diff --git a/CPE435/Lab3/shell b/CPE435/Lab3/shell new file mode 100755 index 0000000..135e86d Binary files /dev/null and b/CPE435/Lab3/shell differ diff --git a/CPE435/Lab3/shell.c b/CPE435/Lab3/shell.c new file mode 100644 index 0000000..2fd7be5 --- /dev/null +++ b/CPE435/Lab3/shell.c @@ -0,0 +1,278 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +char* substr(const char *src, int m, int n); +void pipeFunc(char *command1, char *command2); + +int main() +{ + while (1) + { + printf("My Shell\n"); + printf(">> "); + //following is the temporary string that I want to keep my char[] read from breaking the above char[] myString + //following breaks based on space character + char commandStr[100], commandStrFull[100]; + char *temp; + char *temp2; + char temp3[100]; + //strcpy(commandStr, "exit"); + fgets(commandStr, 100, stdin); + //strcpy(commandStr, "ls -l > a.txt"); + strcpy(commandStrFull,commandStr); + char *filename; + int flag = 0; + // exit program if command is exit + if(strcmp(commandStr, "exit\n")==0) + { + exit(-1); + } + + int redir=0; + int redirIndex; + int pipeNum=0; + int single=0; + char* redirCheckTwo=NULL; + char* command2; + char* command1; + char* pipeCheck = strchr(commandStr, '|'); + char* redirCheck = strchr(commandStr, '>'); + if(pipeCheck!=NULL) + { + pipeNum=1; + redirCheckTwo = strchr(commandStr, '>'); + command1 = strrchr(commandStr, '|'); + redirIndex = strcspn(commandStr, ">"); + } + else single=1; + if (redirCheckTwo!=NULL) + { + command1 = strrchr(commandStr, '|'); + redir=1; + } + if(redirCheck!=NULL) redir=1; + //commandStr[strcspn(commandStr, "\n")] = 0; + // pipe or redirect + if (pipeNum==1 || redir==1) + { + temp = strtok(commandStr," "); //include , inside "" + while(temp!=NULL) + { + //printf("%s\n",temp); + if (strcmp(temp,">")==0 && redir==1) + { + filename = strtok(NULL, " "); + //printf("Filename: %s\n", filename); + } + if (strcmp(temp,"|")==0 && pipeCheck!=NULL) + { + command2 = strtok(NULL," >"); + //puts(strchr(temp, '|')); + flag=1; + } + + if (pipeNum==1 || redir==1) + { + temp = strtok(NULL," "); //include , inside "" + } + else temp2 = strtok(NULL," "); //include , inside "" + } + } + // single command is run + if(single==1 && pipeNum==0 && redir==0){ + commandStr[strcspn(commandStr, "\n")] = 0; + //strcpy(temp,commandStr); + + //execvp expects the arguments to be provided as char[][] + //so please make sure you understand strtok before coming here + //we will use strtok() to break the sequence of command and argument in myArgument to convert to char[][] + char* myBrokenArgs[10]; //this will hold the values after we tokenize + //printf("Starting tokenization...\n"); + myBrokenArgs[0] = strtok(commandStr," "); + int counter = 0; + while(myBrokenArgs[counter]!=NULL) + { + counter+=1; + myBrokenArgs[counter] = strtok(NULL," "); + } + myBrokenArgs[counter] = NULL; + //printf("\ttokenization complete....\n\nNow executing using execvp\n"); + //printf("Following will be the output of execvp\n"); + //printf("=======================================\n"); + if ((strcmp("ls",myBrokenArgs[0]) ==0) && single==1) + { + int id; + //I will spawn a child that will run my execvp command + if((id=fork())==0) + execvp(myBrokenArgs[0],myBrokenArgs); + else if(id<0) + printf("Failed to make child...\n"); + else + { + //parent shall wait until the child is killed + wait(0); + printf("=======================================\n"); + printf("Completed execution\n"); + } + } + else if (strcmp("date",myBrokenArgs[0]) ==0) + { + int id; + //I will spawn a child that will run my execvp command + if((id=fork())==0) + execvp(myBrokenArgs[0],myBrokenArgs); + else if(id<0) + printf("Failed to make child...\n"); + else + { + //parent shall wait until the child is killed + wait(0); + printf("=======================================\n"); + printf("Completed execution\n"); + } + } + else if ((strcmp("ps",myBrokenArgs[0]) ==0)) + { + int id; + //I will spawn a child that will run my execvp command + if((id=fork())==0) + execvp(myBrokenArgs[0],myBrokenArgs); + else if(id<0) + printf("Failed to make child...\n"); + else + { + //parent shall wait until the child is killed + wait(0); + printf("=======================================\n"); + printf("Completed execution\n"); + } + } + } + // pipe is used + if (pipeNum==1 && redirCheck==NULL && single==0) + { + strcpy(commandStrFull, "ls -lah | wc -l"); + int size = strcspn(commandStrFull, "|"); + int end = strcspn(commandStrFull, "\0"); + int beg = strcspn(commandStrFull, "|"); + char* command2 = substr(commandStrFull, beg+2, end); + + end = strcspn(commandStrFull, "|"); + char* command1 = substr(commandStrFull, 0, end-1); + + char* command1Args[10]; //this will hold the values after we tokenize + //printf("Starting tokenization...\n"); + command1Args[0] = strtok(command1," "); + int counter = 0; + while(command1Args[counter]!=NULL) + { + counter+=1; + command1Args[counter] = strtok(NULL,"\0"); + } + command1Args[counter] = NULL; + + char* command2Args[10]; //this will hold the values after we tokenize + //printf("Starting tokenization...\n"); + command2Args[0] = strtok(command2," "); + counter = 0; + while(command2Args[counter]!=NULL) + { + counter+=1; + command2Args[counter] = strtok(NULL," "); + } + command2Args[counter] = NULL; + + int fds[2]; + pipe(fds); + // Child 1 will duplicate downstream into stdin + if(fork() == 0) + { + dup2(fds[0], 0); // normally 0 is for stdin + // will now read to fds[0] + // end of pipe + close(fds[1]); // close other end of pipe + execlp(command2Args[0] ,command2Args[0], command2Args, 0); + //execlp("wc", "wc", "-l", 0); // Note the first argument is the command + // After it are the arguments including + // original command + } + // Child2 duplicates upstream into stdout + else if (fork() == 0) + { + dup2(fds[1], 1); // normally 1 is for stdout + // will now write to fds[1] + // end of pipe + close(fds[0]); // close other end of pipe + execlp(command1Args[0],command1Args[0], command1Args, 0); + } + // Parent + else + { + close(fds[0]); + close(fds[1]); + wait(0); + wait(0); + } + } + if (pipeNum==0 && redir==1) + { + int end = strcspn(commandStrFull, ">"); + int beg = strcspn(commandStrFull, "|"); + char* command1 = substr(commandStrFull, 0, end-1); + char* myBrokenArgs[10]; //this will hold the values after we tokenize + printf("Starting tokenization...\n"); + myBrokenArgs[0] = strtok(command1," "); + int counter = 0; + while(myBrokenArgs[counter]!=NULL) + { + counter+=1; + myBrokenArgs[counter] = strtok(NULL," "); + } + myBrokenArgs[counter] = NULL; + + int myDescriptor = open(filename,O_CREAT|O_RDWR|O_TRUNC,0644); + int id; + //creating a child that redirects the stdout to test.txt + // you can use similar functionality for '>' operator + if((id=fork())==0) + { + //lets call dup2 so that out stdout (second argument) is now copied to (points to) test.txt (first argument) + // what this essentially means is that anything that you send to stdout will be sent to myDescriptor + dup2(myDescriptor,1); //1 is stdout, 0 is stdin and 2 is stderr + execvp(myBrokenArgs[0],myBrokenArgs); + close(myDescriptor); + exit(0); + }else + wait(0); + printf("Completed execution.\n"); + } + } + return 0; + +} + +void pipeFunc(char *command1, char *command2) +{ + +} + +char* substr(const char *src, int m, int n) +{ + // get the length of the destination string + int len = n - m; + + // allocate (len + 1) chars for destination (+1 for extra null character) + char *dest = (char*)malloc(sizeof(char) * (len + 1)); + + // start with m'th char and copy `len` chars into the destination + strncpy(dest, (src + m), len); + + // return the destination string + return dest; +} \ No newline at end of file diff --git a/CPE435/Lab3/test.txt b/CPE435/Lab3/test.txt new file mode 100644 index 0000000..214bb13 --- /dev/null +++ b/CPE435/Lab3/test.txt @@ -0,0 +1 @@ +You would expect this to go to your stdout, but since we called dup2, this will go to test.txt \ No newline at end of file diff --git a/CPE435/Lab4/IPC_SharedMemory.pdf b/CPE435/Lab4/IPC_SharedMemory.pdf new file mode 100644 index 0000000..803d8e5 Binary files /dev/null and b/CPE435/Lab4/IPC_SharedMemory.pdf differ diff --git a/CPE435/Lab4/IPC_SharedMemory.pptx b/CPE435/Lab4/IPC_SharedMemory.pptx new file mode 100644 index 0000000..9d9b876 Binary files /dev/null and b/CPE435/Lab4/IPC_SharedMemory.pptx differ diff --git a/CPE435/Lab4/Lab04.pdf b/CPE435/Lab4/Lab04.pdf new file mode 100644 index 0000000..407010b Binary files /dev/null and b/CPE435/Lab4/Lab04.pdf differ diff --git a/CPE435/Lab4/Process_A b/CPE435/Lab4/Process_A new file mode 100755 index 0000000..c28b852 Binary files /dev/null and b/CPE435/Lab4/Process_A differ diff --git a/CPE435/Lab4/Process_A.c b/CPE435/Lab4/Process_A.c new file mode 100644 index 0000000..5253bb5 --- /dev/null +++ b/CPE435/Lab4/Process_A.c @@ -0,0 +1,73 @@ +/*********************************************************************************** + Code Inherited from Anon + Massively Modified by Prawar Poudel, 3 Feb 2020 (pp0030@uah.edu) + Modified by Noah Eid, 30 Jan 2021 (nae0005@uah.edu) +************************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "line.h" + +/* + Process A creates a shared memory segment + Process A attaches a pointer to the shared memory segment created + .. then it writes an integer value and a character value to it + Process A will then print that character every 4 seconds to terminal + .. a number of times + + Process B will can also access the shared memory segment and change + .. the character being printed + + After the printing operation is done, Process A will detach and delete the shared memory segment + +*/ +main(void) +{ + int i, id ; + struct info *ctrl; + + // create the shared memory segment + // .. id is the file identifier of the shared memory segment + // .. if the key is shared, any process can attach to this shared memory segment + // .. 0666 is the file permission for the shared memory segment + if ( (id = shmget( key,MSIZ,IPC_CREAT | 0666) ) < 0 ) + { + //error…; + printf("error 1\n"); + exit(1) ; + } + + // attach a local pointer to the shared memory segment created + // .. exit if fails + if ( (ctrl = (struct info *) shmat( id, 0, 0)) <= (struct info *) (0) ) + { + //error … ; + printf("error 2\n"); + exit(1) ; + } + + // put some initial data in the shared memory so that we will just print the things before ProcessB is run + ctrl->c = 'a'; + ctrl->length = 10; + + // print line every 4 seconds + for (i = 0 ; i length ; i++ ) + { + putchar (ctrl->c); + putchar ('\n'); + sleep(4); + } + + //now detach the pointer from the shared memory + shmdt(ctrl); + //let us delete the shared memory + shmctl(id,IPC_RMID,NULL); + + //job done +} + diff --git a/CPE435/Lab4/Process_B b/CPE435/Lab4/Process_B new file mode 100755 index 0000000..c8f4e7a Binary files /dev/null and b/CPE435/Lab4/Process_B differ diff --git a/CPE435/Lab4/Process_B.c b/CPE435/Lab4/Process_B.c new file mode 100644 index 0000000..4aa8963 --- /dev/null +++ b/CPE435/Lab4/Process_B.c @@ -0,0 +1,57 @@ +/*********************************************************************************** + Code Inherited from Anon + Massively Modified by Prawar Poudel, 3 Feb 2020 (pp0030@uah.edu) + Modified by Noah Eid, 30 Jan 2021 (nae0005@uah.edu) +************************************************************************************/ +#include +#include +#include +#include +#include + +#include "line.h" + + +/* + + Process B can change the contents of the shared memory that Process A is using + ./ProcessB + +*/ + +main(int argc, char *argv[]) +{ + int id ; + struct info *ctrl; + + if (argc < 3) + { + //error…; + exit(3); + } + // get the id of the already created shared memory segment + // .. function to create is same as getting id of the already created shared memory segment + if ( (id = shmget( key,MSIZ, 0 )) < 0 ) + { + //error … ; + exit(1) ; + } + + // attach a local pointer to the shared memory + ctrl = (struct info *) shmat( id, 0, 0); + if ( ctrl <= (struct info *) (0) ) + { + //error … ; + exit(1) ; + } + + /* copy command line data to shared memory */ + ctrl->c = argv[1][0] ; + ctrl->length = atoi(argv[2]); + + + //detach the pointer from the shared memory + // .. we do not need to delete here, can be done in either of the process + shmdt(ctrl); + exit(0); + } diff --git a/CPE435/Lab4/Process_C.c b/CPE435/Lab4/Process_C.c new file mode 100644 index 0000000..4bf994f --- /dev/null +++ b/CPE435/Lab4/Process_C.c @@ -0,0 +1,89 @@ +/*********************************************************************************** + Code Inherited from Anon + Massively Modified by Prawar Poudel, 3 Feb 2020 (pp0030@uah.edu) +************************************************************************************/ + +#include +#include +#include +#include +#include + +#include "header.h" + +/* + Process C creates a shared memory segment + Process C attaches a pointer to the shared memory segment created + .. then it writes an integer value and a character value to it + .. it prints the character value for the integer number of times + .. then it waits on Process D to update the value of integer and the character + .. .. this will be indicated by the flag value being set to 1 by Process D + .. after the same printing operation is done, Process C will detach and delete the shared memory segment + +*/ +main(void) +{ + int i, id ; + struct info *ctrl; + + // create the shared memory segment + // .. id is the file identifier of the shared memory segment + // .. if the key is shared, any process can attach to this shared memory segment + // .. 0666 is the file permission for the shared memory segment + if ( (id = shmget( key,MSIZ,IPC_CREAT | 0666) ) < 0 ) + { + //error…; + printf("error 1\n"); + exit(1) ; + } + + // attach a local pointer to the shared memory segment created + // .. exit if fails + if ( (ctrl = (struct info *) shmat( id, 0, 0)) <= (struct info *) (0) ){ + //error … ; + printf("error 2\n"); + exit(1) ; } + + // put some initial data in the shared memory so that we will just print the things before Process D is run + ctrl->c = 'a'; + ctrl->length = 10; + ctrl->flag = 0; + + // print the character ctrl->c for ctrl->length times in a single line + for (i = 0 ; i length ; i++ ) + { + putchar (ctrl->c); + putchar (' '); + } + putchar('\n'); + + // flushing stdout just in case + fflush(stdout); + + // signal Process D that Process C is ready for next round, which will be printed below + ctrl->flag = 2; + + // wait for the flag to be set in processB to 1 + // .. flag is 0 right now + // .. once processB starts to run, it will set the flag to 1 + while(ctrl->flag!=1); + + + // print the character ctrl->c for ctrl->length times in a single line + for (i = 0 ; i length ; i++ ) + { + putchar (ctrl->c); + putchar (' '); + } + putchar ('\n'); + // flushing stdout just in case + fflush(stdout); + + //now detach the pointer from the shared memory + shmdt(ctrl); + //let us delete the shared memory + shmctl(id,IPC_RMID,NULL); + + //job done +} + diff --git a/CPE435/Lab4/Process_D.c b/CPE435/Lab4/Process_D.c new file mode 100644 index 0000000..e5a4c6a --- /dev/null +++ b/CPE435/Lab4/Process_D.c @@ -0,0 +1,51 @@ +/*********************************************************************************** + Code Inherited from Anon + Massively Modified by Prawar Poudel, 3 Feb 2020 (pp0030@uah.edu) +************************************************************************************/ +#include +#include +#include +#include +#include + +#include "header.h" + +main(int argc, char *argv[]) +{ + int id ; + struct info *ctrl; + + if (argc < 3) + { + //error…; + exit(3); + } + // get the id of the already created shared memory segment + // .. function to create is same as getting id of the already created shared memory segment + // .. notice the difference between the flags used in Process C and Process D + if ( (id = shmget( key,MSIZ, 0 )) < 0 ) + { + //error … ; + exit(1) ; + } + + // attach a local pointer to the shared memory + ctrl = (struct info *) shmat( id, 0, 0); + if ( ctrl <= (struct info *) (0) ) + { + //error … ; + exit(1) ; + } + // wait until Process C is ready to receive from process D + while(ctrl->flag==0); + + /* copy command line data to shared memory */ + ctrl->c = argv[1][0] ; + ctrl->length = atoi(argv[2]); + ctrl->flag = 1; + + //detach the pointer from the shared memory + // .. we do not need to delete here, can be done in either of the process + shmdt(ctrl); + exit(0); + } diff --git a/CPE435/Lab4/header.h b/CPE435/Lab4/header.h new file mode 100644 index 0000000..cc9021e --- /dev/null +++ b/CPE435/Lab4/header.h @@ -0,0 +1,7 @@ +struct info { + char c; + int length; + char flag; +}; +key_t key = 1243 ; +#define MSIZ sizeof(struct info) diff --git a/CPE435/Lab4/info.h b/CPE435/Lab4/info.h new file mode 100644 index 0000000..a4d4d3a --- /dev/null +++ b/CPE435/Lab4/info.h @@ -0,0 +1,8 @@ +struct info +{ + float value1, value2; + float sum; + int flag; +}; +#define KEY ((key_t)(1234)) +#define MSIZ sizeof(struct info) diff --git a/CPE435/Lab4/line.h b/CPE435/Lab4/line.h new file mode 100644 index 0000000..624fe5b --- /dev/null +++ b/CPE435/Lab4/line.h @@ -0,0 +1,6 @@ +struct info { + char c; + int length; +}; +#define key ((key_t)(1243)) +#define MSIZ sizeof(struct info) diff --git a/CPE435/Lab4/outputForReport.png b/CPE435/Lab4/outputForReport.png new file mode 100644 index 0000000..e6143e8 Binary files /dev/null and b/CPE435/Lab4/outputForReport.png differ diff --git a/CPE435/Lab4/process1 b/CPE435/Lab4/process1 new file mode 100755 index 0000000..aa051c9 Binary files /dev/null and b/CPE435/Lab4/process1 differ diff --git a/CPE435/Lab4/process1.c b/CPE435/Lab4/process1.c new file mode 100644 index 0000000..d3cdaee --- /dev/null +++ b/CPE435/Lab4/process1.c @@ -0,0 +1,69 @@ +#include +#include +#include +#include +#include + +#include "info.h" + + +main(void) +{ + int i, id; + struct info *ctrl; + int v1, v2; + int choice; + + // create the shared memory segment + // .. id is the file identifier of the shared memory segment + // .. if the key is shared, any process can attach to this shared memory segment + // .. 0666 is the file permission for the shared memory segment + if ( (id = shmget( KEY,MSIZ,IPC_CREAT | 0666) ) < 0 ) + { + //error…; + printf("error 1\n"); + exit(1) ; + } + + + // attach a local pointer to the shared memory segment created + // .. exit if fails + if ( (ctrl = (struct info *) shmat( id, 0, 0)) <= (struct info *) (0) ) + { + //error … ; + printf("error 2\n"); + exit(1) ; + } + ctrl->flag=0; + ctrl->value1=0; + ctrl->value1=0; + ctrl->sum=0; + while(ctrl->flag!=-1) + { + //ctrl->flag=0; + // ask for numbers and set flag to 1 + printf("Value 1: "); + scanf("%d",&v1); + printf("Value 2: "); + scanf("%d",&v2); + ctrl->value1 = v1; + ctrl->value2 = v2; + ctrl->flag = 1; + printf("Would you like to continue? Yes(1) or No(-1) : "); + scanf("%d",&choice); + if (choice == -1) + { + ctrl->flag = -1; + } else ctrl->flag=0; + + } + + + //now detach the pointer from the shared memory + shmdt(ctrl); + //let us delete the shared memory + shmctl(id,IPC_RMID,NULL); + + //job done +} + diff --git a/CPE435/Lab4/process2 b/CPE435/Lab4/process2 new file mode 100755 index 0000000..a441bb0 Binary files /dev/null and b/CPE435/Lab4/process2 differ diff --git a/CPE435/Lab4/process2.c b/CPE435/Lab4/process2.c new file mode 100644 index 0000000..56a2252 --- /dev/null +++ b/CPE435/Lab4/process2.c @@ -0,0 +1,46 @@ +#include +#include +#include +#include +#include + +#include "info.h" + +int main() +{ + int id; + struct info *ctrl; + + id = shmget( KEY,MSIZ, 0 ); + // get the id of the already created shared memory segment + // .. function to create is same as getting id of the already created shared memory segment + if ( id < 0 ) + { + //error … ; + exit(1) ; + } + + // attach a local pointer to the shared memory + ctrl = (struct info *) shmat( id, 0, 0); + if ( ctrl <= (struct info *) (0) ) + { + //error … ; + exit(1) ; + } + + while (ctrl->flag!=-1) + { + // if flag is 1, add the numbers from shared memory, set flag to 0 + if (ctrl->flag==1) + { + ctrl->sum = ctrl->value1+ctrl->value2; + printf("Sum: %f + %f = %f\n", ctrl->value1, ctrl->value2, ctrl->sum); + ctrl->flag = 0; + } + } + + //detach the pointer from the shared memory + // .. we do not need to delete here, can be done in either of the process + shmdt(ctrl); + exit(0); +} diff --git a/CPE435/Lab5/IPC Message Queues.pdf b/CPE435/Lab5/IPC Message Queues.pdf new file mode 100644 index 0000000..8d69b0f Binary files /dev/null and b/CPE435/Lab5/IPC Message Queues.pdf differ diff --git a/CPE435/Lab5/IPC Message Queues.pptx b/CPE435/Lab5/IPC Message Queues.pptx new file mode 100644 index 0000000..b84ea80 Binary files /dev/null and b/CPE435/Lab5/IPC Message Queues.pptx differ diff --git a/CPE435/Lab5/Lab05_Assignmnet.pdf b/CPE435/Lab5/Lab05_Assignmnet.pdf new file mode 100644 index 0000000..50cff69 Binary files /dev/null and b/CPE435/Lab5/Lab05_Assignmnet.pdf differ diff --git a/CPE435/Lab5/header.h b/CPE435/Lab5/header.h new file mode 100644 index 0000000..d6e1e11 --- /dev/null +++ b/CPE435/Lab5/header.h @@ -0,0 +1,7 @@ +struct text_message +{ + long mtype; + char mtext[100]; + #define KEY (key_t) 1234 + +}; \ No newline at end of file diff --git a/CPE435/Lab5/lab5Output.png b/CPE435/Lab5/lab5Output.png new file mode 100644 index 0000000..dc8585d Binary files /dev/null and b/CPE435/Lab5/lab5Output.png differ diff --git a/CPE435/Lab5/processA b/CPE435/Lab5/processA new file mode 100755 index 0000000..21e2470 Binary files /dev/null and b/CPE435/Lab5/processA differ diff --git a/CPE435/Lab5/processA.c b/CPE435/Lab5/processA.c new file mode 100644 index 0000000..50c3a0a --- /dev/null +++ b/CPE435/Lab5/processA.c @@ -0,0 +1,74 @@ +#include +#include +#include +#include +#include +#include +#include "header.h" + +main() +{ + char input[100]; + int msid, v; + struct text_message mess; + + // Creating message queue + msid = msgget( KEY, IPC_CREAT | 0666 ); + if ( msid == -1) + { + printf("Queue not joined\n"); + exit(1); + } + + + while (1) + { + printf("Enter a message: "); + fgets(input, sizeof(input), stdin); + input[strcspn(input, "\n")] = 0; + + /* Preparing a message */ + mess.mtype = KEY; + strcpy( mess.mtext, input); + + /* Write a message into queue */ + v = msgsnd (msid, &mess, strlen( input ) + 1, 0); + if ( v < 0 ) + { + printf("\nMessage failed to send\n"); + exit(1); + } + printf("Message sent\n"); + if (strcmp(input,"Exit")==0) + { + msgctl( msid, IPC_RMID, 0); + exit(0); + } + printf("Process will wait\n until Exit\n or new message is received.\n"); + + + + /* Read a message of the given type */ + v = msgrcv( msid, &mess, 100, mess.mtype, 0); // Blocking + + if ( v < 0 ) + { + printf("Error receiving message\n"); + exit(1); + } + else + { + if (strcmp(mess.mtext,"Exit")==0) + { + printf("Exit received\n"); + msgctl( msid, IPC_RMID, 0); + exit(0); + } + else + { + printf("Received: %s\n", mess.mtext); + } + } + } +} + diff --git a/CPE435/Lab5/processB b/CPE435/Lab5/processB new file mode 100755 index 0000000..d60a383 Binary files /dev/null and b/CPE435/Lab5/processB differ diff --git a/CPE435/Lab5/processB.c b/CPE435/Lab5/processB.c new file mode 100644 index 0000000..5d6c2b7 --- /dev/null +++ b/CPE435/Lab5/processB.c @@ -0,0 +1,73 @@ +#include +#include +#include +#include +#include +#include +#include "header.h" + +main() +{ + char input[100]; + int msid, v; + struct text_message mess; + + // Creating message queue + //msid = msgget( KEY, IPC_CREAT | 0644 ); + msid = msgget( KEY, 0 ); + if ( msid == -1) + { + printf("Queue not joined\n"); + exit(1); + } + + while (1) + { + /* Read a message of the given type */ + v = msgrcv( msid, &mess, 100, KEY, 0); // Blocking + + if ( v < 0 ) + { + printf("Error receiving message\n"); + exit(1); + } + else + { + if (strcmp(mess.mtext,"Exit")==0) + { + printf("Exit received\n"); + msgctl( msid, IPC_RMID, 0); + exit(0); + } + else + { + printf("Received: %s\n", mess.mtext); + //msgctl( msid, IPC_RMID, 0); + } + } + printf("Enter a message: "); + fgets(input, sizeof(input), stdin); + input[strcspn(input, "\n")] = 0; + + /* Preparing a message */ + mess.mtype = KEY; + strcpy( mess.mtext, input ); + + /* Write a message into queue */ + v = msgsnd (msid, &mess, strlen( input ) + 1, 0); + if ( v < 0 ) + { + printf("\nMessage failed to send\n"); + exit(1); + } + printf("Message sent\n"); + if (strcmp(mess.mtext,"Exit")==0) + { + msgctl( msid, IPC_RMID, 0); + exit(0); + } + printf("Process will wait\n until Exit\n or new message is received.\n"); + + } +} + diff --git a/CPE435/Lab5/receiver b/CPE435/Lab5/receiver new file mode 100755 index 0000000..40e0c58 Binary files /dev/null and b/CPE435/Lab5/receiver differ diff --git a/CPE435/Lab5/receiver.c b/CPE435/Lab5/receiver.c new file mode 100644 index 0000000..ae47738 --- /dev/null +++ b/CPE435/Lab5/receiver.c @@ -0,0 +1,45 @@ +// Adapted form IPC Message Queues slides +// receiver.c +// usage: ./receiver + +#include +#include +#include +#include +#include +#include + +struct text_message +{ + long mtype; + char mtext[100]; + +}; + +main(int argc, char *argv[]) +{ + int msid, v; + struct text_message mess; + + /* Get a message handle */ + msid = msgget( (key_t) atoi ( argv[1] ), 0 ); + if ( msid == -1) + { + printf("Queue not joined\n"); + exit(1); + } + + /* Read a message of the given type */ + v = msgrcv( msid, &mess, 100, atoi( argv[2] ), IPC_NOWAIT ); // Non-blocking + if ( v < 0 ) + { + printf("Error receiving message\n"); + exit(1); + } + else + { + printf("%d %s\n", mess.mtype, mess.mtext); + msgctl( msid, IPC_RMID, 0); + exit(0); + } +} \ No newline at end of file diff --git a/CPE435/Lab5/sender b/CPE435/Lab5/sender new file mode 100755 index 0000000..bdb2ede Binary files /dev/null and b/CPE435/Lab5/sender differ diff --git a/CPE435/Lab5/sender.c b/CPE435/Lab5/sender.c new file mode 100644 index 0000000..5d45b84 --- /dev/null +++ b/CPE435/Lab5/sender.c @@ -0,0 +1,43 @@ +// Adapted form IPC Message Queues Slides +// sender.c +// usage: ./sender + +#include +#include +#include +#include +#include +#include + +struct text_message +{ + long mtype; + char mtext[100]; +}; + +main(int argc, char *argv[]) +{ + int msid, v; + struct text_message mess; + + /* Creating a message queue */ + msid = msgget((key_t) atoi( argv[1] ), IPC_CREAT | 0666 ); + if( msid == -1 ) + { + printf("Failed to create queue\n"); + exit(1); + } + + /* Preparing a message */ + mess.mtype = atoi( argv[2] ); + strcpy( mess.mtext, argv[3] ); + + /* Write a message into queue */ + v = msgsnd (msid, &mess, strlen( argv[3] ) + 1, 0 ); + if ( v < 0 ) + { + printf("Message failed to send\n"); + exit(1); + } + printf("Message sent\n"); +} diff --git a/CPE435/Lab6/D1.c b/CPE435/Lab6/D1.c new file mode 100644 index 0000000..58bae6d --- /dev/null +++ b/CPE435/Lab6/D1.c @@ -0,0 +1,29 @@ +/* +Compile with gcc Lab06_D1.c -o Lab06 -lpthread + +*/ + +#include +#include +#define NUM_THREADS 5 + +void* printHello(void *threadId) +{ + printf("\n%d:Hello World!\n",threadId); + pthread_exit(NULL); +} +int main() +{ + pthread_t threads[NUM_THREADS]; + int rc,t; + for(t=0;t +#include +#include +#define NUM_THREADS 5 + +//the argument that will be sent will be the (int) id +void *simpleThreadFunc(void* argument) +{ + int myId = (int)argument; + printf("My Id is %d\n",myId); + int a = 0; +} + +int main() +{ + //you can create these dynamically also + pthread_t myThreads[NUM_THREADS]; + int status = 0; + int i; + for(i=0;i +#include +#include +#define NUM_THREADS 100 +int mutexProtectedGlobalVariable; +int unprotectedProtectedGlobalVariable; +pthread_mutex_t myMutex; + +//this function will update the value without any protection +void *unprotectedThreadFunc(void* argument) +{ + int i; + for( i=0;i<10000;i++) unprotectedProtectedGlobalVariable++; } + +//this function will update the value without any protection +void *protectedThreadFunc(void* argument) +{ + int i; + pthread_mutex_lock (&myMutex); + for( i=0;i<10000;i++) mutexProtectedGlobalVariable++; pthread_mutex_unlock (&myMutex); +} + +int main() +{ + mutexProtectedGlobalVariable = 0; + unprotectedProtectedGlobalVariable = 0; + int i; + + //you can create these dynamically also + pthread_t myThreads[NUM_THREADS]; + int status = 0; + printf("Calling unprotected set of threads\n"); + + //first set of five threads will call a function that will update the variable unprotected + for(i=0;i +#include +#include +#define NUM_THREADS 5 +#define ARRSIZE 5 +//this value is a global variable, +// but we will store it as thread local, meaning while it is still global the value will can be modified such that the modified value is thread specific +__thread int myVal; +__thread int myArr[ARRSIZE]; + +void printMyVal(int id) +{ + int i; + printf("My value myVal from thread %d is %d\n", id,myVal); + printf("My arr value are\n"); + for( i=0;i +#include +#include +#define NUM_THREADS 5 +#define ARRSIZE 5 + +//in this program we will use a key defined by pthread_key_t to define a key +pthread_key_t myKey; + +void printMyVal(int myId) +{ + printf("Getting specific value for thread %d using key\n",myId); int *myVal = pthread_getspecific(myKey); + printf("\t..The thread local value in thread id %d is %d\n",myId,*myVal); +} + +//the argument that will be sent will be the (int) id +void *simpleThreadFunc(void* argument) +{ + int myId = (int)argument; + //this variable will be thread specific value that we will print from other function + int myVal = myId*100; + printf("Creating the variable ::%d that will be referred to by Key from threadid %d\n",myVal,myId); + if(!pthread_setspecific(myKey,(void*)&myVal)) + {} + else + { + printf("Error in setting specific key in thread id %d\n",myId); + } + printMyVal(myId); +} + +int main() +{ + //you can create these dynamically also + pthread_t myThreads[NUM_THREADS]; + int status = 0; + pthread_key_create(&myKey,NULL); + int i; + for( i=0;i +#include +#define NUM_THREADS 5 + +void* printHello(void *threadId) +{ + printf("\n%d:Hello World!\n",threadId); + pthread_exit(NULL); +} +int main() +{ + pthread_t threads[NUM_THREADS]; + int rc,t; + for(t=0;t +#include +#include +#define NUM_THREADS 5 + +//the argument that will be sent will be the (int) id +void *simpleThreadFunc(void* argument) +{ + int myId = (int)argument; + printf("My Id is %d\n",myId); + int a = 0; +} + +int main() +{ + //you can create these dynamically also + pthread_t myThreads[NUM_THREADS]; + int status = 0; + int i; + for(i=0;i +#include +#include +#define NUM_THREADS 100 +int mutexProtectedGlobalVariable; +int unprotectedProtectedGlobalVariable; +pthread_mutex_t myMutex; + +//this function will update the value without any protection +void *unprotectedThreadFunc(void* argument) +{ + int i; + for( i=0;i<10000;i++) unprotectedProtectedGlobalVariable++; } + +//this function will update the value without any protection +void *protectedThreadFunc(void* argument) +{ + int i; + pthread_mutex_lock (&myMutex); + for( i=0;i<10000;i++) mutexProtectedGlobalVariable++; pthread_mutex_unlock (&myMutex); +} + +int main() +{ + mutexProtectedGlobalVariable = 0; + unprotectedProtectedGlobalVariable = 0; + int i; + + //you can create these dynamically also + pthread_t myThreads[NUM_THREADS]; + int status = 0; + printf("Calling unprotected set of threads\n"); + + //first set of five threads will call a function that will update the variable unprotected + for(i=0;i +#include +#include +#define NUM_THREADS 5 +#define ARRSIZE 5 +//this value is a global variable, +// but we will store it as thread local, meaning while it is still global the value will can be modified such that the modified value is thread specific +__thread int myVal; +__thread int myArr[ARRSIZE]; + +void printMyVal(int id) +{ + int i; + printf("My value myVal from thread %d is %d\n", id,myVal); + printf("My arr value are\n"); + for( i=0;i +#include +#include +#define NUM_THREADS 5 +#define ARRSIZE 5 + +//in this program we will use a key defined by pthread_key_t to define a key +pthread_key_t myKey; + +void printMyVal(int myId) +{ + printf("Getting specific value for thread %d using key\n",myId); int *myVal = pthread_getspecific(myKey); + printf("\t..The thread local value in thread id %d is %d\n",myId,*myVal); +} + +//the argument that will be sent will be the (int) id +void *simpleThreadFunc(void* argument) +{ + int myId = (int)argument; + //this variable will be thread specific value that we will print from other function + int myVal = myId*100; + printf("Creating the variable ::%d that will be referred to by Key from threadid %d\n",myVal,myId); + if(!pthread_setspecific(myKey,(void*)&myVal)) + {} + else + { + printf("Erorr in setting specific key in thread id %d\n",myId); + } + printMyVal(myId); +} + +int main() +{ + //you can create these dynamically also + pthread_t myThreads[NUM_THREADS]; + int status = 0; + pthread_key_create(&myKey,NULL); + int i; + for( i=0;i +#include +#include +#include +#include + + +#define TIMER_CLEAR (tv1.tv_sec = tv1.tv_usec = tv2.tv_sec = tv2.tv_usec = 0) +#define TIMER_START gettimeofday(&tv1, (struct timezone*)0) +#define TIMER_ELAPSED (double) (tv2.tv_usec-tv1.tv_usec)/1000000.0+(tv2.tv_sec-tv1.tv_sec) +#define TIMER_STOP gettimeofday(&tv2, (struct timezone*)0) +struct timeval tv1,tv2; + +pthread_mutex_t myMutex; + +#define MAX_THREADS 16 + +__thread double areaThread, areaThreadTotal; +__thread double myVal; + +int NUM_THREADS; +double iterations; +int a = 0, b = 1; +double area, h; +double sumOfRectangles; + +// returns square root +double func(double num) +{ + return sqrt(1-pow(num,2)); +} + +void *protectedThreadFunc(void* argument) +{ + int i; + int myId = (int)argument; + TIMER_START; + for(i=0;i<=iterations-1;i++) + { + areaThread=h*func(a+(i-1)*h); + areaThreadTotal+=areaThread; + } + + pthread_mutex_lock (&myMutex); + sumOfRectangles=4*areaThreadTotal; + TIMER_STOP; + pthread_mutex_unlock (&myMutex); + +} + +int main(int argc, char * argv[]) +{ + TIMER_CLEAR; + if (argc < 3) + { + printf("Please specify the iterations or threads\n"); + return -1; + } + area = 0; + int i; + + iterations = atoi(argv[1]); // in other words this is n + + NUM_THREADS = atoi(argv[2]); + + h = (b-a)/iterations; + + //creating pthread array + pthread_t myThreads[NUM_THREADS]; + int status = 0; + + + //printf("Calling protected set of threads\n"); + pthread_mutex_init(&myMutex, NULL); + //next set of threads will call a function that will update the variable protected + for(i=0;i +#include +#include +#define NUM_THREADS 100 +int mutexProtectedGlobalVariable; +int unprotectedProtectedGlobalVariable; +pthread_mutex_t myMutex; + +//this function will update the value without any protection +void *unprotectedThreadFunc(void* argument) +{ + int i; + for( i=0;i<10000;i++) unprotectedProtectedGlobalVariable++; } + +//this function will update the value without any protection +void *protectedThreadFunc(void* argument) +{ + int i; + pthread_mutex_lock (&myMutex); + for( i=0;i<10000;i++) mutexProtectedGlobalVariable++; pthread_mutex_unlock (&myMutex); +} + +int main() +{ + mutexProtectedGlobalVariable = 0; + unprotectedProtectedGlobalVariable = 0; + int i; + + //you can create these dynamically also + pthread_t myThreads[NUM_THREADS]; + int status = 0; + printf("Calling unprotected set of threads\n"); + + //first set of five threads will call a function that will update the variable unprotected + for(i=0;i +#include +#include +#include + + +#define TIMER_CLEAR (tv1.tv_sec = tv1.tv_usec = tv2.tv_sec = tv2.tv_usec = 0) +#define TIMER_START gettimeofday(&tv1, (struct timezone*)0) +#define TIMER_ELAPSED (double) (tv2.tv_usec-tv1.tv_usec)/1000000.0+(tv2.tv_sec-tv1.tv_sec) +#define TIMER_STOP gettimeofday(&tv2, (struct timezone*)0) +struct timeval tv1,tv2; + +double func(double num) +{ + return sqrt(1-pow(num,2)); +} + +int main(int argc, char * argv[]) +{ + TIMER_CLEAR; + if (argc < 2) + { + printf("Please specify the iterations\n"); + return -1; + } + + float iterations = atoi(argv[1]); + // integral bounds + float integral, sumOfRectangles; + double a,b, area; + a=0; + b=1; + double h = (b-a)/iterations; + int i=0; + TIMER_START; + // sum up Trapezoids + for (i; i <= iterations-1; i++) + { + area=h*func(a+(i-1)*h); + sumOfRectangles+=area; + } + integral=4*sumOfRectangles; + TIMER_STOP; + //integral = h*((sqrt(1-pow(a,2))/2)+sumOfTrapezoids+sqrt(1-pow(a,2))/2); + printf("Computed Sum for Rectangular Decomposition: %f\n", integral); + printf("Time elapsed = %f seconds\n", TIMER_ELAPSED); +} \ No newline at end of file diff --git a/CPE435/Lab6/timing.c b/CPE435/Lab6/timing.c new file mode 100644 index 0000000..a9dd5bc --- /dev/null +++ b/CPE435/Lab6/timing.c @@ -0,0 +1,25 @@ +#include +#include + + +#define TIMER_CLEAR (tv1.tv_sec = tv1.tv_usec = tv2.tv_sec = tv2.tv_usec = 0) +#define TIMER_START gettimeofday(&tv1, (struct timezone*)0) +#define TIMER_ELAPSED (double) (tv2.tv_usec-tv1.tv_usec)/1000000.0+(tv2.tv_sec-tv1.tv_sec) +#define TIMER_STOP gettimeofday(&tv2, (struct timezone*)0) +struct timeval tv1,tv2; + + +int main(int argc, char* argv[]) +{ + int i; + TIMER_CLEAR; + TIMER_START; + // Call to function that you want to time + // example + sleep(5); //Timer will give us ~5 seconds + TIMER_STOP; + printf("Time elapsed = %f seconds\n", TIMER_ELAPSED); + + + return 0; +} \ No newline at end of file diff --git a/CPE435/Lab7/Lab07.pdf b/CPE435/Lab7/Lab07.pdf new file mode 100644 index 0000000..f05d68b Binary files /dev/null and b/CPE435/Lab7/Lab07.pdf differ diff --git a/CPE435/Lab7/RoundRobin b/CPE435/Lab7/RoundRobin new file mode 100755 index 0000000..1273a2c Binary files /dev/null and b/CPE435/Lab7/RoundRobin differ diff --git a/CPE435/Lab7/RoundRobin.cpp b/CPE435/Lab7/RoundRobin.cpp new file mode 100644 index 0000000..197067a --- /dev/null +++ b/CPE435/Lab7/RoundRobin.cpp @@ -0,0 +1,85 @@ +#include +#include + +using namespace std; + +struct process +{ + int pid; // Process ID + int burst_time; // CPU Burst Time + int working_time; // Time this process executed, if working_time==burst_time, process is complete + int t_round; // turn around time, time needed for the process to complete + int arrivalTime; // time for a process to arrive to queue, which is zero in this case + int remainTime; // time remaining for a process to complete execution +}; + +main() +{ + int numProcesses; + cout << "Enter the number of processes: "; + cin >> numProcesses; + struct process pr[numProcesses]; + + int i, totalExecutionTime = 0, timeQuantum, flag = 0, n; + float totalWaitingTime = 0; + + for (i = 0; i < numProcesses; i++) + { + cout << "\nEnter PID for process " << i + 1 << " (ms): "; + cin >> pr[i].pid; + + cout << "\nEnter Burst Time for process " << i + 1 << " (ms): "; + cin >> pr[i].burst_time; + } + + // arrival time is zero + for (int i = 0; i < numProcesses; i++) + { + pr[i].arrivalTime = 0; + } + + printf("\nEnter Time Quantum: "); + scanf("%d", &timeQuantum); + + printf("\n"); + for (i = 0; numProcesses != 0;) + { + /** + * this below condition check the remain time for any process is less than or equal with the time quantum + * or not and also check the remain time is greater than 0 or not. if both condition are true that means + * the process can execute fully at one time. + */ + if (pr[i].remainTime <= timeQuantum && pr[i].remainTime > 0) + { + totalExecutionTime += pr[i].remainTime; + pr[i].remainTime = 0; + flag = 1; + } + + else if (pr[i].remainTime > 0) + { + pr[i].remainTime -= timeQuantum; + totalExecutionTime += timeQuantum; + } + + if (flag == 1 && pr[i].remainTime == 0) + { + printf("P[%d] | waiting Time : %d\n", i + 1, totalExecutionTime - pr[i].burst_time); + totalWaitingTime += totalExecutionTime - pr[i].burst_time; + flag = 0; + numProcesses--; + } + + if (i == n - 1) + i = 0; + else if (pr[i + 1].arrivalTime <= totalExecutionTime) + { + i++; + } + else + i = 0; + } + + totalWaitingTime = (float)totalWaitingTime / n; + printf("\nThe Average Waiting Time : %.2f \n", totalWaitingTime); +} diff --git a/CPE435/Lab7/output b/CPE435/Lab7/output new file mode 100755 index 0000000..418a845 Binary files /dev/null and b/CPE435/Lab7/output differ diff --git a/CPE435/Lab7/output.cpp b/CPE435/Lab7/output.cpp new file mode 100644 index 0000000..3cd656c --- /dev/null +++ b/CPE435/Lab7/output.cpp @@ -0,0 +1,16 @@ +#include +#include + +using namespace std; + +int main() +{ + int Grades[5] = { 3, 2, 5, 2 }; + +cout << "| Time (ms) |"; +for (int i = 0; i < sizeof(Grades)/sizeof(int); i++) { + cout << setw(8) << setfill(' ') << i << setw(4) << setfill(' ')<< "|"; +} + + return 0; +} \ No newline at end of file diff --git a/CPE435/Lab7/round_Robin b/CPE435/Lab7/round_Robin new file mode 100755 index 0000000..90035db Binary files /dev/null and b/CPE435/Lab7/round_Robin differ diff --git a/CPE435/Lab7/round_Robin.cpp b/CPE435/Lab7/round_Robin.cpp new file mode 100644 index 0000000..37f9561 --- /dev/null +++ b/CPE435/Lab7/round_Robin.cpp @@ -0,0 +1,150 @@ +#include +#include +#include +#include +#include + +using namespace std; + +int numProcesses; + +struct process{ + int pid; //Process ID + int burst_time; //CPU Burst Time + int working_time; //Time this process executed, if working_time==burst_time, process is complete + int t_round; //turn around time, time needed for the process to complete +}; + + + +void findWaitingTime(int processes[], int n, + int bt[], int wt[], int quantum); + + +void findTurnAroundTime(int processes[], int n, + int bt[], int wt[], int tat[]) +{ + // calculating turnaround time by adding + // bt[i] + wt[i] + for (int i = 0; i < n ; i++) + tat[i] = bt[i] + wt[i]; +} + + +void findavgTime(int processes[], int n, int bt[], + int quantum) +{ + int wt[n], tat[n], total_wt = 0, total_tat = 0; + + // Function to find waiting time of all processes + findWaitingTime(processes, n, bt, wt, quantum); + + // Function to find turn around time for all processes + findTurnAroundTime(processes, n, bt, wt, tat); + + // Display processes along with all details + cout << "Processes "<< " Burst time " + << " Waiting time " << " Turn around time\n"; + + // Calculate total waiting time and total turn + // around time + for (int i=0; i> numProcesses; + + + cout << "\nEnter Quantum Time (ms): "; + cin >> quantumTime; + + for(int i=0; i> pr[i].pid; + + cout << "\nEnter Burst Time for process " << i+1 << " (ms): "; + cin >> pr[i].burst_time; + } + // int x = sizeof pr->pid / sizeof pr[0].pid; + findavgTime(&pr->pid, numProcesses, &pr->burst_time, quantumTime); +} + +void findWaitingTime(int processes[], int n, + int bt[], int wt[], int quantum) +{ + // Make a copy of burst times bt[] to store remaining + // burst times. + int rem_bt[n]; + for (int i = 0 ; i < n ; i++) + rem_bt[i] = bt[i]; + + int t = 0; // Current time + + // Keep traversing processes in round robin manner + // until all of them are not done. + while (1) + { + bool done = true; + + // Traverse all processes one by one repeatedly + for (int i = 0 ; i < n; i++) + { + // If burst time of a process is greater than 0 + // then only need to process further + if (rem_bt[i] > 0) + { + done = false; // There is a pending process + + if (rem_bt[i] > quantum) + { + // Increase the value of t i.e. shows + // how much time a process has been processed + t += quantum; + + // Decrease the burst_time of current process + // by quantum + rem_bt[i] -= quantum; + } + + // If burst time is smaller than or equal to + // quantum. Last cycle for this process + else + { + // Increase the value of t i.e. shows + // how much time a process has been processed + t = t + rem_bt[i]; + + // Waiting time is current time minus time + // used by this process + wt[i] = t - bt[i]; + + // As the process gets fully executed + // make its remaining burst time = 0 + rem_bt[i] = 0; + } + } + } + + // If all processes are done + if (done == true) + break; + } +} \ No newline at end of file diff --git a/CPE435/Lab7/rr b/CPE435/Lab7/rr new file mode 100755 index 0000000..bd40b0a Binary files /dev/null and b/CPE435/Lab7/rr differ diff --git a/CPE435/Lab7/rr.cpp b/CPE435/Lab7/rr.cpp new file mode 100644 index 0000000..5213087 --- /dev/null +++ b/CPE435/Lab7/rr.cpp @@ -0,0 +1,159 @@ +#include +#include +#include + +using namespace std; + +struct process{ + int pid; //Process ID + int burst_time; //CPU Burst Time + int working_time; //Time this process executed, if working_time==burst_time, process is complete + int t_round; //turn around time, time needed for the process to complete + int remainTime; + int wait_time; + int execTime; +}; + + + + +int main() +{ + +int timeArray[10000], pidArray[10000]; +int timeIndex=0; + int count,j,n,time,remain,flag=0,time_quantum; + int wait_time=0,turnaround_time=0,at[n]; + printf("Enter Total Process:\t "); + scanf("%d",&n); + remain=n; + struct process pr[n]; + + for(count=0;count> pr[count].pid; + cout << "\nEnter Burst Time for process " << count + 1 << " (ms): "; + cin >> pr[count].burst_time; + pr[count].remainTime=pr[count].burst_time; + } + + // arrival time is zero + for (int i = 0; i < n; i++) + { + at[i] = 0; + } + printf("Enter Time Quantum:\t"); + scanf("%d",&time_quantum); + for(time=0,count=0;remain!=0;) + { + // the process still has some work time left + if(pr[count].remainTime<=time_quantum && pr[count].remainTime>0) + { + pidArray[timeIndex] = pr[count].pid; + timeArray[timeIndex] = pr[count].remainTime; + time+=pr[count].remainTime; + pr[count].remainTime=0; + flag=1; + // n = timeDuringQuantum - remainingTime + } + // + else if(pr[count].remainTime>0) + { + pr[count].remainTime-=time_quantum; + time+=time_quantum; + pidArray[timeIndex]= pr[count].pid; + timeArray[timeIndex] = time_quantum; + } + else{ + timeIndex--; + } + + if(pr[count].remainTime==0 && flag==1) + { + remain--; + pr[count].t_round = time-at[count]; + pr[count].wait_time = time-at[count]-pr[count].burst_time; + // printf("P[%d]\t|\t%d\t|\t%d\n",count+1,time-at[count],time-at[count]-pr[count].burst_time); + wait_time+=time-at[count]-pr[count].burst_time; + turnaround_time+=time-at[count]; + flag=0; + } + if(count==n-1) + { + count=0; + timeIndex++; + } + else if(at[count+1]<=time) + { + count++; + timeIndex++; + } + else + count=0; + } + + + + +for (int i = 0; i < timeIndex; i++) { + cout << setw(9) << setfill('-') << '-' << setw(6) << setfill('-')<< "-"; +} +cout << endl; + cout << "| Time (ms) |"; +for (int i = 0; i < timeIndex; i++) { + cout << setw(9) << setfill(' ') << timeArray[i] << setw(4) << setfill(' ')<< "|"; +} +cout << endl; +for (int i = 0; i < timeIndex; i++) { + cout << setw(9) << setfill('-') << '-' << setw(6) << setfill('-')<< "-"; +} +cout << endl; + cout << "| PID |"; +for (int i = 0; i < timeIndex; i++) { + cout << setw(9) << setfill(' ') << pidArray[i] << setw(4) << setfill(' ')<< " |"; +} +cout< +#include +#include +#include +#include + +//This function kills the process that makes a call to this function + void kill_func(int killSignal) +{ + printf("Received kill signal %d\n",killSignal); + printf("\tDying process %d\n",getpid()); + exit(0); +} +//this function prints a message and changes the function to handle the SIGINT command to kill_func() +void myFunction(int sigVal) +{ + printf("Received signal %d\n", sigVal); + printf("Now you can kill me..\n"); + signal(SIGINT,kill_func); +} +int main() +{ + //ignore the SIGINT signal + // .. SIGINT is ctrl+c + // .. SIG_IGN is signal ignore + // .since we ignore the signal ctrl+c, you cannot terminate this process with ctrl+c + signal(SIGINT,SIG_IGN); + //for alarm signal, call function myFunction() + // .. means when alarm goes off, myFunction will be called + signal(SIGALRM,myFunction); + //set alarm for 15 seconds from now + alarm(15); + printf("This gets printed as soon as alarm is called\n"); + //just running infinitely + while(1); +} diff --git a/CPE435/Lab8/lab08_demo.cpp b/CPE435/Lab8/lab08_demo.cpp new file mode 100644 index 0000000..d966dc4 --- /dev/null +++ b/CPE435/Lab8/lab08_demo.cpp @@ -0,0 +1,36 @@ +#include +#include +#include +#include +#include + +//This function kills the process that makes a call to this function + void kill_func(int killSignal) +{ + printf("Received kill signal %d\n",killSignal); + printf("\tDying process %d\n",getpid()); + exit(0); +} +//this function prints a message and changes the function to handle the SIGINT command to kill_func() +void myFunction(int sigVal) +{ + printf("Received signal %d\n", sigVal); + printf("Now you can kill me..\n"); + signal(SIGINT,kill_func); +} +int main() +{ + //ignore the SIGINT signal + // .. SIGINT is ctrl+c + // .. SIG_IGN is signal ignore + // .since we ignore the signal ctrl+c, you cannot terminate this process with ctrl+c + signal(SIGINT,SIG_IGN); + //for alarm signal, call function myFunction() + // .. means when alarm goes off, myFunction will be called + signal(SIGALRM,myFunction); + //set alarm for 15 seconds from now + alarm(15); + printf("This gets printed as soon as alarm is called\n"); + //just running infinitely + while(1); +} diff --git a/CPE435/Lab8/program1 b/CPE435/Lab8/program1 new file mode 100755 index 0000000..ec05975 Binary files /dev/null and b/CPE435/Lab8/program1 differ diff --git a/CPE435/Lab8/program1.cpp b/CPE435/Lab8/program1.cpp new file mode 100644 index 0000000..8cece53 --- /dev/null +++ b/CPE435/Lab8/program1.cpp @@ -0,0 +1,107 @@ +#include +#include +#include +#include +#include +#include +using namespace std; + +//this function prints a message and changes the function to handle the SIGINT command to kill_func() +void myFunction(int sigVal); + +// handles after alarm alarm +void alarmFunction(int ignore); +int child; + +// handles SIG_INT while the alarm is active +void ignoreFunc(int ignore); +//This function kills the process that makes a call to this function +void kill_func(int killSignal); + +// handles killing the child +void childKillFunc(int kill); + +int main() +{ + child = fork(); + // ignore the SIGINT signal + // .. SIGINT is ctrl+c + // .. ignoreFunc is the user-defined signal handler + // + signal(SIGINT,ignoreFunc); + // for alarm signal, call function alarmFunction() + // .. means when alarm goes off, alarmFunction will be called + + signal(SIGALRM,alarmFunction); + //set alarm for 15 seconds from now + alarm(10); + //printf("This gets printed as soon as alarm is called\n"); + // just running infinitely + while(1); +} + +void myFunction(int sigVal) +{ + printf("Received signal %d\n", sigVal); + printf("Now you can kill me..\n"); + signal(SIGINT,kill_func); +} + +void alarmFunction(int ignore) +{ + if (child== 0) + { + //define user signal and kill(child, USRSIG1) to send signal to child + + signal(SIGINT,SIG_IGN); + signal(SIGUSR1, childKillFunc); + } + else + { + printf("Received signal %d\n", ignore); + printf("Now you can kill me..\n"); + signal(SIGINT,kill_func); + } +} + +void kill_func(int killSignal) +{ + if(child == 0) + { + + } + else + { + //define user signal and kill(child, USRSIG1) to send signal to child + + printf("Sending signal to child\n"); + kill(child, SIGUSR1); + printf("Received kill signal %d\n",killSignal); + printf("\tDying process %d\n",getpid()); + exit(0); + } + +} + +void childKillFunc(int kill) +{ + if (child == 0) + { + cout << "Received kill signal" << endl; + cout << "Child Process " << getpid() << " is dying" << endl; + exit(0); + } + +} + +void ignoreFunc(int ignore) +{ + + if(child == 0) + { + } + else + { + cout << "Can't kill processes now\n"; + } +} \ No newline at end of file diff --git a/CPE435/Lab8/program1.png b/CPE435/Lab8/program1.png new file mode 100644 index 0000000..79b6af4 Binary files /dev/null and b/CPE435/Lab8/program1.png differ diff --git a/CPE435/Lab8/program2 b/CPE435/Lab8/program2 new file mode 100755 index 0000000..9b4e56c Binary files /dev/null and b/CPE435/Lab8/program2 differ diff --git a/CPE435/Lab8/program2.cpp b/CPE435/Lab8/program2.cpp new file mode 100644 index 0000000..0fdd413 --- /dev/null +++ b/CPE435/Lab8/program2.cpp @@ -0,0 +1,39 @@ +#include +#include +#include +#include +#include +#include +using namespace std; + +// function that prints gibberish +// for 10 seconds and then kills +// the program +void alarmFunction(int alarmVal); + + +// kills program +void killFunction(int killPID); + +int main() +{ + signal(SIGINT,alarmFunction); + while (1); +} + +void alarmFunction(int alarmVal) +{ + signal(SIGINT, SIG_IGN); + signal(SIGALRM,killFunction); + alarm(10); + while (1) + { + printf(" I love coding! "); + } +} + +void killFunction(int killPID) +{ + printf("\n"); + exit(0); +} \ No newline at end of file diff --git a/CPE435/Lab8/program2Output.png b/CPE435/Lab8/program2Output.png new file mode 100644 index 0000000..58b4350 Binary files /dev/null and b/CPE435/Lab8/program2Output.png differ diff --git a/CPE435/Lab9/Lab09.pdf b/CPE435/Lab9/Lab09.pdf new file mode 100644 index 0000000..778111f Binary files /dev/null and b/CPE435/Lab9/Lab09.pdf differ diff --git a/CPE435/Lab9/cachegrind.out.15382 b/CPE435/Lab9/cachegrind.out.15382 new file mode 100644 index 0000000..4d7e7fa --- /dev/null +++ b/CPE435/Lab9/cachegrind.out.15382 @@ -0,0 +1,481 @@ +desc: I1 cache: 32768 B, 64 B, 8-way associative +desc: D1 cache: 32768 B, 64 B, 8-way associative +desc: LL cache: 8388608 B, 64 B, 16-way associative +cmd: ./test1 +events: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +fl=??? +fn=(below main) +0 62 4 4 17 5 0 17 1 0 +fn=??? +0 2049 158 135 1255 123 10 349 18 12 +fn=_Exit +0 8 2 2 1 1 0 0 0 0 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+fn=uname +0 5 1 1 1 0 0 0 0 0 +fn=uselocale +0 42 3 3 18 5 0 8 1 0 +fn=version_check_doit +0 10 1 1 4 0 0 2 0 0 +fn=wctob +0 2432 2 2 768 0 0 640 0 0 +fn=wctype_l +0 876 2 2 139 4 0 153 0 0 +fn=write +0 2 1 1 1 0 0 0 0 0 +summary: 11390488 1372 1343 4351588 9127 5267 1130849 64167 63666 diff --git a/CPE435/Lab9/cachegrind.out.18722 b/CPE435/Lab9/cachegrind.out.18722 new file mode 100644 index 0000000..26d3b6d --- /dev/null +++ b/CPE435/Lab9/cachegrind.out.18722 @@ -0,0 +1,481 @@ +desc: I1 cache: 32768 B, 64 B, 8-way associative +desc: D1 cache: 32768 B, 64 B, 8-way associative +desc: LL cache: 8388608 B, 64 B, 16-way associative +cmd: ./test2 +events: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +fl=??? +fn=(below main) +0 62 4 4 17 5 0 17 1 0 +fn=??? +0 2049 158 135 1255 123 10 349 19 12 +fn=_Exit +0 8 2 2 1 1 0 0 0 0 +fn=_GLOBAL__sub_I_main +0 7 1 1 2 1 0 2 0 0 +fn=_IO_cleanup +0 112 8 8 33 1 1 19 0 0 +fn=_IO_default_setbuf +0 50 4 4 9 0 0 15 0 0 +fn=_IO_default_xsputn +0 338 4 4 90 0 0 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0 27 0 0 +fn=__cxa_guard_acquire +0 32 5 5 13 1 0 7 0 0 +fn=__cxa_guard_release +0 14 3 3 5 0 0 3 0 0 +fn=__cxxabiv1::__si_class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const +0 1400 3 3 440 0 0 360 0 0 +fn=__cxxabiv1::__vmi_class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const +0 528 6 6 208 2 1 144 0 0 +fn=__dynamic_cast +0 2448 4 4 816 14 0 624 0 0 +fn=__exp_finite +0 8 1 1 3 0 0 0 0 0 +fn=__gconv_btwoc_ascii +0 640 1 1 128 0 0 0 0 0 +fn=__gnu_cxx::stdio_sync_filebuf >::overflow(int) +0 6 1 1 1 0 0 0 0 0 +fn=__gnu_cxx::stdio_sync_filebuf >::sync() +0 8 1 1 4 1 0 0 0 0 +fn=__gnu_cxx::stdio_sync_filebuf >::xsputn(char const*, long) +0 10 1 1 2 1 0 0 0 0 +fn=__gnu_cxx::stdio_sync_filebuf >::sync() +0 6 0 0 3 2 0 0 0 0 +fn=__init_misc +0 24 2 2 7 1 0 5 1 0 +fn=__libc_csu_init +0 41 2 2 9 2 0 9 0 0 +fn=__libc_memalign +0 1310 5 5 220 3 0 216 1 1 +fn=__log_finite +0 8 1 1 3 0 0 0 0 0 +fn=__memcmp_sse4_1 +0 111 11 11 38 1 1 0 0 0 +fn=__memcpy_ssse3_back +0 78 10 10 22 3 2 17 4 0 +fn=__new_exitfn +0 215 7 5 55 10 3 21 1 0 +fn=__overflow +0 17 2 2 4 0 0 1 0 0 +fn=__pow_finite +0 5 1 1 3 0 0 0 0 0 +fn=__run_exit_handlers +0 110 4 4 17 5 0 14 0 0 +fn=__sigjmp_save +0 9 0 0 2 0 0 2 0 0 +fn=__sigsetjmp +0 279 5 5 69 0 0 112 3 2 +fn=__static_initialization_and_destruction_0(int, int) +0 17 1 1 4 0 0 5 0 0 +fn=__strcmp_sse42 +0 392 6 6 48 1 1 0 0 0 +fn=__strlen_sse2_pminub +0 27 4 4 3 1 1 0 0 0 +fn=__unregister_atfork +0 28 2 2 12 1 1 4 0 0 +fn=__write_nocancel +0 5 0 0 1 0 0 0 0 0 +fn=_dl_add_to_namespace_list +0 250 3 3 62 0 0 41 0 0 +fn=_dl_add_to_slotinfo +0 48 3 3 18 5 0 12 2 0 +fn=_dl_allocate_tls_init +0 117 6 6 36 4 0 17 0 0 +fn=_dl_allocate_tls_storage +0 332 3 3 7 0 0 295 37 37 +fn=_dl_cache_libcmp +0 3387 4 4 511 33 33 0 0 0 +fn=_dl_catch_error +0 468 4 4 143 0 0 221 5 5 +fn=_dl_check_all_versions +0 117 3 3 19 0 0 11 0 0 +fn=_dl_check_map_versions +0 3897 14 14 1222 31 26 481 39 37 +fn=_dl_count_modids +0 4 2 2 3 0 0 0 0 0 +fn=_dl_debug_initialize +0 65 3 3 22 2 1 4 0 0 +fn=_dl_debug_state +0 2 1 1 2 0 0 0 0 0 +fn=_dl_determine_tlsoffset +0 85 4 4 15 1 0 9 0 0 +fn=_dl_discover_osversion +0 88 4 4 15 2 2 7 1 1 +fn=_dl_dst_count +0 204 1 1 60 0 0 60 1 1 +fn=_dl_fini +0 422 12 12 157 27 0 46 5 0 +fn=_dl_fixup +0 5727 6 6 2154 278 41 502 0 0 +fn=_dl_higher_prime_number +0 144 1 1 14 2 1 0 0 0 +fn=_dl_important_hwcaps +0 267 19 19 48 0 0 45 2 2 +fn=_dl_init +0 397 11 11 118 23 0 38 0 0 +fn=_dl_init_paths +0 379 18 18 44 0 0 41 4 4 +fn=_dl_initial_error_catch_tsd +0 28 0 0 14 0 0 0 0 0 +fn=_dl_load_cache_lookup +0 1252 16 16 249 30 30 111 1 1 +fn=_dl_lookup_symbol_x +0 520999 11 11 84994 1337 1108 30568 19 10 +fn=_dl_map_object +0 2165 23 23 514 0 0 319 10 10 +fn=_dl_map_object_deps +0 2859 38 38 613 7 1 237 3 3 +fn=_dl_map_object_from_fd +0 4474 47 47 986 43 43 464 50 50 +fn=_dl_mcount_wrapper_check +0 512 2 2 384 0 0 0 0 0 +fn=_dl_name_match_p +0 9389 2 2 2429 29 0 1396 4 4 +fn=_dl_new_object +0 1148 12 12 211 7 7 208 41 41 +fn=_dl_next_ld_env_entry +0 268 2 2 93 0 0 2 0 0 +fn=_dl_next_tls_modid +0 12 2 2 6 0 0 2 0 0 +fn=_dl_process_tunable_env_entries +0 243 2 2 82 22 22 1 0 0 +fn=_dl_receive_error +0 28 2 2 10 0 0 12 0 0 +fn=_dl_relocate_object +0 198542 51 51 52290 3815 2933 16275 1049 713 +fn=_dl_runtime_resolve_xsave +0 3320 4 4 3984 1 0 4150 42 26 +fn=_dl_setup_hash +0 161 2 2 49 8 8 42 0 0 +fn=_dl_sort_fini +0 613 7 7 158 5 0 30 0 0 +fn=_dl_start +0 686 17 16 142 26 24 57 19 18 +fn=_dl_sysdep_read_whole_file +0 41 3 3 6 0 0 9 1 1 +fn=_dl_sysdep_start +0 406 11 11 109 15 14 30 5 5 +fn=_dl_sysdep_start_cleanup +0 1 1 1 1 0 0 0 0 0 +fn=_dl_unload_cache +0 10 2 1 3 2 0 2 0 0 +fn=_dl_vdso_vsym +0 28 2 2 12 2 0 0 0 0 +fn=_fxstat +0 70 3 3 7 0 0 0 0 0 +fn=_init +0 60 6 6 14 4 0 18 4 3 +fn=_setjmp +0 2 1 1 0 0 0 0 0 0 +fn=_xstat +0 49 1 1 4 0 0 3 0 0 +fn=access +0 9 1 1 1 0 0 1 0 0 +fn=bcmp +0 2151 15 15 546 11 11 160 2 2 +fn=bool std::has_facet >(std::locale const&) +0 84 2 2 36 1 0 12 0 0 +fn=bool std::has_facet >(std::locale const&) +0 84 2 2 36 0 0 12 0 0 +fn=bool std::has_facet > > >(std::locale const&) +0 84 1 1 36 0 0 12 0 0 +fn=bool std::has_facet > > >(std::locale const&) +0 84 1 1 36 0 0 12 0 0 +fn=bool std::has_facet > > >(std::locale const&) +0 84 2 2 36 0 0 12 0 0 +fn=bool std::has_facet > > >(std::locale const&) +0 84 2 2 36 1 0 12 0 0 +fn=brk +0 12 2 2 1 0 0 1 1 1 +fn=bsearch +0 904 2 2 164 0 0 118 1 1 +fn=btowc +0 8064 4 4 2176 5 0 1024 0 0 +fn=calloc +0 136 1 1 0 0 0 0 0 0 +fn=check_match.9525 +0 67090 5 5 27652 263 151 7912 27 17 +fn=check_stdfiles_vtables +0 11 2 2 7 4 0 0 0 0 +fn=close +0 30 0 0 6 0 0 0 0 0 +fn=cos +0 8 2 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0 +fn=memcpy +0 1063 6 6 179 5 5 149 20 20 +fn=memcpy@@GLIBC_2.14 +0 11 2 2 5 0 0 0 0 0 +fn=memcpy@GLIBC_2.2.5 +0 30 1 1 8 0 0 0 0 0 +fn=mempcpy +0 1556 5 5 214 2 1 149 5 5 +fn=memset +0 5134 4 3 27 0 0 5004 79 79 +fn=mmap +0 623 5 5 138 0 0 114 4 4 +fn=mprotect +0 60 1 1 12 0 0 0 0 0 +fn=munmap +0 5 0 0 1 0 0 0 0 0 +fn=newlocale +0 40 7 7 12 0 0 9 0 0 +fn=open +0 237 1 1 29 0 0 23 0 0 +fn=open_path +0 1539 16 16 523 1 1 192 4 4 +fn=open_verify +0 1758 15 15 410 13 13 358 2 2 +fn=openaux +0 204 2 2 96 0 0 36 0 0 +fn=putc +0 40 4 4 18 0 0 4 0 0 +fn=read +0 25 1 1 5 0 0 0 0 0 +fn=rint +0 5 2 2 3 0 0 0 0 0 +fn=rintf +0 5 1 1 3 0 0 0 0 0 +fn=rtld_lock_default_lock_recursive +0 114 1 1 114 3 1 0 0 0 +fn=rtld_lock_default_unlock_recursive +0 114 0 0 114 0 0 0 0 0 +fn=sbrk +0 17 2 2 5 0 0 2 0 0 +fn=sin +0 8 1 1 3 0 0 0 0 0 +fn=std::__timepunct::_M_initialize_timepunct(__locale_struct*) +0 107 12 12 6 0 0 52 0 0 +fn=std::__timepunct::__timepunct(std::__timepunct_cache*, unsigned long) +0 22 2 2 4 0 0 9 0 0 +fn=std::__timepunct::_M_initialize_timepunct(__locale_struct*) +0 105 12 12 5 0 0 51 0 0 +fn=std::__timepunct::__timepunct(std::__timepunct_cache*, unsigned long) +0 22 2 2 4 0 0 9 1 1 +fn=std::basic_ios >::_M_cache_locale(std::locale const&) +0 120 2 2 12 0 0 44 0 0 +fn=std::basic_ios >::init(std::basic_streambuf >*) +0 88 2 2 12 0 0 40 0 0 +fn=std::basic_ios >::_M_cache_locale(std::locale const&) +0 120 2 2 12 0 0 44 0 0 +fn=std::basic_ios >::init(std::basic_streambuf >*) +0 88 3 3 12 0 0 40 0 0 +fn=std::basic_ostream >& std::__ostream_insert >(std::basic_ostream >&, char const*, long) +0 57 8 8 24 2 0 12 0 0 +fn=std::basic_ostream >& std::endl >(std::basic_ostream >&) +0 20 2 2 7 0 0 3 0 0 +fn=std::basic_ostream >& std::operator<< >(std::basic_ostream >&, char const*) +0 18 2 2 3 0 0 4 0 0 +fn=std::basic_ostream >::flush() +0 42 2 2 21 10 0 6 0 0 +fn=std::codecvt::codecvt(unsigned long) +0 17 1 1 4 0 0 6 1 1 +fn=std::codecvt::codecvt(unsigned long) +0 17 2 2 4 0 0 6 2 2 +fn=std::ctype const& std::use_facet >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::ctype::_M_widen_init() const +0 1056 3 3 9 2 0 263 0 0 +fn=std::ctype::ctype(unsigned short const*, bool, unsigned long) +0 161 8 8 8 1 0 83 9 9 +fn=std::ctype::do_widen(char const*, char const*, char*) const +0 8 1 1 2 0 0 2 0 0 +fn=std::ctype::do_widen(char) const +0 2 1 1 1 0 0 0 0 0 +fn=std::ctype const& std::use_facet >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::ctype::_M_convert_to_wmask(unsigned short) const +0 129 5 5 12 0 0 0 0 0 +fn=std::ctype::_M_initialize_ctype() +0 2757 5 5 5 0 0 810 20 20 +fn=std::ctype::ctype(unsigned long) +0 19 1 1 3 0 0 7 1 1 +fn=std::error_category::error_category() +0 12 1 1 6 1 0 3 0 0 +fn=std::error_category::~error_category() +0 12 1 1 6 1 0 3 0 0 +fn=std::future_category() +0 21 3 3 2 1 1 6 0 0 +fn=std::ios_base::Init::Init() +0 270 31 31 41 8 1 168 16 13 +fn=std::ios_base::Init::~Init() +0 24 3 3 9 8 0 7 0 0 +fn=std::ios_base::_M_init() +0 192 3 3 48 0 0 72 0 0 +fn=std::ios_base::ios_base() +0 472 3 3 8 0 0 216 31 26 +fn=std::locale::_Impl::_Impl(unsigned long) +0 819 66 66 132 14 1 406 44 44 +fn=std::locale::_Impl::_M_install_facet(std::locale::id const*, std::locale::facet const*) +0 7448 7 7 2716 0 0 224 0 0 +fn=std::locale::facet::_S_create_c_locale(__locale_struct*&, char const*, __locale_struct*) +0 9 1 1 2 0 0 3 0 0 +fn=std::locale::facet::_S_get_c_locale() +0 92 1 1 50 1 1 11 0 0 +fn=std::locale::facet::_S_get_c_name() +0 10 1 1 5 0 0 0 0 0 +fn=std::locale::id::_M_id() const +0 705 1 1 226 9 2 56 0 0 +fn=std::locale::locale() +0 462 4 4 176 1 0 132 2 1 +fn=std::locale::operator=(std::locale const&) +0 136 3 3 56 0 0 24 0 0 +fn=std::locale::~locale() +0 96 1 1 40 0 0 16 0 0 +fn=std::messages::messages(unsigned long) +0 19 2 2 4 0 0 8 0 0 +fn=std::messages::messages(unsigned long) +0 19 1 1 4 0 0 8 0 0 +fn=std::moneypunct::_M_initialize_moneypunct(__locale_struct*, char const*) +0 112 5 5 37 1 1 31 0 0 +fn=std::moneypunct::_M_initialize_moneypunct(__locale_struct*, char const*) +0 112 5 5 37 0 0 31 0 0 +fn=std::moneypunct::_M_initialize_moneypunct(__locale_struct*, char const*) +0 108 6 6 29 0 0 32 0 0 +fn=std::moneypunct::_M_initialize_moneypunct(__locale_struct*, char const*) +0 108 6 6 29 0 0 32 0 0 +fn=std::num_get > > const& std::use_facet > > >(std::locale const&) +0 76 1 1 36 0 0 12 0 0 +fn=std::num_get > > const& std::use_facet > > >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::num_put > > const& std::use_facet > > >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::num_put > >::do_put(std::ostreambuf_iterator >, std::ios_base&, char, long) const +0 5 2 2 1 0 0 1 0 0 +fn=std::num_put > > const& std::use_facet > > >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::numpunct::_M_initialize_numpunct(__locale_struct*) +0 413 4 4 136 3 2 75 0 0 +fn=std::numpunct::_M_initialize_numpunct(__locale_struct*) +0 349 6 6 73 0 0 75 3 3 +fn=std::ostream& std::ostream::_M_insert(long) +0 72 7 7 28 4 0 13 0 0 +fn=std::ostream::flush() +0 56 1 1 28 6 0 8 0 0 +fn=std::ostream::operator<<(int) +0 10 1 1 3 0 0 0 0 0 +fn=std::ostream::operator<<(std::ostream& (*)(std::ostream&)) +0 1 1 1 0 0 0 0 0 0 +fn=std::ostream::put(char) +0 40 4 4 17 0 0 6 0 0 +fn=std::ostream::sentry::sentry(std::ostream&) +0 69 2 2 24 3 0 15 0 0 +fn=std::ostreambuf_iterator > std::num_put > >::_M_insert_int(std::ostreambuf_iterator >, std::ios_base&, char, long) const +0 97 7 7 25 4 0 19 0 0 +fn=strcasecmp +0 12 2 2 3 2 0 0 0 0 +fn=strcmp +0 130809 2 2 38693 153 50 0 0 0 +fn=strdup +0 68 1 1 8 0 0 16 0 0 +fn=strlen +0 1462 6 5 159 2 1 0 0 0 +fn=strncasecmp +0 12 2 2 3 0 0 0 0 0 +fn=strnlen +0 5 1 1 3 0 0 0 0 0 +fn=strsep +0 432 1 1 134 0 0 3 0 0 +fn=time +0 15 2 2 1 0 0 5 0 0 +fn=uname +0 5 1 1 1 0 0 0 0 0 +fn=uselocale +0 42 3 3 18 5 0 8 1 0 +fn=version_check_doit +0 10 1 1 4 0 0 2 0 0 +fn=wctob +0 2432 2 2 768 0 0 640 0 0 +fn=wctype_l +0 876 2 2 139 4 0 153 0 0 +fn=write +0 2 1 1 1 0 0 0 0 0 +summary: 11390488 1372 1343 4351588 9127 5267 1130849 1001689 63666 diff --git a/CPE435/Lab9/cachegrind.out.19906 b/CPE435/Lab9/cachegrind.out.19906 new file mode 100644 index 0000000..f4131a8 --- /dev/null +++ b/CPE435/Lab9/cachegrind.out.19906 @@ -0,0 +1,481 @@ +desc: I1 cache: 32768 B, 64 B, 8-way associative +desc: D1 cache: 32768 B, 64 B, 8-way associative +desc: LL cache: 8388608 B, 64 B, 16-way associative +cmd: ./test1 +events: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +fl=??? +fn=(below main) +0 62 4 4 17 5 0 17 1 0 +fn=??? +0 2049 158 135 1255 123 10 349 18 12 +fn=_Exit +0 8 2 2 1 1 0 0 0 0 +fn=_GLOBAL__sub_I_main +0 7 1 1 2 1 0 2 0 0 +fn=_IO_cleanup +0 112 8 8 33 1 1 19 0 0 +fn=_IO_default_setbuf +0 50 4 4 9 0 0 15 0 0 +fn=_IO_default_xsputn +0 338 4 4 90 0 0 23 0 0 +fn=_IO_do_write@@GLIBC_2.2.5 +0 71 7 7 21 0 0 17 0 0 +fn=_IO_doallocbuf +0 25 2 2 8 1 0 4 0 0 +fn=_IO_file_doallocate +0 63 5 5 11 2 0 6 0 0 +fn=_IO_file_overflow@@GLIBC_2.2.5 +0 618 7 7 165 0 0 100 1 0 +fn=_IO_file_setbuf@@GLIBC_2.2.5 +0 15 1 1 3 0 0 8 0 0 +fn=_IO_file_stat +0 4 1 1 1 0 0 0 0 0 +fn=_IO_file_sync@@GLIBC_2.2.5 +0 136 3 3 56 0 0 24 0 0 +fn=_IO_file_write@@GLIBC_2.2.5 +0 36 2 2 8 0 0 5 0 0 +fn=_IO_file_xsputn@@GLIBC_2.2.5 +0 124 7 7 25 0 0 16 0 0 +fn=_IO_flush_all_lockp +0 92 9 9 26 5 2 13 0 0 +fn=_IO_setb +0 21 2 2 5 0 0 5 0 0 +fn=__GI_memcmp +0 857 4 4 143 0 0 0 0 0 +fn=__GI_mempcpy +0 18 3 3 2 0 0 1 0 0 +fn=__GI_strlen +0 947 4 4 121 4 4 0 0 0 +fn=__GI_strrchr +0 34 4 4 2 1 0 0 0 0 +fn=__acos_finite +0 5 1 1 3 0 0 0 0 0 +fn=__asin_finite +0 5 1 1 3 0 0 0 0 0 +fn=__atan2_finite +0 8 1 1 3 0 0 0 0 0 +fn=__cpu_indicator_init +0 81 6 6 17 1 0 11 0 0 +fn=__ctype_init +0 16 2 2 10 4 0 3 0 0 +fn=__cxa_atexit +0 110 2 2 25 0 0 40 2 0 +fn=__cxa_finalize +0 297 5 5 81 2 0 27 0 0 +fn=__cxa_guard_acquire +0 32 5 5 13 1 0 7 0 0 +fn=__cxa_guard_release +0 14 3 3 5 0 0 3 0 0 +fn=__cxxabiv1::__si_class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const +0 1400 3 3 440 0 0 360 0 0 +fn=__cxxabiv1::__vmi_class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const +0 528 6 6 208 2 1 144 0 0 +fn=__dynamic_cast +0 2448 4 4 816 14 0 624 0 0 +fn=__exp_finite +0 8 1 1 3 0 0 0 0 0 +fn=__gconv_btwoc_ascii +0 640 1 1 128 0 0 0 0 0 +fn=__gnu_cxx::stdio_sync_filebuf >::overflow(int) +0 6 1 1 1 0 0 0 0 0 +fn=__gnu_cxx::stdio_sync_filebuf >::sync() +0 8 1 1 4 1 0 0 0 0 +fn=__gnu_cxx::stdio_sync_filebuf >::xsputn(char const*, long) +0 10 1 1 2 1 0 0 0 0 +fn=__gnu_cxx::stdio_sync_filebuf >::sync() +0 6 0 0 3 2 0 0 0 0 +fn=__init_misc +0 24 2 2 7 1 0 5 1 0 +fn=__libc_csu_init +0 41 2 2 9 2 0 9 0 0 +fn=__libc_memalign +0 1310 5 5 220 3 0 216 1 1 +fn=__log_finite +0 8 1 1 3 0 0 0 0 0 +fn=__memcmp_sse4_1 +0 111 11 11 38 1 1 0 0 0 +fn=__memcpy_ssse3_back +0 78 10 10 22 3 2 17 4 0 +fn=__new_exitfn +0 215 7 5 55 10 3 21 1 0 +fn=__overflow +0 17 2 2 4 0 0 1 0 0 +fn=__pow_finite +0 5 1 1 3 0 0 0 0 0 +fn=__run_exit_handlers +0 110 4 4 17 5 0 14 0 0 +fn=__sigjmp_save +0 9 0 0 2 0 0 2 0 0 +fn=__sigsetjmp +0 279 5 5 69 0 0 112 3 2 +fn=__static_initialization_and_destruction_0(int, int) +0 17 1 1 4 0 0 5 0 0 +fn=__strcmp_sse42 +0 392 6 6 48 1 1 0 0 0 +fn=__strlen_sse2_pminub +0 27 4 4 3 1 1 0 0 0 +fn=__unregister_atfork +0 28 2 2 12 1 1 4 0 0 +fn=__write_nocancel +0 5 0 0 1 0 0 0 0 0 +fn=_dl_add_to_namespace_list +0 250 3 3 62 0 0 41 0 0 +fn=_dl_add_to_slotinfo +0 48 3 3 18 5 0 12 2 0 +fn=_dl_allocate_tls_init +0 117 6 6 36 4 0 17 0 0 +fn=_dl_allocate_tls_storage +0 332 3 3 7 0 0 295 37 37 +fn=_dl_cache_libcmp +0 3387 4 4 511 33 33 0 0 0 +fn=_dl_catch_error +0 468 4 4 143 0 0 221 5 5 +fn=_dl_check_all_versions +0 117 3 3 19 0 0 11 0 0 +fn=_dl_check_map_versions +0 3897 14 14 1222 31 26 481 39 37 +fn=_dl_count_modids +0 4 2 2 3 0 0 0 0 0 +fn=_dl_debug_initialize +0 65 3 3 22 2 1 4 0 0 +fn=_dl_debug_state +0 2 1 1 2 0 0 0 0 0 +fn=_dl_determine_tlsoffset +0 85 4 4 15 1 0 9 0 0 +fn=_dl_discover_osversion +0 88 4 4 15 2 2 7 1 1 +fn=_dl_dst_count +0 204 1 1 60 0 0 60 1 1 +fn=_dl_fini +0 422 12 12 157 27 0 46 5 0 +fn=_dl_fixup +0 5727 6 6 2154 278 41 502 0 0 +fn=_dl_higher_prime_number +0 144 1 1 14 2 1 0 0 0 +fn=_dl_important_hwcaps +0 267 19 19 48 0 0 45 2 2 +fn=_dl_init +0 397 11 11 118 23 0 38 0 0 +fn=_dl_init_paths +0 379 18 18 44 0 0 41 4 4 +fn=_dl_initial_error_catch_tsd +0 28 0 0 14 0 0 0 0 0 +fn=_dl_load_cache_lookup +0 1252 16 16 249 30 30 111 1 1 +fn=_dl_lookup_symbol_x +0 520999 11 11 84994 1337 1108 30568 15 10 +fn=_dl_map_object +0 2165 23 23 514 0 0 319 10 10 +fn=_dl_map_object_deps +0 2859 38 38 613 7 1 237 3 3 +fn=_dl_map_object_from_fd +0 4474 47 47 986 43 43 464 50 50 +fn=_dl_mcount_wrapper_check +0 512 2 2 384 0 0 0 0 0 +fn=_dl_name_match_p +0 9389 2 2 2429 29 0 1396 4 4 +fn=_dl_new_object +0 1148 12 12 211 7 7 208 41 41 +fn=_dl_next_ld_env_entry +0 268 2 2 93 0 0 2 0 0 +fn=_dl_next_tls_modid +0 12 2 2 6 0 0 2 0 0 +fn=_dl_process_tunable_env_entries +0 243 2 2 82 22 22 1 0 0 +fn=_dl_receive_error +0 28 2 2 10 0 0 12 0 0 +fn=_dl_relocate_object +0 198542 51 51 52290 3815 2933 16275 1049 713 +fn=_dl_runtime_resolve_xsave +0 3320 4 4 3984 1 0 4150 26 26 +fn=_dl_setup_hash +0 161 2 2 49 8 8 42 0 0 +fn=_dl_sort_fini +0 613 7 7 158 5 0 30 0 0 +fn=_dl_start +0 686 17 16 142 26 24 57 19 18 +fn=_dl_sysdep_read_whole_file +0 41 3 3 6 0 0 9 1 1 +fn=_dl_sysdep_start +0 406 11 11 109 15 14 30 5 5 +fn=_dl_sysdep_start_cleanup +0 1 1 1 1 0 0 0 0 0 +fn=_dl_unload_cache +0 10 2 1 3 2 0 2 0 0 +fn=_dl_vdso_vsym +0 28 2 2 12 2 0 0 0 0 +fn=_fxstat +0 70 3 3 7 0 0 0 0 0 +fn=_init +0 60 6 6 14 4 0 18 4 3 +fn=_setjmp +0 2 1 1 0 0 0 0 0 0 +fn=_xstat +0 49 1 1 4 0 0 3 0 0 +fn=access +0 9 1 1 1 0 0 1 0 0 +fn=bcmp +0 2151 15 15 546 11 11 160 2 2 +fn=bool std::has_facet >(std::locale const&) +0 84 2 2 36 1 0 12 0 0 +fn=bool std::has_facet >(std::locale const&) +0 84 2 2 36 0 0 12 0 0 +fn=bool std::has_facet > > >(std::locale const&) +0 84 1 1 36 0 0 12 0 0 +fn=bool std::has_facet > > >(std::locale const&) +0 84 1 1 36 0 0 12 0 0 +fn=bool std::has_facet > > >(std::locale const&) +0 84 2 2 36 0 0 12 0 0 +fn=bool std::has_facet > > >(std::locale const&) +0 84 2 2 36 1 0 12 0 0 +fn=brk +0 12 2 2 1 0 0 1 1 1 +fn=bsearch +0 904 2 2 164 0 0 118 1 1 +fn=btowc +0 8064 4 4 2176 5 0 1024 0 0 +fn=calloc +0 136 1 1 0 0 0 0 0 0 +fn=check_match.9525 +0 67090 5 5 27652 263 151 7912 22 17 +fn=check_stdfiles_vtables +0 11 2 2 7 4 0 0 0 0 +fn=close +0 30 0 0 6 0 0 0 0 0 +fn=cos +0 8 2 2 3 0 0 0 0 0 +fn=dl_main +0 1288 76 76 269 39 22 145 17 17 +fn=do_lookup_x +0 353038 28 28 113642 2512 638 51810 14 9 +fn=exit +0 6 1 1 1 0 0 2 0 0 +fn=expand_dynamic_string_token +0 66 2 2 12 0 0 18 0 0 +fn=fflush +0 364 5 5 133 4 2 35 0 0 +fn=fillin_rpath +0 253 15 15 51 0 0 59 2 2 +fn=floor +0 5 1 1 3 0 0 0 0 0 +fn=floorf +0 5 2 2 3 0 0 0 0 0 +fn=free +0 54 1 1 27 0 0 9 0 0 +fn=fwrite +0 147 7 7 48 6 2 19 0 0 +fn=gettimeofday +0 15 1 1 1 0 0 5 0 0 +fn=handle_intel.isra.0 +0 94 5 5 14 0 0 26 0 0 +fn=handle_ld_preload +0 686 7 7 70 1 1 17 2 2 +fn=index +0 1401 7 7 117 6 6 0 0 0 +fn=init_cacheinfo +0 150 9 9 11 0 0 15 2 2 +fn=init_cpu_features.constprop.0 +0 122 13 13 18 2 2 21 1 1 +fn=init_tls +0 87 5 5 20 6 0 14 1 1 +fn=intel_02_known_compare +0 324 1 1 162 6 6 0 0 0 +fn=intel_check_word +0 407 11 11 28 0 0 40 1 1 +fn=main +0 10007023 1 1 4003005 3 0 1001006 62500 62388 +fn=malloc +0 120 0 0 0 0 0 0 0 0 +fn=map_doit +0 12 1 1 5 0 0 3 0 0 +fn=match_symbol +0 1563 5 5 617 26 24 171 0 0 +fn=memcpy +0 1061 6 6 179 5 5 149 20 20 +fn=memcpy@@GLIBC_2.14 +0 11 2 2 5 0 0 0 0 0 +fn=memcpy@GLIBC_2.2.5 +0 30 1 1 8 0 0 0 0 0 +fn=mempcpy +0 1556 5 5 214 2 1 149 5 5 +fn=memset +0 5134 4 3 27 0 0 5004 79 79 +fn=mmap +0 623 5 5 138 0 0 114 4 4 +fn=mprotect +0 60 1 1 12 0 0 0 0 0 +fn=munmap +0 5 0 0 1 0 0 0 0 0 +fn=newlocale +0 40 7 7 12 0 0 9 0 0 +fn=open +0 237 1 1 29 0 0 23 0 0 +fn=open_path +0 1539 16 16 523 1 1 192 4 4 +fn=open_verify +0 1758 15 15 410 13 13 358 2 2 +fn=openaux +0 204 2 2 96 0 0 36 0 0 +fn=putc +0 40 4 4 18 0 0 4 0 0 +fn=read +0 25 1 1 5 0 0 0 0 0 +fn=rint +0 5 2 2 3 0 0 0 0 0 +fn=rintf +0 5 1 1 3 0 0 0 0 0 +fn=rtld_lock_default_lock_recursive +0 114 1 1 114 3 1 0 0 0 +fn=rtld_lock_default_unlock_recursive +0 114 0 0 114 0 0 0 0 0 +fn=sbrk +0 17 2 2 5 0 0 2 0 0 +fn=sin +0 8 1 1 3 0 0 0 0 0 +fn=std::__timepunct::_M_initialize_timepunct(__locale_struct*) +0 107 12 12 6 0 0 52 0 0 +fn=std::__timepunct::__timepunct(std::__timepunct_cache*, unsigned long) +0 22 2 2 4 0 0 9 0 0 +fn=std::__timepunct::_M_initialize_timepunct(__locale_struct*) +0 105 12 12 5 0 0 51 0 0 +fn=std::__timepunct::__timepunct(std::__timepunct_cache*, unsigned long) +0 22 2 2 4 0 0 9 1 1 +fn=std::basic_ios >::_M_cache_locale(std::locale const&) +0 120 2 2 12 0 0 44 0 0 +fn=std::basic_ios >::init(std::basic_streambuf >*) +0 88 2 2 12 0 0 40 0 0 +fn=std::basic_ios >::_M_cache_locale(std::locale const&) +0 120 2 2 12 0 0 44 0 0 +fn=std::basic_ios >::init(std::basic_streambuf >*) +0 88 3 3 12 0 0 40 0 0 +fn=std::basic_ostream >& std::__ostream_insert >(std::basic_ostream >&, char const*, long) +0 57 8 8 24 2 0 12 0 0 +fn=std::basic_ostream >& std::endl >(std::basic_ostream >&) +0 20 2 2 7 0 0 3 0 0 +fn=std::basic_ostream >& std::operator<< >(std::basic_ostream >&, char const*) +0 18 2 2 3 0 0 4 0 0 +fn=std::basic_ostream >::flush() +0 42 2 2 21 10 0 6 0 0 +fn=std::codecvt::codecvt(unsigned long) +0 17 1 1 4 0 0 6 1 1 +fn=std::codecvt::codecvt(unsigned long) +0 17 2 2 4 0 0 6 2 2 +fn=std::ctype const& std::use_facet >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::ctype::_M_widen_init() const +0 1056 3 3 9 2 0 263 0 0 +fn=std::ctype::ctype(unsigned short const*, bool, unsigned long) +0 161 8 8 8 1 0 83 9 9 +fn=std::ctype::do_widen(char const*, char const*, char*) const +0 8 1 1 2 0 0 2 0 0 +fn=std::ctype::do_widen(char) const +0 2 1 1 1 0 0 0 0 0 +fn=std::ctype const& std::use_facet >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::ctype::_M_convert_to_wmask(unsigned short) const +0 129 5 5 12 0 0 0 0 0 +fn=std::ctype::_M_initialize_ctype() +0 2757 5 5 5 0 0 810 20 20 +fn=std::ctype::ctype(unsigned long) +0 19 1 1 3 0 0 7 1 1 +fn=std::error_category::error_category() +0 12 1 1 6 1 0 3 0 0 +fn=std::error_category::~error_category() +0 12 1 1 6 1 0 3 0 0 +fn=std::future_category() +0 21 3 3 2 1 1 6 0 0 +fn=std::ios_base::Init::Init() +0 270 31 31 41 8 1 168 16 13 +fn=std::ios_base::Init::~Init() +0 24 3 3 9 8 0 7 0 0 +fn=std::ios_base::_M_init() +0 192 3 3 48 0 0 72 0 0 +fn=std::ios_base::ios_base() +0 472 3 3 8 0 0 216 31 26 +fn=std::locale::_Impl::_Impl(unsigned long) +0 819 66 66 132 14 1 406 44 44 +fn=std::locale::_Impl::_M_install_facet(std::locale::id const*, std::locale::facet const*) +0 7448 7 7 2716 0 0 224 0 0 +fn=std::locale::facet::_S_create_c_locale(__locale_struct*&, char const*, __locale_struct*) +0 9 1 1 2 0 0 3 0 0 +fn=std::locale::facet::_S_get_c_locale() +0 92 1 1 50 1 1 11 0 0 +fn=std::locale::facet::_S_get_c_name() +0 10 1 1 5 0 0 0 0 0 +fn=std::locale::id::_M_id() const +0 705 1 1 226 9 2 56 0 0 +fn=std::locale::locale() +0 462 4 4 176 1 0 132 2 1 +fn=std::locale::operator=(std::locale const&) +0 136 3 3 56 0 0 24 0 0 +fn=std::locale::~locale() +0 96 1 1 40 0 0 16 0 0 +fn=std::messages::messages(unsigned long) +0 19 2 2 4 0 0 8 0 0 +fn=std::messages::messages(unsigned long) +0 19 1 1 4 0 0 8 0 0 +fn=std::moneypunct::_M_initialize_moneypunct(__locale_struct*, char const*) +0 112 5 5 37 1 1 31 0 0 +fn=std::moneypunct::_M_initialize_moneypunct(__locale_struct*, char const*) +0 112 5 5 37 0 0 31 0 0 +fn=std::moneypunct::_M_initialize_moneypunct(__locale_struct*, char const*) +0 108 6 6 29 0 0 32 0 0 +fn=std::moneypunct::_M_initialize_moneypunct(__locale_struct*, char const*) +0 108 6 6 29 0 0 32 0 0 +fn=std::num_get > > const& std::use_facet > > >(std::locale const&) +0 76 1 1 36 0 0 12 0 0 +fn=std::num_get > > const& std::use_facet > > >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::num_put > > const& std::use_facet > > >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::num_put > >::do_put(std::ostreambuf_iterator >, std::ios_base&, char, long) const +0 5 2 2 1 0 0 1 0 0 +fn=std::num_put > > const& std::use_facet > > >(std::locale const&) +0 76 2 2 36 0 0 12 0 0 +fn=std::numpunct::_M_initialize_numpunct(__locale_struct*) +0 413 4 4 136 3 2 75 0 0 +fn=std::numpunct::_M_initialize_numpunct(__locale_struct*) +0 349 6 6 73 0 0 75 3 3 +fn=std::ostream& std::ostream::_M_insert(long) +0 72 7 7 28 4 0 13 0 0 +fn=std::ostream::flush() +0 56 1 1 28 6 0 8 0 0 +fn=std::ostream::operator<<(int) +0 10 1 1 3 0 0 0 0 0 +fn=std::ostream::operator<<(std::ostream& (*)(std::ostream&)) +0 1 1 1 0 0 0 0 0 0 +fn=std::ostream::put(char) +0 40 4 4 17 0 0 6 0 0 +fn=std::ostream::sentry::sentry(std::ostream&) +0 69 2 2 24 3 0 15 0 0 +fn=std::ostreambuf_iterator > std::num_put > >::_M_insert_int(std::ostreambuf_iterator >, std::ios_base&, char, long) const +0 97 7 7 25 4 0 19 0 0 +fn=strcasecmp +0 12 2 2 3 2 0 0 0 0 +fn=strcmp +0 130809 2 2 38693 153 50 0 0 0 +fn=strdup +0 68 1 1 8 0 0 16 0 0 +fn=strlen +0 1457 6 5 157 2 1 0 0 0 +fn=strncasecmp +0 12 2 2 3 0 0 0 0 0 +fn=strnlen +0 5 1 1 3 0 0 0 0 0 +fn=strsep +0 432 1 1 134 0 0 3 0 0 +fn=time +0 15 2 2 1 0 0 5 0 0 +fn=uname +0 5 1 1 1 0 0 0 0 0 +fn=uselocale +0 42 3 3 18 5 0 8 1 0 +fn=version_check_doit +0 10 1 1 4 0 0 2 0 0 +fn=wctob +0 2432 2 2 768 0 0 640 0 0 +fn=wctype_l +0 876 2 2 139 4 0 153 0 0 +fn=write +0 2 1 1 1 0 0 0 0 0 +summary: 11390464 1372 1343 4351585 9127 5267 1130849 64167 63666 diff --git a/CPE435/Lab9/cachegrind.out.27944 b/CPE435/Lab9/cachegrind.out.27944 new file mode 100644 index 0000000..80d4354 --- /dev/null +++ b/CPE435/Lab9/cachegrind.out.27944 @@ -0,0 +1,249 @@ +desc: I1 cache: 32768 B, 64 B, 8-way associative +desc: D1 cache: 32768 B, 64 B, 8-way associative +desc: LL cache: 8388608 B, 64 B, 16-way associative +cmd: ./test3 +events: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +fl=??? +fn=(below main) +0 62 4 4 17 2 0 17 0 0 +fn=??? +0 188 19 16 93 5 0 23 1 1 +fn=_Exit +0 8 2 2 1 0 0 0 0 0 +fn=_IO_cleanup +0 57 3 3 16 0 0 10 0 0 +fn=_IO_flush_all_lockp +0 92 9 9 26 11 5 13 0 0 +fn=__GI_strrchr +0 51 4 4 3 1 0 0 0 0 +fn=__ctype_init +0 16 2 2 10 3 0 3 0 0 +fn=__cxa_atexit +0 22 2 2 5 0 0 8 0 0 +fn=__cxa_finalize +0 46 4 4 12 1 0 6 0 0 +fn=__default_morecore +0 16 1 1 2 0 0 2 0 0 +fn=__init_misc +0 24 2 2 7 0 0 5 1 0 +fn=__libc_csu_init +0 34 2 2 8 1 0 8 0 0 +fn=__libc_memalign +0 740 5 5 124 0 0 122 1 1 +fn=__new_exitfn +0 39 5 5 11 5 3 5 0 0 +fn=__run_exit_handlers +0 54 4 4 9 4 0 9 0 0 +fn=__sigjmp_save +0 9 0 0 2 0 0 2 0 0 +fn=__sigsetjmp +0 79 5 5 19 0 0 32 2 2 +fn=__unregister_atfork +0 7 2 2 3 1 1 1 0 0 +fn=_dl_add_to_namespace_list +0 106 3 3 26 0 0 20 0 0 +fn=_dl_add_to_slotinfo +0 24 3 3 9 3 0 6 0 0 +fn=_dl_addr +0 56525 10 10 13788 1030 865 16 2 0 +fn=_dl_allocate_tls_init +0 81 6 6 25 2 0 13 0 0 +fn=_dl_allocate_tls_storage +0 332 3 3 7 0 0 295 37 37 +fn=_dl_cache_libcmp +0 723 4 4 110 9 9 0 0 0 +fn=_dl_catch_error +0 108 4 4 33 0 0 51 5 5 +fn=_dl_check_all_versions +0 75 3 3 13 0 0 8 0 0 +fn=_dl_check_map_versions +0 1152 14 14 375 14 13 158 12 12 +fn=_dl_count_modids +0 4 2 2 3 0 0 0 0 0 +fn=_dl_debug_initialize +0 41 3 3 13 2 1 4 0 0 +fn=_dl_debug_state +0 2 1 1 2 0 0 0 0 0 +fn=_dl_determine_tlsoffset +0 56 4 4 11 0 0 8 0 0 +fn=_dl_discover_osversion +0 88 4 4 15 2 2 7 1 1 +fn=_dl_dst_count +0 34 1 1 10 0 0 10 1 1 +fn=_dl_fini +0 263 12 12 94 22 0 31 4 0 +fn=_dl_fixup +0 199 5 5 74 10 0 18 0 0 +fn=_dl_important_hwcaps +0 267 19 19 48 0 0 45 2 2 +fn=_dl_init +0 191 11 11 62 6 0 21 0 0 +fn=_dl_init_paths +0 379 18 18 44 0 0 41 4 4 +fn=_dl_initial_error_catch_tsd +0 8 0 0 4 0 0 0 0 0 +fn=_dl_load_cache_lookup +0 331 16 16 62 9 9 31 1 1 +fn=_dl_lookup_symbol_x +0 18712 11 11 3760 101 91 2209 13 4 +fn=_dl_map_object +0 412 23 23 89 0 0 75 9 9 +fn=_dl_map_object_deps +0 1145 38 38 248 1 1 120 4 4 +fn=_dl_map_object_from_fd +0 1733 46 46 380 20 20 183 26 26 +fn=_dl_name_match_p +0 995 2 2 257 3 0 148 4 4 +fn=_dl_new_object +0 593 12 12 103 4 4 109 24 24 +fn=_dl_next_ld_env_entry +0 268 2 2 93 0 0 2 0 0 +fn=_dl_next_tls_modid +0 6 2 2 3 0 0 1 0 0 +fn=_dl_process_tunable_env_entries +0 243 2 2 82 22 22 1 0 0 +fn=_dl_receive_error +0 28 2 2 10 0 0 12 0 0 +fn=_dl_relocate_object +0 18503 47 47 5026 663 613 2260 254 243 +fn=_dl_runtime_resolve_xsave +0 120 4 4 144 1 0 150 20 11 +fn=_dl_setup_hash +0 92 2 2 28 5 5 24 0 0 +fn=_dl_sort_fini +0 199 7 7 54 1 0 21 0 0 +fn=_dl_start +0 686 16 16 142 26 24 57 19 18 +fn=_dl_sysdep_read_whole_file +0 41 3 3 6 0 0 9 1 1 +fn=_dl_sysdep_start +0 406 11 11 109 15 14 30 5 5 +fn=_dl_sysdep_start_cleanup +0 1 1 1 1 0 0 0 0 0 +fn=_dl_unload_cache +0 10 2 1 3 2 0 2 0 0 +fn=_dl_vdso_vsym +0 28 2 2 12 1 0 0 0 0 +fn=_fxstat +0 30 2 2 3 0 0 0 0 0 +fn=_init +0 60 6 6 14 2 0 18 4 3 +fn=_int_malloc +0 145 15 15 22 3 2 25 1 0 +fn=_setjmp +0 2 1 1 0 0 0 0 0 0 +fn=_xstat +0 49 1 1 4 0 0 3 0 0 +fn=access +0 9 1 1 1 0 0 1 0 0 +fn=bcmp +0 1157 14 14 289 11 11 82 2 2 +fn=brk +0 51 3 3 7 0 0 4 1 1 +fn=bsearch +0 904 2 2 164 0 0 118 1 1 +fn=calloc +0 64 1 1 0 0 0 0 0 0 +fn=check_match.9525 +0 4674 5 5 1930 25 12 554 6 4 +fn=check_stdfiles_vtables +0 11 2 2 7 3 0 0 0 0 +fn=close +0 15 0 0 3 0 0 0 0 0 +fn=dl_main +0 1154 76 76 232 28 21 138 17 17 +fn=do_lookup_x +0 23235 14 14 7586 178 134 3571 11 7 +fn=exit +0 6 1 1 1 0 0 2 0 0 +fn=expand_dynamic_string_token +0 66 2 2 12 0 0 18 0 0 +fn=fillin_rpath +0 253 15 15 51 0 0 59 2 2 +fn=free +0 24 1 1 12 0 0 4 0 0 +fn=gettimeofday +0 15 1 1 1 0 0 5 0 0 +fn=handle_intel.isra.0 +0 94 5 5 14 0 0 26 0 0 +fn=handle_ld_preload +0 686 7 7 70 1 1 17 2 2 +fn=index +0 494 7 7 39 2 2 0 0 0 +fn=init_cacheinfo +0 150 9 9 11 0 0 15 2 2 +fn=init_cpu_features.constprop.0 +0 122 13 13 18 2 2 21 1 1 +fn=init_tls +0 65 5 5 14 1 0 13 1 1 +fn=intel_02_known_compare +0 324 1 1 162 6 6 0 0 0 +fn=intel_check_word +0 407 11 11 28 0 0 40 1 1 +fn=main +0 9 0 0 2 1 0 3 0 0 +fn=malloc +0 119 4 4 18 3 0 5 0 0 +fn=malloc_consolidate +0 793 3 3 9 0 0 263 33 32 +fn=malloc_hook_ini +0 11 2 2 3 1 1 3 0 0 +fn=map_doit +0 12 1 1 5 0 0 3 0 0 +fn=match_symbol +0 179 5 5 72 4 4 27 0 0 +fn=memcpy +0 462 6 6 72 0 0 58 6 6 +fn=memcpy@GLIBC_2.2.5 +0 15 1 1 4 0 0 0 0 0 +fn=mempcpy +0 589 5 5 79 2 1 54 4 4 +fn=memset +0 2130 3 3 13 0 0 2068 33 33 +fn=mmap +0 295 3 3 65 0 0 54 1 1 +fn=mprotect +0 30 1 1 6 0 0 0 0 0 +fn=munmap +0 5 0 0 1 0 0 0 0 0 +fn=open +0 87 1 1 11 0 0 8 0 0 +fn=open_path +0 531 16 16 184 1 1 66 4 4 +fn=open_verify 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+415379638 +375954827 +42335249 +1434720003 +219634299 +1241999586 +1289892586 +2031295930 +7116818 +1478085037 +1629158947 +1017045480 +468328566 +1561675606 +1648098279 +10330311 +1117101527 +1580937414 +131224163 +1818970573 +216589031 +45721903 +740251665 +1334734871 +1490207261 +1436651612 +1952541853 +191642544 +1985617327 +1533514245 +1334275970 +253513318 +1909469072 +1376611220 +1688233321 +2129103371 +471127158 +830642259 +2012915653 +478243976 +161243648 +1494590953 +1495289456 +629572215 +908782911 +995904087 +639902526 +2025884438 +429357853 +771126689 diff --git a/CPE435/Lab9/rand b/CPE435/Lab9/rand new file mode 100755 index 0000000..09194a4 Binary files /dev/null and b/CPE435/Lab9/rand differ diff --git a/CPE435/Lab9/rand.c b/CPE435/Lab9/rand.c new file mode 100644 index 0000000..4c5c7bb --- /dev/null +++ b/CPE435/Lab9/rand.c @@ -0,0 +1,15 @@ +#include +#include + +// Generate 1 million random 32-bit integers. + +int main (int argc, char **argv) { + rand(); + FILE *ptr = fopen(argv[1], "w"); + int i, n; + n = atoi(argv[2]); + for (i = 0; i < n; i++) { + int x = (int)rand(); + fprintf(ptr,"%i\n", x); + } +} \ No newline at end of file diff --git a/CPE435/Lab9/rapl-read b/CPE435/Lab9/rapl-read new file mode 100755 index 0000000..2721406 Binary files /dev/null and b/CPE435/Lab9/rapl-read differ diff --git a/CPE435/Lab9/rapl-read.c b/CPE435/Lab9/rapl-read.c new file mode 100644 index 0000000..835e211 --- /dev/null +++ b/CPE435/Lab9/rapl-read.c @@ -0,0 +1,1121 @@ +/* Read the RAPL registers on recent (>sandybridge) Intel processors */ +/* */ +/* There are currently three ways to do this: */ +/* 1. Read the MSRs directly with /dev/cpu/??/msr */ +/* 2. Use the perf_event_open() interface */ +/* 3. Read the values from the sysfs powercap interface */ +/* */ +/* MSR Code originally based on a (never made it upstream) linux-kernel */ +/* RAPL driver by Zhang Rui */ +/* https://lkml.org/lkml/2011/5/26/93 */ +/* Additional contributions by: */ +/* Romain Dolbeau -- romain @ dolbeau.org */ +/* */ +/* For raw MSR access the /dev/cpu/??/msr driver must be enabled and */ +/* permissions set to allow read access. */ +/* You might need to "modprobe msr" before it will work. */ +/* */ +/* perf_event_open() support requires at least Linux 3.14 and to have */ +/* /proc/sys/kernel/perf_event_paranoid < 1 */ +/* */ +/* the sysfs powercap interface got into the kernel in */ +/* 2d281d8196e38dd (3.13) */ +/* */ +/* Compile with: gcc -O2 -Wall -o rapl-read rapl-read.c -lm */ +/* */ +/* Vince Weaver -- vincent.weaver @ maine.edu -- 11 September 2015 */ +/* */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define MSR_RAPL_POWER_UNIT 0x606 + +/* + * Platform specific RAPL Domains. + * Note that PP1 RAPL Domain is supported on 062A only + * And DRAM RAPL Domain is supported on 062D only + */ +/* Package RAPL Domain */ +#define MSR_PKG_RAPL_POWER_LIMIT 0x610 +#define MSR_PKG_ENERGY_STATUS 0x611 +#define MSR_PKG_PERF_STATUS 0x613 +#define MSR_PKG_POWER_INFO 0x614 + +/* PP0 RAPL Domain */ +#define MSR_PP0_POWER_LIMIT 0x638 +#define MSR_PP0_ENERGY_STATUS 0x639 +#define MSR_PP0_POLICY 0x63A +#define MSR_PP0_PERF_STATUS 0x63B + +/* PP1 RAPL Domain, may reflect to uncore devices */ +#define MSR_PP1_POWER_LIMIT 0x640 +#define MSR_PP1_ENERGY_STATUS 0x641 +#define MSR_PP1_POLICY 0x642 + +/* DRAM RAPL Domain */ +#define MSR_DRAM_POWER_LIMIT 0x618 +#define MSR_DRAM_ENERGY_STATUS 0x619 +#define MSR_DRAM_PERF_STATUS 0x61B +#define MSR_DRAM_POWER_INFO 0x61C + +/* PSYS RAPL Domain */ +#define MSR_PLATFORM_ENERGY_STATUS 0x64d + +/* RAPL UNIT BITMASK */ +#define POWER_UNIT_OFFSET 0 +#define POWER_UNIT_MASK 0x0F + +#define ENERGY_UNIT_OFFSET 0x08 +#define ENERGY_UNIT_MASK 0x1F00 + +#define TIME_UNIT_OFFSET 0x10 +#define TIME_UNIT_MASK 0xF000 + +#define quickArraySize 1000000 + +//int arrQuick[quickArraySize]; +struct timeval tv1,tv2; + +#define TIMER_CLEAR (tv1.tv_sec = tv1.tv_usec = tv2.tv_sec = tv2.tv_usec = 0) +#define TIMER_START gettimeofday(&tv1, (struct timezone*)0) +#define TIMER_ELAPSED (double) (tv2.tv_usec-tv1.tv_usec)/1000000.0+(tv2.tv_sec-tv1.tv_sec) +#define TIMER_STOP gettimeofday(&tv2, (struct timezone*)0) + +// function to swap elements +void swap(int *a, int *b); + +// function to find the partition position +int partition(int array[], int low, long int high) { + + // select the rightmost element as pivot + int pivot = array[high]; + + // pointer for greater element + int i = (low - 1); + int j; + // traverse each element of the array + // compare them with the pivot + for (j = low; j < high; j++) { + if (array[j] <= pivot) { + + // if element smaller than pivot is found + // swap it with the greater element pointed by i + i++; + + // swap element at i with element at j + swap(&array[i], &array[j]); + } + } + + // swap the pivot element with the greater element at i + swap(&array[i + 1], &array[high]); + + // return the partition point + return (i + 1); +} + +void quickSort(int array[], int low, long int high) { + if (low < high) { + + // find the pivot element such that + // elements smaller than pivot are on left of pivot + // elements greater than pivot are on right of pivot + int pi = partition(array, low, high); + + // recursive call on the left of pivot + quickSort(array, low, pi - 1); + + // recursive call on the right of pivot + quickSort(array, pi + 1, high); + } +} + +void insertionSort(int array[], long int size) { + int step; + for (step = 1; step < size; step++) { + int key = array[step]; + int j = step - 1; + + // Compare key with each element on the left of it until an element smaller than + // it is found. + // For descending order, change keyarray[j]. + while (key < array[j] && j >= 0) { + array[j + 1] = array[j]; + --j; + } + array[j + 1] = key; + } +} + +// Merges two subarrays of arr[]. +// First subarray is arr[l..m] +// Second subarray is arr[m+1..r] +void merge(int arr[], long int l, long int m, long int r) +{ + long int i, j, k; + long int n1 = m - l + 1; + long int n2 = r - m; + + /* create temp arrays */ + long int L[n1], R[n2]; + + /* Copy data to temp arrays L[] and R[] */ + for (i = 0; i < n1; i++) + L[i] = arr[l + i]; + for (j = 0; j < n2; j++) + R[j] = arr[m + 1 + j]; + + /* Merge the temp arrays back into arr[l..r]*/ + i = 0; // Initial index of first subarray + j = 0; // Initial index of second subarray + k = l; // Initial index of merged subarray + while (i < n1 && j < n2) { + if (L[i] <= R[j]) { + arr[k] = L[i]; + i++; + } + else { + arr[k] = R[j]; + j++; + } + k++; + } + + /* Copy the remaining elements of L[], if there + are any */ + while (i < n1) { + arr[k] = L[i]; + i++; + k++; + } + + /* Copy the remaining elements of R[], if there + are any */ + while (j < n2) { + arr[k] = R[j]; + j++; + k++; + } +} + +/* l is for left index and r is right index of the +sub-array of arr to be sorted */ +void mergeSort(int arr[], long int l, long int r) +{ + if (l < r) { + // Same as (l+r)/2, but avoids overflow for + // large l and h + long int m = l + (r - l) / 2; + + // Sort first and second halves + mergeSort(arr, l, m); + mergeSort(arr, m + 1, r); + + merge(arr, l, m, r); + } +} + +bool sort_verify(int a[], long int size) { + long int i; + bool comp; + for(i=0;i=a[i]) + comp = true; + else comp = false; + } + return comp; +} + +void top_level(long int n); + + + +static int open_msr(int core) { + + char msr_filename[BUFSIZ]; + int fd; + + sprintf(msr_filename, "/dev/cpu/%d/msr", core); + fd = open(msr_filename, O_RDONLY); + if ( fd < 0 ) { + if ( errno == ENXIO ) { + fprintf(stderr, "rdmsr: No CPU %d\n", core); + exit(2); + } else if ( errno == EIO ) { + fprintf(stderr, "rdmsr: CPU %d doesn't support MSRs\n", + core); + exit(3); + } else { + perror("rdmsr:open"); + fprintf(stderr,"Trying to open %s\n",msr_filename); + exit(127); + } + } + + return fd; +} + +static long long read_msr(int fd, int which) { + + uint64_t data; + + if ( pread(fd, &data, sizeof data, which) != sizeof data ) { + perror("rdmsr:pread"); + exit(127); + } + + return (long long)data; +} + +#define CPU_SANDYBRIDGE 42 +#define CPU_SANDYBRIDGE_EP 45 +#define CPU_IVYBRIDGE 58 +#define CPU_IVYBRIDGE_EP 62 +#define CPU_HASWELL 60 +#define CPU_HASWELL_ULT 69 +#define CPU_HASWELL_GT3E 70 +#define CPU_HASWELL_EP 63 +#define CPU_BROADWELL 61 +#define CPU_BROADWELL_GT3E 71 +#define CPU_BROADWELL_EP 79 +#define CPU_BROADWELL_DE 86 +#define CPU_SKYLAKE 78 +#define CPU_SKYLAKE_HS 94 +#define CPU_SKYLAKE_X 85 +#define CPU_KNIGHTS_LANDING 87 +#define CPU_KNIGHTS_MILL 133 +#define CPU_KABYLAKE_MOBILE 142 +#define CPU_KABYLAKE 158 +#define CPU_ATOM_SILVERMONT 55 +#define CPU_ATOM_AIRMONT 76 +#define CPU_ATOM_MERRIFIELD 74 +#define CPU_ATOM_MOOREFIELD 90 +#define CPU_ATOM_GOLDMONT 92 +#define CPU_ATOM_GEMINI_LAKE 122 +#define CPU_ATOM_DENVERTON 95 + +/* TODO: on Skylake, also may support PSys "platform" domain, */ +/* the whole SoC not just the package. */ +/* see dcee75b3b7f025cc6765e6c92ba0a4e59a4d25f4 */ + +static int detect_cpu(void) { + + FILE *fff; + + int family,model=-1; + char buffer[BUFSIZ],*result; + char vendor[BUFSIZ]; + + fff=fopen("/proc/cpuinfo","r"); + if (fff==NULL) return -1; + + while(1) { + result=fgets(buffer,BUFSIZ,fff); + if (result==NULL) break; + + if (!strncmp(result,"vendor_id",8)) { + sscanf(result,"%*s%*s%s",vendor); + + if (strncmp(vendor,"GenuineIntel",12)) { + printf("%s not an Intel chip\n",vendor); + return -1; + } + } + + if (!strncmp(result,"cpu family",10)) { + sscanf(result,"%*s%*s%*s%d",&family); + if (family!=6) { + printf("Wrong CPU family %d\n",family); + return -1; + } + } + + if (!strncmp(result,"model",5)) { + sscanf(result,"%*s%*s%d",&model); + } + + } + + fclose(fff); + + printf("Found "); + + switch(model) { + case CPU_SANDYBRIDGE: + printf("Sandybridge"); + break; + case CPU_SANDYBRIDGE_EP: + printf("Sandybridge-EP"); + break; + case CPU_IVYBRIDGE: + printf("Ivybridge"); + break; + case CPU_IVYBRIDGE_EP: + printf("Ivybridge-EP"); + break; + case CPU_HASWELL: + case CPU_HASWELL_ULT: + case CPU_HASWELL_GT3E: + printf("Haswell"); + break; + case CPU_HASWELL_EP: + printf("Haswell-EP"); + break; + case CPU_BROADWELL: + case CPU_BROADWELL_GT3E: + printf("Broadwell"); + break; + case CPU_BROADWELL_EP: + printf("Broadwell-EP"); + break; + case CPU_SKYLAKE: + case CPU_SKYLAKE_HS: + printf("Skylake"); + break; + case CPU_SKYLAKE_X: + printf("Skylake-X"); + break; + case CPU_KABYLAKE: + case CPU_KABYLAKE_MOBILE: + printf("Kaby Lake"); + break; + case CPU_KNIGHTS_LANDING: + printf("Knight's Landing"); + break; + case CPU_KNIGHTS_MILL: + printf("Knight's Mill"); + break; + case CPU_ATOM_GOLDMONT: + case CPU_ATOM_GEMINI_LAKE: + case CPU_ATOM_DENVERTON: + printf("Atom"); + break; + default: + printf("Unsupported model %d\n",model); + model=-1; + break; + } + + printf(" Processor type\n"); + + return model; +} + +#define MAX_CPUS 1024 +#define MAX_PACKAGES 16 + +static int total_cores=0,total_packages=0; +static int package_map[MAX_PACKAGES]; + +static int detect_packages(void) { + + char filename[BUFSIZ]; + FILE *fff; + int package; + int i; + + for(i=0;i>8)&0x1f)); + time_units=pow(0.5,(double)((result>>16)&0xf)); + + /* On Haswell EP and Knights Landing */ + /* The DRAM units differ from the CPU ones */ + if (different_units) { + dram_energy_units[j]=pow(0.5,(double)16); + printf("DRAM: Using %lf instead of %lf\n", + dram_energy_units[j],cpu_energy_units[j]); + } + else { + dram_energy_units[j]=cpu_energy_units[j]; + } + + printf("\t\tPower units = %.3fW\n",power_units); + printf("\t\tCPU Energy units = %.8fJ\n",cpu_energy_units[j]); + printf("\t\tDRAM Energy units = %.8fJ\n",dram_energy_units[j]); + printf("\t\tTime units = %.8fs\n",time_units); + printf("\n"); + + /* Show package power info */ + result=read_msr(fd,MSR_PKG_POWER_INFO); + thermal_spec_power=power_units*(double)(result&0x7fff); + printf("\t\tPackage thermal spec: %.3fW\n",thermal_spec_power); + minimum_power=power_units*(double)((result>>16)&0x7fff); + printf("\t\tPackage minimum power: %.3fW\n",minimum_power); + maximum_power=power_units*(double)((result>>32)&0x7fff); + printf("\t\tPackage maximum power: %.3fW\n",maximum_power); + time_window=time_units*(double)((result>>48)&0x7fff); + printf("\t\tPackage maximum time window: %.6fs\n",time_window); + + /* Show package power limit */ + result=read_msr(fd,MSR_PKG_RAPL_POWER_LIMIT); + printf("\t\tPackage power limits are %s\n", (result >> 63) ? "locked" : "unlocked"); + double pkg_power_limit_1 = power_units*(double)((result>>0)&0x7FFF); + double pkg_time_window_1 = time_units*(double)((result>>17)&0x007F); + printf("\t\tPackage power limit #1: %.3fW for %.6fs (%s, %s)\n", + pkg_power_limit_1, pkg_time_window_1, + (result & (1LL<<15)) ? "enabled" : "disabled", + (result & (1LL<<16)) ? "clamped" : "not_clamped"); + double pkg_power_limit_2 = power_units*(double)((result>>32)&0x7FFF); + double pkg_time_window_2 = time_units*(double)((result>>49)&0x007F); + printf("\t\tPackage power limit #2: %.3fW for %.6fs (%s, %s)\n", + pkg_power_limit_2, pkg_time_window_2, + (result & (1LL<<47)) ? "enabled" : "disabled", + (result & (1LL<<48)) ? "clamped" : "not_clamped"); + + /* only available on *Bridge-EP */ + if ((cpu_model==CPU_SANDYBRIDGE_EP) || (cpu_model==CPU_IVYBRIDGE_EP)) { + result=read_msr(fd,MSR_PKG_PERF_STATUS); + double acc_pkg_throttled_time=(double)result*time_units; + printf("\tAccumulated Package Throttled Time : %.6fs\n", + acc_pkg_throttled_time); + } + + /* only available on *Bridge-EP */ + if ((cpu_model==CPU_SANDYBRIDGE_EP) || (cpu_model==CPU_IVYBRIDGE_EP)) { + result=read_msr(fd,MSR_PP0_PERF_STATUS); + double acc_pp0_throttled_time=(double)result*time_units; + printf("\tPowerPlane0 (core) Accumulated Throttled Time " + ": %.6fs\n",acc_pp0_throttled_time); + + result=read_msr(fd,MSR_PP0_POLICY); + int pp0_policy=(int)result&0x001f; + printf("\tPowerPlane0 (core) for core %d policy: %d\n",core,pp0_policy); + + } + + + if (pp1_avail) { + result=read_msr(fd,MSR_PP1_POLICY); + int pp1_policy=(int)result&0x001f; + printf("\tPowerPlane1 (on-core GPU if avail) %d policy: %d\n", + core,pp1_policy); + } + close(fd); + + } + printf("\n"); + + for(j=0;j0) { + printf("\t/proc/sys/kernel/perf_event_paranoid is %d\n",paranoid_value); + printf("\tThe value must be 0 or lower to read system-wide RAPL values\n"); + } + + printf("\tPermission denied; run as root or adjust paranoid value\n\n"); + return -1; + } + else { + printf("\terror opening core %d config %d: %s\n\n", + package_map[j], config[i], strerror(errno)); + return -1; + } + } + } + } + + printf("\n\tSleeping 1 second\n\n"); + sleep(1); + + for(j=0;j +main() +{ + int array[1000][1000]; + int i,j; + for(i=0;i<1000;i++) + for(j=0;j<1000;j++) + array[i][j]=0; + cout << "array[0][0] was " << array[0][0] << endl; +} diff --git a/CPE435/Lab9/test2 b/CPE435/Lab9/test2 new file mode 100755 index 0000000..fee89cf Binary files /dev/null and b/CPE435/Lab9/test2 differ diff --git a/CPE435/Lab9/test2.cpp b/CPE435/Lab9/test2.cpp new file mode 100644 index 0000000..6eca21a --- /dev/null +++ b/CPE435/Lab9/test2.cpp @@ -0,0 +1,15 @@ +/* +File: test2.cpp +compile as g++ test2.cpp -o test2 +*/ +using namespace std; +#include +main() +{ + int array[1000][1000]; + int i,j; + for(i=0;i<1000;i++) + for(j=0;j<1000;j++) + array[j][i]=0; + cout << "array[0][0] was " << array[0][0] << endl; +} diff --git a/CPE435/Lab9/test3 b/CPE435/Lab9/test3 new file mode 100755 index 0000000..a9bf706 Binary files /dev/null and b/CPE435/Lab9/test3 differ diff --git a/CPE435/Lab9/test3.c b/CPE435/Lab9/test3.c new file mode 100644 index 0000000..f49673d --- /dev/null +++ b/CPE435/Lab9/test3.c @@ -0,0 +1,7 @@ +//file: test 3 compile as test3 +#include +int main() +{ + char *x = (char*)malloc(100); /* or, in C++, "char *x = new char[100] */ + return 0; +} diff --git a/CPE435/Lab9/test4 b/CPE435/Lab9/test4 new file mode 100755 index 0000000..8f28fb7 Binary files /dev/null and b/CPE435/Lab9/test4 differ diff --git a/CPE435/Lab9/test4.c b/CPE435/Lab9/test4.c new file mode 100644 index 0000000..80edf43 --- /dev/null +++ b/CPE435/Lab9/test4.c @@ -0,0 +1,8 @@ +//file: test4 compile as test4 +#include +int main() +{ + char *x = (char*)malloc(10); + x[10] = 'a'; + return 0; +} diff --git a/CPE435/Lab9/test5 b/CPE435/Lab9/test5 new file mode 100755 index 0000000..d243583 Binary files /dev/null and b/CPE435/Lab9/test5 differ diff --git a/CPE435/Lab9/test5.c b/CPE435/Lab9/test5.c new file mode 100644 index 0000000..9e13359 --- /dev/null +++ b/CPE435/Lab9/test5.c @@ -0,0 +1,11 @@ +//file: test5 compile as test5 +#include +int main() +{ + int x; + if(x == 0) + { + printf("X is zero"); /* replace with cout and include iostream for C++ */ + } + return 0; +} diff --git a/CPE455/.vscode/configurationCache.log b/CPE455/.vscode/configurationCache.log new file mode 100644 index 0000000..a27a703 --- /dev/null +++ b/CPE455/.vscode/configurationCache.log @@ -0,0 +1 @@ +{"buildTargets":["make"],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}} \ No newline at end of file diff --git a/CPE455/.vscode/dryrun.log b/CPE455/.vscode/dryrun.log new file mode 100644 index 0000000..e5e73f0 --- /dev/null +++ b/CPE455/.vscode/dryrun.log @@ -0,0 +1,6 @@ +make --dry-run --always-make --keep-going --print-directory +make: Entering directory `/home/student/anw0044/CPE455' +make: Leaving directory `/home/student/anw0044/CPE455' + +make: *** No targets specified and no makefile found. Stop. + diff --git a/CPE455/.vscode/settings.json b/CPE455/.vscode/settings.json new file mode 100644 index 0000000..65e1ec0 --- /dev/null +++ b/CPE455/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "makefile.extensionOutputFolder": "./.vscode" +} \ No newline at end of file diff --git a/CPE455/.vscode/targets.log b/CPE455/.vscode/targets.log new file mode 100644 index 0000000..5d35af6 --- /dev/null +++ b/CPE455/.vscode/targets.log @@ -0,0 +1,307 @@ +make all --print-data-base --no-builtin-variables --no-builtin-rules --question +# GNU Make 3.82 +# Built for x86_64-redhat-linux-gnu +# Copyright (C) 2010 Free Software Foundation, Inc. +# License GPLv3+: GNU GPL version 3 or later +# This is free software: you are free to change and redistribute it. +# There is NO WARRANTY, to the extent permitted by law. + +# Make data base, printed on Sun Apr 17 17:47:25 2022 + +# Variables + +# automatic + +#include +#include + +#define BUFFER_SIZE 20 + +int main() +{ + char correctPassword[BUFFER_SIZE]; + char suppliedPassword[BUFFER_SIZE]; + + printf("\nEnter the password now: "); + strncpy(correctPassword, "aaaaabbbbbccccc", BUFFER_SIZE); + gets(suppliedPassword); + printf("\n"); + + if (strncmp(suppliedPassword, correctPassword, BUFFER_SIZE) == 0) + { + printf("Login successful\n\n"); + } + else + { + printf("Login failure\n\n"); + } + + printf("suppliedPassword: %s\n", suppliedPassword); + printf("correctPassword: %s\n", correctPassword); + + return 0; +} + + diff --git a/CPE455/Quiz-Bravo/makefile b/CPE455/Quiz-Bravo/makefile new file mode 100644 index 0000000..5e01fd2 --- /dev/null +++ b/CPE455/Quiz-Bravo/makefile @@ -0,0 +1,18 @@ +# +# bapp.c makefile +# + +CC = gcc +CFLAGS = -g + +vulnerable_bapp: bapp.c + $(CC) $(CFLAGS) -fno-stack-protector -z execstack bapp.c -o vulnerable_bapp + +protected_bapp: bapp.c + $(CC) $(CFLAGS) -fstack-protector -z noexecstack bapp.c -o protected_bapp + +clean: + rm vulnerable_bapp protected_bapp + + + diff --git a/CPE455/Quiz-Bravo/protected.txt b/CPE455/Quiz-Bravo/protected.txt new file mode 100644 index 0000000..c30e4af --- /dev/null +++ b/CPE455/Quiz-Bravo/protected.txt @@ -0,0 +1,92 @@ +Script started on Thu 24 Feb 2022 10:16:22 AM CST +[?1034hbash-4.2$ ./protected_bapp + +Enter the password now: aaaa + +Login failure + +suppliedPassword: aaaa +correctPassword: aaaaabbbbbccccc +bash-4.2$ ./protected_bapp + +Enter the password now: aaaaabbbbbccccc + +Login successful + +suppliedPassword: aaaaabbbbbccccc +correctPassword: aaaaabbbbbccccc +bash-4.2$ perl -e 'print "a"x90' | ./protected_bapp + +Enter the password now: +Login failure + +suppliedPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +correctPassword: aaaaabbbbbccccc +*** stack smashing detected ***: ./protected_bapp terminated +Segmentation fault +bash-4.2$ gdb ./protected_bapp +[?1034hGNU gdb (GDB) Red Hat Enterprise Linux 7.6.1-120.el7 +Copyright (C) 2013 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +For bug reporting instructions, please see: +... +Reading symbols from /home/student/anw0044/CPE455/Quiz-Bravo/protected_bapp...done. +(gdb) break main +Breakpoint 1 at 0x400716: file bapp.c, line 13. +(gdb) run +Starting program: /home/student/anw0044/CPE455/Quiz-Bravo/./protected_bapp + +Breakpoint 1, main () at bapp.c:13 +13 { +Missing separate debuginfos, use: debuginfo-install glibc-2.17-325.el7_9.x86_64 +(gdb) info locals +correctPassword = "\000\000\000\000\000\000\000\000\377\265\360\000\000\000\000\000\001\000\000" +suppliedPassword = "\320\340\377\377\377\177\000\000\000\000\000\000\000\000\000\000\340\a@" +(gdb) rstep +17 printf("\nEnter the password now: "); +(gdb) instepinfo locals +correctPassword = "\000\000\000\000\000\000\000\000\377\265\360\000\000\000\000\000\001\000\000" +suppliedPassword = "\320\340\377\377\377\177\000\000\000\000\000\000\000\000\000\000\340\a@" +(gdb) info locals step + +18 strncpy(correctPassword, "aaaaabbbbbccccc", BUFFER_SIZE); +(gdb) stepinfo locals +correctPassword = "\000\000\000\000\000\000\000\000\377\265\360\000\000\000\000\000\001\000\000" +suppliedPassword = "\320\340\377\377\377\177\000\000\000\000\000\000\000\000\000\000\340\a@" +(gdb) info locals step +19 gets(suppliedPassword); +(gdb) stepinfo locals +correctPassword = "aaaaabbbbbccccc\000\000\000\000" +suppliedPassword = "\320\340\377\377\377\177\000\000\000\000\000\000\000\000\000\000\340\a@" +(gdb) info locals step +Enter the password now: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +20 printf("\n"); +(gdb) stepinfo locals +correctPassword = "aaaaabbbbbccccc\000\000\000\000" +suppliedPassword = 'a' +(gdb) info locals stepinfo locals stepinfo locals continue +Continuing. + +Login failure + +suppliedPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +correctPassword: aaaaabbbbbccccc +*** stack smashing detected ***: /home/student/anw0044/CPE455/Quiz-Bravo/./protected_bapp terminated + +Program received signal SIGSEGV, Segmentation fault. +0x00007ffff78060f8 in ?? () from /lib64/libgcc_s.so.1 +Missing separate debuginfos, use: debuginfo-install libgcc-4.8.5-39.el7.x86_64 libgcc-4.8.5-44.el7.x86_64 +(gdb) quit +A debugging session is active. + + Inferior 1 [process 6749] will be killed. + +Quit anyway? (y or n) y +bash-4.2$ exit +exit + +Script done on Thu 24 Feb 2022 10:19:55 AM CST diff --git a/CPE455/Quiz-Bravo/protected_bapp b/CPE455/Quiz-Bravo/protected_bapp new file mode 100755 index 0000000..7856a34 Binary files /dev/null and b/CPE455/Quiz-Bravo/protected_bapp differ diff --git a/CPE455/Quiz-Bravo/vulnerable.txt b/CPE455/Quiz-Bravo/vulnerable.txt new file mode 100644 index 0000000..223d557 --- /dev/null +++ b/CPE455/Quiz-Bravo/vulnerable.txt @@ -0,0 +1,94 @@ +Script started on Thu 24 Feb 2022 10:08:08 AM CST +[?1034hbash-4.2$ ./vulnerable_bapp ` + +Enter the password now: aaaa + +Login failure + +suppliedPassword: aaaa +correctPassword: aaaaabbbbbccccc +bash-4.2$ ./vulnerable_bapp + +Enter the password now: aaaaabbbbbccccc + +Login successful + +suppliedPassword: aaaaabbbbbccccc +correctPassword: aaaaabbbbbccccc +bash-4.2$ perl -e 'print "a"x90' | ./vulnerable_bapp + +Enter the password now: +Login successful + +suppliedPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +correctPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +Segmentation fault +bash-4.2$ perl -e 'print "a"x90' | ./protected_bapp + +Enter the password now: +Login failure + +suppliedPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +correctPassword: aaaaabbbbbccccc +*** stack smashing detected ***: ./protected_bapp terminated +Segmentation fault +bash-4.2$ gdb ./vulnerable_bapp +[?1034hGNU gdb (GDB) Red Hat Enterprise Linux 7.6.1-120.el7 +Copyright (C) 2013 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +For bug reporting instructions, please see: +... +Reading symbols from /home/student/anw0044/CPE455/Quiz-Bravo/vulnerable_bapp...done. +(gdb) (gdb) (gdb) break main +Breakpoint 1 at 0x4006a5: file bapp.c, line 17. +(gdb) run +Starting program: /home/student/anw0044/CPE455/Quiz-Bravo/./vulnerable_bapp + +Breakpoint 1, main () at bapp.c:17 +17 printf("\nEnter the password now: "); +Missing separate debuginfos, use: debuginfo-install glibc-2.17-325.el7_9.x86_64 +(gdb) info locals +correctPassword = "P\a@\000\000\000\000\000\260\005@\000\000\000\000\000\260\341\377\377" +suppliedPassword = "\001\000\000\000\000\000\000\000\235\a@\000\000\000\000\000\320\340\377\377" +(gdb) step + +18 strncpy(correctPassword, "aaaaabbbbbccccc", BUFFER_SIZE); +(gdb) stepinfo locals +correctPassword = "P\a@\000\000\000\000\000\260\005@\000\000\000\000\000\260\341\377\377" +suppliedPassword = "\001\000\000\000\000\000\000\000\235\a@\000\000\000\000\000\320\340\377\377" +(gdb) info locals step +19 gets(suppliedPassword); +(gdb) stepinfo locals +correctPassword = "aaaaabbbbbccccc\000\000\000\000" +suppliedPassword = "\001\000\000\000\000\000\000\000\235\a@\000\000\000\000\000\320\340\377\377" +(gdb) info locals stepinfo locals stepinfo locals runbreak main runinfo locals stepinfo locals stepinfo locals step +Enter the password now: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +20 printf("\n"); +(gdb) stepinfo locals +correctPassword = 'a' +suppliedPassword = 'a' +(gdb) continue +Continuing. + +Login successful + +suppliedPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +correctPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa + +Program received signal SIGSEGV, Segmentation fault. +0x0000000000400744 in main () at bapp.c:35 +35 } +(gdb) quiyt +A debugging session is active. + + Inferior 1 [process 5306] will be killed. + +Quit anyway? (y or n) y +bash-4.2$ exit +exit + +Script done on Thu 24 Feb 2022 10:16:11 AM CST diff --git a/CPE455/Quiz-Bravo/vulnerable_bapp b/CPE455/Quiz-Bravo/vulnerable_bapp new file mode 100755 index 0000000..030d770 Binary files /dev/null and b/CPE455/Quiz-Bravo/vulnerable_bapp differ diff --git a/CPE455/Quiz-Charlie/README.txt b/CPE455/Quiz-Charlie/README.txt new file mode 100644 index 0000000..e33ea22 --- /dev/null +++ b/CPE455/Quiz-Charlie/README.txt @@ -0,0 +1,15 @@ + +capp.c + +sample code uses scanf( ) + + +Correct password is the following fifteen characters: aaaaabbbbbccccc + + +perl -e 'print "a"x90' | ./vulnerable_capp + +perl -e 'print "a"x90' | ./protected_capp + + + diff --git a/CPE455/Quiz-Charlie/after.txt b/CPE455/Quiz-Charlie/after.txt new file mode 100644 index 0000000..f539acb --- /dev/null +++ b/CPE455/Quiz-Charlie/after.txt @@ -0,0 +1,94 @@ +Script started on Thu 24 Feb 2022 10:37:55 AM CST +[?1034hbash-4.2$ ./vulnerable_capp + +Enter the password now: aaaa + +Login failure + +suppliedPassword: aaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 4 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ ./vulnerable_capp + +Enter the password now: aaaaabbbbbccccc + +Login successful + +suppliedPassword: aaaaabbbbbccccc +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 15 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ perl -e 'print "a"x90' | ./vulnerable_capp + +Enter the password now: +Login failure + +suppliedPassword: aaaaaaaaaaaaaaaaaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 19 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ ./protected_capp + +Enter the password now: aaaa + +Login failure + +suppliedPassword: aaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 4 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ ./protected_capp + +Enter the password now: aaaabbbbcccc + +Login failure + +suppliedPassword: aaaabbbbcccc +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 12 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ ./protected_capp + +Enter the password now: aaaaabbbbbccccc + +Login successful + +suppliedPassword: aaaaabbbbbccccc +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 15 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ perl -e 'print "a"x90' | ./protected_capp + +Enter the password now: +Login failure + +suppliedPassword: aaaaaaaaaaaaaaaaaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 19 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ exit +exit + +Script done on Thu 24 Feb 2022 10:41:07 AM CST diff --git a/CPE455/Quiz-Charlie/before.txt b/CPE455/Quiz-Charlie/before.txt new file mode 100644 index 0000000..e774b6e --- /dev/null +++ b/CPE455/Quiz-Charlie/before.txt @@ -0,0 +1,84 @@ +Script started on Thu 24 Feb 2022 10:34:10 AM CST +[?1034hbash-4.2$ ./vulnerable_capp + +Enter the password now: aaaa + +Login failure + +suppliedPassword: aaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 4 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ ./vulnerable_capp + +Enter the password now: aaaaabbbbbccccc + +Login successful + +suppliedPassword: aaaaabbbbbccccc +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 15 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ perl -e 'print "a"x90' | ./vulnerable_capp + +Enter the password now: +Login successful + +suppliedPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 90 +correctPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +sizeof(correctPassword) = 20 +strlen(correctPassword) = 58 + +Segmentation fault +bash-4.2$ ./protected_capp + +Enter the password now: aaaa + +Login failure + +suppliedPassword: aaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 4 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ ./protected_capp perl -e 'print "a"x90' | ./vulnerable_capp ./protected_capp + +Enter the password now: aaaaabbbbbccccc + +Login successful + +suppliedPassword: aaaaabbbbbccccc +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 15 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +bash-4.2$ perl -e 'print "a"x90' | ./protected_capp + +Enter the password now: +Login failure + +suppliedPassword: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 90 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 + +*** stack smashing detected ***: ./protected_capp terminated +Segmentation fault +bash-4.2$ exit +exit + +Script done on Thu 24 Feb 2022 10:36:25 AM CST diff --git a/CPE455/Quiz-Charlie/capp.c b/CPE455/Quiz-Charlie/capp.c new file mode 100644 index 0000000..565ed7f --- /dev/null +++ b/CPE455/Quiz-Charlie/capp.c @@ -0,0 +1,51 @@ +/* + * capp.c + * + */ + +#include +#include +#include + +#define BUFFER_SIZE 20 + +int main() +{ + char correctPassword[BUFFER_SIZE]; + char suppliedPassword[BUFFER_SIZE]; + + printf("\nEnter the password now: "); + strncpy(correctPassword, "aaaaabbbbbccccc", BUFFER_SIZE); + scanf("%19s", suppliedPassword); + printf("\n"); + + if (strncmp(suppliedPassword, correctPassword, BUFFER_SIZE) == 0) + { + printf("Login successful\n\n"); + } + else + { + printf("Login failure\n\n"); + } + + printf("suppliedPassword: %s\n", suppliedPassword); + printf("sizeof(suppliedPassword) = %d\n", sizeof(suppliedPassword)); + printf("strlen(suppliedPassword) = %d\n", strlen(suppliedPassword)); + + printf("correctPassword: %s\n", correctPassword); + printf("sizeof(correctPassword) = %d\n", sizeof(correctPassword)); + printf("strlen(correctPassword) = %d\n", strlen(correctPassword)); + + char myArray[BUFFER_SIZE]; + scanf("%s", myArray); + printf("myArray: %s\n", myArray); + printf("sizeof(myArray) = %d\n", sizeof(myArray)); + printf("strlen(myArray) = %d\n", strlen(myArray)); + + printf("\n"); + + return 0; +} + + + diff --git a/CPE455/Quiz-Charlie/makefile b/CPE455/Quiz-Charlie/makefile new file mode 100644 index 0000000..6c6a511 --- /dev/null +++ b/CPE455/Quiz-Charlie/makefile @@ -0,0 +1,18 @@ +# +# capp.c makefile +# + +CC = gcc +CFLAGS = -g + +vulnerable_capp: capp.c + $(CC) $(CFLAGS) -fno-stack-protector -z execstack capp.c -o vulnerable_capp + +protected_capp: capp.c + $(CC) $(CFLAGS) -fstack-protector -z noexecstack capp.c -o protected_capp + +clean: + rm vulnerable_capp protected_capp + + + diff --git a/CPE455/Quiz-Charlie/myarray b/CPE455/Quiz-Charlie/myarray new file mode 100755 index 0000000..8982d16 Binary files /dev/null and b/CPE455/Quiz-Charlie/myarray differ diff --git a/CPE455/Quiz-Charlie/protected_capp b/CPE455/Quiz-Charlie/protected_capp new file mode 100755 index 0000000..20bbd09 Binary files /dev/null and b/CPE455/Quiz-Charlie/protected_capp differ diff --git a/CPE455/Quiz-Charlie/result.txt b/CPE455/Quiz-Charlie/result.txt new file mode 100644 index 0000000..621e1b4 --- /dev/null +++ b/CPE455/Quiz-Charlie/result.txt @@ -0,0 +1,44 @@ +Script started on Thu 24 Feb 2022 10:42:50 AM CST +[?1034hbash-4.2$ exitperl -e 'print "a"x90' | ./myarray ./myarray gcc -g -fno-stack-protector -z execstack capp.c -o myarray script after.txt gcc -g -fno-stack-protector -z execstack capp.c -o myarray +gcc: error: capp.c: No such file or directory +gcc: fatal error: no input files +compilation terminated. +bash-4.2$ cd CPEQuiz-C +bash: cd: Quiz-C: No such file or directory +bash-4.2$ cd Quiz-Charlie/ +bash-4.2$ cd Quiz-Charlie/gcc -g -fno-stack-protector -z execstack capp.c -o myarray +bash-4.2$ gcc -g -fno-stack-protector -z execstack capp.c -o myarray cd Quiz-Charlie/gcc -g -fno-stack-protector -z execstack capp.c -o myarray exitperl -e 'print "a"x90' | ./myarray ./myarray  + +Enter the password now: aaaaabbbbbcccccdddddeeeee + +Login failure + +suppliedPassword: aaaaabbbbbcccccdddd +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 19 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 +myArray: deeeee +sizeof(myArray) = 20 +strlen(myArray) = 6 + +bash-4.2$ ./myarray gcc -g -fno-stack-protector -z execstack capp.c -o myarray ./myarray gcc -g -fno-stack-protector -z execstack capp.c -o myarray cd Quiz-Charlie/gcc -g -fno-stack-protector -z execstack capp.c -o myarray exitperl -e 'print "a"x90' | ./myarray + +Enter the password now: +Login failure + +suppliedPassword: aaaaaaaaaaaaaaaaaaa +sizeof(suppliedPassword) = 20 +strlen(suppliedPassword) = 19 +correctPassword: aaaaabbbbbccccc +sizeof(correctPassword) = 20 +strlen(correctPassword) = 15 +myArray: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +sizeof(myArray) = 20 +strlen(myArray) = 71 + +bash-4.2$ exit +exit + +Script done on Thu 24 Feb 2022 10:43:39 AM CST diff --git a/CPE455/Quiz-Charlie/vulnerable_capp b/CPE455/Quiz-Charlie/vulnerable_capp new file mode 100755 index 0000000..c5233a8 Binary files /dev/null and b/CPE455/Quiz-Charlie/vulnerable_capp differ diff --git a/CPE455/alpha/.vscode/configurationCache.log b/CPE455/alpha/.vscode/configurationCache.log new file mode 100644 index 0000000..106fa04 --- /dev/null +++ b/CPE455/alpha/.vscode/configurationCache.log @@ -0,0 +1 @@ +{"buildTargets":["clean","fixme","fortified","make","vulnerable"],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[]},"fileIndex":[]}} \ No newline at end of file diff --git a/CPE455/alpha/.vscode/dryrun.log b/CPE455/alpha/.vscode/dryrun.log new file mode 100644 index 0000000..943d08b --- /dev/null +++ b/CPE455/alpha/.vscode/dryrun.log @@ -0,0 +1,5 @@ +make --dry-run --keep-going --print-directory +make: Entering directory `/home/student/anw0044/CPE455/alpha' +make: `fixme' is up to date. +make: Leaving directory `/home/student/anw0044/CPE455/alpha' + diff --git a/CPE455/alpha/.vscode/settings.json b/CPE455/alpha/.vscode/settings.json new file mode 100644 index 0000000..65e1ec0 --- /dev/null +++ b/CPE455/alpha/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "makefile.extensionOutputFolder": "./.vscode" +} \ No newline at end of file diff --git a/CPE455/alpha/.vscode/targets.log b/CPE455/alpha/.vscode/targets.log new file mode 100644 index 0000000..c6610b0 --- /dev/null +++ b/CPE455/alpha/.vscode/targets.log @@ -0,0 +1,327 @@ +make all --print-data-base --no-builtin-variables --no-builtin-rules --question +# GNU Make 3.82 +# Built for x86_64-redhat-linux-gnu +# Copyright (C) 2010 Free Software Foundation, Inc. +# License GPLv3+: GNU GPL version 3 or later +# This is free software: you are free to change and redistribute it. +# There is NO WARRANTY, to the extent permitted by law. + +# Make data base, printed on Tue Feb 15 13:54:28 2022 + +# Variables + +# automatic + +#include + +int main(int argc, char* argv[ ]) +{ + char buffer[5]; + + strcpy(buffer, argv[1]); + puts(buffer); + + return 0; +} \ No newline at end of file diff --git a/CPE455/alpha/fortified b/CPE455/alpha/fortified new file mode 100755 index 0000000..094f14d Binary files /dev/null and b/CPE455/alpha/fortified differ diff --git a/CPE455/alpha/vulnerable b/CPE455/alpha/vulnerable new file mode 100755 index 0000000..f7d642c Binary files /dev/null and b/CPE455/alpha/vulnerable differ diff --git a/CPE455/day8/Makefile b/CPE455/day8/Makefile new file mode 100644 index 0000000..ade65d1 --- /dev/null +++ b/CPE455/day8/Makefile @@ -0,0 +1,7 @@ +CC = gcc +CFLAGS = -Wall + +hello: helloworld.o hellofunction.o + $(CC) $(CFLAGS) helloworld.o hellofunction.o -o hello + +hellorun.o: hello \ No newline at end of file diff --git a/CPE455/day8/hellofunction.c b/CPE455/day8/hellofunction.c new file mode 100644 index 0000000..747313a --- /dev/null +++ b/CPE455/day8/hellofunction.c @@ -0,0 +1 @@ +void greetMe(void); \ No newline at end of file diff --git a/CPE455/day8/hellorun.c b/CPE455/day8/hellorun.c new file mode 100644 index 0000000..4e54061 --- /dev/null +++ b/CPE455/day8/hellorun.c @@ -0,0 +1,3 @@ +int main(){ + greetMe(); +} \ No newline at end of file diff --git a/CPE455/day8/helloworld.c b/CPE455/day8/helloworld.c new file mode 100644 index 0000000..a2064d1 --- /dev/null +++ b/CPE455/day8/helloworld.c @@ -0,0 +1,3 @@ +void greetMe(){ + printf("Hello, World!/n"); +} \ No newline at end of file diff --git a/CPE455/gameproject/.svn/entries b/CPE455/gameproject/.svn/entries new file mode 100644 index 0000000..48082f7 --- /dev/null +++ b/CPE455/gameproject/.svn/entries @@ -0,0 +1 @@ +12 diff --git a/CPE455/gameproject/.svn/format b/CPE455/gameproject/.svn/format new file mode 100644 index 0000000..48082f7 --- /dev/null +++ b/CPE455/gameproject/.svn/format @@ -0,0 +1 @@ +12 diff --git a/CPE455/gameproject/.svn/pristine/00/00cc334162c6faba822a59d9b13770f29d4f25d7.svn-base b/CPE455/gameproject/.svn/pristine/00/00cc334162c6faba822a59d9b13770f29d4f25d7.svn-base new file mode 100644 index 0000000..030f32e --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/00/00cc334162c6faba822a59d9b13770f29d4f25d7.svn-base @@ -0,0 +1,16 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +Z 8 10 +P 2 10 +T 8 15 diff --git a/CPE455/gameproject/.svn/pristine/09/09cbd1250a2dabcfe4f3599d7cf586e03cf1669c.svn-base b/CPE455/gameproject/.svn/pristine/09/09cbd1250a2dabcfe4f3599d7cf586e03cf1669c.svn-base new file mode 100644 index 0000000..0acca62 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/09/09cbd1250a2dabcfe4f3599d7cf586e03cf1669c.svn-base @@ -0,0 +1,52 @@ +#include +#include +#include +#include + +int main(int argc, char *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + switch(shold[0]) + { + case 'M': + printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + break; + default: + printf ("Basic error\n"); + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + printf ("So this line won't print without an argument.\n"); + + // possible dynamic allocation of 2D array + char* ptr = malloc((row * col) * sizeof(char)); + + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/0c/0ca93b555585c0929f22579182092b0ccfba00c4.svn-base b/CPE455/gameproject/.svn/pristine/0c/0ca93b555585c0929f22579182092b0ccfba00c4.svn-base new file mode 100644 index 0000000..286572c --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/0c/0ca93b555585c0929f22579182092b0ccfba00c4.svn-base @@ -0,0 +1,290 @@ +#include +#include +#include +#include +#include +#include + +WINDOW *initscr(void); +int start_color(void); +int cbreak(void); +int noecho(void); +int nodelay(WINDOW *win, bool bf); +int keypad(WINDOW *win, bool bf); +int curs_set(int visibility); +/*void getmaxyx(WINDOW *win, int y, int x); */ +int init_pair(short pair, short f, short b); +/*int attron(int attrs); +int COLOR_PAIR(int n); +int wmove(WINDOW *win, int y, int x); +nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((int)(prow + deltaRow) > row) || ((int)(pcol + deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[(int)(prow + deltaRow)][(int)(pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/15/1583e17e6d821a31e5b54078b098b5b6ffce6450.svn-base b/CPE455/gameproject/.svn/pristine/15/1583e17e6d821a31e5b54078b098b5b6ffce6450.svn-base new file mode 100644 index 0000000..9f65343 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/15/1583e17e6d821a31e5b54078b098b5b6ffce6450.svn-base @@ -0,0 +1,283 @@ +#include +#include +#include +#include +#include +#include + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- why */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/15/15f53f3e2cad80b9ecf4f5ffc3d6a68e1e0e5cfc.svn-base b/CPE455/gameproject/.svn/pristine/15/15f53f3e2cad80b9ecf4f5ffc3d6a68e1e0e5cfc.svn-base new file mode 100644 index 0000000..64a7ced --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/15/15f53f3e2cad80b9ecf4f5ffc3d6a68e1e0e5cfc.svn-base @@ -0,0 +1,429 @@ +#include +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); +extern int noecho(void); + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to open the file so must use bad one bc we cannot create one ourselves as we are not wizards */ + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to get first char from file and we must use bad one as we cannot make one ourselves */ + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + /* parse maze file, + adding chars to array */ + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &row, &col); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to dynamially allocate memory cannot create own as we lack experience */ + maze = (char**)malloc(row * 8); /* allocate memory for rows of array, 8 reperesents size of char* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to dynamially allocate memory cannot create own as we lack experience */ + maze[i] = malloc(col * 8); /* allocate memory for collumns of array, 8 reperesents size of char* */ + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + /* parse maze */ + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow = 0; + deltaCol = 0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + /* check current player position against maze bounds, + if over the bounds, don't move */ + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + /* check future player position to see if wall; + if it is, stay in the same spot + else move to new postion */ + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + /* check curremt position for treasure, + make treasure position a space, + and increment score */ + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + /* check curremt position for zombie, + end game */ + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze); + } + /*printw("\n");*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + endwin(); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to print score for project, so even though not great have to use bad one */ + printf("Score = %u\n", score); + return 0; + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Y was statically allocated no need to free it */ + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Maze has been freed already valgrind shows no leaks error must have ocurred in analysis */ +} + diff --git a/CPE455/gameproject/.svn/pristine/16/16762facfc9a4f3c92e18dab29656e94ced8e54b.svn-base b/CPE455/gameproject/.svn/pristine/16/16762facfc9a4f3c92e18dab29656e94ced8e54b.svn-base new file mode 100644 index 0000000..ec14a84 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/16/16762facfc9a4f3c92e18dab29656e94ced8e54b.svn-base @@ -0,0 +1,8 @@ +CC = gcc +CFLAGS = -g -Wall --pedantic -ansi --coverage + +game: game.c + $(CC) $(CFLAGS) game.c -o game -l ncurses + +clean: + rm game *.gcda *.gcno *.gcov \ No newline at end of file diff --git a/CPE455/gameproject/.svn/pristine/20/207e4e9215a0545cd5392b1846201b3c6f2581f3.svn-base b/CPE455/gameproject/.svn/pristine/20/207e4e9215a0545cd5392b1846201b3c6f2581f3.svn-base new file mode 100644 index 0000000..4523c42 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/20/207e4e9215a0545cd5392b1846201b3c6f2581f3.svn-base @@ -0,0 +1,126 @@ +#include +#include +#include +#include + +void readMaze(char *arr); +void readPlayer(char *arr); +void readZombie(char *arr); +void readTreasure(char *arr); + +int main(int argc, char *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* maze = malloc((row * col) * sizeof(char)); + readMaze(maze); + break; + case 'P': + //case for player + printf ("Player\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* player = malloc((row * col) * sizeof(char)); + readPlayer(player); + break; + + case 'Z': + //case for zombie + printf ("Zombie\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* zombie = malloc((row * col) * sizeof(char)); + readZombie(zombie); + break; + + case 'T': + //case for treasure + printf ("Treasure\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* treasure = malloc((row * col) * sizeof(char)); + readTreasure(treasure); + break; + default: + //printf ("Basic error\n"); + break; + }; + + for(int i=0;i +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + wmove(W, c1,c2); + waddch(W,'#'); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + break; + case 'Z': + wmove(W, c1,c2); + waddch(W,'Z'); + break; + case 'T': + wmove(W, c1,c2); + waddch(W,'T'); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + do{ + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/2d/2d877cb6b6c940c0577898075d07add36d7263b1.svn-base b/CPE455/gameproject/.svn/pristine/2d/2d877cb6b6c940c0577898075d07add36d7263b1.svn-base new file mode 100644 index 0000000..8b8c36b --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/2d/2d877cb6b6c940c0577898075d07add36d7263b1.svn-base @@ -0,0 +1,270 @@ +#include +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if((prow + deltaRow > row) || (pcol + deltaCol > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[prow + deltaRow][pcol + deltaCol] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/30/30471c6243b153a1f5bfd38a922e253a783f48e3.svn-base b/CPE455/gameproject/.svn/pristine/30/30471c6243b153a1f5bfd38a922e253a783f48e3.svn-base new file mode 100644 index 0000000..9cae547 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/30/30471c6243b153a1f5bfd38a922e253a783f48e3.svn-base @@ -0,0 +1,13 @@ +#include + +int main(int argc, char const *argv[]) +{ + printf("Hello, World!\n"); + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + printf ("So this line won't print without an argument.\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/31/31f3426e0bea772955763770a9f3c342efd94edb.svn-base b/CPE455/gameproject/.svn/pristine/31/31f3426e0bea772955763770a9f3c342efd94edb.svn-base new file mode 100644 index 0000000..6a02799 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/31/31f3426e0bea772955763770a9f3c342efd94edb.svn-base @@ -0,0 +1,279 @@ +#include +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if((prow + deltaRow > row) || (pcol + deltaCol > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[prow + deltaRow][pcol + deltaCol] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/33/335631b7e8b402171b32d068a5c94ea23720f155.svn-base b/CPE455/gameproject/.svn/pristine/33/335631b7e8b402171b32d068a5c94ea23720f155.svn-base new file mode 100644 index 0000000..004bd88 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/33/335631b7e8b402171b32d068a5c94ea23720f155.svn-base @@ -0,0 +1,14 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +P 2 10 diff --git a/CPE455/gameproject/.svn/pristine/34/34234b18c80689310a25c37e9946dab500872e46.svn-base b/CPE455/gameproject/.svn/pristine/34/34234b18c80689310a25c37e9946dab500872e46.svn-base new file mode 100644 index 0000000..ed56274 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/34/34234b18c80689310a25c37e9946dab500872e46.svn-base @@ -0,0 +1,334 @@ +#include +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/35/3517ff93f2b1c4f166831d58b9a98824b098eeca.svn-base b/CPE455/gameproject/.svn/pristine/35/3517ff93f2b1c4f166831d58b9a98824b098eeca.svn-base new file mode 100644 index 0000000..601c4ad --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/35/3517ff93f2b1c4f166831d58b9a98824b098eeca.svn-base @@ -0,0 +1,278 @@ +#include +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if((prow + deltaRow > row) || (pcol + deltaCol > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[prow + deltaRow][pcol + deltaCol] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/3d/3d70931b57d57c6ce5a74eb2a8f5d6e57361de7a.svn-base b/CPE455/gameproject/.svn/pristine/3d/3d70931b57d57c6ce5a74eb2a8f5d6e57361de7a.svn-base new file mode 100644 index 0000000..d912bd4 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/3d/3d70931b57d57c6ce5a74eb2a8f5d6e57361de7a.svn-base @@ -0,0 +1,7 @@ +#include + +int main(int argc, char const *argv[]) +{ + printf("Hello, World!\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/3e/3e1d28a283b9370842154f4cd7edbdd60c38fc8d.svn-base b/CPE455/gameproject/.svn/pristine/3e/3e1d28a283b9370842154f4cd7edbdd60c38fc8d.svn-base new file mode 100644 index 0000000..8348d9a --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/3e/3e1d28a283b9370842154f4cd7edbdd60c38fc8d.svn-base @@ -0,0 +1,401 @@ +#include +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); +extern int noecho(void); + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/3f/3fcd394dd754a78a701143791a8390ad95fe15ed.svn-base b/CPE455/gameproject/.svn/pristine/3f/3fcd394dd754a78a701143791a8390ad95fe15ed.svn-base new file mode 100644 index 0000000..17cc560 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/3f/3fcd394dd754a78a701143791a8390ad95fe15ed.svn-base @@ -0,0 +1,129 @@ +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + + /* check to see if argument */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + /* print out maze */ + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/3f/3fd1a9faf5ab97b1dd8d32921fabd6060396a8d3.svn-base b/CPE455/gameproject/.svn/pristine/3f/3fd1a9faf5ab97b1dd8d32921fabd6060396a8d3.svn-base new file mode 100644 index 0000000..9cad5e2 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/3f/3fd1a9faf5ab97b1dd8d32921fabd6060396a8d3.svn-base @@ -0,0 +1,256 @@ +#include +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + wmove(W, c1,c2); + waddch(W,'Z'); + break; + case 'T': + wmove(W, c1,c2); + waddch(W,'T'); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + prow = prow + deltaRow; + pcol = pcol + deltaCol; + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/45/459f5f88bada382e184f36683a9b382e43642533.svn-base b/CPE455/gameproject/.svn/pristine/45/459f5f88bada382e184f36683a9b382e43642533.svn-base new file mode 100644 index 0000000..6669601 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/45/459f5f88bada382e184f36683a9b382e43642533.svn-base @@ -0,0 +1,21 @@ +M 14 21 +##################### +# # # # +# # # # +# # # # +# ####### ####### +# # +# # +# ########### # +# # # +# # # +# ##### # +# # +# # +##################### +T 8 15 +Z 9 10 +Z 6 11 +T 2 8 +P 2 10 +T 2 12 diff --git a/CPE455/gameproject/.svn/pristine/46/46c5de07e2f42af6b4968ab663fc9ca61dad474c.svn-base b/CPE455/gameproject/.svn/pristine/46/46c5de07e2f42af6b4968ab663fc9ca61dad474c.svn-base new file mode 100644 index 0000000..a519383 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/46/46c5de07e2f42af6b4968ab663fc9ca61dad474c.svn-base @@ -0,0 +1,59 @@ +#include +#include +#include +#include + +void readMaze(char *arr); + +int main(int argc, char *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + switch(shold[0]) + { + case 'M': + printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* maze = malloc((row * col) * sizeof(char)); + readMaze(maze); + break; + default: + //printf ("Basic error\n"); + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + //printf ("So this line won't print without an argument.\n"); + + return 0; +} + +void readMaze(char *arr) +{ + +} \ No newline at end of file diff --git a/CPE455/gameproject/.svn/pristine/47/472d3a398f8fb5c1cb06bb5c098c77bcb7b0b248.svn-base b/CPE455/gameproject/.svn/pristine/47/472d3a398f8fb5c1cb06bb5c098c77bcb7b0b248.svn-base new file mode 100644 index 0000000..cefd4d1 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/47/472d3a398f8fb5c1cb06bb5c098c77bcb7b0b248.svn-base @@ -0,0 +1,123 @@ +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; // global array for maze + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // dynamic allocation of array for maze + unsigned int i = 0, j = 0; + maze = malloc(row * sizeof(unsigned int *)); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + unsigned int i = 0; + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/47/47bc003d7e96b71af63519d92df998ea88035739.svn-base b/CPE455/gameproject/.svn/pristine/47/47bc003d7e96b71af63519d92df998ea88035739.svn-base new file mode 100644 index 0000000..736b1c6 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/47/47bc003d7e96b71af63519d92df998ea88035739.svn-base @@ -0,0 +1,290 @@ +#include +#include +#include +#include +#include +#include + +WINDOW *initscr(void); +int start_color(void); +int cbreak(void); +int noecho(void); +int nodelay(WINDOW *win, bool bf); +int keypad(WINDOW *win, bool bf); +int curs_set(int visibility); +/*void getmaxyx(WINDOW *win, int y, int x); */ +int init_pair(short pair, short f, short b); +/*int attron(int attrs); +int COLOR_PAIR(int n); +int wmove(WINDOW *win, int y, int x); +nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if((((int)prow + deltaRow) > row) || (((int)pcol + deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/49/4992c3a0fd9cb1a9d96b3ba88c49fec1ab835f94.svn-base b/CPE455/gameproject/.svn/pristine/49/4992c3a0fd9cb1a9d96b3ba88c49fec1ab835f94.svn-base new file mode 100644 index 0000000..ee0b462 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/49/4992c3a0fd9cb1a9d96b3ba88c49fec1ab835f94.svn-base @@ -0,0 +1,79 @@ +#include +#include +#include +#include + + +// read maze file in to the array +void readMaze(char *arr, int r, int c); + +int main(int argc, char *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + switch(shold[0]) + { + case 'M': + printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + int i = 0, j = 0; + char **maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + maze[i] = malloc(col * sizeof(char)); + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + printf("%c", maze[i][j]); + } + + } + printf("%c", maze[0 * col + 0]); + for(i = 0; i < row; i++) + free(maze[i]); + free(maze); + //int (*maze)[col] = malloc(sizeof(int[row][col])); + //readMaze(maze, row, col); + break; + default: + //printf ("Basic error\n"); + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + //printf ("So this line won't print without an argument.\n"); + + return 0; +} + +void readMaze(char *arr, int row, int col) +{ + + +} \ No newline at end of file diff --git a/CPE455/gameproject/.svn/pristine/4b/4bafeeb5c04c700702a6936e42cfdb29921748e5.svn-base b/CPE455/gameproject/.svn/pristine/4b/4bafeeb5c04c700702a6936e42cfdb29921748e5.svn-base new file mode 100644 index 0000000..6eb25a2 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/4b/4bafeeb5c04c700702a6936e42cfdb29921748e5.svn-base @@ -0,0 +1,146 @@ +#include +#include +#include +#include + +void readPlayer(char *arr); +void readZombie(char *arr); +void readTreasure(char *arr); + +// read maze file in to the array +void readMaze(char *arr, int r, int c); + +int main(int argc, char *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + int i = 0, j = 0; + char **maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + maze[i] = malloc(col * sizeof(char)); + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + printf("%c", maze[i][j]); + } + + } + printf("%c", maze[0 * col + 0]); + for(i = 0; i < row; i++) + free(maze[i]); + free(maze); + //int (*maze)[col] = malloc(sizeof(int[row][col])); + //readMaze(maze, row, col); + break; + case 'P': + //case for player + printf ("Player\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* player = malloc((row * col) * sizeof(char)); + readPlayer(player); + break; + + case 'Z': + //case for zombie + printf ("Zombie\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* zombie = malloc((row * col) * sizeof(char)); + readZombie(zombie); + break; + + case 'T': + //case for treasure + printf ("Treasure\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* treasure = malloc((row * col) * sizeof(char)); + readTreasure(treasure); + break; + default: + //printf ("Basic error\n"); + break; + }; + + for(int i=0;i +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_RED, COLOR_BLACK); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_BLUE); /* White text on Blue background */ + init_pair(4, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + wmove(W, c1,c2); + waddch(W,'#'); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + wmove(W, c1,c2); + waddch(W,'Z'); + break; + case 'T': + wmove(W, c1,c2); + waddch(W,'T'); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + prow = rowLimit/4; + pcol = colLimit/4; + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + prow = prow + deltaRow; + pcol = pcol + deltaCol; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/53/5317919993e8feec9b2542f38a63c928fbcf225a.svn-base b/CPE455/gameproject/.svn/pristine/53/5317919993e8feec9b2542f38a63c928fbcf225a.svn-base new file mode 100644 index 0000000..07f95f2 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/53/5317919993e8feec9b2542f38a63c928fbcf225a.svn-base @@ -0,0 +1,110 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row = 0; /* Holds number of rows for input from file */ + int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l = 0; + int k = 0; + int c1 = 0; + int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%d %d", &row, &col); + // possible dynamic allocation of 2D array + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(char)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'Z'; + printf("%c" , maze[k][l]); + break; + + case 'T': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'T'; + break; + case '\n': + printf("\n"); + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + printf("%c", maze[c1][c2]); + } + } + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/57/57c7e440239b7657ac2ab53850eb3ab0316706eb.svn-base b/CPE455/gameproject/.svn/pristine/57/57c7e440239b7657ac2ab53850eb3ab0316706eb.svn-base new file mode 100644 index 0000000..8e55016 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/57/57c7e440239b7657ac2ab53850eb3ab0316706eb.svn-base @@ -0,0 +1,110 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row = 0; /* Holds number of rows for input from file */ + int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l = 0; + int k = 0; + int c1 = 0; + int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%d %d", &row, &col); + // + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = calloc(row, sizeof(unsigned int *)); + for(i = 0; i < row; i++) + { + maze[i] = calloc(col, sizeof(unsigned int *)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'Z'; + printf("%c" , maze[k][l]); + break; + + case 'T': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'T'; + break; + case '\n': + printf("\n"); + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + printf("%c", maze[c1][c2]); + } + } + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/65/6540ab507557f3e287dcf3b5142c6e92819cc5a4.svn-base b/CPE455/gameproject/.svn/pristine/65/6540ab507557f3e287dcf3b5142c6e92819cc5a4.svn-base new file mode 100644 index 0000000..ca00201 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/65/6540ab507557f3e287dcf3b5142c6e92819cc5a4.svn-base @@ -0,0 +1,290 @@ +#include +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/66/6617dc1be4a07229c96a1ebe2270a77b89942319.svn-base b/CPE455/gameproject/.svn/pristine/66/6617dc1be4a07229c96a1ebe2270a77b89942319.svn-base new file mode 100644 index 0000000..e72a594 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/66/6617dc1be4a07229c96a1ebe2270a77b89942319.svn-base @@ -0,0 +1,151 @@ +#include +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + WINDOW* W = 0; /* Curses Window handle */ + + /* check to see if argument */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + /* Initialize ncurses -- you will want to use the following settings */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, row, col); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_RED, COLOR_BLACK); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_BLUE); /* White text on Blue background */ + init_pair(4, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/68/682a7e79688712ba034b82efc737a7a1173e3340.svn-base b/CPE455/gameproject/.svn/pristine/68/682a7e79688712ba034b82efc737a7a1173e3340.svn-base new file mode 100644 index 0000000..d8fac5a --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/68/682a7e79688712ba034b82efc737a7a1173e3340.svn-base @@ -0,0 +1,128 @@ +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; // global array for maze + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + // read array values, dynamically allocate array + fscanf(mazeFile, "%3d %3d", &row, &col); + unsigned int i = 0, j = 0; + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + // check maze bounds + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + // check maze bounds + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + // check maze bounds + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + // print out maze + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + unsigned int i = 0; + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + maze[i] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/69/691d46afb5202442f026ed969ee14c78fee76bcc.svn-base b/CPE455/gameproject/.svn/pristine/69/691d46afb5202442f026ed969ee14c78fee76bcc.svn-base new file mode 100644 index 0000000..4a9f885 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/69/691d46afb5202442f026ed969ee14c78fee76bcc.svn-base @@ -0,0 +1,128 @@ +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; // global array for maze + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + // read array values, dynamically allocate array + fscanf(mazeFile, "%3d %3d", &row, &col); + unsigned int i = 0, j = 0; + maze = (char**)malloc(row * sizeof(unsigned int *)); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + // check maze bounds + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + // check maze bounds + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + // check maze bounds + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + // print out maze + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + unsigned int i = 0; + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + maze[i] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/69/695cc027ab6fa37aad1fb01361d0eb90c6897155.svn-base b/CPE455/gameproject/.svn/pristine/69/695cc027ab6fa37aad1fb01361d0eb90c6897155.svn-base new file mode 100644 index 0000000..069a821 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/69/695cc027ab6fa37aad1fb01361d0eb90c6897155.svn-base @@ -0,0 +1,110 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row = 0; /* Holds number of rows for input from file */ + int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l = 0; + int k = 0; + int c1 = 0; + int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%d %d", &row, &col); + // possible dynamic allocation of 2D array + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(char)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'Z'; + printf("%c" , maze[k][l]); + break; + + case 'T': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'T'; + break; + case '\n': + printf("\n"); + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + printf("%c", maze[c1][c2]); + } + } + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + //free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/69/698ac018da681d26eaa3ff49d98e868830488fd8.svn-base b/CPE455/gameproject/.svn/pristine/69/698ac018da681d26eaa3ff49d98e868830488fd8.svn-base new file mode 100644 index 0000000..24359f0 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/69/698ac018da681d26eaa3ff49d98e868830488fd8.svn-base @@ -0,0 +1,127 @@ +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + + /* check to see if argument */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + /* print out maze */ + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + /* free the memory */ + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + maze[i] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/6b/6b89f2d5656c9b94d4f6df766281812d5b04ea6f.svn-base b/CPE455/gameproject/.svn/pristine/6b/6b89f2d5656c9b94d4f6df766281812d5b04ea6f.svn-base new file mode 100644 index 0000000..9069b8a --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/6b/6b89f2d5656c9b94d4f6df766281812d5b04ea6f.svn-base @@ -0,0 +1,427 @@ +#include +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); +extern int noecho(void); + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to open the file so must use bad one bc we cannot create one ourselves as we are not wizards */ + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to get first char from file and we must use bad one as we cannot make one ourselves */ + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + /* parse maze file, + adding chars to array */ + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* allocate memory for rows of array */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); /* allocate memory for collumns of array */ + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + /* parse maze */ + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow = 0; + deltaCol = 0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + /* check current player position against maze bounds, + if over the bounds, don't move */ + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + /* check future player position to see if wall; + if it is, stay in the same spot + else move to new postion */ + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + /* check curremt position for treasure, + make treasure position a space, + and increment score */ + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + /* check curremt position for zombie, + end game */ + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze); + } + /*printw("\n");*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + endwin(); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to print score for project, so even though not great have to use bad one */ + printf("Score = %u\n", score); + return 0; + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Y was statically allocated no need to free it */ + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Maze has been freed already valgrind shows no leaks error must have ocurred in analysis */ +} + diff --git a/CPE455/gameproject/.svn/pristine/6c/6c4a430e973cfa8cd956de9620c66ca2ddbd71ed.svn-base b/CPE455/gameproject/.svn/pristine/6c/6c4a430e973cfa8cd956de9620c66ca2ddbd71ed.svn-base new file mode 100644 index 0000000..4b9dcfc --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/6c/6c4a430e973cfa8cd956de9620c66ca2ddbd71ed.svn-base @@ -0,0 +1,151 @@ +#include +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + /*FILE* mazeFile; Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + WINDOW* W = 0; /* Curses Window handle */ + + /* check to see if argument */ + if (argc != 2) + { + printw("An error has ocurred no input file was given.\n"); + return 1; + } + W = fopen(argv[1], "r"); + if (W == NULL) + { + printw("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, W); + while ( feof(W) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + wscanw(W, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + wscanw(W, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + wscanw(W, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + wscanw(W, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + wscanw(W, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + wscanw(W, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, W); + if (feof(W) != 0) + { + break; + } + } + + + fclose(W); + /* Initialize ncurses -- you will want to use the following settings */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, row, col); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_RED, COLOR_BLACK); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_BLUE); /* White text on Blue background */ + init_pair(4, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + printw ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printw("%c", maze[c1][c2]); + } + } + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + printw("\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/6e/6e0beb82967b07ba61b24e8b42ce88d5f3d38777.svn-base b/CPE455/gameproject/.svn/pristine/6e/6e0beb82967b07ba61b24e8b42ce88d5f3d38777.svn-base new file mode 100644 index 0000000..3da09bb --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/6e/6e0beb82967b07ba61b24e8b42ce88d5f3d38777.svn-base @@ -0,0 +1,285 @@ +#include +#include +#include +#include +#include +#include + + +/* */ +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- why */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/6e/6e347204aa32aa41870629708bed69c64ec2a200.svn-base b/CPE455/gameproject/.svn/pristine/6e/6e347204aa32aa41870629708bed69c64ec2a200.svn-base new file mode 100644 index 0000000..f0bf804 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/6e/6e347204aa32aa41870629708bed69c64ec2a200.svn-base @@ -0,0 +1,112 @@ +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; // global array for maze + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // dynamic allocation of array for maze + unsigned int i = 0, j = 0; + maze = malloc(row * sizeof(unsigned int *)); + for(i = 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + unsigned int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/72/7262eca3ddc7e8aaad907c0e0ad69fab93896817.svn-base b/CPE455/gameproject/.svn/pristine/72/7262eca3ddc7e8aaad907c0e0ad69fab93896817.svn-base new file mode 100644 index 0000000..fcaf120 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/72/7262eca3ddc7e8aaad907c0e0ad69fab93896817.svn-base @@ -0,0 +1,287 @@ +#include +#include +#include +#include +#include +#include + +WINDOW *initscr(void); +int start_color(void); +int cbreak(void); +int noecho(void); +int nodelay(WINDOW *win, bool bf); +int keypad(WINDOW *win, bool bf); +int curs_set(int visibility); +/*void getmaxyx(WINDOW *win, int y, int x); */ +int init_pair(short pair, short f, short b); +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if((prow + deltaRow > row) || (pcol + deltaCol > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[prow + deltaRow][pcol + deltaCol] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/72/72e28e0e0c13d4a098ae3bd0d37f8ba93b3021a0.svn-base b/CPE455/gameproject/.svn/pristine/72/72e28e0e0c13d4a098ae3bd0d37f8ba93b3021a0.svn-base new file mode 100644 index 0000000..016a6d6 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/72/72e28e0e0c13d4a098ae3bd0d37f8ba93b3021a0.svn-base @@ -0,0 +1,382 @@ +#include +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/78/7878dde9dd2176fdbb5c412177499cfabf9c7cfd.svn-base b/CPE455/gameproject/.svn/pristine/78/7878dde9dd2176fdbb5c412177499cfabf9c7cfd.svn-base new file mode 100644 index 0000000..4b4c7e6 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/78/7878dde9dd2176fdbb5c412177499cfabf9c7cfd.svn-base @@ -0,0 +1,128 @@ +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + + /* check to see if argument */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + /* print out maze */ + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + /* free the memory */ + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + maze[i] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/7a/7a2f63638bf254ff36facc2886b13e915168a660.svn-base b/CPE455/gameproject/.svn/pristine/7a/7a2f63638bf254ff36facc2886b13e915168a660.svn-base new file mode 100644 index 0000000..529290a --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/7a/7a2f63638bf254ff36facc2886b13e915168a660.svn-base @@ -0,0 +1,156 @@ +#include +#include +#include +#include + +void readPlayer(char *arr); +void readZombie(char *arr); +void readTreasure(char *arr); + +// global array for maze +char **maze; + +// read maze file in to the array +void readMaze(char *arr, int r, int c); + +int main(int argc, char *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(char)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + printf("%c", maze[i][j]); + } + + } + printf("%c", maze[0 * col + 0]); + // for(i = 0; i < row; i++) + { + // free(maze[i]); + } + // free(maze); + // int (*maze)[col] = malloc(sizeof(int[row][col])); + //readMaze(maze, row, col); + break; + case 'P': + //case for player + printf ("Player\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* player = malloc((row * col) * sizeof(char)); + // readPlayer(player); + break; + + case 'Z': + //case for zombie + printf ("Zombie\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* zombie = malloc((row * col) * sizeof(char)); + // readZombie(zombie); + break; + + case 'T': + //case for treasure + printf ("Treasure\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* treasure = malloc((row * col) * sizeof(char)); + // readTreasure(treasure); + break; + case '\n': + break; + default: + //printf ("Basic error\n"); + break; + }; + + // for(int i=0;i +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + WINDOW* W = 0; /* Curses Window handle */ + + /* check to see if argument */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + /* Initialize ncurses -- you will want to use the following settings */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, row, col); /* Query terminal dimensions */ + /* print out maze */ + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/7a/7ad16095f4a29b8551fef45ac4915a1ec05ae23c.svn-base b/CPE455/gameproject/.svn/pristine/7a/7ad16095f4a29b8551fef45ac4915a1ec05ae23c.svn-base new file mode 100644 index 0000000..a95bd3c --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/7a/7ad16095f4a29b8551fef45ac4915a1ec05ae23c.svn-base @@ -0,0 +1,432 @@ +#include +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); +extern int noecho(void); + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to open the file so must use bad one bc we cannot create one ourselves as we are not wizards */ + mazeFile = fopen(argv[1], "r"); /* open file */ + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to get first char from file and we must use bad one as we cannot make one ourselves */ + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + /* parse maze file, + adding chars to array */ + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &row, &col); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to dynamially allocate memory cannot create own as we lack experience */ + maze = (char**)malloc(row * 8); /* allocate memory for rows of array, 8 reperesents size of char* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to dynamially allocate memory cannot create own as we lack experience */ + maze[i] = malloc(col * 8); /* allocate memory for collumns of array, 8 reperesents size of char* */ + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + /* start ncurses coloring of maze */ + for (c1 =(unsigned)0; c1 < row; c1++) + { + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + /* parse maze */ + switch(maze[c1][c2]) + { + /* color wall green */ + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + /* place space at position specified in array */ + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + /* place player at position specified in file */ + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + /* place zombie at position specified in file */ + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + /* place treasure at position specified in file */ + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow = 0; + deltaCol = 0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + /* check current player position against maze bounds, + if over the bounds, don't move */ + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + /* check future player position to see if wall; + if it is, stay in the same spot, + else move to new postion */ + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + /* check curremt position for treasure, + make treasure position a space, + and increment score */ + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + /* check curremt position for zombie, + end game */ + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze); + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + endwin(); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to print score for project, so even though not great have to use bad one */ + printf("Score = %u\n", score); + return 0; + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Y was statically allocated no need to free it */ + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Maze has been freed already valgrind shows no leaks error must have ocurred in analysis */ +} + diff --git a/CPE455/gameproject/.svn/pristine/7c/7c3fee53676f1b653f28dae1914c500198216af4.svn-base b/CPE455/gameproject/.svn/pristine/7c/7c3fee53676f1b653f28dae1914c500198216af4.svn-base new file mode 100644 index 0000000..3aad3e8 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/7c/7c3fee53676f1b653f28dae1914c500198216af4.svn-base @@ -0,0 +1,18 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +T 8 15 +Z 8 10 +P 2 10 +Z 7 24 +T 2 20 diff --git a/CPE455/gameproject/.svn/pristine/80/806357297ee076027dfd366b261d24cb23eca808.svn-base b/CPE455/gameproject/.svn/pristine/80/806357297ee076027dfd366b261d24cb23eca808.svn-base new file mode 100644 index 0000000..d93c51a --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/80/806357297ee076027dfd366b261d24cb23eca808.svn-base @@ -0,0 +1,113 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(unsigned int *)); + for(i = 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/81/815539cf95fba3ca6ff177a893b163c73b0b78b3.svn-base b/CPE455/gameproject/.svn/pristine/81/815539cf95fba3ca6ff177a893b163c73b0b78b3.svn-base new file mode 100644 index 0000000..481fd74 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/81/815539cf95fba3ca6ff177a893b163c73b0b78b3.svn-base @@ -0,0 +1,253 @@ +#include +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_RED, COLOR_BLACK); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_BLUE); /* White text on Blue background */ + init_pair(4, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + wmove(W, c1,c2); + waddch(W,'#'); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + wmove(W, c1,c2); + waddch(W,'Z'); + break; + case 'T': + wmove(W, c1,c2); + waddch(W,'T'); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + prow = prow + deltaRow; + pcol = pcol + deltaCol; + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/81/819a64ad5e27abeca5ba5d4495358cd2715b10fd.svn-base b/CPE455/gameproject/.svn/pristine/81/819a64ad5e27abeca5ba5d4495358cd2715b10fd.svn-base new file mode 100644 index 0000000..cafd5ff --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/81/819a64ad5e27abeca5ba5d4495358cd2715b10fd.svn-base @@ -0,0 +1,283 @@ +#include +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/83/83aaa46d61443165e3c881f99b86a049e5380c87.svn-base b/CPE455/gameproject/.svn/pristine/83/83aaa46d61443165e3c881f99b86a049e5380c87.svn-base new file mode 100644 index 0000000..9d95a9d --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/83/83aaa46d61443165e3c881f99b86a049e5380c87.svn-base @@ -0,0 +1,164 @@ +#include +#include +#include +#include + +void readPlayer(char *arr); +void readZombie(char *arr); +void readTreasure(char *arr); + +// global array for maze +char **maze; + +// read maze file in to the array +void readMaze(char *arr, int r, int c); + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + //printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + // printf("%d\n", row); + // possible dynamic allocation of 2D array + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(char)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + //fscanf(mazeFile, "%c", &chold); + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + printf ("\n"); + fscanf(mazeFile, "%c", &maze[i][j]); + } + printf("%c", maze[i][j]); + } + + } + // printf("%c", maze[0 * col + 0]); + // for(i = 0; i < row; i++) + //{ + // free(maze[i]); + //} + // free(maze); + // int (*maze)[col] = malloc(sizeof(int[row][col])); + //readMaze(maze, row, col); + break; + case 'P': + //case for player + //printf ("Player\n"); + fscanf(mazeFile, "%d %d", &row, &col); + maze[row][col] = 'P'; + //printf("%c" , maze[row][col]); + //printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* player = malloc((row * col) * sizeof(char)); + // readPlayer(player); + break; + + case 'Z': + //case for zombie + printf ("Zombie\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* zombie = malloc((row * col) * sizeof(char)); + // readZombie(zombie); + break; + + case 'T': + //case for treasure + printf ("Treasure\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* treasure = malloc((row * col) * sizeof(char)); + // readTreasure(treasure); + break; + case '\n': + printf("\n"); + break; + default: + //printf ("Basic error\n"); + break; + }; + + // for(int i=0;i +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // dynamic allocation of array for maze + unsigned int i = 0, j = 0; + maze = malloc(row * sizeof(unsigned int *)); + for(i = 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + unsigned int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/94/94bb5efa80c90ab41661bb05909edab0644b9303.svn-base b/CPE455/gameproject/.svn/pristine/94/94bb5efa80c90ab41661bb05909edab0644b9303.svn-base new file mode 100644 index 0000000..77d9e8c --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/94/94bb5efa80c90ab41661bb05909edab0644b9303.svn-base @@ -0,0 +1,417 @@ +#include +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); +extern int noecho(void); + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to open the file so must use bad one bc we cannot create one ourselves as we are not wizards */ + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to get first char from file and we must use bad one as we cannot make one ourselves */ + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &row, &col); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Have to use function to dynamically allocate memory even though all are named bad as no other ones exist */ + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Have to use function to dynamically allocate memory even though all are named bad as no other ones exist */ + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze); + } + /*printw("\n");*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + endwin(); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to print score for project, so even though not great have to use bad one */ + printf("Score = %u\n", score); + return 0; + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Y was statically allocated no need to free it */ + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Maze has been freed already valgrind shows no leaks error must have ocurred in analysis */ +} + diff --git a/CPE455/gameproject/.svn/pristine/9a/9ab75e624d15e88ed0d743153bc886d43e06d9e5.svn-base b/CPE455/gameproject/.svn/pristine/9a/9ab75e624d15e88ed0d743153bc886d43e06d9e5.svn-base new file mode 100644 index 0000000..c30d620 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/9a/9ab75e624d15e88ed0d743153bc886d43e06d9e5.svn-base @@ -0,0 +1,118 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l; + int k; + int c1; + int c2; + + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + //printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + // printf("%d\n", row); + // possible dynamic allocation of 2D array + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(char)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + //fscanf(mazeFile, "%c", &chold); + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + printf ("\n"); + fscanf(mazeFile, "%c", &maze[i][j]); + } + printf("%c", maze[i][j]); + } + } + break; + case 'P': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'P'; + printf("%c" , maze[k][l]); + break; + + case 'Z': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'Z'; + printf("%c" , maze[k][l]); + break; + + case 'T': + //case for treasure + printf ("Treasure\n"); + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'T'; + printf("%c" , maze[k][l]); + break; + case '\n': + printf("\n"); + break; + default: + //printf ("Basic error\n"); + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + printf("%c", maze[c1][c2]); + } + } + //printf ("So this line won't print without an argument.\n"); + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + free(maze[i]); + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/a7/a7e46494db01f659f4164aa77fba0104708c105b.svn-base b/CPE455/gameproject/.svn/pristine/a7/a7e46494db01f659f4164aa77fba0104708c105b.svn-base new file mode 100644 index 0000000..d1a5ed7 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/a7/a7e46494db01f659f4164aa77fba0104708c105b.svn-base @@ -0,0 +1,113 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + int row = 0; /* Holds number of rows for input from file */ + int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l = 0; + int k = 0; + int c1 = 0; + int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(unsigned int *)); + for(i = 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/aa/aa1c21d8690d0717f9f998d3ac91b21c2f6f0929.svn-base b/CPE455/gameproject/.svn/pristine/aa/aa1c21d8690d0717f9f998d3ac91b21c2f6f0929.svn-base new file mode 100644 index 0000000..9849d29 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/aa/aa1c21d8690d0717f9f998d3ac91b21c2f6f0929.svn-base @@ -0,0 +1,254 @@ +#include +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_RED, COLOR_BLACK); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_BLUE); /* White text on Blue background */ + init_pair(4, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + wmove(W, c1,c2); + waddch(W,'#'); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + wmove(W, c1,c2); + waddch(W,'Z'); + break; + case 'T': + wmove(W, c1,c2); + waddch(W,'T'); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + prow = rowLimit/4; + pcol = colLimit/4; + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + prow = prow + deltaRow; + pcol = pcol + deltaCol; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/aa/aaaa9c84d0316f12195ba39fe935b3dfc1439476.svn-base b/CPE455/gameproject/.svn/pristine/aa/aaaa9c84d0316f12195ba39fe935b3dfc1439476.svn-base new file mode 100644 index 0000000..c550ef6 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/aa/aaaa9c84d0316f12195ba39fe935b3dfc1439476.svn-base @@ -0,0 +1,15 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +P 2 10 +Z 8 10 diff --git a/CPE455/gameproject/.svn/pristine/b0/b04c8291e1b519efd40b97b35960b9fe99a03e08.svn-base b/CPE455/gameproject/.svn/pristine/b0/b04c8291e1b519efd40b97b35960b9fe99a03e08.svn-base new file mode 100644 index 0000000..7ac8a28 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/b0/b04c8291e1b519efd40b97b35960b9fe99a03e08.svn-base @@ -0,0 +1,27 @@ +#include +#include +#include +#include + +int main(int argc, char const *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fclose(mazeFile); + printf ("So this line won't print without an argument.\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/bb/bb9fb7f1389939ebd7c061043b5120ade797367e.svn-base b/CPE455/gameproject/.svn/pristine/bb/bb9fb7f1389939ebd7c061043b5120ade797367e.svn-base new file mode 100644 index 0000000..f8a014e --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/bb/bb9fb7f1389939ebd7c061043b5120ade797367e.svn-base @@ -0,0 +1,150 @@ +#include +#include +#include +#include + +void readPlayer(char *arr); +void readZombie(char *arr); +void readTreasure(char *arr); + +// global array for maze +char **maze; + +// read maze file in to the array +void readMaze(char *arr, int r, int c); + +int main(int argc, char *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + maze[i] = malloc(col * sizeof(char)); + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + printf("%c", maze[i][j]); + } + + } + printf("%c", maze[0 * col + 0]); + for(i = 0; i < row; i++) + free(maze[i]); + free(maze); + //int (*maze)[col] = malloc(sizeof(int[row][col])); + //readMaze(maze, row, col); + break; + case 'P': + //case for player + printf ("Player\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* player = malloc((row * col) * sizeof(char)); + readPlayer(player); + break; + + case 'Z': + //case for zombie + printf ("Zombie\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* zombie = malloc((row * col) * sizeof(char)); + readZombie(zombie); + break; + + case 'T': + //case for treasure + printf ("Treasure\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + char* treasure = malloc((row * col) * sizeof(char)); + readTreasure(treasure); + break; + default: + //printf ("Basic error\n"); + break; + }; + + // for(int i=0;i +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + prow = prow + deltaRow; + pcol = pcol + deltaCol; + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/c2/c2fe754be079eb0b947e0b5d29a74fb579767b5c.svn-base b/CPE455/gameproject/.svn/pristine/c2/c2fe754be079eb0b947e0b5d29a74fb579767b5c.svn-base new file mode 100644 index 0000000..ef24ee2 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/c2/c2fe754be079eb0b947e0b5d29a74fb579767b5c.svn-base @@ -0,0 +1,114 @@ +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; // global array for maze + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // dynamic allocation of array for maze + unsigned int i = 0, j = 0; + maze = malloc(row * sizeof(unsigned int *)); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + unsigned int i = 0; + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/c4/c4acfdf60a48bdc3f9fdeac051c47abad0a1b1bb.svn-base b/CPE455/gameproject/.svn/pristine/c4/c4acfdf60a48bdc3f9fdeac051c47abad0a1b1bb.svn-base new file mode 100644 index 0000000..819a5c5 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/c4/c4acfdf60a48bdc3f9fdeac051c47abad0a1b1bb.svn-base @@ -0,0 +1,3 @@ + +game: + gcc game.c -o game \ No newline at end of file diff --git a/CPE455/gameproject/.svn/pristine/c5/c5be78044fa882e0a63f94bd7e91907cbd98dbb6.svn-base b/CPE455/gameproject/.svn/pristine/c5/c5be78044fa882e0a63f94bd7e91907cbd98dbb6.svn-base new file mode 100644 index 0000000..111d389 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/c5/c5be78044fa882e0a63f94bd7e91907cbd98dbb6.svn-base @@ -0,0 +1,397 @@ +#include +#include +#include +#include +#include +#include + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/c8/c825065e56d9780cef34d996b4db8c563bd639ae.svn-base b/CPE455/gameproject/.svn/pristine/c8/c825065e56d9780cef34d996b4db8c563bd639ae.svn-base new file mode 100644 index 0000000..1641948 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/c8/c825065e56d9780cef34d996b4db8c563bd639ae.svn-base @@ -0,0 +1,124 @@ +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; // global array for maze + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // dynamic allocation of array for maze + unsigned int i = 0, j = 0; + maze = (char**)malloc(row * sizeof(unsigned int *)); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = (char*)malloc(col * sizeof(unsigned int *)); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + unsigned int i = 0; + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + maze[i] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/c8/c8e59f9b6a795aa9f98e540bd9a8650f6233ad0f.svn-base b/CPE455/gameproject/.svn/pristine/c8/c8e59f9b6a795aa9f98e540bd9a8650f6233ad0f.svn-base new file mode 100644 index 0000000..20b1f9a --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/c8/c8e59f9b6a795aa9f98e540bd9a8650f6233ad0f.svn-base @@ -0,0 +1,128 @@ +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + + /* check to see if argument */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + unsigned int i = 0, j = 0; + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + /* print out maze */ + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + /* free the memory */ + unsigned int i = 0; + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + maze[i] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/cc/ccdbc11d00d1044fe1f65d7dfc69a99cdc958cab.svn-base b/CPE455/gameproject/.svn/pristine/cc/ccdbc11d00d1044fe1f65d7dfc69a99cdc958cab.svn-base new file mode 100644 index 0000000..7af6f0c --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/cc/ccdbc11d00d1044fe1f65d7dfc69a99cdc958cab.svn-base @@ -0,0 +1,134 @@ +#include +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + WINDOW* W = 0; /* Curses Window handle */ + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + /*printw("%c", maze[c1][c2]);*/ + } + } + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/cd/cdb2e0867e9b53241a0f95803804be952659af50.svn-base b/CPE455/gameproject/.svn/pristine/cd/cdb2e0867e9b53241a0f95803804be952659af50.svn-base new file mode 100644 index 0000000..8b713f2 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/cd/cdb2e0867e9b53241a0f95803804be952659af50.svn-base @@ -0,0 +1,176 @@ +#include +#include +#include +#include + +void readPlayer(char *arr); +void readZombie(char *arr); +void readTreasure(char *arr); + +// global array for maze +char **maze; + +// read maze file in to the array +void readMaze(char *arr, int r, int c); + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l; + int k; + int c1; + int c2; + + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + //printf ("Maze encountered\n"); + fscanf(mazeFile, "%d %d", &row, &col); + // printf("%d\n", row); + // possible dynamic allocation of 2D array + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(char)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + //fscanf(mazeFile, "%c", &chold); + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + printf ("\n"); + fscanf(mazeFile, "%c", &maze[i][j]); + } + printf("%c", maze[i][j]); + } + + } + // printf("%c", maze[0 * col + 0]); + // for(i = 0; i < row; i++) + //{ + // free(maze[i]); + //} + // free(maze); + // int (*maze)[col] = malloc(sizeof(int[row][col])); + //readMaze(maze, row, col); + break; + case 'P': + //case for player + //printf ("Player\n"); + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'P'; + printf("%c" , maze[k][l]); + //printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* player = malloc((row * col) * sizeof(char)); + // readPlayer(player); + break; + + case 'Z': + //case for zombie + printf ("Zombie\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* zombie = malloc((row * col) * sizeof(char)); + // readZombie(zombie); + break; + + case 'T': + //case for treasure + printf ("Treasure\n"); + fscanf(mazeFile, "%d %d", &row, &col); + printf("%d\n", row); + // possible dynamic allocation of 2D array + // char* treasure = malloc((row * col) * sizeof(char)); + // readTreasure(treasure); + break; + case '\n': + printf("\n"); + break; + default: + //printf ("Basic error\n"); + break; + }; + + // for(int i=0;i +#include +#include +#include + +int main(int argc, char const *argv[]) +{ + printf("Hello, World!\n"); + FILE* mazeFile; /* Maze Input File */ + char c; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + switch(shold[0]) + { + case 'M': + printf ("Maze encountered\n"); + break; + default: + printf ("Basic error\n"); + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + printf ("So this line won't print without an argument.\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/d2/d268bdc1953be5b38f37088ea477e89870f363fe.svn-base b/CPE455/gameproject/.svn/pristine/d2/d268bdc1953be5b38f37088ea477e89870f363fe.svn-base new file mode 100644 index 0000000..316ba77 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/d2/d268bdc1953be5b38f37088ea477e89870f363fe.svn-base @@ -0,0 +1,39 @@ +M 22 75 +########################################################################### +# # # +# # # +# # # +# ################## # # +# # # # +# # # # +# # ############ # # # +# # # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # +# # # # +# ######################### # +# # # +# # # +# # # +########################################################################### +P 10 30 +Z 19 5 +Z 19 10 +Z 19 15 +T 5 43 +T 10 43 +T 15 43 +Z 2 5 +Z 2 10 +Z 2 15 +T 5 55 +T 10 55 +T 15 55 +T 5 67 +T 10 67 +T 15 67 diff --git a/CPE455/gameproject/.svn/pristine/d4/d400ec16eba9622fe5a1a756c604f99f024df258.svn-base b/CPE455/gameproject/.svn/pristine/d4/d400ec16eba9622fe5a1a756c604f99f024df258.svn-base new file mode 100644 index 0000000..73df2d4 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/d4/d400ec16eba9622fe5a1a756c604f99f024df258.svn-base @@ -0,0 +1,151 @@ +#include +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + WINDOW* W = 0; /* Curses Window handle */ + + /* check to see if argument */ + if (argc != 2) + { + printw("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printw("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + /* Initialize ncurses -- you will want to use the following settings */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, row, col); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_RED, COLOR_BLACK); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_BLUE); /* White text on Blue background */ + init_pair(4, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + printw ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printw("%c", maze[c1][c2]); + } + } + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + printw("\n"); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/d7/d78573182d078f24e5f32bc8465664d0cf8f424b.svn-base b/CPE455/gameproject/.svn/pristine/d7/d78573182d078f24e5f32bc8465664d0cf8f424b.svn-base new file mode 100644 index 0000000..dfb7593 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/d7/d78573182d078f24e5f32bc8465664d0cf8f424b.svn-base @@ -0,0 +1,294 @@ +#include +#include +#include +#include +#include +#include + +WINDOW *initscr(void); +int start_color(void); +int cbreak(void); +int noecho(void); +int nodelay(WINDOW *win, bool bf); +int keypad(WINDOW *win, bool bf); +int curs_set(int visibility); +/*void getmaxyx(WINDOW *win, int y, int x); */ +int init_pair(short pair, short f, short b); +/*int attron(int attrs); +int COLOR_PAIR(int n); +int wmove(WINDOW *win, int y, int x); +nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/db/db75edfbeb0b72d9513f0ee57319d6936cd52f32.svn-base b/CPE455/gameproject/.svn/pristine/db/db75edfbeb0b72d9513f0ee57319d6936cd52f32.svn-base new file mode 100644 index 0000000..6b20b1b --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/db/db75edfbeb0b72d9513f0ee57319d6936cd52f32.svn-base @@ -0,0 +1,127 @@ +#include +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0, j = 0; + + /* check to see if argument */ + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + /* print out maze */ + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + /* free the memory */ + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + maze[i] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/dc/dca3f0eb6d1b5a543d670d8b2499ed45a852e2c0.svn-base b/CPE455/gameproject/.svn/pristine/dc/dca3f0eb6d1b5a543d670d8b2499ed45a852e2c0.svn-base new file mode 100644 index 0000000..29747c8 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/dc/dca3f0eb6d1b5a543d670d8b2499ed45a852e2c0.svn-base @@ -0,0 +1,380 @@ +#include +#include +#include +#include +#include +#include + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/de/de10cfd31f2b11c7889d140f781ac2000667ad65.svn-base b/CPE455/gameproject/.svn/pristine/de/de10cfd31f2b11c7889d140f781ac2000667ad65.svn-base new file mode 100644 index 0000000..391c94e --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/de/de10cfd31f2b11c7889d140f781ac2000667ad65.svn-base @@ -0,0 +1,290 @@ +#include +#include +#include +#include +#include +#include + +WINDOW *initscr(void); +int start_color(void); +int cbreak(void); +int noecho(void); +int nodelay(WINDOW *win, bool bf); +int keypad(WINDOW *win, bool bf); +int curs_set(int visibility); +/*void getmaxyx(WINDOW *win, int y, int x); */ +int init_pair(short pair, short f, short b); +/*int attron(int attrs); +int COLOR_PAIR(int n); +int wmove(WINDOW *win, int y, int x); +nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + deltaRow) > row) || ((pcol + deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[prow + deltaRow][pcol + deltaCol] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/de/de1b20d73f68f82c2fda85caf70e24076cfdb1c0.svn-base b/CPE455/gameproject/.svn/pristine/de/de1b20d73f68f82c2fda85caf70e24076cfdb1c0.svn-base new file mode 100644 index 0000000..d1be330 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/de/de1b20d73f68f82c2fda85caf70e24076cfdb1c0.svn-base @@ -0,0 +1,108 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row; /* Holds number of rows for input from file */ + int col; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l; + int k; + int c1; + int c2; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%d %d", &row, &col); + // possible dynamic allocation of 2D array + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(char *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(char)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'Z'; + printf("%c" , maze[k][l]); + break; + + case 'T': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'T'; + break; + case '\n': + printf("\n"); + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + printf("%c", maze[c1][c2]); + } + } + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + free(maze[i]); + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/de/de8431241c69d2c39f63d0eeebfe5e7861cae881.svn-base b/CPE455/gameproject/.svn/pristine/de/de8431241c69d2c39f63d0eeebfe5e7861cae881.svn-base new file mode 100644 index 0000000..595abf9 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/de/de8431241c69d2c39f63d0eeebfe5e7861cae881.svn-base @@ -0,0 +1,269 @@ +#include +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if((prow + deltaRow > row) || (pcol + deltaCol > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[prow + deltaRow][pcol + deltaCol] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/df/df743a21ea509dae23c3d1e5e5171f7e739169d9.svn-base b/CPE455/gameproject/.svn/pristine/df/df743a21ea509dae23c3d1e5e5171f7e739169d9.svn-base new file mode 100644 index 0000000..32011ec --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/df/df743a21ea509dae23c3d1e5e5171f7e739169d9.svn-base @@ -0,0 +1,110 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row = 0; /* Holds number of rows for input from file */ + int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l = 0; + int k = 0; + int c1 = 0; + int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(unsigned int *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'Z'; + printf("%c" , maze[k][l]); + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + maze[k][l] = 'T'; + break; + case '\n': + printf("\n"); + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + printf("%c", maze[c1][c2]); + } + } + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/e0/e096549e64981f8e8dd5137f7123b3b88672c3f2.svn-base b/CPE455/gameproject/.svn/pristine/e0/e096549e64981f8e8dd5137f7123b3b88672c3f2.svn-base new file mode 100644 index 0000000..7915b8e --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/e0/e096549e64981f8e8dd5137f7123b3b88672c3f2.svn-base @@ -0,0 +1,110 @@ +#include +#include +#include +#include + + +// global array for maze +char **maze; + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold; /* Holds character for line input from file */ + int row = 0; /* Holds number of rows for input from file */ + int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + int l = 0; + int k = 0; + int c1 = 0; + int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( !feof(mazeFile) ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%d %d", &row, &col); + // + // dynamic allocation of array for maze + int i = 0, j = 0; + maze = malloc(row * sizeof(unsigned int *)); + for(i = 0; i < row; i++) + { + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = 0; i < row; i++) + { + for (j = 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'Z'; + printf("%c" , maze[k][l]); + break; + + case 'T': + fscanf(mazeFile, "%d %d", &k, &l); + maze[k][l] = 'T'; + break; + case '\n': + printf("\n"); + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile)) + { + break; + } + } + fclose(mazeFile); + for (c1 =0; c1 < row; c1++) + { + printf ("\n"); + for (c2=0; c2 < col; c2++) + { + printf("%c", maze[c1][c2]); + } + } + + //free the memory + int i = 0; + for(i = 0; i < row; i++) + { + free(maze[i]); + } + free(maze); + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/e2/e2b3c034eb755257cb8f41cf13543c997fcf89b2.svn-base b/CPE455/gameproject/.svn/pristine/e2/e2b3c034eb755257cb8f41cf13543c997fcf89b2.svn-base new file mode 100644 index 0000000..a9d5413 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/e2/e2b3c034eb755257cb8f41cf13543c997fcf89b2.svn-base @@ -0,0 +1,287 @@ +#include +#include +#include +#include +#include +#include + +WINDOW *initscr(void); +int start_color(void); +int cbreak(void); +int noecho(void); +int nodelay(WINDOW *win, bool bf); +int keypad(WINDOW *win, bool bf); +int curs_set(int visibility); +/*void getmaxyx(WINDOW *win, int y, int x); */ +int init_pair(short pair, short f, short b); + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if((prow + deltaRow > row) || (pcol + deltaCol > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[prow + deltaRow][pcol + deltaCol] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/ec/ec8863cd79ce860c2c555cbb79c665add208fd97.svn-base b/CPE455/gameproject/.svn/pristine/ec/ec8863cd79ce860c2c555cbb79c665add208fd97.svn-base new file mode 100644 index 0000000..b1e4156 --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/ec/ec8863cd79ce860c2c555cbb79c665add208fd97.svn-base @@ -0,0 +1,285 @@ +#include +#include +#include +#include +#include +#include + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- why */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/f6/f68b734635aa3ba8786542f587fa2ea3a19a451b.svn-base b/CPE455/gameproject/.svn/pristine/f6/f68b734635aa3ba8786542f587fa2ea3a19a451b.svn-base new file mode 100644 index 0000000..5392d9a --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/f6/f68b734635aa3ba8786542f587fa2ea3a19a451b.svn-base @@ -0,0 +1,254 @@ +#include +#include +#include +#include +#include +#include + + +/*nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_RED, COLOR_BLACK); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_BLUE); /* White text on Blue background */ + init_pair(4, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + wmove(W, c1,c2); + waddch(W,'#'); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + wmove(W, c1,c2); + waddch(W,'Z'); + break; + case 'T': + wmove(W, c1,c2); + waddch(W,'T'); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + prow = rowLimit/4; + pcol = colLimit/4; + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + prow = prow + deltaRow; + pcol = pcol + deltaCol; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/f6/f6c516c156e60e7945b5f0aff408753dbc5067d4.svn-base b/CPE455/gameproject/.svn/pristine/f6/f6c516c156e60e7945b5f0aff408753dbc5067d4.svn-base new file mode 100644 index 0000000..be3bbdb --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/f6/f6c516c156e60e7945b5f0aff408753dbc5067d4.svn-base @@ -0,0 +1,124 @@ +#include +#include +#include +#include + + + + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + char chold = NULL; /* Holds character for line input from file */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; // global array for maze + unsigned int c1 = 0; + unsigned int c2 = 0; + + // check to see if + if (argc != 2) + { + printf("An error has ocurred no input file was given.\n"); + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + printf("Error in opening the file.\n"); + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + switch(shold[0]) + { + case 'M': + fscanf(mazeFile, "%3d %3d", &row, &col); + // dynamic allocation of array for maze + unsigned int i = 0, j = 0; + maze = (char**)malloc(row * sizeof(unsigned int *)); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * sizeof(unsigned int *)); + } + for (i = (unsigned) 0; i < row; i++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[i][j]); + if (maze[i][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[i][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3d %3d", &k, &l); + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + fclose(mazeFile); + for (c1 =(unsigned)0; c1 < row; c1++) + { + printf ("\n"); + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + printf("%c", maze[c1][c2]); + } + } + + //free the memory + unsigned int i = 0; + for(i = (unsigned)0; i < row; i++) + { + free(maze[i]); + maze[i] = NULL; + } + if(maze != NULL){ + free(maze); + } + printf("\n"); + + return 0; +} diff --git a/CPE455/gameproject/.svn/pristine/f8/f8f4e279838d991c603b0eedd19dfaeaef0a56a8.svn-base b/CPE455/gameproject/.svn/pristine/f8/f8f4e279838d991c603b0eedd19dfaeaef0a56a8.svn-base new file mode 100644 index 0000000..964efed --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/f8/f8f4e279838d991c603b0eedd19dfaeaef0a56a8.svn-base @@ -0,0 +1,290 @@ +#include +#include +#include +#include +#include +#include + +WINDOW *initscr(void); +int start_color(void); +int cbreak(void); +int noecho(void); +int nodelay(WINDOW *win, bool bf); +int keypad(WINDOW *win, bool bf); +int curs_set(int visibility); +/*void getmaxyx(WINDOW *win, int y, int x); */ +int init_pair(short pair, short f, short b); +/*int attron(int attrs); +int COLOR_PAIR(int n); +int wmove(WINDOW *win, int y, int x); +nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/fc/fc6bc8cae0cfab930cf4b017b0925ef3bc071243.svn-base b/CPE455/gameproject/.svn/pristine/fc/fc6bc8cae0cfab930cf4b017b0925ef3bc071243.svn-base new file mode 100644 index 0000000..934aeec --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/fc/fc6bc8cae0cfab930cf4b017b0925ef3bc071243.svn-base @@ -0,0 +1,290 @@ +#include +#include +#include +#include +#include +#include + +WINDOW *initscr(void); +int start_color(void); +int cbreak(void); +int noecho(void); +int nodelay(WINDOW *win, bool bf); +int keypad(WINDOW *win, bool bf); +int curs_set(int visibility); +/*void getmaxyx(WINDOW *win, int y, int x); */ +int init_pair(short pair, short f, short b); +/*int attron(int attrs); +int COLOR_PAIR(int n); +int wmove(WINDOW *win, int y, int x); +nothing*/ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ +unsigned int pcol = 0; +unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + fclose(mazeFile); + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + /*printw("%c", maze[c1][c2]);*/ + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if((prow + deltaRow > row) || (pcol + deltaCol > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[prow + deltaRow][pcol + deltaCol] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + deltaRow; + pcol = pcol + deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/pristine/fe/fe8d4c143d050b50954b09e753da9f52225ec692.svn-base b/CPE455/gameproject/.svn/pristine/fe/fe8d4c143d050b50954b09e753da9f52225ec692.svn-base new file mode 100644 index 0000000..318011c --- /dev/null +++ b/CPE455/gameproject/.svn/pristine/fe/fe8d4c143d050b50954b09e753da9f52225ec692.svn-base @@ -0,0 +1,285 @@ +#include +#include +#include +#include +#include +#include + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + mazeFile = fopen(argv[1], "r"); + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + fscanf(mazeFile, "%3u %3u", &row, &col); + maze = (char**)malloc(row * 8); /* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + maze[i] = malloc(col * 8); + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- why */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + + for (c1 =(unsigned)0; c1 < row; c1++) + { + /*printw ("\n");*/ + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + switch(maze[c1][c2]) + { + case '#': + /* read array values, dynamically allocate array*/ + attron(COLOR_PAIR(2)); + wmove(W, c1,c2); + waddch(W,'#'); + attroff(COLOR_PAIR(2)); + break; + case ' ': + wmove(W, c1,c2); + waddch(W,' '); + break; + case 'P': + wmove(W, c1,c2); + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + case 'Z': + attron(COLOR_PAIR(4)); + wmove(W, c1,c2); + waddch(W,'Z'); + attroff(COLOR_PAIR(4)); + break; + case 'T': + attron(COLOR_PAIR(5)); + wmove(W, c1,c2); + waddch(W,'T'); + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow =0; + deltaCol =0; + + + + do{ + + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + attron(COLOR_PAIR(1)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + if(maze[prow][pcol] == 'Z') + { + break; + } + + attron(COLOR_PAIR(3)); + wmove(W,prow,pcol); + waddch(W, 'P'); + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + free(maze); + } + /*printw("\n");*/ + endwin(); + printf("Score = %u\n", score); + return 0; +} + diff --git a/CPE455/gameproject/.svn/wc.db b/CPE455/gameproject/.svn/wc.db new file mode 100644 index 0000000..3312f62 Binary files /dev/null and b/CPE455/gameproject/.svn/wc.db differ diff --git a/CPE455/gameproject/.vscode/configurationCache.log b/CPE455/gameproject/.vscode/configurationCache.log new file mode 100644 index 0000000..c1581d4 --- /dev/null +++ b/CPE455/gameproject/.vscode/configurationCache.log @@ -0,0 +1 @@ +{"buildTargets":["clean","game","make"],"launchTargets":["/home/student/anw0044/CPE455/gameproject>game()"],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":["/home/student/anw0044/CPE455/gameproject"],"compilerArgs":["-g","-Wall","--pedantic","-ansi","--coverage","game.c","-o","game","-l","ncurses"],"compilerPath":"/usr/bin/gcc","windowsSdkVersion":""},"fileIndex":[["/home/student/anw0044/CPE455/gameproject/game.c",{"uri":{"$mid":1,"fsPath":"/home/student/anw0044/CPE455/gameproject/game.c","path":"/home/student/anw0044/CPE455/gameproject/game.c","scheme":"file"},"configuration":{"defines":[],"includePath":[],"forcedInclude":[],"compilerPath":"/usr/bin/gcc","compilerArgs":["-g","-Wall","--pedantic","-ansi","--coverage","game.c","-o","game","-l","ncurses"],"windowsSdkVersion":""},"compileCommand":{"command":"gcc -g -Wall --pedantic -ansi --coverage game.c -o game -l ncurses","directory":"/home/student/anw0044/CPE455/gameproject","file":"/home/student/anw0044/CPE455/gameproject/game.c"}}]]}} \ No newline at end of file diff --git a/CPE455/gameproject/.vscode/dryrun.log b/CPE455/gameproject/.vscode/dryrun.log new file mode 100644 index 0000000..be93bd0 --- /dev/null +++ b/CPE455/gameproject/.vscode/dryrun.log @@ -0,0 +1,5 @@ +make --dry-run --always-make --keep-going --print-directory +make: Entering directory `/home/student/anw0044/CPE455/gameproject' +gcc -g -Wall --pedantic -ansi --coverage game.c -o game -l ncurses +make: Leaving directory `/home/student/anw0044/CPE455/gameproject' + diff --git a/CPE455/gameproject/.vscode/launch.json b/CPE455/gameproject/.vscode/launch.json new file mode 100644 index 0000000..3e051d5 --- /dev/null +++ b/CPE455/gameproject/.vscode/launch.json @@ -0,0 +1,33 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "(gdb) Launch", + "type": "cppdbg", + "request": "launch", + "program": "enter program name, for example ${workspaceFolder}/a.out", + "args": [], + "stopAtEntry": false, + "cwd": "${fileDirname}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + }, + { + "description": "Set Disassembly Flavor to Intel", + "text": "-gdb-set disassembly-flavor intel", + "ignoreFailures": true + } + ] + } + + ] +} \ No newline at end of file diff --git a/CPE455/gameproject/.vscode/settings.json b/CPE455/gameproject/.vscode/settings.json new file mode 100644 index 0000000..393fb13 --- /dev/null +++ b/CPE455/gameproject/.vscode/settings.json @@ -0,0 +1,14 @@ +{ + "makefile.extensionOutputFolder": "./.vscode", + "C_Cpp.default.configurationProvider": "ms-vscode.makefile-tools", + "makefile.launchConfigurations": [ + { + "cwd": "/home/student/anw0044/CPE455/gameproject", + "binaryPath": "/home/student/anw0044/CPE455/gameproject/game", + "binaryArgs": [] + } + ], + "files.associations": { + "string.h": "c" + } +} \ No newline at end of file diff --git a/CPE455/gameproject/.vscode/targets.log b/CPE455/gameproject/.vscode/targets.log new file mode 100644 index 0000000..4beea99 --- /dev/null +++ b/CPE455/gameproject/.vscode/targets.log @@ -0,0 +1,309 @@ +make all --print-data-base --no-builtin-variables --no-builtin-rules --question +# GNU Make 3.82 +# Built for x86_64-redhat-linux-gnu +# Copyright (C) 2010 Free Software Foundation, Inc. +# License GPLv3+: GNU GPL version 3 or later +# This is free software: you are free to change and redistribute it. +# There is NO WARRANTY, to the extent permitted by law. + +# Make data base, printed on Thu Apr 28 08:13:06 2022 + +# Variables + +# automatic + +#include +#include +#include +#include +#include + +extern WINDOW* initscr(void); +extern int start_color(void); +extern int noecho(void); + + +/* LDRA_EXCLUDE RULE VIOLATION FALSE POSITIVE -- why */ + +int main(int argc, char *argv[]) +{ + FILE* mazeFile; /* Maze Input File */ + unsigned int row = 0; /* Holds number of rows for input from file */ + unsigned int col = 0; /* Holds number of cols for input from file */ + unsigned int pcol = 0; + unsigned int prow = 0; + char shold[2000]; /* Holds lines for input from file */ + unsigned int l = 0; + unsigned int k = 0; + char **maze; /* array for maze */ + unsigned int c1 = 0; + unsigned int c2 = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int x = 0; + unsigned int y = 0; + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + unsigned int score = 0; + + + WINDOW* W = 0; /* Curses Window handle */ + unsigned int rowLimit,colLimit; /* Num of rows and columns in terminal window */ + /* Initialize ncurses -- you will want to use the following settings */ + + + + /* check to see if argument */ + if (argc != 2) + { + /*printw("An error has ocurred no input file was given.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to open the file so must use bad one bc we cannot create one ourselves as we are not wizards */ + mazeFile = fopen(argv[1], "r"); /* open file */ + if (mazeFile == NULL) + { + /*printw("Error in opening the file.\n");*/ + return 1; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to get first char from file and we must use bad one as we cannot make one ourselves */ + fgets(shold, 2, mazeFile); + while ( feof(mazeFile) == 0 ) + { + + /* parse maze file, + adding chars to array */ + switch(shold[0]) + { + case 'M': + /* read array values, dynamically allocate array */ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &row, &col); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to dynamially allocate memory cannot create own as we lack experience */ + maze = (char**)malloc(row * 8); /* allocate memory for rows of array, 8 reperesents size of char* */ + for(i = (unsigned) 0; i < row; i++) + { + if (maze==NULL) + { + break; + } + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to dynamially allocate memory cannot create own as we lack experience */ + maze[i] = malloc(col * 8); /* allocate memory for collumns of array, 8 reperesents size of char* */ + } + for (x = (unsigned) 0; x < row; x++) + { + for (j = (unsigned) 0; j < col; j++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + if (maze[x][j] == '\n') + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%c", &maze[x][j]); + } + } + } + break; + case 'P': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'P'; + break; + + case 'Z': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'Z'; + break; + + case 'T': + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fscanf(mazeFile, "%3u %3u", &k, &l); + /* check maze bounds */ + if(k>= row || l>= col){ + break; + } + maze[k][l] = 'T'; + break; + default: + break; + }; + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to scan content from file, have ensured we will not scan extra */ + fgets(shold, 2, mazeFile); + if (feof(mazeFile) != 0) + { + break; + } + } + + + + rowLimit = row; + colLimit = col; + fclose(mazeFile); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + start_color(); /* Enable use of color with ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + noecho(); /* Disable echo printing of chars type by user */ + if (W == NULL) + { + return 0; + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + keypad(W, true); /* Enable keypad and arrow keys */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + curs_set(0); /* Set cursor to be invisible - 0 */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(2, COLOR_GREEN, COLOR_GREEN); /* Red text on Black background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(3, COLOR_WHITE, COLOR_WHITE); /* White text on Blue background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(4, COLOR_RED, COLOR_RED); /* Yellow text on Yellow background */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + init_pair(5, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + /* start ncurses coloring of maze */ + for (c1 =(unsigned)0; c1 < row; c1++) + { + for (c2=(unsigned)0; c2 < col; c2++) + { + if (maze==NULL) + { + break; + } + /* parse maze */ + switch(maze[c1][c2]) + { + /* color wall green */ + case '#': + /* read array values, dynamically allocate array*/ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(2)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'#'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(2)); + break; + /* place space at position specified in array */ + case ' ': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,' '); + break; + /* place player at position specified in file */ + case 'P': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'P'); + prow=c1; + pcol=c2; + break; + /* place zombie at position specified in file */ + case 'Z': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(4)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'Z'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(4)); + break; + /* place treasure at position specified in file */ + case 'T': + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(5)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W, c1,c2); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W,'T'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(5)); + break; + + default: + break; + }; + } + } + + deltaRow = 0; + deltaCol = 0; + + + + do{ + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == (int)'a' || kb == (int)'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaRow =0; + deltaCol =-1; + } + else if (kb == (int)'d' || kb == (int)'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaRow =0; + deltaCol =1; + } + else if (kb == (int)'w' || kb == (int)'i' || kb == KEY_UP) + { + /* Move Up */ + deltaRow =-1; + deltaCol =0; + } + else if (kb == (int)'s' || kb == (int)'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaRow =1; + deltaCol =0; + } + else if (kb == (int)'q') + { + /* q to exit player movement loop */ + break; + }; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(1)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(1)); + /* check current player position against maze bounds, + if over the bounds, don't move */ + if(((prow + (unsigned int)deltaRow) > row) || ((pcol + (unsigned int)deltaCol) > col)){ + deltaRow = 0; + deltaCol = 0; + } + /* check future player position to see if wall; + if it is, stay in the same spot, + else move to new postion */ + if(maze[((int)prow + deltaRow)][((int)pcol + deltaCol)] == '#'){ + prow = prow; + pcol = pcol; + } + else{ + prow = prow + (unsigned int)deltaRow; + pcol = pcol + (unsigned int)deltaCol; + } + /* check curremt position for treasure, + make treasure position a space, + and increment score */ + if(maze[prow][pcol] == 'T') + { + maze[prow][pcol] = ' '; + score++; + } + /* check curremt position for zombie, + end game */ + if(maze[prow][pcol] == 'Z') + { + break; + } + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attron(COLOR_PAIR(3)); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wmove(W,prow,pcol); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + waddch(W, 'P'); + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + attroff(COLOR_PAIR(3)); + + deltaRow =0; + deltaCol =0; + + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + /* free the memory */ + for(y = (unsigned)0; y < row; y++) + { + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze[y]); + maze[y] = NULL; + } + if(maze != NULL){ + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to free allocated memory, cannot create one ourselves bc we are not wizards */ + free(maze); + } + /* LDRA_EXCLUDE 170 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 496 S FALSE POSITIVE -- needed for ncurses */ + /* LDRA_EXCLUDE 41 D FALSE POSITIVE -- needed for ncurses */ + endwin(); + /* LDRA_EXCLUDE 44 S FALSE POSITIVE -- Need function to print score for project, so even though not great have to use bad one */ + printf("Score = %u\n", score); + return 0; + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Y was statically allocated no need to free it */ + /* LDRA_EXCLUDE 50 D FALSE POSITIVE -- Maze has been freed already valgrind shows no leaks error must have ocurred in analysis */ +} + diff --git a/CPE455/gameproject/game.gcda b/CPE455/gameproject/game.gcda new file mode 100644 index 0000000..9581743 Binary files /dev/null and b/CPE455/gameproject/game.gcda differ diff --git a/CPE455/gameproject/game.gcno b/CPE455/gameproject/game.gcno new file mode 100644 index 0000000..c647113 Binary files /dev/null and b/CPE455/gameproject/game.gcno differ diff --git a/CPE455/gameproject/maze1.txt b/CPE455/gameproject/maze1.txt new file mode 100644 index 0000000..004bd88 --- /dev/null +++ b/CPE455/gameproject/maze1.txt @@ -0,0 +1,14 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +P 2 10 diff --git a/CPE455/gameproject/maze2.txt b/CPE455/gameproject/maze2.txt new file mode 100644 index 0000000..c550ef6 --- /dev/null +++ b/CPE455/gameproject/maze2.txt @@ -0,0 +1,15 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +P 2 10 +Z 8 10 diff --git a/CPE455/gameproject/maze3.txt b/CPE455/gameproject/maze3.txt new file mode 100644 index 0000000..030f32e --- /dev/null +++ b/CPE455/gameproject/maze3.txt @@ -0,0 +1,16 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +Z 8 10 +P 2 10 +T 8 15 diff --git a/CPE455/gameproject/maze4.txt b/CPE455/gameproject/maze4.txt new file mode 100644 index 0000000..383995d --- /dev/null +++ b/CPE455/gameproject/maze4.txt @@ -0,0 +1,16 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +T 8 15 +Z 8 10 +P 2 10 diff --git a/CPE455/gameproject/maze5.txt b/CPE455/gameproject/maze5.txt new file mode 100644 index 0000000..3aad3e8 --- /dev/null +++ b/CPE455/gameproject/maze5.txt @@ -0,0 +1,18 @@ +M 12 40 +######################################## +# # # # +# # # # +# # # # +# # ###### ############ ### # +# # # # # # +# # # # # # +# # ###### #### ########## # +# # # # +# # # # +# # # # +######################################## +T 8 15 +Z 8 10 +P 2 10 +Z 7 24 +T 2 20 diff --git a/CPE455/gameproject/maze6.txt b/CPE455/gameproject/maze6.txt new file mode 100644 index 0000000..6669601 --- /dev/null +++ b/CPE455/gameproject/maze6.txt @@ -0,0 +1,21 @@ +M 14 21 +##################### +# # # # +# # # # +# # # # +# ####### ####### +# # +# # +# ########### # +# # # +# # # +# ##### # +# # +# # +##################### +T 8 15 +Z 9 10 +Z 6 11 +T 2 8 +P 2 10 +T 2 12 diff --git a/CPE455/gameproject/maze7.txt b/CPE455/gameproject/maze7.txt new file mode 100644 index 0000000..316ba77 --- /dev/null +++ b/CPE455/gameproject/maze7.txt @@ -0,0 +1,39 @@ +M 22 75 +########################################################################### +# # # +# # # +# # # +# ################## # # +# # # # +# # # # +# # ############ # # # +# # # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # +# # # # +# ######################### # +# # # +# # # +# # # +########################################################################### +P 10 30 +Z 19 5 +Z 19 10 +Z 19 15 +T 5 43 +T 10 43 +T 15 43 +Z 2 5 +Z 2 10 +Z 2 15 +T 5 55 +T 10 55 +T 15 55 +T 5 67 +T 10 67 +T 15 67 diff --git a/CPE455/lab01/driver.c b/CPE455/lab01/driver.c new file mode 100644 index 0000000..43c700d --- /dev/null +++ b/CPE455/lab01/driver.c @@ -0,0 +1,121 @@ +/* + * + * driver.c + * + * DO NOT MOFIFY OR SUBMIT THE CODE IN THIS FILE + * + */ + +#include +#include +#include +#include + +#include "stack.h" + + +/* bar( ) : writes bar of * to stdout */ +void bar(void) { printf("****************************************************************\n"); } + +/* main( ) : driver function to test */ +int main(int argc, char* argv[]) +{ + FILE* testFile; /* Input file */ + char c; /* First char of line input from file */ + int temp; /* Integer input from file */ + char s[2000]; /* Holds line input from file */ + + struct Node* headPtr = NULL; /* Pointer to top of stack */ + + if (argc != 2) + { + printf("Error: missing name of input file\n"); + return 1; + } + + testFile = fopen(argv[1], "r"); + + if ( testFile == NULL ) + { + printf("Error: unable to open file. Exiting now...\n"); + return 1; + } + + /* Echo print comment line in input file */ + fgets(s, 2000, testFile); + printf("Comment: %s\n",s); + + /* Priming read */ + fgets(s, 2, testFile); + + while ( !feof(testFile) ) + { + switch(s[0]) + { + case 'p': /* Print */ + printf("Print(): top [ "); + Print(headPtr); + printf("] bottom\n"); + break; + + case '+': /* Push */ + fscanf(testFile, "%c", &c); + fscanf(testFile, "%d", &temp); + printf("Push(%d)\n", temp); + Push(&headPtr, temp); + break; + + case '-': /* Pop */ + fscanf(testFile, "%c", &c); + temp = Pop(&headPtr); + printf("Pop(): %d\n", temp); + break; + + case 's': /* Size */ + printf("Size() = %d\n", Size(headPtr)); + break; + + case 'b': /* Bar */ + bar(); + break; + + case 'c': /* Clear */ + Clear(&headPtr); + printf("Clear()\n"); + break; + + case '\n': + break; + + default: /* Handle error */ + printf("Error: unknown command - %c\n", c); + break; + }; + + fgets(s, 2, testFile); + + if (feof(testFile)) + { + break; + } + } + + Clear(&headPtr); + fclose(testFile); + + return 0; +} + +/* Print(...) : outputs the current contents of the stack top to bottom separated by spaces */ +void Print(struct Node* headPtr) +{ + struct Node* tempPtr = headPtr; + + while (tempPtr != NULL) + { + printf("%d ", tempPtr->data); + tempPtr = tempPtr->nextPtr; + } +} + + diff --git a/CPE455/lab01/driver.o b/CPE455/lab01/driver.o new file mode 100644 index 0000000..6cec500 Binary files /dev/null and b/CPE455/lab01/driver.o differ diff --git a/CPE455/lab01/input1.txt b/CPE455/lab01/input1.txt new file mode 100644 index 0000000..9c55815 --- /dev/null +++ b/CPE455/lab01/input1.txt @@ -0,0 +1,30 @@ +# input1.txt - test push and clear operations +b +p +b ++ 5 +p +b ++ 10 +p +b ++ 15 +p +b ++ 20 +p +b +c +p +b ++ 1 ++ 2 ++ 3 ++ 4 ++ 5 +p +b +c +p +b + diff --git a/CPE455/lab01/input2.txt b/CPE455/lab01/input2.txt new file mode 100644 index 0000000..a3f9806 --- /dev/null +++ b/CPE455/lab01/input2.txt @@ -0,0 +1,29 @@ +# input2.txt - test pop operation +b +p +b ++ 1 ++ 2 ++ 3 ++ 4 ++ 5 +p +b +- +p +b +- +p +b +- +p +b +- +p +b +- +p +b +p +b + diff --git a/CPE455/lab01/input3.txt b/CPE455/lab01/input3.txt new file mode 100644 index 0000000..eb2ce83 --- /dev/null +++ b/CPE455/lab01/input3.txt @@ -0,0 +1,36 @@ +# input3.txt - test size operation +b +p +s +b ++ 1 ++ 2 ++ 3 ++ 4 ++ 5 +p +s +b +- +p +s +b +- +p +s +b +- +p +s +b +- +p +s +b +- +p +s +b +p +s +b diff --git a/CPE455/lab01/input4.txt b/CPE455/lab01/input4.txt new file mode 100644 index 0000000..04936c6 --- /dev/null +++ b/CPE455/lab01/input4.txt @@ -0,0 +1,36 @@ +# input4.txt - test clear operation +b +c +p +b ++ 99 +p +c +p +b ++ 5 +p +b ++ 10 +p +b ++ 15 +p +b ++ 20 +p +b +c +p +b ++ 1 ++ 2 ++ 3 ++ 4 ++ 5 +p +b +c +p +b + diff --git a/CPE455/lab01/lab01 b/CPE455/lab01/lab01 new file mode 100755 index 0000000..77228f7 Binary files /dev/null and b/CPE455/lab01/lab01 differ diff --git a/CPE455/lab01/makefile b/CPE455/lab01/makefile new file mode 100644 index 0000000..09bc0b6 --- /dev/null +++ b/CPE455/lab01/makefile @@ -0,0 +1,20 @@ +# +# lab01 makefile - DO NOT MODIFY THIS MAKEFILE +# + +CC = gcc +CFLAGS = -g -Wall -pedantic + +lab01: driver.o stack.o + $(CC) $(CFLAGS) driver.o stack.o -o lab01 + +driver.o: driver.c stack.h + $(CC) $(CFLAGS) -c driver.c + +stack.o: stack.c stack.h + $(CC) $(CFLAGS) -c stack.c + +clean: + rm lab01 driver.o stack.o + + diff --git a/CPE455/lab01/stack.c b/CPE455/lab01/stack.c new file mode 100644 index 0000000..8d9ee90 --- /dev/null +++ b/CPE455/lab01/stack.c @@ -0,0 +1,64 @@ +/* + * + * stack.c + * + * ADD ALL YOUR CODE HERE AND SUBMIT ONLY stack.c + * + * Be sure to test functionality with all input files + * + * and eliminate all memory leaks + * + */ + +#include +#include +#include +#include + +#include "stack.h" + + + +/* Push(...) : adds a new node containing value to the top of the stack assuming stack is not full */ +void Push(struct Node** headPtr, int value) +{ + struct Node * ptr = (struct Node*) malloc(sizeof(struct Node)); + ptr->data = value; + ptr->nextPtr = *headPtr; + *headPtr=ptr; +} + +/* Pop(...) : removes and frees node from top of stack, returning the data from the removed node, + * assuming the stack is not empty + */ +int Pop(struct Node** headPtr) +{ + struct Node * ptr = *headPtr; + int data = ptr->data; + ptr->nextPtr = *headPtr; + + ptr->nextPtr=NULL; + + + return data; +} + +/* Clear(...) : removes and frees all nodes from stack */ +void Clear(struct Node** headPtr) +{ + +} + +/* Size(...) : returns the number of nodes currently stored in the stack */ +uint32_t Size(struct Node* headPtr) +{ + struct Node * ptr = (struct Node*) malloc(sizeof(struct Node)); + + + return 0; /* Replace this statement with correct code */ +} + + + + + diff --git a/CPE455/lab01/stack.h b/CPE455/lab01/stack.h new file mode 100644 index 0000000..5bb9d93 --- /dev/null +++ b/CPE455/lab01/stack.h @@ -0,0 +1,45 @@ +/* + * + * stack.h + * + * DO NOT MOFIFY OR SUBMIT THE CODE IN THIS FILE + * + */ + +#ifndef STACK_H +#define STACK_H + + +struct Node +{ + int data; /* Data member of node structure */ + struct Node* nextPtr; /* Address of next node structure variable in the sequence */ +}; + +extern void Print(struct Node* headPtr); +/* Print(...) : outputs the current contents of the stack top to bottom separated by spaces */ + + +extern uint32_t Size(struct Node* headPtr); +/* Size(...) : returns the number of nodes currently stored in the stack */ + + +extern void Push(struct Node** headPtr, int value); +/* Push(...) : adds a new node containing value to the top of the stack assuming stack is not full */ + + +extern int Pop(struct Node** headPtr); +/* Pop(...) : removes and frees node from top of stack, returning the data from the removed node, + * assuming the stack is not empty + */ + + +extern void Clear(struct Node** headPtr); +/* Clear(...) : removes and frees all nodes from stack */ + + +#endif + + + + diff --git a/CPE455/lab01/stack.o b/CPE455/lab01/stack.o new file mode 100644 index 0000000..86106b4 Binary files /dev/null and b/CPE455/lab01/stack.o differ diff --git a/CPE455/lab02/.vscode/c_cpp_properties.json b/CPE455/lab02/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..dab2f43 --- /dev/null +++ b/CPE455/lab02/.vscode/c_cpp_properties.json @@ -0,0 +1,16 @@ +{ + "configurations": [ + { + "name": "linux-gcc-x64", + "includePath": [ + "${workspaceFolder}/**" + ], + "compilerPath": "/usr/bin/gcc", + "cStandard": "${default}", + "cppStandard": "${default}", + "intelliSenseMode": "linux-gcc-x64", + "compilerArgs": [] + } + ], + "version": 4 +} \ No newline at end of file diff --git a/CPE455/lab02/.vscode/launch.json b/CPE455/lab02/.vscode/launch.json new file mode 100644 index 0000000..1c3b9fc --- /dev/null +++ b/CPE455/lab02/.vscode/launch.json @@ -0,0 +1,28 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "C/C++ Runner: Debug Session", + "type": "cppdbg", + "request": "launch", + "args": [ + "" + ], + "stopAtEntry": false, + "cwd": "/home/student/anw0044/CPE455/lab02", + "environment": [], + "program": "/home/student/anw0044/CPE455/lab02/build/Debug/outDebug", + "internalConsoleOptions": "openOnSessionStart", + "MIMode": "gdb", + "miDebuggerPath": "/usr/bin/gdb", + "externalConsole": false, + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + } + ] +} \ No newline at end of file diff --git a/CPE455/lab02/.vscode/settings.json b/CPE455/lab02/.vscode/settings.json new file mode 100644 index 0000000..862cfc6 --- /dev/null +++ b/CPE455/lab02/.vscode/settings.json @@ -0,0 +1,30 @@ +{ + "C_Cpp_Runner.cCompilerPath": "/usr/bin/gcc", + "C_Cpp_Runner.cppCompilerPath": "/usr/bin/g++", + "C_Cpp_Runner.debuggerPath": "/usr/bin/gdb", + "C_Cpp_Runner.cStandard": "", + "C_Cpp_Runner.cppStandard": "", + "C_Cpp_Runner.msvcBatchPath": "", + "C_Cpp_Runner.warnings": [ + "-Wall", + "-Wextra", + "-Wpedantic" + ], + "C_Cpp_Runner.enableWarnings": true, + "C_Cpp_Runner.warningsAsError": false, + "C_Cpp_Runner.compilerArgs": [], + "C_Cpp_Runner.linkerArgs": [], + "C_Cpp_Runner.includePaths": [], + "C_Cpp_Runner.includeSearch": [ + "*", + "**/*" + ], + "C_Cpp_Runner.excludeSearch": [ + "**/build", + "**/build/**", + "**/.*", + "**/.*/**", + "**/.vscode", + "**/.vscode/**" + ] +} \ No newline at end of file diff --git a/CPE455/lab02/input.txt b/CPE455/lab02/input.txt new file mode 100644 index 0000000..a1db313 --- /dev/null +++ b/CPE455/lab02/input.txt @@ -0,0 +1 @@ +AAAABBBBCCCCDDDDEEEEFFFFGGGGHHHH diff --git a/CPE455/lab02/keyboardbo b/CPE455/lab02/keyboardbo new file mode 100755 index 0000000..c877ab6 Binary files /dev/null and b/CPE455/lab02/keyboardbo differ diff --git a/CPE455/lab02/keyboardbo.cpp b/CPE455/lab02/keyboardbo.cpp new file mode 100644 index 0000000..bbcd03d --- /dev/null +++ b/CPE455/lab02/keyboardbo.cpp @@ -0,0 +1,27 @@ + +#include + +using namespace std; + +int main( int argc, char* argv[ ] ) +{ + char a = 'A'; + char b = 'B'; + char buffer[4]; + char c = 'C'; + char d = 'D'; + + cout << "Enter up to 4 characters now: " << endl; + cin >> buffer; + cout << endl; + + cout << "buff = " << buffer << endl; + cout << "a = " << a << endl; + cout << "b = " << b << endl; + cout << "c = " << c << endl; + cout << "d = " << d << endl; + + return 0; +} + + diff --git a/CPE455/lab02/lab02.txt b/CPE455/lab02/lab02.txt new file mode 100644 index 0000000..27e7e9a --- /dev/null +++ b/CPE455/lab02/lab02.txt @@ -0,0 +1,2053 @@ +Script started on Thu 03 Mar 2022 09:47:42 AM CST +[?1034hbash-4.2$ gcc ++ -g mykeyboardbo.cpp -o keyboardbo.cpp  +bash-4.2$ file keyboardbo +keyboardbo: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), dynamically linked (uses shared libs), for GNU/Linux 2.6.32, BuildID[sha1]=069e77de925d719c6954141d01129fb285470713, not stripped +bash-4.2$ objdump -d keyboardbo + +keyboardbo: file format elf64-x86-64 + + +Disassembly of section .init: + +0000000000400750 <_init>: + 400750: 48 83 ec 08 sub $0x8,%rsp + 400754: 48 8b 05 9d 08 20 00 mov 0x20089d(%rip),%rax # 600ff8 <__gmon_start__> + 40075b: 48 85 c0 test %rax,%rax + 40075e: 74 05 je 400765 <_init+0x15> + 400760: e8 1b 00 00 00 callq 400780 <__gmon_start__@plt> + 400765: 48 83 c4 08 add $0x8,%rsp + 400769: c3 retq + +Disassembly of section .plt: + +0000000000400770 <.plt>: + 400770: ff 35 92 08 20 00 pushq 0x200892(%rip) # 601008 <_GLOBAL_OFFSET_TABLE_+0x8> + 400776: ff 25 94 08 20 00 jmpq *0x200894(%rip) # 601010 <_GLOBAL_OFFSET_TABLE_+0x10> + 40077c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000400780 <__gmon_start__@plt>: + 400780: ff 25 92 08 20 00 jmpq *0x200892(%rip) # 601018 <__gmon_start__> + 400786: 68 00 00 00 00 pushq $0x0 + 40078b: e9 e0 ff ff ff jmpq 400770 <.plt> + +0000000000400790 <_ZNSt8ios_base4InitC1Ev@plt>: + 400790: ff 25 8a 08 20 00 jmpq *0x20088a(%rip) # 601020 <_ZNSt8ios_base4InitC1Ev@GLIBCXX_3.4> + 400796: 68 01 00 00 00 pushq $0x1 + 40079b: e9 d0 ff ff ff jmpq 400770 <.plt> + +00000000004007a0 <__libc_start_main@plt>: + 4007a0: ff 25 82 08 20 00 jmpq *0x200882(%rip) # 601028 <__libc_start_main@GLIBC_2.2.5> + 4007a6: 68 02 00 00 00 pushq $0x2 + 4007ab: e9 c0 ff ff ff jmpq 400770 <.plt> + +00000000004007b0 <__cxa_atexit@plt>: + 4007b0: ff 25 7a 08 20 00 jmpq *0x20087a(%rip) # 601030 <__cxa_atexit@GLIBC_2.2.5> + 4007b6: 68 03 00 00 00 pushq $0x3 + 4007bb: e9 b0 ff ff ff jmpq 400770 <.plt> + +00000000004007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt>: + 4007c0: ff 25 72 08 20 00 jmpq *0x200872(%rip) # 601038 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@GLIBCXX_3.4> + 4007c6: 68 04 00 00 00 pushq $0x4 + 4007cb: e9 a0 ff ff ff jmpq 400770 <.plt> + +00000000004007d0 <_ZNSt8ios_base4InitD1Ev@plt>: + 4007d0: ff 25 6a 08 20 00 jmpq *0x20086a(%rip) # 601040 <_ZNSt8ios_base4InitD1Ev@GLIBCXX_3.4> + 4007d6: 68 05 00 00 00 pushq $0x5 + 4007db: e9 90 ff ff ff jmpq 400770 <.plt> + +00000000004007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>: + 4007e0: ff 25 62 08 20 00 jmpq *0x200862(%rip) # 601048 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@GLIBCXX_3.4> + 4007e6: 68 06 00 00 00 pushq $0x6 + 4007eb: e9 80 ff ff ff jmpq 400770 <.plt> + +00000000004007f0 <_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_@plt>: + 4007f0: ff 25 5a 08 20 00 jmpq *0x20085a(%rip) # 601050 <_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_@GLIBCXX_3.4> + 4007f6: 68 07 00 00 00 pushq $0x7 + 4007fb: e9 70 ff ff ff jmpq 400770 <.plt> + +0000000000400800 <_ZNSolsEPFRSoS_E@plt>: + 400800: ff 25 52 08 20 00 jmpq *0x200852(%rip) # 601058 <_ZNSolsEPFRSoS_E@GLIBCXX_3.4> + 400806: 68 08 00 00 00 pushq $0x8 + 40080b: e9 60 ff ff ff jmpq 400770 <.plt> + +0000000000400810 <_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@plt>: + 400810: ff 25 4a 08 20 00 jmpq *0x20084a(%rip) # 601060 <_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GLIBCXX_3.4> + 400816: 68 09 00 00 00 pushq $0x9 + 40081b: e9 50 ff ff ff jmpq 400770 <.plt> + +Disassembly of section .text: + +0000000000400820 <_start>: + 400820: 31 ed xor %ebp,%ebp + 400822: 49 89 d1 mov %rdx,%r9 + 400825: 5e pop %rsi + 400826: 48 89 e2 mov %rsp,%rdx + 400829: 48 83 e4 f0 and $0xfffffffffffffff0,%rsp + 40082d: 50 push %rax + 40082e: 54 push %rsp + 40082f: 49 c7 c0 10 0b 40 00 mov $0x400b10,%r8 + 400836: 48 c7 c1 a0 0a 40 00 mov $0x400aa0,%rcx + 40083d: 48 c7 c7 0d 09 40 00 mov $0x40090d,%rdi + 400844: e8 57 ff ff ff callq 4007a0 <__libc_start_main@plt> + 400849: f4 hlt + 40084a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000400850 : + 400850: b8 77 10 60 00 mov $0x601077,%eax + 400855: 55 push %rbp + 400856: 48 2d 70 10 60 00 sub $0x601070,%rax + 40085c: 48 83 f8 0e cmp $0xe,%rax + 400860: 48 89 e5 mov %rsp,%rbp + 400863: 77 02 ja 400867 + 400865: 5d pop %rbp + 400866: c3 retq + 400867: b8 00 00 00 00 mov $0x0,%eax + 40086c: 48 85 c0 test %rax,%rax + 40086f: 74 f4 je 400865 + 400871: 5d pop %rbp + 400872: bf 70 10 60 00 mov $0x601070,%edi + 400877: ff e0 jmpq *%rax + 400879: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +0000000000400880 : + 400880: b8 70 10 60 00 mov $0x601070,%eax + 400885: 55 push %rbp + 400886: 48 2d 70 10 60 00 sub $0x601070,%rax + 40088c: 48 c1 f8 03 sar $0x3,%rax + 400890: 48 89 e5 mov %rsp,%rbp + 400893: 48 89 c2 mov %rax,%rdx + 400896: 48 c1 ea 3f shr $0x3f,%rdx + 40089a: 48 01 d0 add %rdx,%rax + 40089d: 48 d1 f8 sar %rax + 4008a0: 75 02 jne 4008a4 + 4008a2: 5d pop %rbp + 4008a3: c3 retq + 4008a4: ba 00 00 00 00 mov $0x0,%edx + 4008a9: 48 85 d2 test %rdx,%rdx + 4008ac: 74 f4 je 4008a2 + 4008ae: 5d pop %rbp + 4008af: 48 89 c6 mov %rax,%rsi + 4008b2: bf 70 10 60 00 mov $0x601070,%edi + 4008b7: ff e2 jmpq *%rdx + 4008b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +00000000004008c0 <__do_global_dtors_aux>: + 4008c0: 80 3d e9 09 20 00 00 cmpb $0x0,0x2009e9(%rip) # 6012b0 + 4008c7: 75 11 jne 4008da <__do_global_dtors_aux+0x1a> + 4008c9: 55 push %rbp + 4008ca: 48 89 e5 mov %rsp,%rbp + 4008cd: e8 7e ff ff ff callq 400850 + 4008d2: 5d pop %rbp + 4008d3: c6 05 d6 09 20 00 01 movb $0x1,0x2009d6(%rip) # 6012b0 + 4008da: f3 c3 repz retq + 4008dc: 0f 1f 40 00 nopl 0x0(%rax) + +00000000004008e0 : + 4008e0: 48 83 3d 08 05 20 00 cmpq $0x0,0x200508(%rip) # 600df0 <__JCR_END__> + 4008e7: 00 + 4008e8: 74 1e je 400908 + 4008ea: b8 00 00 00 00 mov $0x0,%eax + 4008ef: 48 85 c0 test %rax,%rax + 4008f2: 74 14 je 400908 + 4008f4: 55 push %rbp + 4008f5: bf f0 0d 60 00 mov $0x600df0,%edi + 4008fa: 48 89 e5 mov %rsp,%rbp + 4008fd: ff d0 callq *%rax + 4008ff: 5d pop %rbp + 400900: e9 7b ff ff ff jmpq 400880 + 400905: 0f 1f 00 nopl (%rax) + 400908: e9 73 ff ff ff jmpq 400880 + +000000000040090d
: + 40090d: 55 push %rbp + 40090e: 48 89 e5 mov %rsp,%rbp + 400911: 53 push %rbx + 400912: 48 83 ec 28 sub $0x28,%rsp + 400916: 89 7d dc mov %edi,-0x24(%rbp) + 400919: 48 89 75 d0 mov %rsi,-0x30(%rbp) + 40091d: c6 45 ef 41 movb $0x41,-0x11(%rbp) + 400921: c6 45 ee 42 movb $0x42,-0x12(%rbp) + 400925: c6 45 ed 43 movb $0x43,-0x13(%rbp) + 400929: c6 45 ec 44 movb $0x44,-0x14(%rbp) + 40092d: be 30 0b 40 00 mov $0x400b30,%esi + 400932: bf a0 11 60 00 mov $0x6011a0,%edi + 400937: e8 a4 fe ff ff callq 4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 40093c: be 10 08 40 00 mov $0x400810,%esi + 400941: 48 89 c7 mov %rax,%rdi + 400944: e8 b7 fe ff ff callq 400800 <_ZNSolsEPFRSoS_E@plt> + 400949: 48 8d 45 e0 lea -0x20(%rbp),%rax + 40094d: 48 89 c6 mov %rax,%rsi + 400950: bf 80 10 60 00 mov $0x601080,%edi + 400955: e8 96 fe ff ff callq 4007f0 <_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_@plt> + 40095a: be 10 08 40 00 mov $0x400810,%esi + 40095f: bf a0 11 60 00 mov $0x6011a0,%edi + 400964: e8 97 fe ff ff callq 400800 <_ZNSolsEPFRSoS_E@plt> + 400969: be 4f 0b 40 00 mov $0x400b4f,%esi + 40096e: bf a0 11 60 00 mov $0x6011a0,%edi + 400973: e8 68 fe ff ff callq 4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 400978: 48 8d 55 e0 lea -0x20(%rbp),%rdx + 40097c: 48 89 d6 mov %rdx,%rsi + 40097f: 48 89 c7 mov %rax,%rdi + 400982: e8 59 fe ff ff callq 4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 400987: be 10 08 40 00 mov $0x400810,%esi + 40098c: 48 89 c7 mov %rax,%rdi + 40098f: e8 6c fe ff ff callq 400800 <_ZNSolsEPFRSoS_E@plt> + 400994: 0f be 5d ef movsbl -0x11(%rbp),%ebx + 400998: be 57 0b 40 00 mov $0x400b57,%esi + 40099d: bf a0 11 60 00 mov $0x6011a0,%edi + 4009a2: e8 39 fe ff ff callq 4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 4009a7: 89 de mov %ebx,%esi + 4009a9: 48 89 c7 mov %rax,%rdi + 4009ac: e8 0f fe ff ff callq 4007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt> + 4009b1: be 10 08 40 00 mov $0x400810,%esi + 4009b6: 48 89 c7 mov %rax,%rdi + 4009b9: e8 42 fe ff ff callq 400800 <_ZNSolsEPFRSoS_E@plt> + 4009be: 0f be 5d ee movsbl -0x12(%rbp),%ebx + 4009c2: be 5c 0b 40 00 mov $0x400b5c,%esi + 4009c7: bf a0 11 60 00 mov $0x6011a0,%edi + 4009cc: e8 0f fe ff ff callq 4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 4009d1: 89 de mov %ebx,%esi + 4009d3: 48 89 c7 mov %rax,%rdi + 4009d6: e8 e5 fd ff ff callq 4007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt> + 4009db: be 10 08 40 00 mov $0x400810,%esi + 4009e0: 48 89 c7 mov %rax,%rdi + 4009e3: e8 18 fe ff ff callq 400800 <_ZNSolsEPFRSoS_E@plt> + 4009e8: 0f be 5d ed movsbl -0x13(%rbp),%ebx + 4009ec: be 61 0b 40 00 mov $0x400b61,%esi + 4009f1: bf a0 11 60 00 mov $0x6011a0,%edi + 4009f6: e8 e5 fd ff ff callq 4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 4009fb: 89 de mov %ebx,%esi + 4009fd: 48 89 c7 mov %rax,%rdi + 400a00: e8 bb fd ff ff callq 4007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt> + 400a05: be 10 08 40 00 mov $0x400810,%esi + 400a0a: 48 89 c7 mov %rax,%rdi + 400a0d: e8 ee fd ff ff callq 400800 <_ZNSolsEPFRSoS_E@plt> + 400a12: 0f be 5d ec movsbl -0x14(%rbp),%ebx + 400a16: be 66 0b 40 00 mov $0x400b66,%esi + 400a1b: bf a0 11 60 00 mov $0x6011a0,%edi + 400a20: e8 bb fd ff ff callq 4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 400a25: 89 de mov %ebx,%esi + 400a27: 48 89 c7 mov %rax,%rdi + 400a2a: e8 91 fd ff ff callq 4007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt> + 400a2f: be 10 08 40 00 mov $0x400810,%esi + 400a34: 48 89 c7 mov %rax,%rdi + 400a37: e8 c4 fd ff ff callq 400800 <_ZNSolsEPFRSoS_E@plt> + 400a3c: b8 00 00 00 00 mov $0x0,%eax + 400a41: 48 83 c4 28 add $0x28,%rsp + 400a45: 5b pop %rbx + 400a46: 5d pop %rbp + 400a47: c3 retq + +0000000000400a48 <_Z41__static_initialization_and_destruction_0ii>: + 400a48: 55 push %rbp + 400a49: 48 89 e5 mov %rsp,%rbp + 400a4c: 48 83 ec 10 sub $0x10,%rsp + 400a50: 89 7d fc mov %edi,-0x4(%rbp) + 400a53: 89 75 f8 mov %esi,-0x8(%rbp) + 400a56: 83 7d fc 01 cmpl $0x1,-0x4(%rbp) + 400a5a: 75 27 jne 400a83 <_Z41__static_initialization_and_destruction_0ii+0x3b> + 400a5c: 81 7d f8 ff ff 00 00 cmpl $0xffff,-0x8(%rbp) + 400a63: 75 1e jne 400a83 <_Z41__static_initialization_and_destruction_0ii+0x3b> + 400a65: bf b1 12 60 00 mov $0x6012b1,%edi + 400a6a: e8 21 fd ff ff callq 400790 <_ZNSt8ios_base4InitC1Ev@plt> + 400a6f: ba 28 0b 40 00 mov $0x400b28,%edx + 400a74: be b1 12 60 00 mov $0x6012b1,%esi + 400a79: bf d0 07 40 00 mov $0x4007d0,%edi + 400a7e: e8 2d fd ff ff callq 4007b0 <__cxa_atexit@plt> + 400a83: c9 leaveq + 400a84: c3 retq + +0000000000400a85 <_GLOBAL__sub_I_main>: + 400a85: 55 push %rbp + 400a86: 48 89 e5 mov %rsp,%rbp + 400a89: be ff ff 00 00 mov $0xffff,%esi + 400a8e: bf 01 00 00 00 mov $0x1,%edi + 400a93: e8 b0 ff ff ff callq 400a48 <_Z41__static_initialization_and_destruction_0ii> + 400a98: 5d pop %rbp + 400a99: c3 retq + 400a9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000400aa0 <__libc_csu_init>: + 400aa0: 41 57 push %r15 + 400aa2: 41 89 ff mov %edi,%r15d + 400aa5: 41 56 push %r14 + 400aa7: 49 89 f6 mov %rsi,%r14 + 400aaa: 41 55 push %r13 + 400aac: 49 89 d5 mov %rdx,%r13 + 400aaf: 41 54 push %r12 + 400ab1: 4c 8d 25 20 03 20 00 lea 0x200320(%rip),%r12 # 600dd8 <__frame_dummy_init_array_entry> + 400ab8: 55 push %rbp + 400ab9: 48 8d 2d 28 03 20 00 lea 0x200328(%rip),%rbp # 600de8 <__init_array_end> + 400ac0: 53 push %rbx + 400ac1: 4c 29 e5 sub %r12,%rbp + 400ac4: 31 db xor %ebx,%ebx + 400ac6: 48 c1 fd 03 sar $0x3,%rbp + 400aca: 48 83 ec 08 sub $0x8,%rsp + 400ace: e8 7d fc ff ff callq 400750 <_init> + 400ad3: 48 85 ed test %rbp,%rbp + 400ad6: 74 1e je 400af6 <__libc_csu_init+0x56> + 400ad8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 400adf: 00 + 400ae0: 4c 89 ea mov %r13,%rdx + 400ae3: 4c 89 f6 mov %r14,%rsi + 400ae6: 44 89 ff mov %r15d,%edi + 400ae9: 41 ff 14 dc callq *(%r12,%rbx,8) + 400aed: 48 83 c3 01 add $0x1,%rbx + 400af1: 48 39 eb cmp %rbp,%rbx + 400af4: 75 ea jne 400ae0 <__libc_csu_init+0x40> + 400af6: 48 83 c4 08 add $0x8,%rsp + 400afa: 5b pop %rbx + 400afb: 5d pop %rbp + 400afc: 41 5c pop %r12 + 400afe: 41 5d pop %r13 + 400b00: 41 5e pop %r14 + 400b02: 41 5f pop %r15 + 400b04: c3 retq + 400b05: 90 nop + 400b06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 400b0d: 00 00 00 + +0000000000400b10 <__libc_csu_fini>: + 400b10: f3 c3 repz retq + +Disassembly of section .fini: + +0000000000400b14 <_fini>: + 400b14: 48 83 ec 08 sub $0x8,%rsp + 400b18: 48 83 c4 08 add $0x8,%rsp + 400b1c: c3 retq +bash-4.2$ hexdump -C keyboardbo +00000000 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00 |.ELF............| +00000010 02 00 3e 00 01 00 00 00 20 08 40 00 00 00 00 00 |..>..... .@.....| +00000020 40 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 |@........F......| +00000030 00 00 00 00 40 00 38 00 09 00 40 00 23 00 22 00 |....@.8...@.#.".| +00000040 06 00 00 00 05 00 00 00 40 00 00 00 00 00 00 00 |........@.......| +00000050 40 00 40 00 00 00 00 00 40 00 40 00 00 00 00 00 |@.@.....@.@.....| +00000060 f8 01 00 00 00 00 00 00 f8 01 00 00 00 00 00 00 |................| +00000070 08 00 00 00 00 00 00 00 03 00 00 00 04 00 00 00 |................| +00000080 38 02 00 00 00 00 00 00 38 02 40 00 00 00 00 00 |8.......8.@.....| +00000090 38 02 40 00 00 00 00 00 1c 00 00 00 00 00 00 00 |8.@.............| +000000a0 1c 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 |................| +000000b0 01 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 |................| +000000c0 00 00 40 00 00 00 00 00 00 00 40 00 00 00 00 00 |..@.......@.....| +000000d0 ec 0c 00 00 00 00 00 00 ec 0c 00 00 00 00 00 00 |................| +000000e0 00 00 20 00 00 00 00 00 01 00 00 00 06 00 00 00 |.. .............| +000000f0 d8 0d 00 00 00 00 00 00 d8 0d 60 00 00 00 00 00 |..........`.....| +00000100 d8 0d 60 00 00 00 00 00 94 02 00 00 00 00 00 00 |..`.............| +00000110 e0 04 00 00 00 00 00 00 00 00 20 00 00 00 00 00 |.......... .....| +00000120 02 00 00 00 06 00 00 00 f8 0d 00 00 00 00 00 00 |................| +00000130 f8 0d 60 00 00 00 00 00 f8 0d 60 00 00 00 00 00 |..`.......`.....| +00000140 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 |................| +00000150 08 00 00 00 00 00 00 00 04 00 00 00 04 00 00 00 |................| +00000160 54 02 00 00 00 00 00 00 54 02 40 00 00 00 00 00 |T.......T.@.....| +00000170 54 02 40 00 00 00 00 00 44 00 00 00 00 00 00 00 |T.@.....D.......| +00000180 44 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 |D...............| +00000190 50 e5 74 64 04 00 00 00 6c 0b 00 00 00 00 00 00 |P.td....l.......| +000001a0 6c 0b 40 00 00 00 00 00 6c 0b 40 00 00 00 00 00 |l.@.....l.@.....| +000001b0 44 00 00 00 00 00 00 00 44 00 00 00 00 00 00 00 |D.......D.......| +000001c0 04 00 00 00 00 00 00 00 51 e5 74 64 06 00 00 00 |........Q.td....| +000001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +* +000001f0 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 |................| +00000200 52 e5 74 64 04 00 00 00 d8 0d 00 00 00 00 00 00 |R.td............| +00000210 d8 0d 60 00 00 00 00 00 d8 0d 60 00 00 00 00 00 |..`.......`.....| +00000220 28 02 00 00 00 00 00 00 28 02 00 00 00 00 00 00 |(.......(.......| +00000230 01 00 00 00 00 00 00 00 2f 6c 69 62 36 34 2f 6c |......../lib64/l| +00000240 64 2d 6c 69 6e 75 78 2d 78 38 36 2d 36 34 2e 73 |d-linux-x86-64.s| +00000250 6f 2e 32 00 04 00 00 00 10 00 00 00 01 00 00 00 |o.2.............| +00000260 47 4e 55 00 00 00 00 00 02 00 00 00 06 00 00 00 |GNU.............| +00000270 20 00 00 00 04 00 00 00 14 00 00 00 03 00 00 00 | ...............| +00000280 47 4e 55 00 06 9e 77 de 92 5d 71 9c 69 54 14 1d |GNU...w..]q.iT..| +00000290 01 12 9f b2 85 47 07 13 03 00 00 00 09 00 00 00 |.....G..........| +000002a0 01 00 00 00 06 00 00 00 00 00 10 02 01 01 14 00 |................| +000002b0 09 00 00 00 0a 00 00 00 0b 00 00 00 73 96 07 02 |............s...| +000002c0 21 fd f4 09 28 45 d5 4c 15 98 0c 43 00 00 00 00 |!...(E.L...C....| +000002d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000002e0 00 00 00 00 00 00 00 00 10 00 00 00 20 00 00 00 |............ ...| +000002f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000300 40 01 00 00 12 00 00 00 00 00 00 00 00 00 00 00 |@...............| +00000310 00 00 00 00 00 00 00 00 87 01 00 00 12 00 00 00 |................| +00000320 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000330 7a 01 00 00 12 00 00 00 00 00 00 00 00 00 00 00 |z...............| +00000340 00 00 00 00 00 00 00 00 f9 00 00 00 12 00 00 00 |................| +00000350 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000360 4a 00 00 00 12 00 00 00 00 00 00 00 00 00 00 00 |J...............| +00000370 00 00 00 00 00 00 00 00 bd 00 00 00 12 00 00 00 |................| +00000380 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00000390 2f 01 00 00 12 00 00 00 00 00 00 00 00 00 00 00 |/...............| +000003a0 00 00 00 00 00 00 00 00 37 00 00 00 11 00 19 00 |........7.......| +000003b0 80 10 60 00 00 00 00 00 18 01 00 00 00 00 00 00 |..`.............| +000003c0 82 00 00 00 12 00 00 00 10 08 40 00 00 00 00 00 |..........@.....| +000003d0 00 00 00 00 00 00 00 00 1f 00 00 00 12 00 00 00 |................| +000003e0 d0 07 40 00 00 00 00 00 00 00 00 00 00 00 00 00 |..@.............| +000003f0 40 00 00 00 11 00 19 00 a0 11 60 00 00 00 00 00 |@.........`.....| +00000400 10 01 00 00 00 00 00 00 00 6c 69 62 73 74 64 63 |.........libstdc| +00000410 2b 2b 2e 73 6f 2e 36 00 5f 5f 67 6d 6f 6e 5f 73 |++.so.6.__gmon_s| +00000420 74 61 72 74 5f 5f 00 5f 5a 4e 53 74 38 69 6f 73 |tart__._ZNSt8ios| +00000430 5f 62 61 73 65 34 49 6e 69 74 44 31 45 76 00 5f |_base4InitD1Ev._| +00000440 5a 53 74 33 63 69 6e 00 5f 5a 53 74 34 63 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31 33 |_traitsIcEERSt13| +00000520 62 61 73 69 63 5f 6f 73 74 72 65 61 6d 49 63 54 |basic_ostreamIcT| +00000530 5f 45 53 35 5f 63 00 5f 5a 4e 53 6f 6c 73 45 50 |_ES5_c._ZNSolsEP| +00000540 46 52 53 6f 53 5f 45 00 5f 5a 4e 53 74 38 69 6f |FRSoS_E._ZNSt8io| +00000550 73 5f 62 61 73 65 34 49 6e 69 74 43 31 45 76 00 |s_base4InitC1Ev.| +00000560 6c 69 62 6d 2e 73 6f 2e 36 00 6c 69 62 67 63 63 |libm.so.6.libgcc| +00000570 5f 73 2e 73 6f 2e 31 00 6c 69 62 63 2e 73 6f 2e |_s.so.1.libc.so.| +00000580 36 00 5f 5f 63 78 61 5f 61 74 65 78 69 74 00 5f |6.__cxa_atexit._| +00000590 5f 6c 69 62 63 5f 73 74 61 72 74 5f 6d 61 69 6e |_libc_start_main| +000005a0 00 47 4c 49 42 43 5f 32 2e 32 2e 35 00 47 4c 49 |.GLIBC_2.2.5.GLI| +000005b0 42 43 58 58 5f 33 2e 34 00 00 00 00 00 00 02 00 |BCXX_3.4........| +000005c0 03 00 03 00 02 00 02 00 02 00 02 00 02 00 02 00 |................| +000005d0 02 00 02 00 00 00 00 00 01 00 01 00 70 01 00 00 |............p...| +000005e0 10 00 00 00 20 00 00 00 75 1a 69 09 00 00 03 00 |.... ...u.i.....| +000005f0 99 01 00 00 00 00 00 00 01 00 01 00 01 00 00 00 |................| +00000600 10 00 00 00 00 00 00 00 74 29 92 08 00 00 02 00 |........t)......| +00000610 a5 01 00 00 00 00 00 00 f8 0f 60 00 00 00 00 00 |..........`.....| +00000620 06 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 |................| +00000630 80 10 60 00 00 00 00 00 05 00 00 00 09 00 00 00 |..`.............| +00000640 00 00 00 00 00 00 00 00 a0 11 60 00 00 00 00 00 |..........`.....| +00000650 05 00 00 00 0c 00 00 00 00 00 00 00 00 00 00 00 |................| +00000660 18 10 60 00 00 00 00 00 07 00 00 00 01 00 00 00 |..`.............| +00000670 00 00 00 00 00 00 00 00 20 10 60 00 00 00 00 00 |........ .`.....| +00000680 07 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 |................| +00000690 28 10 60 00 00 00 00 00 07 00 00 00 03 00 00 00 |(.`.............| +000006a0 00 00 00 00 00 00 00 00 30 10 60 00 00 00 00 00 |........0.`.....| +000006b0 07 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 |................| +000006c0 38 10 60 00 00 00 00 00 07 00 00 00 05 00 00 00 |8.`.............| +000006d0 00 00 00 00 00 00 00 00 40 10 60 00 00 00 00 00 |........@.`.....| +000006e0 07 00 00 00 0b 00 00 00 00 00 00 00 00 00 00 00 |................| +000006f0 48 10 60 00 00 00 00 00 07 00 00 00 06 00 00 00 |H.`.............| +00000700 00 00 00 00 00 00 00 00 50 10 60 00 00 00 00 00 |........P.`.....| +00000710 07 00 00 00 07 00 00 00 00 00 00 00 00 00 00 00 |................| +00000720 58 10 60 00 00 00 00 00 07 00 00 00 08 00 00 00 |X.`.............| +00000730 00 00 00 00 00 00 00 00 60 10 60 00 00 00 00 00 |........`.`.....| +00000740 07 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 |................| +00000750 48 83 ec 08 48 8b 05 9d 08 20 00 48 85 c0 74 05 |H...H.... .H..t.| +00000760 e8 1b 00 00 00 48 83 c4 08 c3 00 00 00 00 00 00 |.....H..........| +00000770 ff 35 92 08 20 00 ff 25 94 08 20 00 0f 1f 40 00 |.5.. ..%.. ...@.| +00000780 ff 25 92 08 20 00 68 00 00 00 00 e9 e0 ff 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00 00 00 |................| +00004c30 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004c40 fa 00 00 00 08 00 00 00 03 00 00 00 00 00 00 00 |................| +00004c50 80 10 60 00 00 00 00 00 6c 10 00 00 00 00 00 00 |..`.....l.......| +00004c60 38 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |8...............| +00004c70 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ...............| +00004c80 ff 00 00 00 01 00 00 00 30 00 00 00 00 00 00 00 |........0.......| +00004c90 00 00 00 00 00 00 00 00 6c 10 00 00 00 00 00 00 |........l.......| +00004ca0 2d 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |-...............| +00004cb0 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 |................| +00004cc0 08 01 00 00 01 00 00 00 00 00 00 00 00 00 00 00 |................| +00004cd0 00 00 00 00 00 00 00 00 99 10 00 00 00 00 00 00 |................| +00004ce0 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |0...............| +00004cf0 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004d00 17 01 00 00 01 00 00 00 00 00 00 00 00 00 00 00 |................| +00004d10 00 00 00 00 00 00 00 00 c9 10 00 00 00 00 00 00 |................| +00004d20 ad 15 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004d30 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004d40 23 01 00 00 01 00 00 00 00 00 00 00 00 00 00 00 |#...............| +00004d50 00 00 00 00 00 00 00 00 76 26 00 00 00 00 00 00 |........v&......| +00004d60 db 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004d70 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004d80 31 01 00 00 01 00 00 00 00 00 00 00 00 00 00 00 |1...............| +00004d90 00 00 00 00 00 00 00 00 51 2a 00 00 00 00 00 00 |........Q*......| +00004da0 5c 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |\...............| +00004db0 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004dc0 3d 01 00 00 01 00 00 00 30 00 00 00 00 00 00 00 |=.......0.......| +00004dd0 00 00 00 00 00 00 00 00 ad 2c 00 00 00 00 00 00 |.........,......| +00004de0 ac 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004df0 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 |................| +00004e00 01 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 |................| +00004e10 00 00 00 00 00 00 00 00 60 39 00 00 00 00 00 00 |........`9......| +00004e20 80 07 00 00 00 00 00 00 21 00 00 00 36 00 00 00 |........!...6...| +00004e30 08 00 00 00 00 00 00 00 18 00 00 00 00 00 00 00 |................| +00004e40 09 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 |................| +00004e50 00 00 00 00 00 00 00 00 e0 40 00 00 00 00 00 00 |.........@......| +00004e60 d5 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004e70 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004e80 11 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 |................| +00004e90 00 00 00 00 00 00 00 00 b5 44 00 00 00 00 00 00 |.........D......| +00004ea0 48 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |H...............| +00004eb0 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00004ec0 +bash-4.2$ cat keyboardbo.cpp + +#include + +using namespace std; + +int main( int argc, char* argv[ ] ) +{ + char a = 'A'; + char b = 'B'; + char buffer[4]; + char c = 'C'; + char d = 'D'; + + cout << "Enter up to 4 characters now: " << endl; + cin >> buffer; + cout << endl; + + cout << "buff = " << buffer << endl; + cout << "a = " << a << endl; + cout << "b = " << b << endl; + cout << "c = " << c << endl; + cout << "d = " << d << endl; + + return 0; +} + + +bash-4.2$ cat input.txt +AAAABBBBCCCCDDDDEEEEFFFFGGGGHHHH +bash-4.2$ ./keyboardbo < input.txt +Enter up to 4 characters now: + +buff = AAAABBBBCCCCDDDDEEEEFFFFGGGGHHHH +a = D +b = D +c = D +d = D +bash-4.2$ gdb ./keyboardbo +[?1034hGNU gdb (GDB) Red Hat Enterprise Linux 7.6.1-120.el7 +Copyright (C) 2013 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +For bug reporting instructions, please see: +... +Reading symbols from /home/student/anw0044/CPE455/lab02/keyboardbo...done. +(gdb) break maoin +Breakpoint 1 at 0x40091d: file keyboardbo.cpp, line 8. +(gdb) info breakpoints +Num Type Disp Enb Address What +1 breakpoint keep y 0x000000000040091d in main(int, char**) at keyboardbo.cpp:8 +(gdb) run < input.txt +Starting program: /home/student/anw0044/CPE455/lab02/./keyboardbo < input.txt + +Breakpoint 1, main (argc=1, argv=0x7fffffffe168) at keyboardbo.cpp:8 +8 char a = 'A'; +Missing separate debuginfos, use: debuginfo-install glibc-2.17-325.el7_9.x86_64 libgcc-4.8.5-44.el7.x86_64 libstdc++-4.8.5-44.el7.x86_64 +(gdb) info locals +a = 0 '\000' +buffer = "\240\n@" +c = 0 '\000' +b = 0 '\000' +d = 0 '\000' +(gdb) info args +argc = 1 +argv = 0x7fffffffe168 +(gdb) (gdb) (gdb) (gdb)  (gdb) (gdb) info registers +rax 0x40090d 4196621 +rbx 0x0 0 +rcx 0x60 96 +rdx 0x7fffffffe178 140737488347512 +rsi 0x7fffffffe168 140737488347496 +rdi 0x1 1 +rbp 0x7fffffffe080 0x7fffffffe080 +rsp 0x7fffffffe050 0x7fffffffe050 +r8 0x7ffff75b5e80 140737343348352 +r9 0x0 0 +r10 0x7fffffffda60 140737488345696 +r11 0x7ffff7226f30 140737339617072 +r12 0x400820 4196384 +r13 0x7fffffffe160 140737488347488 +r14 0x0 0 +r15 0x0 0 +rip 0x40091d 0x40091d +eflags 0x206 [ PF IF ] +---Type to continue, or q to quit--- +cs 0x33 51 +ss 0x2b 43 +ds 0x0 0 +es 0x0 0 +fs 0x0 0 +gs 0x0 0 +(gdb) info files +Symbols from "/home/student/anw0044/CPE455/lab02/keyboardbo". +Unix child process: + Using the running image of child process 14050. + While running this, GDB does not access memory from... +Local exec file: + `/home/student/anw0044/CPE455/lab02/keyboardbo', file type elf64-x86-64. + Entry point: 0x400820 + 0x0000000000400238 - 0x0000000000400254 is .interp + 0x0000000000400254 - 0x0000000000400274 is .note.ABI-tag + 0x0000000000400274 - 0x0000000000400298 is .note.gnu.build-id + 0x0000000000400298 - 0x00000000004002cc is .gnu.hash + 0x00000000004002d0 - 0x0000000000400408 is .dynsym + 0x0000000000400408 - 0x00000000004005b9 is .dynstr + 0x00000000004005ba - 0x00000000004005d4 is .gnu.version + 0x00000000004005d8 - 0x0000000000400618 is .gnu.version_r + 0x0000000000400618 - 0x0000000000400660 is .rela.dyn + 0x0000000000400660 - 0x0000000000400750 is .rela.plt + 0x0000000000400750 - 0x000000000040076a is .init + 0x0000000000400770 - 0x0000000000400820 is .plt + 0x0000000000400820 - 0x0000000000400b12 is .text + 0x0000000000400b14 - 0x0000000000400b1d is .fini + 0x0000000000400b20 - 0x0000000000400b6b is .rodata +---Type to continue, or q to quit--- + 0x0000000000400b6c - 0x0000000000400bb0 is .eh_frame_hdr + 0x0000000000400bb0 - 0x0000000000400cec is .eh_frame + 0x0000000000600dd8 - 0x0000000000600de8 is .init_array + 0x0000000000600de8 - 0x0000000000600df0 is .fini_array + 0x0000000000600df0 - 0x0000000000600df8 is .jcr + 0x0000000000600df8 - 0x0000000000600ff8 is .dynamic + 0x0000000000600ff8 - 0x0000000000601000 is .got + 0x0000000000601000 - 0x0000000000601068 is .got.plt + 0x0000000000601068 - 0x000000000060106c is .data + 0x0000000000601080 - 0x00000000006012b8 is .bss + 0x00007ffff7ddb1c8 - 0x00007ffff7ddb1ec is .note.gnu.build-id in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddb1f0 - 0x00007ffff7ddb2ac is .hash in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddb2b0 - 0x00007ffff7ddb390 is .gnu.hash in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddb390 - 0x00007ffff7ddb630 is .dynsym in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddb630 - 0x00007ffff7ddb7cf is .dynstr in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddb7d0 - 0x00007ffff7ddb808 is .gnu.version in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddb808 - 0x00007ffff7ddb8ac is .gnu.version_d in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddb8b0 - 0x00007ffff7ddb9e8 is .rela.dyn in /lib64/ld-linux-x86-64.so.2 +---Type to continue, or q to quit--- + 0x00007ffff7ddb9e8 - 0x00007ffff7ddba78 is .rela.plt in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddba80 - 0x00007ffff7ddbaf0 is .plt in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ddbaf0 - 0x00007ffff7df7060 is .text in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7df7060 - 0x00007ffff7df9da0 is .rodata in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7df9da0 - 0x00007ffff7df9da1 is .stapsdt.base in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7df9da4 - 0x00007ffff7dfa418 is .eh_frame_hdr in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7dfa418 - 0x00007ffff7dfc960 is .eh_frame in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ffcb40 - 0x00007ffff7ffcdfc is .data.rel.ro in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ffce00 - 0x00007ffff7ffcf90 is .dynamic in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ffcf90 - 0x00007ffff7ffcff0 is .got in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ffd000 - 0x00007ffff7ffdf78 is .data in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ffdf80 - 0x00007ffff7ffe150 is .bss in /lib64/ld-linux-x86-64.so.2 + 0x00007ffff7ad3200 - 0x00007ffff7ad3224 is .note.gnu.build-id in /lib64/libstdc++.so.6 + 0x00007ffff7ad3228 - 0x00007ffff7ad8bf4 is .gnu.hash in /lib64/libstdc++.so.6 + 0x00007ffff7ad8bf8 - 0x00007ffff7aef380 is .dynsym in /lib64/libstdc++.so.6 + 0x00007ffff7aef380 - 0x00007ffff7b16791 is .dynstr in /lib64/libstdc++.so.6 + 0x00007ffff7b16792 - 0x00007ffff7b18588 is .gnu.version in /lib64/libstdc++.so.6 + 0x00007ffff7b18588 - 0x00007ffff7b189a0 is .gnu.version_d in /lib64/libstdc++.so.6 +---Type to continue, or q to quit--- + 0x00007ffff7b189a0 - 0x00007ffff7b18a80 is .gnu.version_r in /lib64/libstdc++.so.6 + 0x00007ffff7b18a80 - 0x00007ffff7b27db0 is .rela.dyn in /lib64/libstdc++.so.6 + 0x00007ffff7b27db0 - 0x00007ffff7b2bb78 is .rela.plt in /lib64/libstdc++.so.6 + 0x00007ffff7b2bb78 - 0x00007ffff7b2bb92 is .init in /lib64/libstdc++.so.6 + 0x00007ffff7b2bba0 - 0x00007ffff7b2e4e0 is .plt in /lib64/libstdc++.so.6 + 0x00007ffff7b2e4e0 - 0x00007ffff7b9559a is .text in /lib64/libstdc++.so.6 + 0x00007ffff7b9559c - 0x00007ffff7b955a5 is .fini in /lib64/libstdc++.so.6 + 0x00007ffff7b955c0 - 0x00007ffff7b9bb90 is .rodata in /lib64/libstdc++.so.6 + 0x00007ffff7b9bb90 - 0x00007ffff7b9bb91 is .stapsdt.base in /lib64/libstdc++.so.6 + 0x00007ffff7b9bb94 - 0x00007ffff7ba0628 is .eh_frame_hdr in /lib64/libstdc++.so.6 + 0x00007ffff7ba0628 - 0x00007ffff7bb778c is .eh_frame in /lib64/libstdc++.so.6 + 0x00007ffff7bb778c - 0x00007ffff7bbbdeb is .gcc_except_table in /lib64/libstdc++.so.6 + 0x00007ffff7dbcd10 - 0x00007ffff7dbcd30 is .tbss in /lib64/libstdc++.so.6 + 0x00007ffff7dbcd10 - 0x00007ffff7dbcd50 is .init_array in /lib64/libstdc++.so.6 + 0x00007ffff7dbcd50 - 0x00007ffff7dbcd58 is .fini_array in /lib64/libstdc++.so.6 + 0x00007ffff7dbcd58 - 0x00007ffff7dbcd60 is .jcr in /lib64/libstdc++.so.6 + 0x00007ffff7dbcd60 - 0x00007ffff7dc34d8 is .data.rel.ro in /lib64/libstdc++.so.6 + 0x00007ffff7dc34d8 - 0x00007ffff7dc36f8 is .dynamic in /lib64/libstdc++.so.6 +---Type to continue, or q to quit--- + 0x00007ffff7dc36f8 - 0x00007ffff7dc3fe8 is .got in /lib64/libstdc++.so.6 + 0x00007ffff7dc4000 - 0x00007ffff7dc54b0 is .got.plt in /lib64/libstdc++.so.6 + 0x00007ffff7dc54c0 - 0x00007ffff7dc57b8 is .data in /lib64/libstdc++.so.6 + 0x00007ffff7dc57c0 - 0x00007ffff7dda420 is .bss in /lib64/libstdc++.so.6 + 0x00007ffff77d11c8 - 0x00007ffff77d11ec is .note.gnu.build-id in /lib64/libm.so.6 + 0x00007ffff77d11ec - 0x00007ffff77d120c is .note.ABI-tag in /lib64/libm.so.6 + 0x00007ffff77d1210 - 0x00007ffff77d2678 is .gnu.hash in /lib64/libm.so.6 + 0x00007ffff77d2678 - 0x00007ffff77d4d78 is .dynsym in /lib64/libm.so.6 + 0x00007ffff77d4d78 - 0x00007ffff77d5a18 is .dynstr in /lib64/libm.so.6 + 0x00007ffff77d5a18 - 0x00007ffff77d5d58 is .gnu.version in /lib64/libm.so.6 + 0x00007ffff77d5d58 - 0x00007ffff77d5dd8 is .gnu.version_d in /lib64/libm.so.6 + 0x00007ffff77d5dd8 - 0x00007ffff77d5e28 is .gnu.version_r in /lib64/libm.so.6 + 0x00007ffff77d5e28 - 0x00007ffff77d5f60 is .rela.dyn in /lib64/libm.so.6 + 0x00007ffff77d5f60 - 0x00007ffff77d61a0 is .rela.plt in /lib64/libm.so.6 + 0x00007ffff77d61a0 - 0x00007ffff77d61ba is .init in /lib64/libm.so.6 + 0x00007ffff77d61c0 - 0x00007ffff77d6350 is .plt in /lib64/libm.so.6 + 0x00007ffff77d6350 - 0x00007ffff7841336 is .text in /lib64/libm.so.6 + 0x00007ffff7841338 - 0x00007ffff7841341 is .fini in /lib64/libm.so.6 +---Type to continue, or q to quit--- + 0x00007ffff7841360 - 0x00007ffff78c96a4 is .rodata in /lib64/libm.so.6 + 0x00007ffff78c96a4 - 0x00007ffff78c96a5 is .stapsdt.base in /lib64/libm.so.6 + 0x00007ffff78c96a8 - 0x00007ffff78ca8d4 is .eh_frame_hdr in /lib64/libm.so.6 + 0x00007ffff78ca8d8 - 0x00007ffff78d04c4 is .eh_frame in /lib64/libm.so.6 + 0x00007ffff78d04c8 - 0x00007ffff78d1834 is .hash in /lib64/libm.so.6 + 0x00007ffff7ad1d60 - 0x00007ffff7ad1d68 is .init_array in /lib64/libm.so.6 + 0x00007ffff7ad1d68 - 0x00007ffff7ad1d70 is .fini_array in /lib64/libm.so.6 + 0x00007ffff7ad1d70 - 0x00007ffff7ad1d78 is .jcr in /lib64/libm.so.6 + 0x00007ffff7ad1d78 - 0x00007ffff7ad1d80 is .data.rel.ro in /lib64/libm.so.6 + 0x00007ffff7ad1d80 - 0x00007ffff7ad1fb0 is .dynamic in /lib64/libm.so.6 + 0x00007ffff7ad1fb0 - 0x00007ffff7ad2000 is .got in /lib64/libm.so.6 + 0x00007ffff7ad2000 - 0x00007ffff7ad20d8 is .got.plt in /lib64/libm.so.6 + 0x00007ffff7ad20d8 - 0x00007ffff7ad20e4 is .data in /lib64/libm.so.6 + 0x00007ffff7ad20f0 - 0x00007ffff7ad2138 is .bss in /lib64/libm.so.6 + 0x00007ffff75bb1c8 - 0x00007ffff75bb1ec is .note.gnu.build-id in /lib64/libgcc_s.so.1 + 0x00007ffff75bb1f0 - 0x00007ffff75bb6e0 is .gnu.hash in /lib64/libgcc_s.so.1 + 0x00007ffff75bb6e0 - 0x00007ffff75bc6e8 is .dynsym in /lib64/libgcc_s.so.1 + 0x00007ffff75bc6e8 - 0x00007ffff75bcf8e is .dynstr in /lib64/libgcc_s.so.1 +---Type to continue, or q to quit--- + 0x00007ffff75bcf8e - 0x00007ffff75bd0e4 is .gnu.version in /lib64/libgcc_s.so.1 + 0x00007ffff75bd0e8 - 0x00007ffff75bd288 is .gnu.version_d in /lib64/libgcc_s.so.1 + 0x00007ffff75bd288 - 0x00007ffff75bd2b8 is .gnu.version_r in /lib64/libgcc_s.so.1 + 0x00007ffff75bd2b8 - 0x00007ffff75bd3c0 is .rela.dyn in /lib64/libgcc_s.so.1 + 0x00007ffff75bd3c0 - 0x00007ffff75bd7e0 is .rela.plt in /lib64/libgcc_s.so.1 + 0x00007ffff75bd7e0 - 0x00007ffff75bd7fa is .init in /lib64/libgcc_s.so.1 + 0x00007ffff75bd800 - 0x00007ffff75bdad0 is .plt in /lib64/libgcc_s.so.1 + 0x00007ffff75bdad0 - 0x00007ffff75cd285 is .text in /lib64/libgcc_s.so.1 + 0x00007ffff75cd288 - 0x00007ffff75cd291 is .fini in /lib64/libgcc_s.so.1 + 0x00007ffff75cd2a0 - 0x00007ffff75cdd00 is .rodata in /lib64/libgcc_s.so.1 + 0x00007ffff75cdd00 - 0x00007ffff75cdd01 is .stapsdt.base in /lib64/libgcc_s.so.1 + 0x00007ffff75cdd04 - 0x00007ffff75ce248 is .eh_frame_hdr in /lib64/libgcc_s.so.1 + 0x00007ffff75ce248 - 0x00007ffff75cfc94 is .eh_frame in /lib64/libgcc_s.so.1 + 0x00007ffff77cfdb0 - 0x00007ffff77cfdc0 is .init_array in /lib64/libgcc_s.so.1 + 0x00007ffff77cfdc0 - 0x00007ffff77cfdc8 is .fini_array in /lib64/libgcc_s.so.1 + 0x00007ffff77cfdc8 - 0x00007ffff77cfdd0 is .jcr in /lib64/libgcc_s.so.1 + 0x00007ffff77cfdd0 - 0x00007ffff77cfdd8 is .data.rel.ro in /lib64/libgcc_s.so.1 + 0x00007ffff77cfdd8 - 0x00007ffff77cffc8 is .dynamic in /lib64/libgcc_s.so.1 +---Type to continue, or q to quit--- + 0x00007ffff77cffc8 - 0x00007ffff77d0000 is .got in /lib64/libgcc_s.so.1 + 0x00007ffff77d0000 - 0x00007ffff77d0178 is .got.plt in /lib64/libgcc_s.so.1 + 0x00007ffff77d0178 - 0x00007ffff77d0180 is .data in /lib64/libgcc_s.so.1 + 0x00007ffff77d0180 - 0x00007ffff77d0400 is .bss in /lib64/libgcc_s.so.1 + 0x00007ffff71ed270 - 0x00007ffff71ed294 is .note.gnu.build-id in /lib64/libc.so.6 + 0x00007ffff71ed294 - 0x00007ffff71ed2b4 is .note.ABI-tag in /lib64/libc.so.6 + 0x00007ffff71ed2b8 - 0x00007ffff71f0d84 is .gnu.hash in /lib64/libc.so.6 + 0x00007ffff71f0d88 - 0x00007ffff71fdfd0 is .dynsym in /lib64/libc.so.6 + 0x00007ffff71fdfd0 - 0x00007ffff7203acd is .dynstr in /lib64/libc.so.6 + 0x00007ffff7203ace - 0x00007ffff7204c54 is .gnu.version in /lib64/libc.so.6 + 0x00007ffff7204c58 - 0x00007ffff7204f60 is .gnu.version_d in /lib64/libc.so.6 + 0x00007ffff7204f60 - 0x00007ffff7204f90 is .gnu.version_r in /lib64/libc.so.6 + 0x00007ffff7204f90 - 0x00007ffff720c7d8 is .rela.dyn in /lib64/libc.so.6 + 0x00007ffff720c7d8 - 0x00007ffff720c910 is .rela.plt in /lib64/libc.so.6 + 0x00007ffff720c910 - 0x00007ffff720c9f0 is .plt in /lib64/libc.so.6 + 0x00007ffff720c9f0 - 0x00007ffff735cb6f is .text in /lib64/libc.so.6 + 0x00007ffff735cb70 - 0x00007ffff735e5d9 is __libc_freeres_fn in /lib64/libc.so.6 + 0x00007ffff735e5e0 - 0x00007ffff735e8e2 is __libc_thread_freeres_fn in /lib64/libc.so.6 +---Type to continue, or q to quit--- + 0x00007ffff735e900 - 0x00007ffff737bc50 is .rodata in /lib64/libc.so.6 + 0x00007ffff737bc50 - 0x00007ffff737bc51 is .stapsdt.base in /lib64/libc.so.6 + 0x00007ffff737bc60 - 0x00007ffff737bc7c is .interp in /lib64/libc.so.6 + 0x00007ffff737bc7c - 0x00007ffff7382778 is .eh_frame_hdr in /lib64/libc.so.6 + 0x00007ffff7382778 - 0x00007ffff73acc2c is .eh_frame in /lib64/libc.so.6 + 0x00007ffff73acc2c - 0x00007ffff73ad015 is .gcc_except_table in /lib64/libc.so.6 + 0x00007ffff73ad018 - 0x00007ffff73b0310 is .hash in /lib64/libc.so.6 + 0x00007ffff75b06f0 - 0x00007ffff75b0700 is .tdata in /lib64/libc.so.6 + 0x00007ffff75b0700 - 0x00007ffff75b0790 is .tbss in /lib64/libc.so.6 + 0x00007ffff75b0700 - 0x00007ffff75b0710 is .init_array in /lib64/libc.so.6 + 0x00007ffff75b0710 - 0x00007ffff75b0810 is __libc_subfreeres in /lib64/libc.so.6 + 0x00007ffff75b0810 - 0x00007ffff75b0818 is __libc_atexit in /lib64/libc.so.6 + 0x00007ffff75b0818 - 0x00007ffff75b0838 is __libc_thread_subfreeres in /lib64/libc.so.6 + 0x00007ffff75b0840 - 0x00007ffff75b15a8 is __libc_IO_vtables in /lib64/libc.so.6 + 0x00007ffff75b15c0 - 0x00007ffff75b3b60 is .data.rel.ro in /lib64/libc.so.6 + 0x00007ffff75b3b60 - 0x00007ffff75b3d50 is .dynamic in /lib64/libc.so.6 + 0x00007ffff75b3d50 - 0x00007ffff75b3ff0 is .got in /lib64/libc.so.6 + 0x00007ffff75b4000 - 0x00007ffff75b4080 is .got.plt in /lib64/libc.so.6 +---Type to continue, or q to quit--- + 0x00007ffff75b4080 - 0x00007ffff75b58a0 is .data in /lib64/libc.so.6 + 0x00007ffff75b58a0 - 0x00007ffff75ba200 is .bss in /lib64/libc.so.6 +(gdb) print &a +$1 = 0x7fffffffe06f "" +(gdb) priny t &b +$2 = 0x7fffffffe06e "" +(gdb) print &bc +$3 = 0x7fffffffe06d "" +(gdb) print &cdd +$4 = 0x7fffffffe06c "" +(gdb) print &dbuffp[0] +No symbol "buff" in current context. +(gdb) print &buff[0]e[0]r[0] +$5 = 0x7fffffffe060 "\240\n@" +(gdb) print &buffer[0]]1] +$6 = 0x7fffffffe061 "\n@" +(gdb) print &buffer[1]]2] +$7 = 0x7fffffffe062 "@" +(gdb) print &buffer[2]]3] +$8 = 0x7fffffffe063 "" +(gdb) print &buffer[3]]3]whatis a +type = char +(gdb) whatis abuffer +type = char [4] +(gdb) whatis arhhgc +type = int +(gdb) whatis argcv +type = char ** +(gdb) list +3 +4 using namespace std; +5 +6 int main( int argc, char* argv[ ] ) +7 { +8 char a = 'A'; +9 char b = 'B'; +10 char buffer[4]; +11 char c = 'C'; +12 char d = 'D'; +(gdb) dissassemble main +Dump of assembler code for function main(int, char**): + 0x000000000040090d <+0>: push %rbp + 0x000000000040090e <+1>: mov %rsp,%rbp + 0x0000000000400911 <+4>: push %rbx + 0x0000000000400912 <+5>: sub $0x28,%rsp + 0x0000000000400916 <+9>: mov %edi,-0x24(%rbp) + 0x0000000000400919 <+12>: mov %rsi,-0x30(%rbp) +=> 0x000000000040091d <+16>: movb $0x41,-0x11(%rbp) + 0x0000000000400921 <+20>: movb $0x42,-0x12(%rbp) + 0x0000000000400925 <+24>: movb $0x43,-0x13(%rbp) + 0x0000000000400929 <+28>: movb $0x44,-0x14(%rbp) + 0x000000000040092d <+32>: mov $0x400b30,%esi + 0x0000000000400932 <+37>: mov $0x6011a0,%edi + 0x0000000000400937 <+42>: callq 0x4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 0x000000000040093c <+47>: mov $0x400810,%esi + 0x0000000000400941 <+52>: mov %rax,%rdi + 0x0000000000400944 <+55>: callq 0x400800 <_ZNSolsEPFRSoS_E@plt> + 0x0000000000400949 <+60>: lea -0x20(%rbp),%rax +---Type to continue, or q to quit--- + 0x000000000040094d <+64>: mov %rax,%rsi + 0x0000000000400950 <+67>: mov $0x601080,%edi + 0x0000000000400955 <+72>: callq 0x4007f0 <_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_@plt> + 0x000000000040095a <+77>: mov $0x400810,%esi + 0x000000000040095f <+82>: mov $0x6011a0,%edi + 0x0000000000400964 <+87>: callq 0x400800 <_ZNSolsEPFRSoS_E@plt> + 0x0000000000400969 <+92>: mov $0x400b4f,%esi + 0x000000000040096e <+97>: mov $0x6011a0,%edi + 0x0000000000400973 <+102>: callq 0x4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 0x0000000000400978 <+107>: lea -0x20(%rbp),%rdx + 0x000000000040097c <+111>: mov %rdx,%rsi + 0x000000000040097f <+114>: mov %rax,%rdi + 0x0000000000400982 <+117>: callq 0x4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 0x0000000000400987 <+122>: mov $0x400810,%esi + 0x000000000040098c <+127>: mov %rax,%rdi + 0x000000000040098f <+130>: callq 0x400800 <_ZNSolsEPFRSoS_E@plt> + 0x0000000000400994 <+135>: movsbl -0x11(%rbp),%ebx + 0x0000000000400998 <+139>: mov $0x400b57,%esi +---Type to continue, or q to quit--- + 0x000000000040099d <+144>: mov $0x6011a0,%edi + 0x00000000004009a2 <+149>: callq 0x4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 0x00000000004009a7 <+154>: mov %ebx,%esi + 0x00000000004009a9 <+156>: mov %rax,%rdi + 0x00000000004009ac <+159>: callq 0x4007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt> + 0x00000000004009b1 <+164>: mov $0x400810,%esi + 0x00000000004009b6 <+169>: mov %rax,%rdi + 0x00000000004009b9 <+172>: callq 0x400800 <_ZNSolsEPFRSoS_E@plt> + 0x00000000004009be <+177>: movsbl -0x12(%rbp),%ebx + 0x00000000004009c2 <+181>: mov $0x400b5c,%esi + 0x00000000004009c7 <+186>: mov $0x6011a0,%edi + 0x00000000004009cc <+191>: callq 0x4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 0x00000000004009d1 <+196>: mov %ebx,%esi + 0x00000000004009d3 <+198>: mov %rax,%rdi + 0x00000000004009d6 <+201>: callq 0x4007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt> + 0x00000000004009db <+206>: mov $0x400810,%esi + 0x00000000004009e0 <+211>: mov %rax,%rdi + 0x00000000004009e3 <+214>: callq 0x400800 <_ZNSolsEPFRSoS_E@plt> +---Type to continue, or q to quit--- + 0x00000000004009e8 <+219>: movsbl -0x13(%rbp),%ebx + 0x00000000004009ec <+223>: mov $0x400b61,%esi + 0x00000000004009f1 <+228>: mov $0x6011a0,%edi + 0x00000000004009f6 <+233>: callq 0x4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 0x00000000004009fb <+238>: mov %ebx,%esi + 0x00000000004009fd <+240>: mov %rax,%rdi + 0x0000000000400a00 <+243>: callq 0x4007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt> + 0x0000000000400a05 <+248>: mov $0x400810,%esi + 0x0000000000400a0a <+253>: mov %rax,%rdi + 0x0000000000400a0d <+256>: callq 0x400800 <_ZNSolsEPFRSoS_E@plt> + 0x0000000000400a12 <+261>: movsbl -0x14(%rbp),%ebx + 0x0000000000400a16 <+265>: mov $0x400b66,%esi + 0x0000000000400a1b <+270>: mov $0x6011a0,%edi + 0x0000000000400a20 <+275>: callq 0x4007e0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt> + 0x0000000000400a25 <+280>: mov %ebx,%esi + 0x0000000000400a27 <+282>: mov %rax,%rdi + 0x0000000000400a2a <+285>: callq 0x4007c0 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@plt> + 0x0000000000400a2f <+290>: mov $0x400810,%esi +---Type to continue, or q to quit--- + 0x0000000000400a34 <+295>: mov %rax,%rdi + 0x0000000000400a37 <+298>: callq 0x400800 <_ZNSolsEPFRSoS_E@plt> + 0x0000000000400a3c <+303>: mov $0x0,%eax + 0x0000000000400a41 <+308>: add $0x28,%rsp + 0x0000000000400a45 <+312>: pop %rbx + 0x0000000000400a46 <+313>: pop %rbp + 0x0000000000400a47 <+314>: retq +End of assembler dump. +(gdb) step +9 char b = 'B'; +(gdb) info locals +a = 65 'A' +buffer = "\240\n@" +c = 0 '\000' +b = 0 '\000' +d = 0 '\000' +(gdb) info locals step +11 char c = 'C'; +(gdb) stepinfo locals +a = 65 'A' +buffer = "\240\n@" +c = 0 '\000' +b = 66 'B' +d = 0 '\000' +(gdb) info locals step +12 char d = 'D'; +(gdb) stepinfo locals +a = 65 'A' +buffer = "\240\n@" +c = 67 'C' +b = 66 'B' +d = 0 '\000' +(gdb) info locals step +14 cout << "Enter up to 4 characters now: " << endl; +(gdb) stepinfo locals +a = 65 'A' +buffer = "\240\n@" +c = 67 'C' +b = 66 'B' +d = 68 'D' +(gdb) info locals step +Enter up to 4 characters now: +15 cin >> buffer; +(gdb) stepinfo locals +a = 65 'A' +buffer = "\240\n@" +c = 67 'C' +b = 66 'B' +d = 68 'D' +(gdb) info locals step +16 cout << endl; +(gdb) x/32xw &buffer +0x7fffffffe060: 0x41414141 0x42424242 0x43434343 0x44444444 +0x7fffffffe070: 0x45454545 0x46464646 0x47474747 0x48484848 +0x7fffffffe080: 0x00000000 0x00000000 0xf720f555 0x00007fff +0x7fffffffe090: 0x00000000 0x00000020 0xffffe168 0x00007fff +0x7fffffffe0a0: 0x00000000 0x00000001 0x0040090d 0x00000000 +0x7fffffffe0b0: 0x00000000 0x00000000 0x4c53bf81 0xec0ef21b +0x7fffffffe0c0: 0x00400820 0x00000000 0xffffe160 0x00007fff +0x7fffffffe0d0: 0x00000000 0x00000000 0x00000000 0x00000000 +(gdb) print buffer[0[] +$9 = 65 'A' +(gdb) \print buffer[0]&buffer[0] +$10 = 0x7fffffffe060 "AAAABBBBCCCCDDDDEEEEFFFFGGGGHHHH" +(gdb) print &buffer[0]]1] +$11 = 0x7fffffffe061 "AAABBBBCCCCDDDDEEEEFFFFGGGGHHHH" +(gdb) print &buffer[1]]2] +$12 = 0x7fffffffe062 "AABBBBCCCCDDDDEEEEFFFFGGGGHHHH" +(gdb) print &buffer[2]=]]]3] +$13 = 0x7fffffffe063 "ABBBBCCCCDDDDEEEEFFFFGGGGHHHH" +(gdb) print &buffer[3]=]]]4] +$14 = 0x7fffffffe064 "BBBBCCCCDDDDEEEEFFFFGGGGHHHH" +(gdb) print &buffer[4]3]2]1]0]buffer[0] x/32xw &buffer stepinfo locals stepx/32xw &buffer print buffer[0] +$15 = "AAAA" +(gdb) print buffer&buffer[4]3]2]1]0] = 'A' +$16 = 65 'A' +(gdb) print buffer[0] = 'A''B'[1@1 +$17 = 66 'B' +(gdb) print buffer[1] = 'B''3''D''C'[1@2 +$18 = 67 'C' +(gdb) print buffer[2] = 'C''D'[1@c[1@3 +$19 = 68 'D' +(gdb) print buffer[3] = 'D''D''E'[1@4 +$20 = 69 'E' +(gdb) x/32xw &buffer +0x7fffffffe060: 0x44434241 0x42424245 0x43434343 0x44444444 +0x7fffffffe070: 0x45454545 0x46464646 0x47474747 0x48484848 +0x7fffffffe080: 0x00000000 0x00000000 0xf720f555 0x00007fff +0x7fffffffe090: 0x00000000 0x00000020 0xffffe168 0x00007fff +0x7fffffffe0a0: 0x00000000 0x00000001 0x0040090d 0x00000000 +0x7fffffffe0b0: 0x00000000 0x00000000 0x4c53bf81 0xec0ef21b +0x7fffffffe0c0: 0x00400820 0x00000000 0xffffe160 0x00007fff +0x7fffffffe0d0: 0x00000000 0x00000000 0x00000000 0x00000000 +(gdb) (gdb) (gdb)  (gdb) (gdb) print &buffer[4] - &buffer[0] +$21 = 4 +(gdb) quit +A debugging session is active. + + Inferior 1 [process 14050] will be killed. + +Quit anyway? (y or n) y +bash-4.2$ exit +exit + +Script done on Thu 03 Mar 2022 10:06:31 AM CST diff --git a/CPE455/lab03/enigma b/CPE455/lab03/enigma new file mode 100755 index 0000000..fdf8774 Binary files /dev/null and b/CPE455/lab03/enigma differ diff --git a/CPE455/lab03/enigma.txt b/CPE455/lab03/enigma.txt new file mode 100644 index 0000000..f7b7f0b --- /dev/null +++ b/CPE455/lab03/enigma.txt @@ -0,0 +1,476 @@ +Script started on Thu 03 Mar 2022 10:33:44 AM CST +[?1034hbash-4.2$ chmod 755 ./enigma +bash-4.2$ lds =-l +total 16 +-rwxr-xr-x 1 anw0044 student 9888 Feb 28 2021 enigma +-rw------- 1 anw0044 student 0 Mar 3 10:33 enigma.txt +-rw------- 1 anw0044 student 3266 Mar 3 10:31 enigma.zip +bash-4.2$ file +file filefrag file-roller +bash-4.2$ file ./enigma +./enigma: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), dynamically linked (uses shared libs), for GNU/Linux 2.6.32, BuildID[sha1]=c7a8237c624481a50e6b5d824e109b71838dd18b, not stripped +bash-4.2$ readelf -a ./enigma +ELF Header: + Magic: 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00 + Class: ELF64 + Data: 2's complement, little endian + Version: 1 (current) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: EXEC (Executable file) + Machine: Advanced Micro Devices X86-64 + Version: 0x1 + Entry point address: 0x400520 + Start of program headers: 64 (bytes into file) + Start of section headers: 7648 (bytes into file) + Flags: 0x0 + Size of this header: 64 (bytes) + Size of program headers: 56 (bytes) + Number of program headers: 9 + Size of section headers: 64 (bytes) + Number of section headers: 35 + Section header string table index: 34 + +Section Headers: + [Nr] Name Type Address Offset + Size EntSize Flags Link Info Align + [ 0] NULL 0000000000000000 00000000 + 0000000000000000 0000000000000000 0 0 0 + [ 1] .interp PROGBITS 0000000000400238 00000238 + 000000000000001c 0000000000000000 A 0 0 1 + [ 2] .note.ABI-tag NOTE 0000000000400254 00000254 + 0000000000000020 0000000000000000 A 0 0 4 + [ 3] .note.gnu.build-i NOTE 0000000000400274 00000274 + 0000000000000024 0000000000000000 A 0 0 4 + [ 4] .gnu.hash GNU_HASH 0000000000400298 00000298 + 000000000000001c 0000000000000000 A 5 0 8 + [ 5] .dynsym DYNSYM 00000000004002b8 000002b8 + 00000000000000a8 0000000000000018 A 6 1 8 + [ 6] .dynstr STRTAB 0000000000400360 00000360 + 0000000000000053 0000000000000000 A 0 0 1 + [ 7] .gnu.version VERSYM 00000000004003b4 000003b4 + 000000000000000e 0000000000000002 A 5 0 2 + [ 8] .gnu.version_r VERNEED 00000000004003c8 000003c8 + 0000000000000020 0000000000000000 A 6 1 8 + [ 9] .rela.dyn RELA 00000000004003e8 000003e8 + 0000000000000018 0000000000000018 A 5 0 8 + [10] .rela.plt RELA 0000000000400400 00000400 + 0000000000000090 0000000000000018 AI 5 23 8 + [11] .init PROGBITS 0000000000400490 00000490 + 000000000000001a 0000000000000000 AX 0 0 4 + [12] .plt PROGBITS 00000000004004b0 000004b0 + 0000000000000070 0000000000000010 AX 0 0 16 + [13] .text PROGBITS 0000000000400520 00000520 + 0000000000000212 0000000000000000 AX 0 0 16 + [14] .fini PROGBITS 0000000000400734 00000734 + 0000000000000009 0000000000000000 AX 0 0 4 + [15] .rodata PROGBITS 0000000000400740 00000740 + 0000000000000042 0000000000000000 A 0 0 8 + [16] .eh_frame_hdr PROGBITS 0000000000400784 00000784 + 0000000000000034 0000000000000000 A 0 0 4 + [17] .eh_frame PROGBITS 00000000004007b8 000007b8 + 00000000000000f4 0000000000000000 A 0 0 8 + [18] .init_array INIT_ARRAY 0000000000600e10 00000e10 + 0000000000000008 0000000000000008 WA 0 0 8 + [19] .fini_array FINI_ARRAY 0000000000600e18 00000e18 + 0000000000000008 0000000000000008 WA 0 0 8 + [20] .jcr PROGBITS 0000000000600e20 00000e20 + 0000000000000008 0000000000000000 WA 0 0 8 + [21] .dynamic DYNAMIC 0000000000600e28 00000e28 + 00000000000001d0 0000000000000010 WA 6 0 8 + [22] .got PROGBITS 0000000000600ff8 00000ff8 + 0000000000000008 0000000000000008 WA 0 0 8 + [23] .got.plt PROGBITS 0000000000601000 00001000 + 0000000000000048 0000000000000008 WA 0 0 8 + [24] .data PROGBITS 0000000000601048 00001048 + 0000000000000018 0000000000000000 WA 0 0 8 + [25] .bss NOBITS 0000000000601060 00001060 + 0000000000000008 0000000000000000 WA 0 0 1 + [26] .comment PROGBITS 0000000000000000 00001060 + 000000000000005a 0000000000000001 MS 0 0 1 + [27] .debug_aranges PROGBITS 0000000000000000 000010ba + 0000000000000030 0000000000000000 0 0 1 + [28] .debug_info PROGBITS 0000000000000000 000010ea + 00000000000000f4 0000000000000000 0 0 1 + [29] .debug_abbrev PROGBITS 0000000000000000 000011de + 000000000000007e 0000000000000000 0 0 1 + [30] .debug_line PROGBITS 0000000000000000 0000125c + 000000000000005e 0000000000000000 0 0 1 + [31] .debug_str PROGBITS 0000000000000000 000012ba + 00000000000000ec 0000000000000001 MS 0 0 1 + [32] .symtab SYMTAB 0000000000000000 000013a8 + 00000000000006d8 0000000000000018 33 51 8 + [33] .strtab STRTAB 0000000000000000 00001a80 + 0000000000000216 0000000000000000 0 0 1 + [34] .shstrtab STRTAB 0000000000000000 00001c96 + 0000000000000148 0000000000000000 0 0 1 +Key to Flags: + W (write), A (alloc), X (execute), M (merge), S (strings), I (info), + L (link order), O (extra OS processing required), G (group), T (TLS), + C (compressed), x (unknown), o (OS specific), E (exclude), + l (large), p (processor specific) + +There are no section groups in this file. + +Program Headers: + Type Offset VirtAddr PhysAddr + FileSiz MemSiz Flags Align + PHDR 0x0000000000000040 0x0000000000400040 0x0000000000400040 + 0x00000000000001f8 0x00000000000001f8 R E 8 + INTERP 0x0000000000000238 0x0000000000400238 0x0000000000400238 + 0x000000000000001c 0x000000000000001c R 1 + [Requesting program interpreter: /lib64/ld-linux-x86-64.so.2] + LOAD 0x0000000000000000 0x0000000000400000 0x0000000000400000 + 0x00000000000008ac 0x00000000000008ac R E 200000 + LOAD 0x0000000000000e10 0x0000000000600e10 0x0000000000600e10 + 0x0000000000000250 0x0000000000000258 RW 200000 + DYNAMIC 0x0000000000000e28 0x0000000000600e28 0x0000000000600e28 + 0x00000000000001d0 0x00000000000001d0 RW 8 + NOTE 0x0000000000000254 0x0000000000400254 0x0000000000400254 + 0x0000000000000044 0x0000000000000044 R 4 + GNU_EH_FRAME 0x0000000000000784 0x0000000000400784 0x0000000000400784 + 0x0000000000000034 0x0000000000000034 R 4 + GNU_STACK 0x0000000000000000 0x0000000000000000 0x0000000000000000 + 0x0000000000000000 0x0000000000000000 RW 10 + GNU_RELRO 0x0000000000000e10 0x0000000000600e10 0x0000000000600e10 + 0x00000000000001f0 0x00000000000001f0 R 1 + + Section to Segment mapping: + Segment Sections... + 00 + 01 .interp + 02 .interp .note.ABI-tag .note.gnu.build-id .gnu.hash .dynsym .dynstr .gnu.version .gnu.version_r .rela.dyn .rela.plt .init .plt .text .fini .rodata .eh_frame_hdr .eh_frame + 03 .init_array .fini_array .jcr .dynamic .got .got.plt .data .bss + 04 .dynamic + 05 .note.ABI-tag .note.gnu.build-id + 06 .eh_frame_hdr + 07 + 08 .init_array .fini_array .jcr .dynamic .got + +Dynamic section at offset 0xe28 contains 24 entries: + Tag Type Name/Value + 0x0000000000000001 (NEEDED) Shared library: [libc.so.6] + 0x000000000000000c (INIT) 0x400490 + 0x000000000000000d (FINI) 0x400734 + 0x0000000000000019 (INIT_ARRAY) 0x600e10 + 0x000000000000001b (INIT_ARRAYSZ) 8 (bytes) + 0x000000000000001a (FINI_ARRAY) 0x600e18 + 0x000000000000001c (FINI_ARRAYSZ) 8 (bytes) + 0x000000006ffffef5 (GNU_HASH) 0x400298 + 0x0000000000000005 (STRTAB) 0x400360 + 0x0000000000000006 (SYMTAB) 0x4002b8 + 0x000000000000000a (STRSZ) 83 (bytes) + 0x000000000000000b (SYMENT) 24 (bytes) + 0x0000000000000015 (DEBUG) 0x0 + 0x0000000000000003 (PLTGOT) 0x601000 + 0x0000000000000002 (PLTRELSZ) 144 (bytes) + 0x0000000000000014 (PLTREL) RELA + 0x0000000000000017 (JMPREL) 0x400400 + 0x0000000000000007 (RELA) 0x4003e8 + 0x0000000000000008 (RELASZ) 24 (bytes) + 0x0000000000000009 (RELAENT) 24 (bytes) + 0x000000006ffffffe (VERNEED) 0x4003c8 + 0x000000006fffffff (VERNEEDNUM) 1 + 0x000000006ffffff0 (VERSYM) 0x4003b4 + 0x0000000000000000 (NULL) 0x0 + +Relocation section '.rela.dyn' at offset 0x3e8 contains 1 entries: + Offset Info Type Sym. Value Sym. Name + Addend +000000600ff8 000600000006 R_X86_64_GLOB_DAT 0000000000000000 __gmon_start__ + 0 + +Relocation section '.rela.plt' at offset 0x400 contains 6 entries: + Offset Info Type Sym. Value Sym. Name + Addend +000000601018 000100000007 R_X86_64_JUMP_SLO 0000000000000000 putchar@GLIBC_2.2.5 + 0 +000000601020 000200000007 R_X86_64_JUMP_SLO 0000000000000000 puts@GLIBC_2.2.5 + 0 +000000601028 000300000007 R_X86_64_JUMP_SLO 0000000000000000 printf@GLIBC_2.2.5 + 0 +000000601030 000400000007 R_X86_64_JUMP_SLO 0000000000000000 __libc_start_main@GLIBC_2.2.5 + 0 +000000601038 000500000007 R_X86_64_JUMP_SLO 0000000000000000 strcmp@GLIBC_2.2.5 + 0 +000000601040 000600000007 R_X86_64_JUMP_SLO 0000000000000000 __gmon_start__ + 0 + +The decoding of unwind sections for machine type Advanced Micro Devices X86-64 is not currently supported. + +Symbol table '.dynsym' contains 7 entries: + Num: Value Size Type Bind Vis Ndx Name + 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND + 1: 0000000000000000 0 FUNC GLOBAL DEFAULT UND putchar@GLIBC_2.2.5 (2) + 2: 0000000000000000 0 FUNC GLOBAL DEFAULT UND puts@GLIBC_2.2.5 (2) + 3: 0000000000000000 0 FUNC GLOBAL DEFAULT UND printf@GLIBC_2.2.5 (2) + 4: 0000000000000000 0 FUNC GLOBAL DEFAULT UND __libc_start_main@GLIBC_2.2.5 (2) + 5: 0000000000000000 0 FUNC GLOBAL DEFAULT UND strcmp@GLIBC_2.2.5 (2) + 6: 0000000000000000 0 NOTYPE WEAK DEFAULT UND __gmon_start__ + +Symbol table '.symtab' contains 73 entries: + Num: Value Size Type Bind Vis Ndx Name + 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND + 1: 0000000000400238 0 SECTION LOCAL DEFAULT 1 + 2: 0000000000400254 0 SECTION LOCAL DEFAULT 2 + 3: 0000000000400274 0 SECTION LOCAL DEFAULT 3 + 4: 0000000000400298 0 SECTION LOCAL DEFAULT 4 + 5: 00000000004002b8 0 SECTION LOCAL DEFAULT 5 + 6: 0000000000400360 0 SECTION LOCAL DEFAULT 6 + 7: 00000000004003b4 0 SECTION LOCAL DEFAULT 7 + 8: 00000000004003c8 0 SECTION LOCAL DEFAULT 8 + 9: 00000000004003e8 0 SECTION LOCAL DEFAULT 9 + 10: 0000000000400400 0 SECTION LOCAL DEFAULT 10 + 11: 0000000000400490 0 SECTION LOCAL DEFAULT 11 + 12: 00000000004004b0 0 SECTION LOCAL DEFAULT 12 + 13: 0000000000400520 0 SECTION LOCAL DEFAULT 13 + 14: 0000000000400734 0 SECTION LOCAL DEFAULT 14 + 15: 0000000000400740 0 SECTION LOCAL DEFAULT 15 + 16: 0000000000400784 0 SECTION LOCAL DEFAULT 16 + 17: 00000000004007b8 0 SECTION LOCAL DEFAULT 17 + 18: 0000000000600e10 0 SECTION LOCAL DEFAULT 18 + 19: 0000000000600e18 0 SECTION LOCAL DEFAULT 19 + 20: 0000000000600e20 0 SECTION LOCAL DEFAULT 20 + 21: 0000000000600e28 0 SECTION LOCAL DEFAULT 21 + 22: 0000000000600ff8 0 SECTION LOCAL DEFAULT 22 + 23: 0000000000601000 0 SECTION LOCAL DEFAULT 23 + 24: 0000000000601048 0 SECTION LOCAL DEFAULT 24 + 25: 0000000000601060 0 SECTION LOCAL DEFAULT 25 + 26: 0000000000000000 0 SECTION LOCAL DEFAULT 26 + 27: 0000000000000000 0 SECTION LOCAL DEFAULT 27 + 28: 0000000000000000 0 SECTION LOCAL DEFAULT 28 + 29: 0000000000000000 0 SECTION LOCAL DEFAULT 29 + 30: 0000000000000000 0 SECTION LOCAL DEFAULT 30 + 31: 0000000000000000 0 SECTION LOCAL DEFAULT 31 + 32: 0000000000000000 0 FILE LOCAL DEFAULT ABS crtstuff.c + 33: 0000000000600e20 0 OBJECT LOCAL DEFAULT 20 __JCR_LIST__ + 34: 0000000000400550 0 FUNC LOCAL DEFAULT 13 deregister_tm_clones + 35: 0000000000400580 0 FUNC LOCAL DEFAULT 13 register_tm_clones + 36: 00000000004005c0 0 FUNC LOCAL DEFAULT 13 __do_global_dtors_aux + 37: 0000000000601060 1 OBJECT LOCAL DEFAULT 25 completed.6355 + 38: 0000000000600e18 0 OBJECT LOCAL DEFAULT 19 __do_global_dtors_aux_fin + 39: 00000000004005e0 0 FUNC LOCAL DEFAULT 13 frame_dummy + 40: 0000000000600e10 0 OBJECT LOCAL DEFAULT 18 __frame_dummy_init_array_ + 41: 0000000000000000 0 FILE LOCAL DEFAULT ABS enigma.c + 42: 0000000000000000 0 FILE LOCAL DEFAULT ABS crtstuff.c + 43: 00000000004008a8 0 OBJECT LOCAL DEFAULT 17 __FRAME_END__ + 44: 0000000000600e20 0 OBJECT LOCAL DEFAULT 20 __JCR_END__ + 45: 0000000000000000 0 FILE LOCAL DEFAULT ABS + 46: 0000000000600e18 0 NOTYPE LOCAL DEFAULT 18 __init_array_end + 47: 0000000000600e28 0 OBJECT LOCAL DEFAULT 21 _DYNAMIC + 48: 0000000000600e10 0 NOTYPE LOCAL DEFAULT 18 __init_array_start + 49: 0000000000400784 0 NOTYPE LOCAL DEFAULT 16 __GNU_EH_FRAME_HDR + 50: 0000000000601000 0 OBJECT LOCAL DEFAULT 23 _GLOBAL_OFFSET_TABLE_ + 51: 0000000000400730 2 FUNC GLOBAL DEFAULT 13 __libc_csu_fini + 52: 0000000000000000 0 FUNC GLOBAL DEFAULT UND putchar@@GLIBC_2.2.5 + 53: 0000000000601048 0 NOTYPE WEAK DEFAULT 24 data_start + 54: 0000000000000000 0 FUNC GLOBAL DEFAULT UND puts@@GLIBC_2.2.5 + 55: 0000000000601060 0 NOTYPE GLOBAL DEFAULT 24 _edata + 56: 0000000000400734 0 FUNC GLOBAL DEFAULT 14 _fini + 57: 0000000000000000 0 FUNC GLOBAL DEFAULT UND printf@@GLIBC_2.2.5 + 58: 0000000000000000 0 FUNC GLOBAL DEFAULT UND __libc_start_main@@GLIBC_ + 59: 0000000000601048 0 NOTYPE GLOBAL DEFAULT 24 __data_start + 60: 0000000000000000 0 FUNC GLOBAL DEFAULT UND strcmp@@GLIBC_2.2.5 + 61: 0000000000000000 0 NOTYPE WEAK DEFAULT UND __gmon_start__ + 62: 0000000000400748 0 OBJECT GLOBAL HIDDEN 15 __dso_handle + 63: 0000000000400740 4 OBJECT GLOBAL DEFAULT 15 _IO_stdin_used + 64: 00000000004006c0 101 FUNC GLOBAL DEFAULT 13 __libc_csu_init + 65: 0000000000601068 0 NOTYPE GLOBAL DEFAULT 25 _end + 66: 0000000000400520 0 FUNC GLOBAL DEFAULT 13 _start + 67: 0000000000601060 0 NOTYPE GLOBAL DEFAULT 25 __bss_start + 68: 000000000040060d 175 FUNC GLOBAL DEFAULT 13 main + 69: 0000000000601050 8 OBJECT GLOBAL DEFAULT 24 USER + 70: 0000000000601060 0 OBJECT GLOBAL HIDDEN 24 __TMC_END__ + 71: 0000000000400490 0 FUNC GLOBAL DEFAULT 11 _init + 72: 0000000000601058 8 OBJECT GLOBAL DEFAULT 24 PASSWORD + +Version symbols section '.gnu.version' contains 7 entries: + Addr: 00000000004003b4 Offset: 0x0003b4 Link: 5 (.dynsym) + 000: 0 (*local*) 2 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) + 004: 2 (GLIBC_2.2.5) 2 (GLIBC_2.2.5) 0 (*local*) + +Version needs section '.gnu.version_r' contains 1 entries: + Addr: 0x00000000004003c8 Offset: 0x0003c8 Link: 6 (.dynstr) + 000000: Version: 1 File: libc.so.6 Cnt: 1 + 0x0010: Name: GLIBC_2.2.5 Flags: none Version: 2 + +Displaying notes found at file offset 0x00000254 with length 0x00000020: + Owner Data size Description + GNU 0x00000010 NT_GNU_ABI_TAG (ABI version tag) + OS: Linux, ABI: 2.6.32 + +Displaying notes found at file offset 0x00000274 with length 0x00000024: + Owner Data size Description + GNU 0x00000014 NT_GNU_BUILD_ID (unique build ID bitstring) + Build ID: c7a8237c624481a50e6b5d824e109b71838dd18b +bash-4.2$ bash-4.2$ bash-4.2$ nm ./enigma +0000000000601060 B __bss_start +0000000000601060 b completed.6355 +0000000000601048 D __data_start +0000000000601048 W data_start +0000000000400550 t deregister_tm_clones +00000000004005c0 t __do_global_dtors_aux +0000000000600e18 t __do_global_dtors_aux_fini_array_entry +0000000000400748 R __dso_handle +0000000000600e28 d _DYNAMIC +0000000000601060 D _edata +0000000000601068 B _end +0000000000400734 T _fini +00000000004005e0 t frame_dummy +0000000000600e10 t __frame_dummy_init_array_entry +00000000004008a8 r __FRAME_END__ +0000000000601000 d _GLOBAL_OFFSET_TABLE_ + w __gmon_start__ +0000000000400784 r __GNU_EH_FRAME_HDR +0000000000400490 T _init +0000000000600e18 t __init_array_end +0000000000600e10 t __init_array_start +0000000000400740 R _IO_stdin_used +0000000000600e20 d __JCR_END__ +0000000000600e20 d __JCR_LIST__ +0000000000400730 T __libc_csu_fini +00000000004006c0 T __libc_csu_init + U __libc_start_main@@GLIBC_2.2.5 +000000000040060d T main +0000000000601058 D PASSWORD + U printf@@GLIBC_2.2.5 + U putchar@@GLIBC_2.2.5 + U puts@@GLIBC_2.2.5 +0000000000400580 t register_tm_clones +0000000000400520 T _start + U strcmp@@GLIBC_2.2.5 +0000000000601060 D __TMC_END__ +0000000000601050 D USER +bash-4.2$ gdb ./enigma +[?1034hGNU gdb (GDB) Red Hat Enterprise Linux 7.6.1-120.el7 +Copyright (C) 2013 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +For bug reporting instructions, please see: +... +Reading symbols from /home/student/anw0044/CPE455/lab03/enigma...done. +(gdb) break main +Breakpoint 1 at 0x40061c: file enigma.c, line 12. +(gdb) \set args hello world +(gdb) run +Starting program: /home/student/anw0044/CPE455/lab03/./enigma hello world + +Breakpoint 1, main (argc=3, argv=0x7fffffffe158) at enigma.c:12 +12 enigma.c: No such file or directory. +Missing separate debuginfos, use: debuginfo-install glibc-2.17-325.el7_9.x86_64 +(gdb) print argc +$1 = 3 +(gdb) print argcv[0] +$2 = 0x7fffffffe524 "/home/student/anw0044/CPE455/lab03/./enigma" +(gdb) print argv[0]]1] +$3 = 0x7fffffffe550 "hello" +(gdb) print argv[1]]2] +$4 = 0x7fffffffe556 "world" +(gdb) print argv[2]]3] +$5 = 0x0 +(gdb) print USER +$6 = 0x400750 "CPEX55" +(gdb) print USERPASSWORD +$7 = 0x400757 "qwerty" +(gdb) info files +Symbols from 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0x00007ffff7dda200 is .bss in /lib64/libc.so.6 +(gdb) +(gdb) +(gdb) info args +argc = 3 +argv = 0x7fffffffe158 +(gdb) info locals +k = 0 +(gdb) imfnfo breakpoints  +Num Type Disp Enb Address What +1 breakpoint keep y 0x000000000040061c in main at enigma.c:12 + breakpoint already hit 1 time +(gdb) c +Continuing. +Authentication error +[Inferior 1 (process 19311) exited normally] +(gdb) quit +bash-4.2$ exit +exit + +Script done on Thu 03 Mar 2022 10:37:58 AM CST diff --git a/CPE455/lab03/enigma.zip b/CPE455/lab03/enigma.zip new file mode 100644 index 0000000..316b8b8 Binary files /dev/null and b/CPE455/lab03/enigma.zip differ diff --git a/CPE455/lab04/CPEX55-Lab04-SQL.pdf b/CPE455/lab04/CPEX55-Lab04-SQL.pdf new file mode 100644 index 0000000..224171a Binary files /dev/null and b/CPE455/lab04/CPEX55-Lab04-SQL.pdf differ diff --git a/CPE455/lab05/CPEX55-Lab05-Fuzzing.pdf b/CPE455/lab05/CPEX55-Lab05-Fuzzing.pdf new file mode 100644 index 0000000..8aedd97 Binary files /dev/null and b/CPE455/lab05/CPEX55-Lab05-Fuzzing.pdf differ diff --git a/CPE455/lab05/Makefile b/CPE455/lab05/Makefile new file mode 100644 index 0000000..13d5d9a --- /dev/null +++ b/CPE455/lab05/Makefile @@ -0,0 +1,8 @@ +CC := afl-gcc +CFLAGS := -Wno-unused-result + +all: crashy.c + $(CC) $(CFLAGS) -o crashy crashy.c + +clean: + rm crashy diff --git a/CPE455/lab05/crashy b/CPE455/lab05/crashy new file mode 100755 index 0000000..5af2c22 Binary files /dev/null and b/CPE455/lab05/crashy differ diff --git a/CPE455/lab05/crashy.c b/CPE455/lab05/crashy.c new file mode 100644 index 0000000..83b7fab --- /dev/null +++ b/CPE455/lab05/crashy.c @@ -0,0 +1,83 @@ +#include +#include +#include + +int main(int argc, char *argv[]) { + + FILE *fp; + unsigned int sz, len, ptr; + char *buffer; + char type; + char tmp_char; + int tmp_int; + char *tmp_string; + + if(argc != 2) { + fprintf(stderr, "Usage: %s \n", argv[0]); + return 1; + } + + fp = fopen(argv[1], "r"); + if(!fp) { + fprintf(stderr, "Failed to open '%s'\n", argv[1]); + return 1; + } + + fseek(fp, 0, SEEK_END); + sz = ftell(fp); + fseek(fp, 0, SEEK_SET); + + buffer = malloc(sz); + if(!buffer) { + fprintf(stderr, "Failed to allocate %d bytes of memory\n", sz); + return 1; + } + + fread(buffer, sizeof(char), sz, fp); + + ptr = 0; + while(ptr < sz) { + + type = buffer[ptr++]; + switch(type) { + + case '\x01': // integer + tmp_int = *(int *)(buffer + ptr); + ptr += sizeof(int); + printf("i: 0x%08x\n", tmp_int); + break; + + case '\x02': // char + tmp_char = buffer[ptr++]; + printf("c: 0x%02x\n", (unsigned char)tmp_char); + break; + + case '\x03': // string + len = *(int *)(buffer + ptr); + ptr += sizeof(int); + tmp_string = malloc(len); + if(!tmp_string) { + fprintf(stderr, "Failed to allocate %d bytes of memory\n", len); + return 1; + } + strcpy(tmp_string, (buffer + ptr)); + printf("s: %s\n", tmp_string); + ptr += len; + break; + + case '\x04': // comment + printf("#: %s\n", (buffer + ptr)); + while(*(buffer + ptr++) != '\x00'); + break; + + case '\xff': // END + return 0; + + default: + fprintf(stderr, "Unknown data type '%c'\n", type); + + } + + } + +} \ No newline at end of file diff --git a/CPE455/lab05/crashy.zip b/CPE455/lab05/crashy.zip new file mode 100644 index 0000000..53f136d Binary files /dev/null and b/CPE455/lab05/crashy.zip differ diff --git a/CPE455/lab05/inputFiles/example1 b/CPE455/lab05/inputFiles/example1 new file mode 100644 index 0000000..d3125c8 Binary files /dev/null and b/CPE455/lab05/inputFiles/example1 differ diff --git a/CPE455/lab05/inputFiles/example2 b/CPE455/lab05/inputFiles/example2 new file mode 100644 index 0000000..3ad05b2 Binary files /dev/null and b/CPE455/lab05/inputFiles/example2 differ diff --git a/CPE455/lab05/inputFiles/example3 b/CPE455/lab05/inputFiles/example3 new file mode 100644 index 0000000..151cde6 Binary files /dev/null and b/CPE455/lab05/inputFiles/example3 differ diff --git a/CPE455/lab05/inputFiles/example4 b/CPE455/lab05/inputFiles/example4 new file mode 100644 index 0000000..acd56ef --- /dev/null +++ b/CPE455/lab05/inputFiles/example4 @@ -0,0 +1 @@ +ABCÿ \ No newline at end of file diff --git a/CPE455/lab05/inputFiles/example5 b/CPE455/lab05/inputFiles/example5 new file mode 100644 index 0000000..8f022ba Binary files /dev/null and b/CPE455/lab05/inputFiles/example5 differ diff --git a/CPE455/lab06/.vscode/c_cpp_properties.json b/CPE455/lab06/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..dab2f43 --- /dev/null +++ b/CPE455/lab06/.vscode/c_cpp_properties.json @@ -0,0 +1,16 @@ +{ + "configurations": [ + { + "name": "linux-gcc-x64", + "includePath": [ + "${workspaceFolder}/**" + ], + "compilerPath": "/usr/bin/gcc", + "cStandard": "${default}", + "cppStandard": "${default}", + "intelliSenseMode": "linux-gcc-x64", + "compilerArgs": [] + } + ], + "version": 4 +} \ No newline at end of file diff --git a/CPE455/lab06/.vscode/launch.json b/CPE455/lab06/.vscode/launch.json new file mode 100644 index 0000000..083420c --- /dev/null +++ b/CPE455/lab06/.vscode/launch.json @@ -0,0 +1,28 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "C/C++ Runner: Debug Session", + "type": "cppdbg", + "request": "launch", + "args": [ + "" + ], + "stopAtEntry": false, + "cwd": "/home/student/anw0044/CPE455/lab06", + "environment": [], + "program": "/home/student/anw0044/CPE455/lab06/build/Debug/outDebug", + "internalConsoleOptions": "openOnSessionStart", + "MIMode": "gdb", + "miDebuggerPath": "/usr/bin/gdb", + "externalConsole": false, + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + } + ] +} \ No newline at end of file diff --git a/CPE455/lab06/.vscode/settings.json b/CPE455/lab06/.vscode/settings.json new file mode 100644 index 0000000..862cfc6 --- /dev/null +++ b/CPE455/lab06/.vscode/settings.json @@ -0,0 +1,30 @@ +{ + "C_Cpp_Runner.cCompilerPath": "/usr/bin/gcc", + "C_Cpp_Runner.cppCompilerPath": "/usr/bin/g++", + "C_Cpp_Runner.debuggerPath": "/usr/bin/gdb", + "C_Cpp_Runner.cStandard": "", + "C_Cpp_Runner.cppStandard": "", + "C_Cpp_Runner.msvcBatchPath": "", + "C_Cpp_Runner.warnings": [ + "-Wall", + "-Wextra", + "-Wpedantic" + ], + "C_Cpp_Runner.enableWarnings": true, + "C_Cpp_Runner.warningsAsError": false, + "C_Cpp_Runner.compilerArgs": [], + "C_Cpp_Runner.linkerArgs": [], + "C_Cpp_Runner.includePaths": [], + "C_Cpp_Runner.includeSearch": [ + "*", + "**/*" + ], + "C_Cpp_Runner.excludeSearch": [ + "**/build", + "**/build/**", + "**/.*", + "**/.*/**", + "**/.vscode", + "**/.vscode/**" + ] +} \ No newline at end of file diff --git a/CPE455/lab06/CPEX55-Lab06-StaticAnalysis.pdf b/CPE455/lab06/CPEX55-Lab06-StaticAnalysis.pdf new file mode 100644 index 0000000..8e864f1 Binary files /dev/null and b/CPE455/lab06/CPEX55-Lab06-StaticAnalysis.pdf differ diff --git a/CPE455/lab06/JSF-AV-rules.pdf b/CPE455/lab06/JSF-AV-rules.pdf new file mode 100644 index 0000000..b93008f Binary files /dev/null and b/CPE455/lab06/JSF-AV-rules.pdf differ diff --git a/CPE455/lab06/a.out b/CPE455/lab06/a.out new file mode 100755 index 0000000..6e4de42 Binary files /dev/null and b/CPE455/lab06/a.out differ diff --git a/CPE455/lab06/clang++.txt b/CPE455/lab06/clang++.txt new file mode 100644 index 0000000..e92431e --- /dev/null +++ b/CPE455/lab06/clang++.txt @@ -0,0 +1,10 @@ +ec3.cpp:11:5: warning: array index 10 is past the end of the array (which contains 10 elements) [-Warray-bounds] + a[10] = 0; + ^ ~~ +ec3.cpp:8:5: note: array 'a' declared here + char a[10]; + ^ +ec3.cpp:66:1: warning: control may reach end of non-void function [-Wreturn-type] +} +^ +2 warnings generated. diff --git a/CPE455/lab06/clang++all.txt b/CPE455/lab06/clang++all.txt new file mode 100644 index 0000000..3cb3758 --- /dev/null +++ b/CPE455/lab06/clang++all.txt @@ -0,0 +1,13 @@ +ec3.cpp:43:10: warning: unused variable 'q' [-Wunused-variable] + int* q = new int; + ^ +ec3.cpp:11:5: warning: array index 10 is past the end of the array (which contains 10 elements) [-Warray-bounds] + a[10] = 0; + ^ ~~ +ec3.cpp:8:5: note: array 'a' declared here + char a[10]; + ^ +ec3.cpp:66:1: warning: control may reach end of non-void function [-Wreturn-type] +} +^ +3 warnings generated. diff --git a/CPE455/lab06/cppcheck-all.txt b/CPE455/lab06/cppcheck-all.txt new file mode 100644 index 0000000..28e1d7f --- /dev/null +++ b/CPE455/lab06/cppcheck-all.txt @@ -0,0 +1,48 @@ +ec3.cpp:55:5: style: Assignment of function parameter has no effect outside the function. [uselessAssignmentArg] + a = a + 1; // No side effect outside function + ^ +ec3.cpp:11:6: error: Array 'a[10]' accessed at index 10, which is out of bounds. [arrayIndexOutOfBounds] + a[10] = 0; + ^ +ec3.cpp:16:10: error: Array 'a[10]' accessed at index 10, which is out of bounds. [arrayIndexOutOfBounds] + a[k] = k; + ^ +ec3.cpp:62:0: error: Found a exit path from function with non-void return type that has missing return statement [missingReturn] + return false; +^ +ec3.cpp:33:6: error: Null pointer dereference: x [nullPointer] + *x = 1; + ^ +ec3.cpp:32:14: note: Assignment 'x=0', assigned value is 0 + int* x = 0; + ^ +ec3.cpp:33:6: note: Null pointer dereference + *x = 1; + ^ +ec3.cpp:29:6: error: Uninitialized variable: p [uninitvar] + *p = 5; + ^ +ec3.cpp:47:12: error: Memory is allocated but not initialized: r [uninitdata] + delete r; + ^ +ec3.cpp:23:14: style: Variable 'a[m]' is assigned a value that is never used. [unreadVariable] + a[m] = m; + ^ +ec3.cpp:43:12: style: Variable 'q' is assigned a value that is never used. [unreadVariable] + int* q = new int; + ^ +ec3.cpp:28:10: style: Variable 'p' is not assigned a value. [unassignedVariable] + int* p; + ^ +ec3.cpp:43:10: style: Variable 'q' is allocated memory that is never used. [unusedAllocatedMemory] + int* q = new int; + ^ +ec3.cpp:46:10: style: Variable 'r' is allocated memory that is never used. [unusedAllocatedMemory] + int* r = new int[4]; + ^ +ec3.cpp:55:7: style: Variable 'a' is assigned a value that is never used. [unreadVariable] + a = a + 1; // No side effect outside function + ^ +ec3.cpp:53:0: style: The function 'f' is never used. [unusedFunction] + +^ diff --git a/CPE455/lab06/cppcheck.txt b/CPE455/lab06/cppcheck.txt new file mode 100644 index 0000000..f90702b --- /dev/null +++ b/CPE455/lab06/cppcheck.txt @@ -0,0 +1,24 @@ +ec3.cpp:11:6: error: Array 'a[10]' accessed at index 10, which is out of bounds. [arrayIndexOutOfBounds] + a[10] = 0; + ^ +ec3.cpp:16:10: error: Array 'a[10]' accessed at index 10, which is out of bounds. [arrayIndexOutOfBounds] + a[k] = k; + ^ +ec3.cpp:62:0: error: Found a exit path from function with non-void return type that has missing return statement [missingReturn] + return false; +^ +ec3.cpp:33:6: error: Null pointer dereference: x [nullPointer] + *x = 1; + ^ +ec3.cpp:32:14: note: Assignment 'x=0', assigned value is 0 + int* x = 0; + ^ +ec3.cpp:33:6: note: Null pointer dereference + *x = 1; + ^ +ec3.cpp:29:6: error: Uninitialized variable: p [uninitvar] + *p = 5; + ^ +ec3.cpp:47:12: error: Memory is allocated but not initialized: r [uninitdata] + delete r; + ^ diff --git a/CPE455/lab06/ec3.cpp b/CPE455/lab06/ec3.cpp new file mode 100644 index 0000000..2be2f48 --- /dev/null +++ b/CPE455/lab06/ec3.cpp @@ -0,0 +1,68 @@ + + +void f(int a); +bool g(int& b); + +int main(int argc, char* argv[]) +{ + char a[10]; + + // Array bounds error + a[10] = 0; + + // Array bounds error via loop + for(int k = 0; k <= 10; k++) + { + a[k] = k; + } + + // Array bounds error via loop + int m = 0; + while (true) + { + a[m] = m; + m++; + } + + // Pointer variable p uninitialized + int* p; + *p = 5; + + // Null pointer dereference + int* x = 0; + *x = 1; + + // Trigger path in function g that does not return Boolean + int c = -1; + if ( g(c) ) + c = 2; + else + c = 3; + + // Memory leak + int* q = new int; + + // Memory leak + int* r = new int[4]; + delete r; + + return 0; +} + +// Unused function f +void f(int a) +{ + a = a + 1; // No side effect outside function +} + +// Function g has one path that does not return a Boolean value +bool g(int& b) +{ + if (b > 0) + return false; + + b = 0; + // Exit without returning a Boolean +} + + diff --git a/CPE455/lab06/g++.txt b/CPE455/lab06/g++.txt new file mode 100644 index 0000000..e69de29 diff --git a/CPE455/lab06/g++all.txt b/CPE455/lab06/g++all.txt new file mode 100644 index 0000000..6017aca --- /dev/null +++ b/CPE455/lab06/g++all.txt @@ -0,0 +1,11 @@ +ec3.cpp: In function ‘int main(int, char**)’: +ec3.cpp:8:10: warning: variable ‘a’ set but not used [-Wunused-but-set-variable] + char a[10]; + ^ +ec3.cpp:43:10: warning: unused variable ‘q’ [-Wunused-variable] + int* q = new int; + ^ +ec3.cpp: In function ‘bool g(int&)’: +ec3.cpp:66:1: warning: control reaches end of non-void function [-Wreturn-type] + } + ^ diff --git a/CPE455/lab06/sei-cert-c-coding-standard-2016-v01.pdf b/CPE455/lab06/sei-cert-c-coding-standard-2016-v01.pdf new file mode 100644 index 0000000..739dc93 Binary files /dev/null and b/CPE455/lab06/sei-cert-c-coding-standard-2016-v01.pdf differ diff --git a/CPE455/lab07/Makefile b/CPE455/lab07/Makefile new file mode 100644 index 0000000..13d5d9a --- /dev/null +++ b/CPE455/lab07/Makefile @@ -0,0 +1,8 @@ +CC := afl-gcc +CFLAGS := -Wno-unused-result + +all: crashy.c + $(CC) $(CFLAGS) -o crashy crashy.c + +clean: + rm crashy diff --git a/CPE455/lab07/crashy b/CPE455/lab07/crashy new file mode 100755 index 0000000..a8b37a0 Binary files /dev/null and b/CPE455/lab07/crashy differ diff --git a/CPE455/lab07/crashy.c b/CPE455/lab07/crashy.c new file mode 100644 index 0000000..83b7fab --- /dev/null +++ b/CPE455/lab07/crashy.c @@ -0,0 +1,83 @@ +#include +#include +#include + +int main(int argc, char *argv[]) { + + FILE *fp; + unsigned int sz, len, ptr; + char *buffer; + char type; + char tmp_char; + int tmp_int; + char *tmp_string; + + if(argc != 2) { + fprintf(stderr, "Usage: %s \n", argv[0]); + return 1; + } + + fp = fopen(argv[1], "r"); + if(!fp) { + fprintf(stderr, "Failed to open '%s'\n", argv[1]); + return 1; + } + + fseek(fp, 0, SEEK_END); + sz = ftell(fp); + fseek(fp, 0, SEEK_SET); + + buffer = malloc(sz); + if(!buffer) { + fprintf(stderr, "Failed to allocate %d bytes of memory\n", sz); + return 1; + } + + fread(buffer, sizeof(char), sz, fp); + + ptr = 0; + while(ptr < sz) { + + type = buffer[ptr++]; + switch(type) { + + case '\x01': // integer + tmp_int = *(int *)(buffer + ptr); + ptr += sizeof(int); + printf("i: 0x%08x\n", tmp_int); + break; + + case '\x02': // char + tmp_char = buffer[ptr++]; + printf("c: 0x%02x\n", (unsigned char)tmp_char); + break; + + case '\x03': // string + len = *(int *)(buffer + ptr); + ptr += sizeof(int); + tmp_string = malloc(len); + if(!tmp_string) { + fprintf(stderr, "Failed to allocate %d bytes of memory\n", len); + return 1; + } + strcpy(tmp_string, (buffer + ptr)); + printf("s: %s\n", tmp_string); + ptr += len; + break; + + case '\x04': // comment + printf("#: %s\n", (buffer + ptr)); + while(*(buffer + ptr++) != '\x00'); + break; + + case '\xff': // END + return 0; + + default: + fprintf(stderr, "Unknown data type '%c'\n", type); + + } + + } + +} \ No newline at end of file diff --git a/CPE455/lab07/crashy.c.gcov b/CPE455/lab07/crashy.c.gcov new file mode 100644 index 0000000..8bd8a21 --- /dev/null +++ b/CPE455/lab07/crashy.c.gcov @@ -0,0 +1,88 @@ + -: 0:Source:crashy.c + -: 0:Graph:crashy.gcno + -: 0:Data:crashy.gcda + -: 0:Runs:9 + -: 0:Programs:1 + -: 1:#include + -: 2:#include + -: 3:#include + -: 4: + 9: 5:int main(int argc, char *argv[]) { + -: 6: + -: 7: FILE *fp; + -: 8: unsigned int sz, len, ptr; + -: 9: char *buffer; + -: 10: char type; + -: 11: char tmp_char; + -: 12: int tmp_int; + -: 13: char *tmp_string; + -: 14: + 9: 15: if(argc != 2) { + 1: 16: fprintf(stderr, "Usage: %s \n", argv[0]); + 1: 17: return 1; + -: 18: } + -: 19: + 8: 20: fp = fopen(argv[1], "r"); + 8: 21: if(!fp) { + 1: 22: fprintf(stderr, "Failed to open '%s'\n", argv[1]); + 1: 23: return 1; + -: 24: } + -: 25: + 7: 26: fseek(fp, 0, SEEK_END); + 7: 27: sz = ftell(fp); + 7: 28: fseek(fp, 0, SEEK_SET); + -: 29: + 7: 30: buffer = malloc(sz); + 7: 31: if(!buffer) { + 1: 32: fprintf(stderr, "Failed to allocate %d bytes of memory\n", sz); + 1: 33: return 1; + -: 34: } + -: 35: + 6: 36: fread(buffer, sizeof(char), sz, fp); + -: 37: + 6: 38: ptr = 0; + 31: 39: while(ptr < sz) { + -: 40: + 25: 41: type = buffer[ptr++]; + 25: 42: switch(type) { + -: 43: + -: 44: case '\x01': // integer + 8: 45: tmp_int = *(int *)(buffer + ptr); + 8: 46: ptr += sizeof(int); + 8: 47: printf("i: 0x%08x\n", tmp_int); + 8: 48: break; + -: 49: + -: 50: case '\x02': // char + 5: 51: tmp_char = buffer[ptr++]; + 5: 52: printf("c: 0x%02x\n", (unsigned char)tmp_char); + 5: 53: break; + -: 54: + -: 55: case '\x03': // string + 6: 56: len = *(int *)(buffer + ptr); + 6: 57: ptr += sizeof(int); + 6: 58: tmp_string = malloc(len); + 6: 59: if(!tmp_string) { + 1: 60: fprintf(stderr, "Failed to allocate %d bytes of memory\n", len); + 1: 61: return 1; + -: 62: } + 5: 63: strcpy(tmp_string, (buffer + ptr)); + 5: 64: printf("s: %s\n", tmp_string); + 5: 65: ptr += len; + 5: 66: break; + -: 67: + -: 68: case '\x04': // comment + 1: 69: printf("#: %s\n", (buffer + ptr)); + 1: 70: while(*(buffer + ptr++) != '\x00'); + 1: 71: break; + -: 72: + -: 73: case '\xff': // END + 5: 74: return 0; + -: 75: + -: 76: default: + #####: 77: fprintf(stderr, "Unknown data type '%c'\n", type); + -: 78: + -: 79: } + -: 80: + -: 81: } + -: 82: + #####: 83:} diff --git a/CPE455/lab07/crashy.gcda b/CPE455/lab07/crashy.gcda new file mode 100644 index 0000000..33a4fd8 Binary files /dev/null and b/CPE455/lab07/crashy.gcda differ diff --git a/CPE455/lab07/crashy.gcno b/CPE455/lab07/crashy.gcno new file mode 100644 index 0000000..8fb3fff Binary files /dev/null and b/CPE455/lab07/crashy.gcno differ diff --git a/CPE455/lab07/crashy.zip b/CPE455/lab07/crashy.zip new file mode 100644 index 0000000..53f136d Binary files /dev/null and b/CPE455/lab07/crashy.zip differ diff --git a/CPE455/lab07/example1 b/CPE455/lab07/example1 new file mode 100644 index 0000000..d3125c8 Binary files /dev/null and b/CPE455/lab07/example1 differ diff --git a/CPE455/lab07/example2 b/CPE455/lab07/example2 new file mode 100644 index 0000000..3ad05b2 Binary files /dev/null and b/CPE455/lab07/example2 differ diff --git a/CPE455/lab07/example3 b/CPE455/lab07/example3 new file mode 100644 index 0000000..151cde6 Binary files /dev/null and b/CPE455/lab07/example3 differ diff --git a/CPE455/lab07/example4 b/CPE455/lab07/example4 new file mode 100644 index 0000000..acd56ef --- /dev/null +++ b/CPE455/lab07/example4 @@ -0,0 +1 @@ +ABCÿ \ No newline at end of file diff --git a/CPE455/lab07/example5 b/CPE455/lab07/example5 new file mode 100644 index 0000000..8f022ba Binary files /dev/null and b/CPE455/lab07/example5 differ diff --git a/CPE455/lab07/lab07.txt b/CPE455/lab07/lab07.txt new file mode 100644 index 0000000..3f677cd --- /dev/null +++ b/CPE455/lab07/lab07.txt @@ -0,0 +1,409 @@ +Script started on Tue 29 Mar 2022 09:53:31 AM CDT +[?1034hbash-4.2$ gcc -g --coverage crashy.c -o crashy +bash-4.2$ ./vcrashy +Usage: ./crashy +bash-4.2$ gcov crashy.c +File 'crashy.c' +Lines executed:9.30% of 43 +Creating 'crashy.c.gcov' + +bash-4.2$ ./crashy example1 +i: 0x78563412 +c: 0xcc +s: hello +bash-4.2$ ./crashy example1 gcov crashy.c +File 'crashy.c' +Lines executed:74.42% of 43 +Creating 'crashy.c.gcov' + +bash-4.2$ gcov crashy.c  ./crashy example12 +i: 0x00000001 +i: 0x00000002 +i: 0x00000003 +i: 0x00000004 +i: 0x00000005 +bash-4.2$ ./crashy example2 gcov crashy.c +File 'crashy.c' +Lines executed:74.42% of 43 +Creating 'crashy.c.gcov' + +bash-4.2$ gcov crashy.c  ./crashy example23 +s: this +s: is +s: an +s: example +bash-4.2$ ./crashy example3 gcov crashy.c +File 'crashy.c' +Lines executed:74.42% of 43 +Creating 'crashy.c.gcov' + +bash-4.2$ gcov crashy.c  ./crashy example34 +c: 0x41 +c: 0x42 +c: 0x43 +bash-4.2$ ./crashy example4 gcov crashy.c +File 'crashy.c' +Lines executed:74.42% of 43 +Creating 'crashy.c.gcov' + +bash-4.2$ gcov crashy.c  ./crashy example45 +i: 0x00001337 +#: ELITE +bash-4.2$ ./crashy example5 gcov crashy.c +File 'crashy.c' +Lines executed:81.40% of 43 +Creating 'crashy.c.gcov' + +bash-4.2$ more crashy +crashy crashy.c crashy.c.gcov crashy.gcda crashy.gcno crashy.zip +bash-4.2$ more crashy.c.gcov + -: 0:Source:crashy.c + -: 0:Graph:crashy.gcno + -: 0:Data:crashy.gcda + -: 0:Runs:6 + -: 0:Programs:1 + -: 1:#include + -: 2:#include + -: 3:#include + -: 4: + 6: 5:int main(int argc, char *argv[]) { + -: 6: + -: 7: FILE *fp; + -: 8: unsigned int sz, len, ptr; + -: 9: char *buffer; + -: 10: char type; + -: 11: char tmp_char; + -: 12: int tmp_int; + -: 13: char *tmp_string; + -: 14: + 6: 15: if(argc != 2) { + 1: 16: fprintf(stderr, "Usage: %s \n", argv[0]); + 1: 17: return 1; + -: 18: } + -: 19: + 5: 20: fp = fopen(argv[1], "r"); + 5: 21: if(!fp) { + #####: 22: fprintf(stderr, "Failed to open '%s'\n", argv[1]); + #####: 23: return 1; + -: 24: } + -: 25: + 5: 26: fseek(fp, 0, SEEK_END); + 5: 27: sz = ftell(fp); + 5: 28: fseek(fp, 0, SEEK_SET); + -: 29: + 5: 30: buffer = malloc(sz); + 5: 31: if(!buffer) { + #####: 32: fprintf(stderr, "Failed to allocate %d bytes of memory\n", sz); + #####: 33: return 1; + -: 34: } + -: 35: + 5: 36: fread(buffer, sizeof(char), sz, fp); + -: 37: + 5: 38: ptr = 0; + 27: 39: while(ptr < sz) { + -: 40: + 22: 41: type = buffer[ptr++]; + 22: 42: switch(type) { + -: 43: + -: 44: case '\x01': // integer + 7: 45: tmp_int = *(int *)(buffer + ptr); + 7: 46: ptr += sizeof(int); +--More--(55%) 7: 47: printf("i: 0x%08x\n", tmp_int); +--More--(57%) 7: 48: break; +--More--(58%) -: 49: +--More--(59%) -: 50: case '\x02': // char +--More--(60%) 4: 51: tmp_char = buffer[ptr++]; +--More--(61%) 4: 52: printf("c: 0x%02x\n", (unsigned char)tmp_char); +--More--(64%) 4: 53: break; +--More--(65%) -: 54: +--More--(65%) -: 55: case '\x03': // string +--More--(67%) 5: 56: len = *(int *)(buffer + ptr); +--More--(68%) 5: 57: ptr += sizeof(int); +--More--(70%) 5: 58: tmp_string = malloc(len); +--More--(71%) 5: 59: if(!tmp_string) { +--More--(72%) #####: 60: fprintf(stderr, "Failed to allocate %d bytes of m +--More--(75%) emory\n", len); +--More--(75%) #####: 61: return 1; +--More--(76%) -: 62: } +--More--(77%) 5: 63: strcpy(tmp_string, (buffer + ptr)); +--More--(79%) 5: 64: printf("s: %s\n", tmp_string); +--More--(81%) 5: 65: ptr += len; +--More--(82%) 5: 66: break; +--More--(83%) -: 67: +--More--(83%) -: 68: case '\x04': // comment +--More--(85%) 1: 69: printf("#: %s\n", (buffer + ptr)); +--More--(86%) 1: 70: while(*(buffer + ptr++) != '\x00'); +--More--(88%) 1: 71: break; +--More--(89%) -: 72: +--More--(90%) -: 73: case '\xff': // END +--More--(91%) 5: 74: return 0; +--More--(92%) -: 75: +--More--(93%) -: 76: default: +--More--(94%) #####: 77: fprintf(stderr, "Unknown data type '%c'\n", type); +--More--(96%) bash-4.2$ more crashy.c.gcov + -: 0:Source:crashy.c + -: 0:Graph:crashy.gcno + -: 0:Data:crashy.gcda + -: 0:Runs:6 + -: 0:Programs:1 + -: 1:#include + -: 2:#include + -: 3:#include + -: 4: + 6: 5:int main(int argc, char *argv[]) { + -: 6: + -: 7: FILE *fp; + -: 8: unsigned int sz, len, ptr; + -: 9: char *buffer; + -: 10: char type; + -: 11: char tmp_char; + -: 12: int tmp_int; + -: 13: char *tmp_string; + -: 14: + 6: 15: if(argc != 2) { + 1: 16: fprintf(stderr, "Usage: %s \n", argv[0]); + 1: 17: return 1; + -: 18: } + -: 19: + 5: 20: fp = fopen(argv[1], "r"); + 5: 21: if(!fp) { + #####: 22: fprintf(stderr, "Failed to open '%s'\n", argv[1]); + #####: 23: return 1; + -: 24: } + -: 25: + 5: 26: fseek(fp, 0, SEEK_END); + 5: 27: sz = ftell(fp); + 5: 28: fseek(fp, 0, SEEK_SET); + -: 29: + 5: 30: buffer = malloc(sz); + 5: 31: if(!buffer) { + #####: 32: fprintf(stderr, "Failed to allocate %d bytes of memory\n", sz); + #####: 33: return 1; + -: 34: } + -: 35: + 5: 36: fread(buffer, sizeof(char), sz, fp); + -: 37: + 5: 38: ptr = 0; + 27: 39: while(ptr < sz) { + -: 40: + 22: 41: type = buffer[ptr++]; + 22: 42: switch(type) { + -: 43: + -: 44: case '\x01': // integer + 7: 45: tmp_int = *(int *)(buffer + ptr); + 7: 46: ptr += sizeof(int); +--More--(55%) 7: 47: printf("i: 0x%08x\n", tmp_int); +--More--(57%) 7: 48: break; +--More--(58%) -: 49: +--More--(59%) -: 50: case '\x02': // char +--More--(60%) 4: 51: tmp_char = buffer[ptr++]; +--More--(61%) 4: 52: printf("c: 0x%02x\n", (unsigned char)tmp_char); +--More--(64%) 4: 53: break; +--More--(65%) -: 54: +--More--(65%) -: 55: case '\x03': // string +--More--(67%) 5: 56: len = *(int *)(buffer + ptr); +--More--(68%) 5: 57: ptr += sizeof(int); +--More--(70%) 5: 58: tmp_string = malloc(len); +--More--(71%) 5: 59: if(!tmp_string) { +--More--(72%) #####: 60: fprintf(stderr, "Failed to allocate %d bytes of memory\n", len); +--More--(75%) #####: 61: return 1; +--More--(76%) -: 62: } +--More--(77%) 5: 63: strcpy(tmp_string, (buffer + ptr)); +--More--(79%) 5: 64: printf("s: %s\n", tmp_string); +--More--(81%) 5: 65: ptr += len; +--More--(82%) 5: 66: break; +--More--(83%) -: 67: +--More--(83%) -: 68: case '\x04': // comment +--More--(85%) 1: 69: printf("#: %s\n", (buffer + ptr)); +--More--(86%) 1: 70: while(*(buffer + ptr++) != '\x00'); +--More--(88%) 1: 71: break; +--More--(89%) -: 72: +--More--(90%) -: 73: case '\xff': // END +--More--(91%) 5: 74: return 0; +--More--(92%) -: 75: +--More--(93%) -: 76: default: +--More--(94%) #####: 77: fprintf(stderr, "Unknown data type '%c'\n", type); +--More--(96%) -: 78: +--More--(96%) -: 79: } +--More--(97%) -: 80: +--More--(98%) -: 81: } +--More--(98%) -: 82: +--More--(99%) #####: 83:} +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ +bash-4.2$ ./crashy example6 +Failed to open 'example6' +bash-4.2$ ./crashy example6 more crashy.c.gcov gcov crashy.c +File 'crashy.c' +Lines executed:86.05% of 43 +Creating 'crashy.c.gcov' + +bash-4.2$ gdb ./crashy +[?1034hGNU gdb (GDB) Red Hat Enterprise Linux 7.6.1-120.el7 +Copyright (C) 2013 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +For bug reporting instructions, please see: +... +Reading symbols from /home/student/anw0044/CPE455/lab07/crashy...done. +(gdb) (gdb) break main +Breakpoint 1 at 0x400e4c: file crashy.c, line 15. +(gdb) break 31 +Breakpoint 2 at 0x400fa7: file crashy.c, line 31. +(gdb) break 3159 +Breakpoint 3 at 0x401153: file crashy.c, line 59. +(gdb) break 5931main3159 run example1 +Starting program: /home/student/anw0044/CPE455/lab07/./crashy example1 + +Breakpoint 1, main (argc=2, argv=0x7fffffffe438) at crashy.c:15 +15 if(argc != 2) { +Missing separate debuginfos, use: debuginfo-install glibc-2.17-325.el7_9.x86_64 +(gdb) continue +Continuing. + +Breakpoint 2, main (argc=2, argv=0x7fffffffe438) at crashy.c:31 +31 if(!buffer) { +(gdb) print buffer=0 +$1 = 0x0 +(gdb) conytinue +Continuing. +Failed to allocate 19 bytes of memory +[Inferior 1 (process 1861) exited with code 01] +(gdb) continue print buffer=0 continue run example1 +Starting program: /home/student/anw0044/CPE455/lab07/./crashy example1 + +Breakpoint 1, main (argc=2, argv=0x7fffffffe438) at crashy.c:15 +15 if(argc != 2) { +(gdb) print tmp_string=0 +$2 = 0x0 +(gdb) continue +Continuing. + +Breakpoint 2, main (argc=2, argv=0x7fffffffe438) at crashy.c:31 +31 if(!buffer) { +(gdb) continue +Continuing. +i: 0x78563412 +c: 0xcc + +Breakpoint 3, main (argc=2, argv=0x7fffffffe438) at crashy.c:59 +59 if(!tmp_string) { +(gdb) continue print tmp_string=0 +$3 = 0x0 +(gdb) continue +Continuing. +Failed to allocate 6 bytes of memory +[Inferior 1 (process 1910) exited with code 01] +(gdb) quit +bash-4.2$ gdb ./crashycov crashy.c ./crashy example6 gcov crashy.c +File 'crashy.c' +Lines executed:95.35% of 43 +Creating 'crashy.c.gcov' + +bash-4.2$ cat crashy.c.gcov + -: 0:Source:crashy.c + -: 0:Graph:crashy.gcno + -: 0:Data:crashy.gcda + -: 0:Runs:9 + -: 0:Programs:1 + -: 1:#include + -: 2:#include + -: 3:#include + -: 4: + 9: 5:int main(int argc, char *argv[]) { + -: 6: + -: 7: FILE *fp; + -: 8: unsigned int sz, len, ptr; + -: 9: char *buffer; + -: 10: char type; + -: 11: char tmp_char; + -: 12: int tmp_int; + -: 13: char *tmp_string; + -: 14: + 9: 15: if(argc != 2) { + 1: 16: fprintf(stderr, "Usage: %s \n", argv[0]); + 1: 17: return 1; + -: 18: } + -: 19: + 8: 20: fp = fopen(argv[1], "r"); + 8: 21: if(!fp) { + 1: 22: fprintf(stderr, "Failed to open '%s'\n", argv[1]); + 1: 23: return 1; + -: 24: } + -: 25: + 7: 26: fseek(fp, 0, SEEK_END); + 7: 27: sz = ftell(fp); + 7: 28: fseek(fp, 0, SEEK_SET); + -: 29: + 7: 30: buffer = malloc(sz); + 7: 31: if(!buffer) { + 1: 32: fprintf(stderr, "Failed to allocate %d bytes of memory\n", sz); + 1: 33: return 1; + -: 34: } + -: 35: + 6: 36: fread(buffer, sizeof(char), sz, fp); + -: 37: + 6: 38: ptr = 0; + 31: 39: while(ptr < sz) { + -: 40: + 25: 41: type = buffer[ptr++]; + 25: 42: switch(type) { + -: 43: + -: 44: case '\x01': // integer + 8: 45: tmp_int = *(int *)(buffer + ptr); + 8: 46: ptr += sizeof(int); + 8: 47: printf("i: 0x%08x\n", tmp_int); + 8: 48: break; + -: 49: + -: 50: case '\x02': // char + 5: 51: tmp_char = buffer[ptr++]; + 5: 52: printf("c: 0x%02x\n", (unsigned char)tmp_char); + 5: 53: break; + -: 54: + -: 55: case '\x03': // string + 6: 56: len = *(int *)(buffer + ptr); + 6: 57: ptr += sizeof(int); + 6: 58: tmp_string = malloc(len); + 6: 59: if(!tmp_string) { + 1: 60: fprintf(stderr, "Failed to allocate %d bytes of memory\n", len); + 1: 61: return 1; + -: 62: } + 5: 63: strcpy(tmp_string, (buffer + ptr)); + 5: 64: printf("s: %s\n", tmp_string); + 5: 65: ptr += len; + 5: 66: break; + -: 67: + -: 68: case '\x04': // comment + 1: 69: printf("#: %s\n", (buffer + ptr)); + 1: 70: while(*(buffer + ptr++) != '\x00'); + 1: 71: break; + -: 72: + -: 73: case '\xff': // END + 5: 74: return 0; + -: 75: + -: 76: default: + #####: 77: fprintf(stderr, "Unknown data type '%c'\n", type); + -: 78: + -: 79: } + -: 80: + -: 81: } + -: 82: + #####: 83:} +bash-4.2$ exit +exit + +Script done on Tue 29 Mar 2022 10:04:36 AM CDT diff --git a/CPE455/lab08/Screenshot from 2022-03-29 10-31-29.png b/CPE455/lab08/Screenshot from 2022-03-29 10-31-29.png new file mode 100644 index 0000000..d560bc9 Binary files /dev/null and b/CPE455/lab08/Screenshot from 2022-03-29 10-31-29.png differ diff --git a/CPE455/lab08/Screenshot from 2022-03-29 10-31-40.png b/CPE455/lab08/Screenshot from 2022-03-29 10-31-40.png new file mode 100644 index 0000000..459780e Binary files /dev/null and b/CPE455/lab08/Screenshot from 2022-03-29 10-31-40.png differ diff --git a/CPE455/lab08/Screenshot from 2022-03-29 10-32-02.png b/CPE455/lab08/Screenshot from 2022-03-29 10-32-02.png new file mode 100644 index 0000000..9da3b5e Binary files /dev/null and b/CPE455/lab08/Screenshot from 2022-03-29 10-32-02.png differ diff --git a/CPE455/lab08/Screenshot from 2022-03-29 10-33-02.png b/CPE455/lab08/Screenshot from 2022-03-29 10-33-02.png new file mode 100644 index 0000000..68aba69 Binary files /dev/null and b/CPE455/lab08/Screenshot from 2022-03-29 10-33-02.png differ diff --git a/CPE455/lab08/Screenshot from 2022-03-29 10-36-03.png b/CPE455/lab08/Screenshot from 2022-03-29 10-36-03.png new file mode 100644 index 0000000..8a5c925 Binary files /dev/null and b/CPE455/lab08/Screenshot from 2022-03-29 10-36-03.png differ diff --git a/CPE455/lab08/Screenshot from 2022-03-29 10-37-00.png b/CPE455/lab08/Screenshot from 2022-03-29 10-37-00.png new file mode 100644 index 0000000..138dab0 Binary files /dev/null and b/CPE455/lab08/Screenshot from 2022-03-29 10-37-00.png differ diff --git a/CPE455/lab08/calligraph.pdf b/CPE455/lab08/calligraph.pdf new file mode 100644 index 0000000..45c0237 Binary files /dev/null and b/CPE455/lab08/calligraph.pdf differ diff --git a/CPE455/lab08/flowgraph.pdf b/CPE455/lab08/flowgraph.pdf new file mode 100644 index 0000000..9c780a4 Binary files /dev/null and b/CPE455/lab08/flowgraph.pdf differ diff --git a/CPE455/lab08/kiviat.pdf b/CPE455/lab08/kiviat.pdf new file mode 100644 index 0000000..8703a43 Binary files /dev/null and b/CPE455/lab08/kiviat.pdf differ diff --git a/CPE455/lab08/mode-s.c b/CPE455/lab08/mode-s.c new file mode 100644 index 0000000..3b318ea --- /dev/null +++ b/CPE455/lab08/mode-s.c @@ -0,0 +1,740 @@ +#include "mode-s.h" + +#define MODE_S_PREAMBLE_US 8 // microseconds +#define MODE_S_LONG_MSG_BITS 112 +#define MODE_S_SHORT_MSG_BITS 56 +#define MODE_S_FULL_LEN (MODE_S_PREAMBLE_US+MODE_S_LONG_MSG_BITS) + +#define MODE_S_ICAO_CACHE_TTL 60 // Time to live of cached addresses. + +static uint16_t maglut[129*129*2]; +static int maglut_initialized = 0; + +// =============================== Initialization =========================== + +void mode_s_init(mode_s_t *self) { + int i, q; + + self->fix_errors = 1; + self->check_crc = 1; + self->aggressive = 0; + + // Allocate the ICAO address cache. We use two uint32_t for every entry + // because it's a addr / timestamp pair for every entry + memset(&self->icao_cache, 0, sizeof(self->icao_cache)); + + // Populate the I/Q -> Magnitude lookup table. It is used because sqrt or + // round may be expensive and may vary a lot depending on the libc used. + // + // We scale to 0-255 range multiplying by 1.4 in order to ensure that every + // different I/Q pair will result in a different magnitude value, not losing + // any resolution. + if (!maglut_initialized) { + for (i = 0; i <= 128; i++) { + for (q = 0; q <= 128; q++) { + maglut[i*129+q] = round(sqrt(i*i+q*q)*360); + } + } + maglut_initialized = 1; + } +} + +// ===================== Mode S detection and decoding ===================== + +// Parity table for MODE S Messages. +// +// The table contains 112 elements, every element corresponds to a bit set in +// the message, starting from the first bit of actual data after the preamble. +// +// For messages of 112 bit, the whole table is used. For messages of 56 bits +// only the last 56 elements are used. +// +// The algorithm is as simple as xoring all the elements in this table for +// which the corresponding bit on the message is set to 1. +// +// The latest 24 elements in this table are set to 0 as the checksum at the end +// of the message should not affect the computation. +// +// Note: this function can be used with DF11 and DF17, other modes have the CRC +// xored with the sender address as they are reply to interrogations, but a +// casual listener can't split the address from the checksum. +uint32_t mode_s_checksum_table[] = { + 0x3935ea, 0x1c9af5, 0xf1b77e, 0x78dbbf, 0xc397db, 0x9e31e9, 0xb0e2f0, 0x587178, + 0x2c38bc, 0x161c5e, 0x0b0e2f, 0xfa7d13, 0x82c48d, 0xbe9842, 0x5f4c21, 0xd05c14, + 0x682e0a, 0x341705, 0xe5f186, 0x72f8c3, 0xc68665, 0x9cb936, 0x4e5c9b, 0xd8d449, + 0x939020, 0x49c810, 0x24e408, 0x127204, 0x093902, 0x049c81, 0xfdb444, 0x7eda22, + 0x3f6d11, 0xe04c8c, 0x702646, 0x381323, 0xe3f395, 0x8e03ce, 0x4701e7, 0xdc7af7, + 0x91c77f, 0xb719bb, 0xa476d9, 0xadc168, 0x56e0b4, 0x2b705a, 0x15b82d, 0xf52612, + 0x7a9309, 0xc2b380, 0x6159c0, 0x30ace0, 0x185670, 0x0c2b38, 0x06159c, 0x030ace, + 0x018567, 0xff38b7, 0x80665f, 0xbfc92b, 0xa01e91, 0xaff54c, 0x57faa6, 0x2bfd53, + 0xea04ad, 0x8af852, 0x457c29, 0xdd4410, 0x6ea208, 0x375104, 0x1ba882, 0x0dd441, + 0xf91024, 0x7c8812, 0x3e4409, 0xe0d800, 0x706c00, 0x383600, 0x1c1b00, 0x0e0d80, + 0x0706c0, 0x038360, 0x01c1b0, 0x00e0d8, 0x00706c, 0x003836, 0x001c1b, 0xfff409, + 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000 +}; + +uint32_t mode_s_checksum(unsigned char *msg, int bits) { + uint32_t crc = 0; + int offset = (bits == 112) ? 0 : (112-56); + int j; + + for(j = 0; j < bits; j++) { + int byte = j/8; + int bit = j%8; + int bitmask = 1 << (7-bit); + + // If bit is set, xor with corresponding table entry. + if (msg[byte] & bitmask) + crc ^= mode_s_checksum_table[j+offset]; + } + return crc; // 24 bit checksum. +} + +// Given the Downlink Format (DF) of the message, return the message length in +// bits. +int mode_s_msg_len_by_type(int type) { + if (type == 16 || type == 17 || + type == 19 || type == 20 || + type == 21) + return MODE_S_LONG_MSG_BITS; + else + return MODE_S_SHORT_MSG_BITS; +} + +// Try to fix single bit errors using the checksum. On success modifies the +// original buffer with the fixed version, and returns the position of the +// error bit. Otherwise if fixing failed -1 is returned. +int fix_single_bit_errors(unsigned char *msg, int bits) { + int j; + unsigned char aux[MODE_S_LONG_MSG_BITS/8]; + + for (j = 0; j < bits; j++) { + int byte = j/8; + int bitmask = 1 << (7-(j%8)); + uint32_t crc1, crc2; + + memcpy(aux, msg, bits/8); + aux[byte] ^= bitmask; // Flip j-th bit. + + crc1 = ((uint32_t)aux[(bits/8)-3] << 16) | + ((uint32_t)aux[(bits/8)-2] << 8) | + (uint32_t)aux[(bits/8)-1]; + crc2 = mode_s_checksum(aux, bits); + + if (crc1 == crc2) { + // The error is fixed. Overwrite the original buffer with the + // corrected sequence, and returns the error bit position. + memcpy(msg, aux, bits/8); + return j; + } + } + return -1; +} + +// Similar to fix_single_bit_errors() but try every possible two bit +// combination. This is very slow and should be tried only against DF17 +// messages that don't pass the checksum, and only in Aggressive Mode. +int fix_two_bits_errors(unsigned char *msg, int bits) { + int j, i; + unsigned char aux[MODE_S_LONG_MSG_BITS/8]; + + for (j = 0; j < bits; j++) { + int byte1 = j/8; + int bitmask1 = 1 << (7-(j%8)); + + // Don't check the same pairs multiple times, so i starts from j+1 + for (i = j+1; i < bits; i++) { + int byte2 = i/8; + int bitmask2 = 1 << (7-(i%8)); + uint32_t crc1, crc2; + + memcpy(aux, msg, bits/8); + + aux[byte1] ^= bitmask1; // Flip j-th bit. + aux[byte2] ^= bitmask2; // Flip i-th bit. + + crc1 = ((uint32_t)aux[(bits/8)-3] << 16) | + ((uint32_t)aux[(bits/8)-2] << 8) | + (uint32_t)aux[(bits/8)-1]; + crc2 = mode_s_checksum(aux, bits); + + if (crc1 == crc2) { + // The error is fixed. Overwrite the original buffer with the + // corrected sequence, and returns the error bit position. + memcpy(msg, aux, bits/8); + // We return the two bits as a 16 bit integer by shifting 'i' + // on the left. This is possible since 'i' will always be + // non-zero because i starts from j+1. + return j | (i<<8); + } + } + } + return -1; +} + +// Hash the ICAO address to index our cache of MODE_S_ICAO_CACHE_LEN elements, +// that is assumed to be a power of two. +uint32_t icao_cache_has_addr(uint32_t a) { + // The following three rounds wil make sure that every bit affects every + // output bit with ~ 50% of probability. + a = ((a >> 16) ^ a) * 0x45d9f3b; + a = ((a >> 16) ^ a) * 0x45d9f3b; + a = ((a >> 16) ^ a); + return a & (MODE_S_ICAO_CACHE_LEN-1); +} + +// Add the specified entry to the cache of recently seen ICAO addresses. Note +// that we also add a timestamp so that we can make sure that the entry is only +// valid for MODE_S_ICAO_CACHE_TTL seconds. +void add_recently_seen_icao_addr(mode_s_t *self, uint32_t addr) { + uint32_t h = icao_cache_has_addr(addr); + self->icao_cache[h*2] = addr; + self->icao_cache[h*2+1] = (uint32_t) time(NULL); +} + +// Returns 1 if the specified ICAO address was seen in a DF format with proper +// checksum (not xored with address) no more than * MODE_S_ICAO_CACHE_TTL +// seconds ago. Otherwise returns 0. +int icao_addr_was_recently_seen(mode_s_t *self, uint32_t addr) { + uint32_t h = icao_cache_has_addr(addr); + uint32_t a = self->icao_cache[h*2]; + int32_t t = self->icao_cache[h*2+1]; + + return a && a == addr && time(NULL)-t <= MODE_S_ICAO_CACHE_TTL; +} + +// If the message type has the checksum xored with the ICAO address, try to +// brute force it using a list of recently seen ICAO addresses. +// +// Do this in a brute-force fashion by xoring the predicted CRC with the +// address XOR checksum field in the message. This will recover the address: if +// we found it in our cache, we can assume the message is ok. +// +// This function expects mm->msgtype and mm->msgbits to be correctly populated +// by the caller. +// +// On success the correct ICAO address is stored in the mode_s_msg structure in +// the aa3, aa2, and aa1 fiedls. +// +// If the function successfully recovers a message with a correct checksum it +// returns 1. Otherwise 0 is returned. +int brute_force_ap(mode_s_t *self, unsigned char *msg, struct mode_s_msg *mm) { + unsigned char aux[MODE_S_LONG_MSG_BYTES]; + int msgtype = mm->msgtype; + int msgbits = mm->msgbits; + + if (msgtype == 0 || // Short air surveillance + msgtype == 4 || // Surveillance, altitude reply + msgtype == 5 || // Surveillance, identity reply + msgtype == 16 || // Long Air-Air survillance + msgtype == 20 || // Comm-A, altitude request + msgtype == 21 || // Comm-A, identity request + msgtype == 24) // Comm-C ELM + { + uint32_t addr; + uint32_t crc; + int lastbyte = (msgbits/8)-1; + + // Work on a copy. + memcpy(aux, msg, msgbits/8); + + // Compute the CRC of the message and XOR it with the AP field so that + // we recover the address, because: + // + // (ADDR xor CRC) xor CRC = ADDR. + crc = mode_s_checksum(aux, msgbits); + aux[lastbyte] ^= crc & 0xff; + aux[lastbyte-1] ^= (crc >> 8) & 0xff; + aux[lastbyte-2] ^= (crc >> 16) & 0xff; + + // If the obtained address exists in our cache we consider the message + // valid. + addr = aux[lastbyte] | (aux[lastbyte-1] << 8) | (aux[lastbyte-2] << 16); + if (icao_addr_was_recently_seen(self, addr)) { + mm->aa1 = aux[lastbyte-2]; + mm->aa2 = aux[lastbyte-1]; + mm->aa3 = aux[lastbyte]; + return 1; + } + } + return 0; +} + +// Decode the 13 bit AC altitude field (in DF 20 and others). Returns the +// altitude, and set 'unit' to either MODE_S_UNIT_METERS or MDOES_UNIT_FEETS. +int decode_ac13_field(unsigned char *msg, int *unit) { + int m_bit = msg[3] & (1<<6); + int q_bit = msg[3] & (1<<4); + + if (!m_bit) { + *unit = MODE_S_UNIT_FEET; + if (q_bit) { + // N is the 11 bit integer resulting from the removal of bit Q and M + int n = ((msg[2]&31)<<6) | + ((msg[3]&0x80)>>2) | + ((msg[3]&0x20)>>1) | + (msg[3]&15); + // The final altitude is due to the resulting number multiplied by + // 25, minus 1000. + return n*25-1000; + } else { + // TODO: Implement altitude where Q=0 and M=0 + } + } else { + *unit = MODE_S_UNIT_METERS; + // TODO: Implement altitude when meter unit is selected. + } + return 0; +} + +// Decode the 12 bit AC altitude field (in DF 17 and others). Returns the +// altitude or 0 if it can't be decoded. +int decode_ac12_field(unsigned char *msg, int *unit) { + int q_bit = msg[5] & 1; + + if (q_bit) { + // N is the 11 bit integer resulting from the removal of bit Q + *unit = MODE_S_UNIT_FEET; + int n = ((msg[5]>>1)<<4) | ((msg[6]&0xF0) >> 4); + // The final altitude is due to the resulting number multiplied by 25, + // minus 1000. + return n*25-1000; + } else { + return 0; + } +} + +static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789??????"; + +// Decode a raw Mode S message demodulated as a stream of bytes by +// mode_s_detect(), and split it into fields populating a mode_s_msg structure. +void mode_s_decode(mode_s_t *self, struct mode_s_msg *mm, unsigned char *msg) { + uint32_t crc2; // Computed CRC, used to verify the message CRC. + + // Work on our local copy + memcpy(mm->msg, msg, MODE_S_LONG_MSG_BYTES); + msg = mm->msg; + + // Get the message type ASAP as other operations depend on this + mm->msgtype = msg[0]>>3; // Downlink Format + mm->msgbits = mode_s_msg_len_by_type(mm->msgtype); + + // CRC is always the last three bytes. + mm->crc = ((uint32_t)msg[(mm->msgbits/8)-3] << 16) | + ((uint32_t)msg[(mm->msgbits/8)-2] << 8) | + (uint32_t)msg[(mm->msgbits/8)-1]; + crc2 = mode_s_checksum(msg, mm->msgbits); + + // Check CRC and fix single bit errors using the CRC when possible (DF 11 and 17). + mm->errorbit = -1; // No error + mm->crcok = (mm->crc == crc2); + + if (!mm->crcok && self->fix_errors && (mm->msgtype == 11 || mm->msgtype == 17)) { + if ((mm->errorbit = fix_single_bit_errors(msg, mm->msgbits)) != -1) { + mm->crc = mode_s_checksum(msg, mm->msgbits); + mm->crcok = 1; + } else if (self->aggressive && mm->msgtype == 17 && + (mm->errorbit = fix_two_bits_errors(msg, mm->msgbits)) != -1) { + mm->crc = mode_s_checksum(msg, mm->msgbits); + mm->crcok = 1; + } + } + + // Note that most of the other computation happens *after* we fix the + // single bit errors, otherwise we would need to recompute the fields + // again. + mm->ca = msg[0] & 7; // Responder capabilities. + + // ICAO address + mm->aa1 = msg[1]; + mm->aa2 = msg[2]; + mm->aa3 = msg[3]; + + // DF 17 type (assuming this is a DF17, otherwise not used) + mm->metype = msg[4] >> 3; // Extended squitter message type. + mm->mesub = msg[4] & 7; // Extended squitter message subtype. + + // Fields for DF4,5,20,21 + mm->fs = msg[0] & 7; // Flight status for DF4,5,20,21 + mm->dr = msg[1] >> 3 & 31; // Request extraction of downlink request. + mm->um = ((msg[1] & 7)<<3)| // Request extraction of downlink request. + msg[2]>>5; + + // In the squawk (identity) field bits are interleaved like that (message + // bit 20 to bit 32): + // + // C1-A1-C2-A2-C4-A4-ZERO-B1-D1-B2-D2-B4-D4 + // + // So every group of three bits A, B, C, D represent an integer from 0 to + // 7. + // + // The actual meaning is just 4 octal numbers, but we convert it into a + // base ten number tha happens to represent the four octal numbers. + // + // For more info: http://en.wikipedia.org/wiki/Gillham_code + { + int a, b, c, d; + + a = ((msg[3] & 0x80) >> 5) | + ((msg[2] & 0x02) >> 0) | + ((msg[2] & 0x08) >> 3); + b = ((msg[3] & 0x02) << 1) | + ((msg[3] & 0x08) >> 2) | + ((msg[3] & 0x20) >> 5); + c = ((msg[2] & 0x01) << 2) | + ((msg[2] & 0x04) >> 1) | + ((msg[2] & 0x10) >> 4); + d = ((msg[3] & 0x01) << 2) | + ((msg[3] & 0x04) >> 1) | + ((msg[3] & 0x10) >> 4); + mm->identity = a*1000 + b*100 + c*10 + d; + } + + // DF 11 & 17: try to populate our ICAO addresses whitelist. DFs with an AP + // field (xored addr and crc), try to decode it. + if (mm->msgtype != 11 && mm->msgtype != 17) { + // Check if we can check the checksum for the Downlink Formats where + // the checksum is xored with the aircraft ICAO address. We try to + // brute force it using a list of recently seen aircraft addresses. + if (brute_force_ap(self, msg, mm)) { + // We recovered the message, mark the checksum as valid. + mm->crcok = 1; + } else { + mm->crcok = 0; + } + } else { + // If this is DF 11 or DF 17 and the checksum was ok, we can add this + // address to the list of recently seen addresses. + if (mm->crcok && mm->errorbit == -1) { + uint32_t addr = (mm->aa1 << 16) | (mm->aa2 << 8) | mm->aa3; + add_recently_seen_icao_addr(self, addr); + } + } + + // Decode 13 bit altitude for DF0, DF4, DF16, DF20 + if (mm->msgtype == 0 || mm->msgtype == 4 || + mm->msgtype == 16 || mm->msgtype == 20) { + mm->altitude = decode_ac13_field(msg, &mm->unit); + } + + // Decode extended squitter specific stuff. + if (mm->msgtype == 17) { + // Decode the extended squitter message. + + if (mm->metype >= 1 && mm->metype <= 4) { + // Aircraft Identification and Category + mm->aircraft_type = mm->metype-1; + mm->flight[0] = (ais_charset)[msg[5]>>2]; + mm->flight[1] = ais_charset[((msg[5]&3)<<4)|(msg[6]>>4)]; + mm->flight[2] = ais_charset[((msg[6]&15)<<2)|(msg[7]>>6)]; + mm->flight[3] = ais_charset[msg[7]&63]; + mm->flight[4] = ais_charset[msg[8]>>2]; + mm->flight[5] = ais_charset[((msg[8]&3)<<4)|(msg[9]>>4)]; + mm->flight[6] = ais_charset[((msg[9]&15)<<2)|(msg[10]>>6)]; + mm->flight[7] = ais_charset[msg[10]&63]; + mm->flight[8] = '\0'; + } else if (mm->metype >= 9 && mm->metype <= 18) { + // Airborne position Message + mm->fflag = msg[6] & (1<<2); + mm->tflag = msg[6] & (1<<3); + mm->altitude = decode_ac12_field(msg, &mm->unit); + mm->raw_latitude = ((msg[6] & 3) << 15) | + (msg[7] << 7) | + (msg[8] >> 1); + mm->raw_longitude = ((msg[8]&1) << 16) | + (msg[9] << 8) | + msg[10]; + } else if (mm->metype == 19 && mm->mesub >= 1 && mm->mesub <= 4) { + // Airborne Velocity Message + if (mm->mesub == 1 || mm->mesub == 2) { + mm->ew_dir = (msg[5]&4) >> 2; + mm->ew_velocity = ((msg[5]&3) << 8) | msg[6]; + mm->ns_dir = (msg[7]&0x80) >> 7; + mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + mm->vert_rate_source = (msg[8]&0x10) >> 4; + mm->vert_rate_sign = (msg[8]&0x8) >> 3; + mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + // Compute velocity and angle from the two speed components + mm->velocity = sqrt(mm->ns_velocity*mm->ns_velocity+ + mm->ew_velocity*mm->ew_velocity); + if (mm->velocity) { + int ewv = mm->ew_velocity; + int nsv = mm->ns_velocity; + double heading; + + if (mm->ew_dir) ewv *= -1; + if (mm->ns_dir) nsv *= -1; + heading = atan2(ewv, nsv); + + // Convert to degrees. + mm->heading = heading * 360 / (M_PI*2); + // We don't want negative values but a 0-360 scale. + if (mm->heading < 0) mm->heading += 360; + } else { + mm->heading = 0; + } + } else if (mm->mesub == 3 || mm->mesub == 4) { + mm->heading_is_valid = msg[5] & (1<<2); + mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + (msg[6] >> 3)); + } + } + } + mm->phase_corrected = 0; // Set to 1 by the caller if needed. +} + +// Turn I/Q samples pointed by `data` into the magnitude vector pointed by `mag` +void mode_s_compute_magnitude_vector(unsigned char *data, uint16_t *mag, uint32_t size) { + uint32_t j; + + // Compute the magnitude vector. It's just SQRT(I^2 + Q^2), but we rescale + // to the 0-255 range to exploit the full resolution. + for (j = 0; j < size; j += 2) { + int i = data[j]-127; + int q = data[j+1]-127; + + if (i < 0) i = -i; + if (q < 0) q = -q; + mag[j/2] = maglut[i*129+q]; + } +} + +// Return -1 if the message is out of fase left-side +// Return 1 if the message is out of fase right-size +// Return 0 if the message is not particularly out of phase. +// +// Note: this function will access mag[-1], so the caller should make sure to +// call it only if we are not at the start of the current buffer. +int detect_out_of_phase(uint16_t *mag) { + if (mag[3] > mag[2]/3) return 1; + if (mag[10] > mag[9]/3) return 1; + if (mag[6] > mag[7]/3) return -1; + if (mag[-1] > mag[1]/3) return -1; + return 0; +} + +// This function does not really correct the phase of the message, it just +// applies a transformation to the first sample representing a given bit: +// +// If the previous bit was one, we amplify it a bit. +// If the previous bit was zero, we decrease it a bit. +// +// This simple transformation makes the message a bit more likely to be +// correctly decoded for out of phase messages: +// +// When messages are out of phase there is more uncertainty in sequences of the +// same bit multiple times, since 11111 will be transmitted as continuously +// altering magnitude (high, low, high, low...) +// +// However because the message is out of phase some part of the high is mixed +// in the low part, so that it is hard to distinguish if it is a zero or a one. +// +// However when the message is out of phase passing from 0 to 1 or from 1 to 0 +// happens in a very recognizable way, for instance in the 0 -> 1 transition, +// magnitude goes low, high, high, low, and one of of the two middle samples +// the high will be *very* high as part of the previous or next high signal +// will be mixed there. +// +// Applying our simple transformation we make more likely if the current bit is +// a zero, to detect another zero. Symmetrically if it is a one it will be more +// likely to detect a one because of the transformation. In this way similar +// levels will be interpreted more likely in the correct way. +void apply_phase_correction(uint16_t *mag) { + int j; + + mag += 16; // Skip preamble. + for (j = 0; j < (MODE_S_LONG_MSG_BITS-1)*2; j += 2) { + if (mag[j] > mag[j+1]) { + // One + mag[j+2] = (mag[j+2] * 5) / 4; + } else { + // Zero + mag[j+2] = (mag[j+2] * 4) / 5; + } + } +} + +// Detect a Mode S messages inside the magnitude buffer pointed by 'mag' and of +// size 'maglen' bytes. Every detected Mode S message is convert it into a +// stream of bits and passed to the function to display it. +void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + unsigned char bits[MODE_S_LONG_MSG_BITS]; + unsigned char msg[MODE_S_LONG_MSG_BITS/2]; + uint16_t aux[MODE_S_LONG_MSG_BITS*2]; + uint32_t j; + int use_correction = 0; + + // The Mode S preamble is made of impulses of 0.5 microseconds at the + // following time offsets: + // + // 0 - 0.5 usec: first impulse. + // 1.0 - 1.5 usec: second impulse. + // 3.5 - 4 usec: third impulse. + // 4.5 - 5 usec: last impulse. + // + // Since we are sampling at 2 Mhz every sample in our magnitude vector is + // 0.5 usec, so the preamble will look like this, assuming there is an + // impulse at offset 0 in the array: + // + // 0 ----------------- + // 1 - + // 2 ------------------ + // 3 -- + // 4 - + // 5 -- + // 6 - + // 7 ------------------ + // 8 -- + // 9 ------------------- + for (j = 0; j < maglen - MODE_S_FULL_LEN*2; j++) { + int low, high, delta, i, errors; + int good_message = 0; + + if (use_correction) goto good_preamble; // We already checked it. + + // First check of relations between the first 10 samples representing a + // valid preamble. We don't even investigate further if this simple + // test is not passed. + if (!(mag[j] > mag[j+1] && + mag[j+1] < mag[j+2] && + mag[j+2] > mag[j+3] && + mag[j+3] < mag[j] && + mag[j+4] < mag[j] && + mag[j+5] < mag[j] && + mag[j+6] < mag[j] && + mag[j+7] > mag[j+8] && + mag[j+8] < mag[j+9] && + mag[j+9] > mag[j+6])) + { + continue; + } + + // The samples between the two spikes must be < than the average of the + // high spikes level. We don't test bits too near to the high levels as + // signals can be out of phase so part of the energy can be in the near + // samples. + high = (mag[j]+mag[j+2]+mag[j+7]+mag[j+9])/6; + if (mag[j+4] >= high || + mag[j+5] >= high) + { + continue; + } + + // Similarly samples in the range 11-14 must be low, as it is the space + // between the preamble and real data. Again we don't test bits too + // near to high levels, see above. + if (mag[j+11] >= high || + mag[j+12] >= high || + mag[j+13] >= high || + mag[j+14] >= high) + { + continue; + } + +good_preamble: + // If the previous attempt with this message failed, retry using + // magnitude correction. + if (use_correction) { + memcpy(aux, mag+j+MODE_S_PREAMBLE_US*2, sizeof(aux)); + if (j && detect_out_of_phase(mag+j)) { + apply_phase_correction(mag+j); + } + // TODO ... apply other kind of corrections. + } + + // Decode all the next 112 bits, regardless of the actual message size. + // We'll check the actual message type later. + errors = 0; + for (i = 0; i < MODE_S_LONG_MSG_BITS*2; i += 2) { + low = mag[j+i+MODE_S_PREAMBLE_US*2]; + high = mag[j+i+MODE_S_PREAMBLE_US*2+1]; + delta = low-high; + if (delta < 0) delta = -delta; + + if (i > 0 && delta < 256) { + bits[i/2] = bits[i/2-1]; + } else if (low == high) { + // Checking if two adiacent samples have the same magnitude is + // an effective way to detect if it's just random noise that + // was detected as a valid preamble. + bits[i/2] = 2; // error + if (i < MODE_S_SHORT_MSG_BITS*2) errors++; + } else if (low > high) { + bits[i/2] = 1; + } else { + // (low < high) for exclusion + bits[i/2] = 0; + } + } + + // Restore the original message if we used magnitude correction. + if (use_correction) + memcpy(mag+j+MODE_S_PREAMBLE_US*2, aux, sizeof(aux)); + + // Pack bits into bytes + for (i = 0; i < MODE_S_LONG_MSG_BITS; i += 8) { + msg[i/8] = + bits[i]<<7 | + bits[i+1]<<6 | + bits[i+2]<<5 | + bits[i+3]<<4 | + bits[i+4]<<3 | + bits[i+5]<<2 | + bits[i+6]<<1 | + bits[i+7]; + } + + int msgtype = msg[0]>>3; + int msglen = mode_s_msg_len_by_type(msgtype)/8; + + // Last check, high and low bits are different enough in magnitude to + // mark this as real message and not just noise? + delta = 0; + for (i = 0; i < msglen*8*2; i += 2) { + delta += abs(mag[j+i+MODE_S_PREAMBLE_US*2]- + mag[j+i+MODE_S_PREAMBLE_US*2+1]); + } + delta /= msglen*4; + + // Filter for an average delta of three is small enough to let almost + // every kind of message to pass, but high enough to filter some random + // noise. + if (delta < 10*255) { + use_correction = 0; + continue; + } + + // If we reached this point, and error is zero, we are very likely with + // a Mode S message in our hands, but it may still be broken and CRC + // may not be correct. This is handled by the next layer. + if (errors == 0 || (self->aggressive && errors < 3)) { + struct mode_s_msg mm; + + // Decode the received message + mode_s_decode(self, &mm, msg); + + // Skip this message if we are sure it's fine. + if (mm.crcok) { + j += (MODE_S_PREAMBLE_US+(msglen*8))*2; + good_message = 1; + if (use_correction) + mm.phase_corrected = 1; + } + + // Pass data to the next layer + if (self->check_crc == 0 || mm.crcok) { + cb(self, &mm); + } + } + + // Retry with phase correction if possible. + if (!good_message && !use_correction) { + j--; + use_correction = 1; + } else { + use_correction = 0; + } + } +} diff --git a/CPE455/lab08/mode-s_15.met b/CPE455/lab08/mode-s_15.met new file mode 100644 index 0000000..6890836 --- /dev/null +++ b/CPE455/lab08/mode-s_15.met @@ -0,0 +1,511 @@ + + ******************************************************************** + ****** ****** + ****** LDRA Testbed (R) Quality Review Report ****** + ****** ****** + ****** File : /home/student/anw0044/CPE455/lab08/mode-s.c ****** + ****** ****** + ******************************************************************** + + + Report Production + ----------------- + * C/C++ LDRA Testbed Version: 9.8.2 + * Report Produced On: Tue Mar 29 2022 at 10:19:30 + * Metrics Data File: /apps/ldra2019/ldra_toolsuite/metpen.dat + + Report Configuration + -------------------- + * Report Format: By Metric + * Procedures Reported: All Procedures + * Show Metric Passes: Yes + * Show Metric Fails: Yes + * Reporting Scope: Source file and associated header + + Analysis Phases Completed + ------------------------- + * Static: Yes + * Complexity: Yes + * Dataflow: Yes + + + + + -------------------------------------------------------------------------------- + + + Contents + -------- + + Metrics + * List of File and Procedure Metrics + + Procedure Table + + Results + * Results for each Metric + + + + List of Metrics to be Displayed + ------------------------------- + Reformatted Code Information for File + ------------------------------------- + * Total reformatted Lines, Total comments in ref. Code, Executable ref. Lines, Non-executable ref. Lines + Number of Procedures, Total source Lines, Expansion Factor. + + Procedure Information + --------------------- + * Executable reformatted Lines, Number of Basic Blocks, Average Length of Basic Blocks, Procedure Entry Points + Procedure Exit Points. + + Comments Associated with Procedures (% of total) + ------------------------------------------------ + * Total Comments, Comments in Headers, Comments in Declarations, Comments in Executable Code + Blank Lines. + + Ratio of Comments to Executable lines (%) + ----------------------------------------- + * Executable reformatted Lines, Total Comments/Exe. Lines, Header Comments/Exe. Lines, Declaration Comments/Exe. Lines + Code Comments/Exe. Lines. + + Complexity Metrics + ------------------ + * Knots, Cyclomatic Complexity, Essential Knots, Essential Cyclomatic Complexity + Procedure Structured (SPV). + + Halsteads Metrics + ----------------- + * Total Operators, Total Operands, Unique Operators, Unique Operands + Vocabulary, Length, Volume. + + Loop/Interval Analysis + ---------------------- + * Number of Loops, Depth of Loop Nesting, Number of Order 1 Intervals, Maximum Interval Nesting + Reducible (Intervals). + + LCSAJ and Unreachability + ------------------------ + * Total LCSAJs, Reachable LCSAJs, Unreachable LCSAJs, Maximum LCSAJ Density + Unreachable Lines, Unreachable Branches. + + Dataflow Information + -------------------- + * Globals in Procedure, File Fan in, Fan Out. + + + + + -------------------------------------------------------------------------------- + + + ************** + * * + * mode-s.c * + * * + ************** + + ***************************************************** + * * + * Overall Results - Percentage of metrics passing * + * * + ***************************************************** + + Total Metrics: 48 + Clarity Metrics: 14 (of which 4 are whole file only) + Maintainability Metrics: 11 (of which 7 are whole file only) + Testability Metrics: 15 (of which 7 are whole file only) + + + =============================================================================================== + PROCEDURE ALL METRICS CLARITY MAINTAINABILITY TESTABILITY + =============================================================================================== + + mode_s_init 85 ######### 70 ######## 75 ######## 88 ######### + mode_s_checksum 96 ########## 90 ########## 100 ########### 100 ########### + mode_s_msg_len_by_type 74 ######## 40 ##### 100 ########### 88 ######### + fix_single_bit_errors 74 ######## 70 ######## 50 ###### 75 ######## + fix_two_bits_errors 74 ######## 80 ######### 25 ### 75 ######## + icao_cache_has_addr 81 ######### 50 ###### 100 ########### 100 ########### + add_recently_seen_icao_addr + 78 ######## 40 ##### 100 ########### 100 ########### + icao_addr_was_recently_seen + 81 ######### 50 ###### 100 ########### 100 ########### + brute_force_ap 89 ######### 90 ########## 100 ########### 88 ######### + decode_ac13_field 78 ######## 70 ######## 75 ######## 88 ######### + + decode_ac12_field 85 ######### 70 ######## 100 ########### 88 ######### + mode_s_decode 78 ######## 90 ########## 50 ###### 38 #### + mode_s_compute_magnitude_vector + 85 ######### 60 ####### 100 ########### 100 ########### + detect_out_of_phase 81 ######### 60 ####### 100 ########### 88 ######### + apply_phase_correction 96 ########## 90 ########## 100 ########### 100 ########### + mode_s_detect 63 ####### 90 ########## 0 38 #### + + Total for mode-s.c 89 ######### 100 ########### 82 ######### 80 ######### + + + + -------------------------------------------------------------------------------- + + + ************************************************** + * * + * File and Procedure Results, Metric by Metric * + * * + ************************************************** + + + + Reformatted Code Information for File (mode-s.c) + ------------------------------------------------ + + ============================================================================================================================== + FILE TOTAL REF. TOTAL EXECUTABLE NON-EXECUTABLE NUMBER OF TOTAL EXPANSION + LINES COMMENTS REF. LINES REF. LINES PROCEDURES SRC. LINES FACTOR + ============================================================================================================================== + + Total for mode-s.c 1407 (P) 242 (P) (17%) 918 (P) (65%) 247 (P) (18%) 16 (P) 740 (P) 1.90 (P) + + + + -------------------------------------------------------------------------------- + + Procedure Information (mode-s.c) + -------------------------------- + + ================================================================================= + PROCEDURE EXECUTABLE BASIC AVE. BLOCK PROCEDURE PROCEDURE + LINES BLOCKS LENGTH ENTRIES EXITS + ================================================================================= + + mode_s_init 35 (P) 11 (P) 3.18 (P) 1 (P) 1 (P) + mode_s_checksum 27 (P) 10 (P) 2.70 (P) 1 (P) 1 (P) + mode_s_msg_len_by_type 23 (P) 11 (P) 2.09 (P) 1 (P) 3 (F) + fix_single_bit_errors 38 (P) 8 (P) 4.75 (P) 1 (P) 2 (F) + fix_two_bits_errors 49 (P) 12 (P) 4.08 (P) 1 (P) 2 (F) + icao_cache_has_addr 9 (P) 1 (P) 9.00 (F) 1 (P) 1 (P) + add_recently_seen_icao_addr + 7 (P) 1 (P) 7.00 (F) 1 (P) 1 (P) + icao_addr_was_recently_seen + 14 (P) 4 (P) 3.50 (P) 1 (P) 1 (P) + brute_force_ap 42 (P) 13 (P) 3.23 (P) 1 (P) 2 (F) + decode_ac13_field 25 (P) 8 (P) 3.12 (P) 1 (P) 2 (F) + + decode_ac12_field 16 (P) 6 (P) 2.67 (P) 1 (P) 3 (F) + mode_s_decode 285 (F) 69 (F) 4.13 (P) 1 (P) 1 (P) + mode_s_compute_magnitude_vector + 28 (P) 9 (P) 3.11 (P) 1 (P) 1 (P) + detect_out_of_phase 39 (P) 13 (P) 3.00 (P) 1 (P) 5 (F) + apply_phase_correction 26 (P) 8 (P) 3.25 (P) 1 (P) 1 (P) + mode_s_detect 255 (F) 90 (F) 2.83 (P) 1 (P) 1 (P) + + Total for mode-s.c 918 (P) 274 (P) 3.35 (P) 1 (P) 13 (F) + + + + -------------------------------------------------------------------------------- + + Comments Associated with Procedures (% of total) (mode-s.c) + ----------------------------------------------------------- + + ====================================================================================================== + PROCEDURE TOTAL IN IN IN BLANK + COMMENTS HEADERS DECLARATIONS EXECUTABLE CODE COMMENTS + ====================================================================================================== + + mode_s_init 9 (F) 1 (F) (11%) 0 (P) (0%) 8 (P) (89%) 1 (P) + mode_s_checksum 20 (P) 18 (P) (90%) 0 (P) (0%) 2 (P) (10%) 5 (P) + mode_s_msg_len_by_type 2 (F) 2 (F) (100%) 0 (P) (0%) 0 (F) (0%) 0 (P) + fix_single_bit_errors 6 (F) 3 (F) (50%) 0 (P) (0%) 3 (P) (50%) 0 (P) + fix_two_bits_errors 11 (P) 3 (F) (27%) 0 (P) (0%) 8 (P) (73%) 0 (P) + icao_cache_has_addr 4 (F) 2 (F) (50%) 2 (P) (50%) 0 (F) (0%) 0 (P) + add_recently_seen_icao_addr + 3 (F) 3 (F) (100%) 0 (P) (0%) 0 (F) (0%) 0 (P) + icao_addr_was_recently_seen + 3 (F) 3 (F) (100%) 0 (P) (0%) 0 (F) (0%) 0 (P) + brute_force_ap 23 (P) 15 (P) (65%) 0 (P) (0%) 8 (P) (35%) 5 (P) + decode_ac13_field 7 (F) 2 (F) (29%) 0 (P) (0%) 5 (P) (71%) 0 (P) + + decode_ac12_field 5 (F) 2 (F) (40%) 0 (P) (0%) 3 (P) (60%) 0 (P) + mode_s_decode 51 (P) 2 (F) (4%) 2 (P) (4%) 47 (P) (92%) 4 (P) + mode_s_compute_magnitude_vector + 3 (F) 1 (F) (33%) 2 (P) (67%) 0 (F) (0%) 0 (P) + detect_out_of_phase 6 (F) 6 (P) (100%) 0 (P) (0%) 0 (F) (0%) 1 (P) + apply_phase_correction 29 (P) 26 (P) (90%) 0 (P) (0%) 3 (P) (10%) 6 (P) + mode_s_detect 60 (P) 3 (F) (5%) 22 (P) (37%) 35 (P) (58%) 3 (P) + + Total for mode-s.c 242 (P) 92 (P) (38%) 28 (P) (12%) 122 (P) (50%) 25 (P) + + + + -------------------------------------------------------------------------------- + + Ratio of Comments to Executable lines (%) (mode-s.c) + ---------------------------------------------------- + + =================================================================================== + PROCEDURE EXECUTABLE TOTAL IN IN IN + LINES COMMENTS(%) HEADERS(%) DECL.(%) CODE(%) + =================================================================================== + + mode_s_init 35 (P) 26 (P) 3 (P) 0 (F) 23 (P) + mode_s_checksum 27 (P) 74 (P) 67 (P) 0 (F) 7 (P) + mode_s_msg_len_by_type 23 (P) 9 (F) 9 (P) 0 (F) 0 (F) + fix_single_bit_errors 38 (P) 16 (P) 8 (P) 0 (F) 8 (P) + fix_two_bits_errors 49 (P) 22 (P) 6 (P) 0 (F) 16 (P) + icao_cache_has_addr 9 (P) 44 (P) 22 (P) 22 (P) 0 (F) + add_recently_seen_icao_addr + 7 (P) 43 (P) 43 (P) 0 (F) 0 (F) + icao_addr_was_recently_seen + 14 (P) 21 (P) 21 (P) 0 (F) 0 (F) + brute_force_ap 42 (P) 55 (P) 36 (P) 0 (F) 19 (P) + decode_ac13_field 25 (P) 28 (P) 8 (P) 0 (F) 20 (P) + + decode_ac12_field 16 (P) 31 (P) 13 (P) 0 (F) 19 (P) + mode_s_decode 285 (F) 18 (P) 1 (P) 1 (P) 16 (P) + mode_s_compute_magnitude_vector + 28 (P) 11 (P) 4 (P) 7 (P) 0 (F) + detect_out_of_phase 39 (P) 15 (P) 15 (P) 0 (F) 0 (F) + apply_phase_correction 26 (P) 112 (P) 100 (P) 0 (F) 12 (P) + mode_s_detect 255 (F) 24 (P) 1 (P) 9 (P) 14 (P) + + Total for mode-s.c 918 (P) 26 (P) 10 3 (P) 13 (P) + + + + -------------------------------------------------------------------------------- + + Complexity Metrics (mode-s.c) + ----------------------------- + + ====================================================================================== + PROCEDURE CYCLOMATIC ESSENTIAL ESS. CYCL. STRUCTURED + KNOTS COMPLEXITY KNOTS COMPLEXITY PROC (SPV) + ====================================================================================== + + mode_s_init 8 (F) 4 (P) 0 (P) 1 (P) Yes (P) + mode_s_checksum 5 (P) 4 (P) 0 (P) 1 (P) Yes (P) + mode_s_msg_len_by_type 3 (P) 6 (P) 0 (P) 1 (P) Yes (P) + fix_single_bit_errors 7 (F) 3 (P) 4 (F) 3 (P) No (F) + fix_two_bits_errors 13 (F) 4 (P) 7 (F) 4 (F) No (F) + icao_cache_has_addr 0 (P) 1 (P) 0 (P) 1 (P) Yes (P) + add_recently_seen_icao_addr + 0 (P) 1 (P) 0 (P) 1 (P) Yes (P) + icao_addr_was_recently_seen + 0 (P) 3 (P) 0 (P) 1 (P) Yes (P) + brute_force_ap 2 (P) 9 (P) 2 (P) 3 (P) No (F) + decode_ac13_field 4 (P) 3 (P) 3 (F) 3 (P) No (F) + + decode_ac12_field 3 (P) 2 (P) 0 (P) 1 (P) Yes (P) + mode_s_decode 7 (F) 34 (F) 0 (P) 1 (P) Yes (P) + mode_s_compute_magnitude_vector + 4 (P) 4 (P) 0 (P) 1 (P) Yes (P) + detect_out_of_phase 4 (P) 5 (P) 0 (P) 1 (P) Yes (P) + apply_phase_correction 5 (P) 3 (P) 0 (P) 1 (P) Yes (P) + mode_s_detect 36 (F) 42 (F) 13 (F) 6 (F) No (F) + + Total for mode-s.c 101 (F) 113 (P) 29 (P) 15 (P) No (F) + + + + -------------------------------------------------------------------------------- + + Halsteads Metrics (mode-s.c) + ---------------------------- + + ============================================================================================================ + FILE TOTAL TOTAL UNIQUE UNIQUE + OPERATORS OPERANDS OPERATORS OPERANDS VOCABULARY LENGTH VOLUME + ============================================================================================================ + + Total for mode-s.c 952 (F) 908 (P) 33 (P) 174 (P) 207 (P) 1860 (P) 14309 (P) + + + + -------------------------------------------------------------------------------- + + Loop/Interval Analysis (mode-s.c) + --------------------------------- + + ======================================================================================= + PROCEDURE NUMBER OF NESTING ORDER 1 MAX. INT. REDUCIBLE + LOOPS DEPTH INTERVALS NESTING (INTERVALS) + ======================================================================================= + + mode_s_init 2 (P) 2 (P) 4 (P) 3 (P) Yes (P) + mode_s_checksum 1 (P) 1 (P) 2 (P) 2 (P) Yes (P) + mode_s_msg_len_by_type 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + fix_single_bit_errors 1 (P) 1 (P) 2 (P) 2 (P) Yes (P) + fix_two_bits_errors 2 (P) 2 (P) 4 (P) 3 (P) Yes (P) + icao_cache_has_addr 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + add_recently_seen_icao_addr + 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + icao_addr_was_recently_seen + 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + brute_force_ap 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + decode_ac13_field 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + + decode_ac12_field 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + mode_s_decode 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + mode_s_compute_magnitude_vector + 1 (P) 1 (P) 2 (P) 2 (P) Yes (P) + detect_out_of_phase 0 (P) 0 (P) 1 (P) 1 (P) Yes (P) + apply_phase_correction 1 (P) 1 (P) 2 (P) 2 (P) Yes (P) + mode_s_detect 4 (P) 2 (P) 6 (F) 3 (P) Yes (P) + + Total for mode-s.c 12 (P) 2 (P) 16 (P) 3 (P) Yes (P) + + + + -------------------------------------------------------------------------------- + + LCSAJ and Unreachability (mode-s.c) + ----------------------------------- + + ================================================================================================= + FILE TOTAL REACHABLE UNREACHABLE MAX. LCSAJ UNREACHABLE UNREACHABLE + LCSAJS LCSAJS LCSAJS DENSITY LINES BRANCHES + ================================================================================================= + + Total for mode-s.c 387 (P) 376 (P) 11 (F) 18 (P) 0 (P) 6 (P) + + + + -------------------------------------------------------------------------------- + + Dataflow Information (mode-s.c) + ------------------------------- + + ===================================================== + PROCEDURE GLOBALS IN FILE FAN + PROCEDURE FAN IN OUT + ===================================================== + + mode_s_init 0 (P) 0 (P) 3 (P) + mode_s_checksum 1 (P) 4 (P) 0 (P) + mode_s_msg_len_by_type 0 (P) 2 (P) 0 (P) + fix_single_bit_errors 1 (P) 1 (P) 2 (P) + fix_two_bits_errors 1 (P) 1 (P) 2 (P) + icao_cache_has_addr 0 (P) 2 (P) 0 (P) + add_recently_seen_icao_addr + 0 (P) 1 (P) 2 (P) + icao_addr_was_recently_seen + 0 (P) 1 (P) 2 (P) + brute_force_ap 1 (P) 1 (P) 3 (P) + decode_ac13_field 0 (P) 1 (P) 0 (P) + + decode_ac12_field 0 (P) 1 (P) 0 (P) + mode_s_decode 1 (P) 1 (P) 11 (F) + mode_s_compute_magnitude_vector + 0 (P) 0 (P) 0 (P) + detect_out_of_phase 0 (P) 1 (P) 0 (P) + apply_phase_correction 0 (P) 1 (P) 0 (P) + mode_s_detect 1 (P) 0 (P) 7 (F) + + Total for mode-s.c 6 (P) 18 (P) 32 (P) + + + + -------------------------------------------------------------------------------- + + + ****************** + * * + * Key to Terms * + * * + ****************** + + + Clarity + ------- + Metrics that indicate how easy it is likely to be + to read and understand the purpose of a source code module or procedure: + + * Executable ref. Lines + * Total Comments + * Comments in Headers + * Comments in Declarations + * Comments in Executable Code + * Blank Lines + * Total Comments/Exe. Lines + * Declaration Comments/Exe. Lines + * Code Comments/Exe. Lines + * Average Length of Basic Blocks + * Unique Operands + * Total LCSAJs + * Depth of Loop Nesting + * Expansion Factor + + + Testability + ----------- + Metrics that indicate the amount testing that will be required, + particularly with respect to achieving high Dynamic Coverage : + + * Knots + * Cyclomatic Complexity + * Executable reformatted Lines + * Number of Basic Blocks + * Total Operands + * Number of Loops + * Procedure Exit Points + * Number of Procedures + * Total LCSAJs + * Unreachable LCSAJs + * Maximum LCSAJ Density + * Unreachable Lines + * Unreachable Branches + * File Fan in + * Fan Out + + + Maintainability + --------------- + Metrics that indicate the level of consideration that must be given + to modifying a source code module or procedure: + + * Essential Knots + * Essential Cyclomatic Complexity + * Knots + * Cyclomatic Complexity + * Vocabulary + * Number of Procedures + * Total LCSAJs + * Unreachable LCSAJs + * Maximum LCSAJ Density + * Unreachable Lines + * Unreachable Branches + + + Metric results Pass/Fail indicators. + ------------------------------------ + The display of Pass and Fail indicators is controlled by two environment variables: + + ===================================================================== + RESULT ENVIRONMENT FLAG INDICATOR + ===================================================================== + Pass SHOW_METRIC_PASS (P) + Fail SHOW_METRIC_FAIL (F) + + + + Upper and lower limits for a "Total for " metric can be derived from the + upper and lower limits for a procedure where appropriate. + This is achieved using the 'c' marker in the Metrics Data File. + + The base for this calculation is currently variable between files: + (Number of procedures in each source file) + + + + -------------------------------------------------------------------------------- + =========================================================== + * * + * End of Quality Review Report * + * * + * Copyright (C) 2019 Liverpool Data Research Associates * + * * + =========================================================== + + diff --git a/CPE455/lab08/mode-s_15.ovr b/CPE455/lab08/mode-s_15.ovr new file mode 100644 index 0000000..2c21875 --- /dev/null +++ b/CPE455/lab08/mode-s_15.ovr @@ -0,0 +1,104 @@ + + ******************************************************************** + ****** ****** + ****** LDRA Testbed (R) Test Manager Report ****** + ****** ****** + ****** File : /home/student/anw0044/CPE455/lab08/mode-s.c ****** + ****** ****** + ******************************************************************** + + + Report Production + ----------------- + * C/C++ LDRA Testbed Version: 9.8.2 + * Report Produced On: Tue Mar 29 2022 at 10:18:34 + + Report Configuration + -------------------- + * Report Format: Procedure Listing * Reporting Scope: Source file and associated header + + + + ------------------------------------------------------------ + + + ************************ + * * + * Code Review Report * + * * + ************************ + + =========================================================================================== + QUALITY RESULT ------ NUMBER OF UNIQUE VIOLATIONS ------ + % IN FUNCTION # IN FUNCTION BREAKDOWN + =========================================================================================== + mode_s_detect Fail 14 ## Number - 27 4-M 18-C 5-O + apply_phase_correction Fail 4 # Number - 8 5-C 3-O + detect_out_of_phase Fail 5 # Number - 9 6-C 3-O + mode_s_compute_magnitude_vector + Fail 6 # Number - 12 9-C 3-O + mode_s_decode Fail 14 ## Number - 27 1-M 22-C 4-O + decode_ac12_field Fail 7 # Number - 13 9-C 4-O + decode_ac13_field Fail 7 # Number - 14 9-C 5-O + brute_force_ap Fail 10 ## Number - 19 1-M 13-C 5-O + icao_addr_was_recently_seen + Fail 5 # Number - 9 6-C 3-O + add_recently_seen_icao_addr + Fail 1 # Number - 2 2-C + icao_cache_has_addr Fail 2 # Number - 4 2-C 2-O + fix_two_bits_errors Fail 5 # Number - 10 1-M 6-C 3-O + fix_single_bit_errors Fail 5 # Number - 10 1-M 6-C 3-O + mode_s_msg_len_by_type Fail 3 # Number - 5 2-C 3-O + mode_s_checksum Fail 6 # Number - 12 9-C 3-O + mode_s_init Fail 4 # Number - 8 6-C 2-O + (189 out of 375 checked) + + + + ------------------------------------------------------------ + + + *************************** + * * + * Quality Review Report * + * * + *************************** + + =============================================================================================== + TESTABILITY MAINTAINABILITY CLARITY ALL METRICS + =============================================================================================== + + mode_s_detect 38 #### 0 90 ########## 63 ####### + apply_phase_correction 100 ########### 100 ########### 90 ########## 96 ########## + detect_out_of_phase 88 ######### 100 ########### 60 ####### 81 ######### + mode_s_compute_magnitude_vector + 100 ########### 100 ########### 60 ####### 85 ######### + mode_s_decode 38 #### 50 ###### 90 ########## 78 ######## + decode_ac12_field 88 ######### 100 ########### 70 ######## 85 ######### + decode_ac13_field 88 ######### 75 ######## 70 ######## 78 ######## + brute_force_ap 88 ######### 100 ########### 90 ########## 89 ######### + icao_addr_was_recently_seen + 100 ########### 100 ########### 50 ###### 81 ######### + add_recently_seen_icao_addr + 100 ########### 100 ########### 40 ##### 78 ######## + + icao_cache_has_addr 100 ########### 100 ########### 50 ###### 81 ######### + fix_two_bits_errors 75 ######## 25 ### 80 ######### 74 ######## + fix_single_bit_errors 75 ######## 50 ###### 70 ######## 74 ######## + mode_s_msg_len_by_type 88 ######### 100 ########### 40 ##### 74 ######## + mode_s_checksum 100 ########### 100 ########### 90 ########## 96 ########## + mode_s_init 88 ######### 75 ######## 70 ######## 85 ######### + + + + ------------------------------------------------------------ + + =========================================================== + * * + * End of Test Manager Report * + * * + * Copyright (C) 2019 Liverpool Data Research Associates * + * * + =========================================================== + + diff --git a/CPE455/lab08/mode-s_15.rpf b/CPE455/lab08/mode-s_15.rpf new file mode 100644 index 0000000..6ba80a3 --- /dev/null +++ b/CPE455/lab08/mode-s_15.rpf @@ -0,0 +1,3453 @@ + + ******************************************************************** + ****** ****** + ****** LDRA Testbed (R) Code Review Report ****** + ****** ****** + ****** File : /home/student/anw0044/CPE455/lab08/mode-s.c ****** + ****** ****** + ******************************************************************** + + + + ---------------------------------------------------------------------------------------------------- + *************************** + * * + * Overall Result: FAIL * + * * + *************************** + ---------------------------------------------------------------------------------------------------- + + + Report Production + ----------------- + * C/C++ LDRA Testbed Version: 9.8.2 * Config. File: /apps/ldra2019/ldra_toolsuite/c/creport.dat + * Produced On: Tue Mar 29 2022 at 10:19:09 * Penalty File: /apps/ldra2019/ldra_toolsuite/c/cpen.dat + + + Report Configuration + -------------------- + * Report Level: Detailed Report * Procedures Reported: Fails Only + * Programming Standards Model: MISRA-C:2012(Ed 3 Rev 1) + * Line Numbers refer to: Original Source File + * Violation Details: Violations and Associated Source + * Reporting Scope: Source file and associated header + + + Analysis Phases Run + ------------------- + * Static: Yes * Complexity: Yes + * Static Data Flow: Yes * Information Flow: No + * Cross Reference: Yes + + + + + + + -------------------------------------------------------------------------------- + + + Contents + -------- + Overall Code Review Summary + * Totals of Violations for each Standard + * Table of Procedure Results + * Table of Global Basic Information + + Report on Program Components + * Code Review Results Global Program and Selected Procedures + + Key to Terms + + + + + ********************************* + * * + * Overall Code Review Summary * + * * + ********************************* + + + Totals of Violations for Selected Code Review Standards + ------------------------------------------------------- + '-' indicates required Analysis Phase results are not yet available. + 'Off' indicates that the standard is switched off in the Penalty File (pen.dat). + '*' indicates standard has been violated. + + ============================================================================================================== + NUMBER OF + VIOLATIONS LDRA CODE MANDATORY STANDARDS MISRA-C:2012(ED 3 REV 1) CODE + ============================================================================================================== + 0 36 S Function has no return statement. MISRA-C:2012(Ed 3 Rev 1) R.17.4 + 0 54 S Sizeof operator with side effects. MISRA-C:2012(Ed 3 Rev 1) R.13.6 + 0 66 S Function with empty return expression. MISRA-C:2012(Ed 3 Rev 1) R.17.4 + 2 401 S * Use of sizeof on an array parameter. MISRA-C:2012(Ed 3 Rev 1) R.12.5 + 0 407 S free used on string. MISRA-C:2012(Ed 3 Rev 1) R.22.2 + 0 480 S String function params access same variable. MISRA-C:2012(Ed 3 Rev 1) R.19.1 + 0 483 S Freed parameter is not heap item. MISRA-C:2012(Ed 3 Rev 1) R.22.2 + 0 484 S Attempt to use already freed object. MISRA-C:2012(Ed 3 Rev 1) R.22.2 + 0 489 S Insufficient space for operation. MISRA-C:2012(Ed 3 Rev 1) R.1.3,R.21.17,R.21.18 + 1 496 S * Function call with no prior declaration. MISRA-C:2012(Ed 3 Rev 1) R.17.3 + 0 545 S Assignment of overlapping storage. MISRA-C:2012(Ed 3 Rev 1) R.19.1 + 0 591 S Inappropriate use of file pointer. MISRA-C:2012(Ed 3 Rev 1) R.22.5 + 0 600 S Argument of strlen is unterminated. MISRA-C:2012(Ed 3 Rev 1) R.21.17 + 0 614 S Use of static keyword in array parameter. MISRA-C:2012(Ed 3 Rev 1) R.17.6 + 0 631 S Declaration not reachable. MISRA-C:2012(Ed 3 Rev 1) R.9.1 + 0 644 S realloc ptr does not originate from allocation function. + MISRA-C:2012(Ed 3 Rev 1) R.22.2 + 0 647 S Overlapping data items in memcpy. MISRA-C:2012(Ed 3 Rev 1) R.19.1 + 0 652 S Object created by malloc used before initialisation. + MISRA-C:2012(Ed 3 Rev 1) R.9.1 + 0 663 S Invalid value may be passed to function in . + MISRA-C:2012(Ed 3 Rev 1) R.21.13 + 0 2 D Function does not return a value on all paths. MISRA-C:2012(Ed 3 Rev 1) R.17.4 + 0 48 D Attempt to write to unopened file. MISRA-C:2012(Ed 3 Rev 1) R.22.6 + 0 51 D Attempt to read from freed memory. MISRA-C:2012(Ed 3 Rev 1) R.22.2 + 0 53 D Attempt to use uninitialised pointer. MISRA-C:2012(Ed 3 Rev 1) R.9.1 + 3 69 D * Procedure contains UR data flow anomalies. MISRA-C:2012(Ed 3 Rev 1) R.9.1 + 0 98 D Attempt to write to file opened read only. MISRA-C:2012(Ed 3 Rev 1) R.22.4 + 0 107 D Attempt to change system call capture string. MISRA-C:2012(Ed 3 Rev 1) R.21.19 + 0 113 D File closed more than once. MISRA-C:2012(Ed 3 Rev 1) R.22.6 + 0 125 D free called on variable with no allocated space. MISRA-C:2012(Ed 3 Rev 1) R.22.2 + 0 133 D Pointer from system function used after subsequent call. + MISRA-C:2012(Ed 3 Rev 1) R.21.20 + 7 140 D * Copy source parameter not checked before use. MISRA-C:2012(Ed 3 Rev 1) R.21.17 + 0 66 X Insufficient array space at call. MISRA-C:2012(Ed 3 Rev 1) R.1.3,R.21.17,R.21.18 + 0 70 X Array has insufficient space. MISRA-C:2012(Ed 3 Rev 1) R.1.3,R.21.17,R.21.18 + 0 71 X Insufficient space for copy. MISRA-C:2012(Ed 3 Rev 1) R.1.3,R.21.17,R.21.18 + 0 79 X Size mismatch in memcpy/memset. MISRA-C:2012(Ed 3 Rev 1) R.1.3,R.21.18 + + + + + ============================================================================================================== + NUMBER OF + VIOLATIONS LDRA CODE REQUIRED STANDARDS MISRA-C:2012(ED 3 REV 1) CODE + ============================================================================================================== + 0 1 S Procedure name reused. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 2 9 S * Assignment operation in expression. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.2,R.13.4 + 0 11 S No brackets to loop body. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + 17 12 S * No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + 0 20 S Parameter not declared explicitly. MISRA-C:2012(Ed 3 Rev 1) R.8.1 + 0 21 S Number of parameters does not match. MISRA-C:2012(Ed 3 Rev 1) R.1.1,R.1.3 + 0 30 S Deprecated usage of ++ or -- operators found. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.2,R.13.3 + 0 35 S Static procedure is not explicitly called in code analysed. + MISRA-C:2012(Ed 3 Rev 1) R.2.1 + 0 37 S Procedure parameter has a type but no identifier. MISRA-C:2012(Ed 3 Rev 1) R.8.2 + 0 39 S Unsuitable type for loop variable. MISRA-C:2012(Ed 3 Rev 1) R.14.1 + 0 43 S Use of setjmp/longjmp. MISRA-C:2012(Ed 3 Rev 1) R.21.4 + 0 44 S Use of banned function, type or variable. MISRA-C:2012(Ed 3 Rev 1) D.4.12,R.1.3,R.17.1,R.21.3,R.21.6,R.21.7,R.21.8,R.21.9,R.21.10,R.21.12 + 0 47 S Array bound exceeded. MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 0 48 S No default case in switch statement. MISRA-C:2012(Ed 3 Rev 1) R.16.4 + 57 50 S * Use of shift operator on signed type. MISRA-C:2012(Ed 3 Rev 1) R.10.1 + 1 51 S * Shifting value too far. MISRA-C:2012(Ed 3 Rev 1) R.12.2 + 0 52 S Unsigned expression negated. MISRA-C:2012(Ed 3 Rev 1) R.10.1 + 0 57 S Statement with no side effect. MISRA-C:2012(Ed 3 Rev 1) R.2.2 + 3 59 S * Else alternative missing in if. MISRA-C:2012(Ed 3 Rev 1) R.15.7 + 0 60 S Empty switch statement. MISRA-C:2012(Ed 3 Rev 1) R.16.6 + 0 61 S Switch contains default only. MISRA-C:2012(Ed 3 Rev 1) R.16.6 + 0 62 S Switch case not terminated with break. MISRA-C:2012(Ed 3 Rev 1) R.16.3 + 0 63 S Empty parameter list to procedure/function. MISRA-C:2012(Ed 3 Rev 1) R.8.2 + 0 64 S Void procedure used in expression. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 65 S Void variable passed as parameter. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 71 S Pointer assignment to wider scope. MISRA-C:2012(Ed 3 Rev 1) R.18.6 + 0 72 S Signed bit field less than 2 bits wide. MISRA-C:2012(Ed 3 Rev 1) R.6.2 + 0 73 S Bit field not signed or unsigned int. MISRA-C:2012(Ed 3 Rev 1) R.6.1 + 0 78 S Macro parameter not in brackets. MISRA-C:2012(Ed 3 Rev 1) R.20.7 + 0 83 S Octal number found. MISRA-C:2012(Ed 3 Rev 1) R.7.1 + 0 86 S Attempt to define reserved word. MISRA-C:2012(Ed 3 Rev 1) R.20.4,R.21.1 + 0 88 S Procedure is not pure assembler. MISRA-C:2012(Ed 3 Rev 1) D.4.3 + 0 92 S Duplicate use of a name in an enumeration. MISRA-C:2012(Ed 3 Rev 1) R.5.3 + 13 93 S * Value is not of appropriate type. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + 0 94 S Casting operation on a pointer. MISRA-C:2012(Ed 3 Rev 1) R.11.1,R.11.2,R.11.3,R.11.7 + 0 95 S Casting operation to a pointer. MISRA-C:2012(Ed 3 Rev 1) R.11.1,R.11.2,R.11.3,R.11.5,R.11.7 + 11 96 S * Use of mixed mode arithmetic. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + 0 100 S #include filename is non conformant. MISRA-C:2012(Ed 3 Rev 1) R.20.2 + 0 101 S Function return type inconsistent. MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 0 102 S Function and prototype return inconsistent (MR). MISRA-C:2012(Ed 3 Rev 1) R.8.4 + 0 103 S Function and prototype param inconsistent (MR). MISRA-C:2012(Ed 3 Rev 1) R.8.4 + 0 104 S Struct field initialisation incorrect. MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 0 105 S Initialisation brace { } fault. MISRA-C:2012(Ed 3 Rev 1) R.9.2 + 0 107 S Type mismatch in ternary expression. MISRA-C:2012(Ed 3 Rev 1) R.10.4 + 0 109 S Array subscript is not integral. MISRA-C:2012(Ed 3 Rev 1) R.10.1 + 0 112 S Typedef name redeclared. MISRA-C:2012(Ed 3 Rev 1) R.5.6 + 0 113 S Non standard character in source. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 30 114 S * Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + 0 118 S main must be int (void) or int (int,char*[]). MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 119 S Nested comment found. MISRA-C:2012(Ed 3 Rev 1) R.3.1 + 135 120 S * Use of bit operator on signed type. MISRA-C:2012(Ed 3 Rev 1) R.10.1 + 0 121 S Use of boolean expression in switch. MISRA-C:2012(Ed 3 Rev 1) R.16.7 + 0 122 S Use of abort, exit, etc. MISRA-C:2012(Ed 3 Rev 1) R.21.8 + 0 123 S Use of underlying enum representation value. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4 + 0 125 S Use of ## or # in a macro. MISRA-C:2012(Ed 3 Rev 1) R.20.10,R.20.12 + 0 126 S A #if has no #endif in the same file. MISRA-C:2012(Ed 3 Rev 1) R.20.14 + 0 127 S Array has no bounds specified. MISRA-C:2012(Ed 3 Rev 1) R.8.11,R.9.5 + 0 128 S Parameter has same name as global variable. MISRA-C:2012(Ed 3 Rev 1) R.5.3 + 0 130 S Included file is not permitted. MISRA-C:2012(Ed 3 Rev 1) R.21.5,R.21.6,R.21.10,R.21.11 + 0 131 S Name reused in inner scope. MISRA-C:2012(Ed 3 Rev 1) R.5.3 + 2 132 S * Assignment operator in boolean expression. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.4 + 0 134 S Volatile variable in complex expression. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.2 + 0 135 S Parameter list is KR. MISRA-C:2012(Ed 3 Rev 1) R.8.1,R.8.2 + 0 136 S Bit operator with boolean operand. MISRA-C:2012(Ed 3 Rev 1) R.10.1 + 0 139 S Construct leads to infeasible code. MISRA-C:2012(Ed 3 Rev 1) R.14.3 + 0 140 S Infeasible loop condition found. MISRA-C:2012(Ed 3 Rev 1) R.14.3 + 0 145 S #if has invalid expression. MISRA-C:2012(Ed 3 Rev 1) R.1.1 + 0 147 S Spurious characters after preprocessor directive. MISRA-C:2012(Ed 3 Rev 1) R.20.13 + 0 156 S Use of 'defined' keyword in macro body. MISRA-C:2012(Ed 3 Rev 1) R.21.1 + 0 157 S Modification of string literal. MISRA-C:2012(Ed 3 Rev 1) R.7.4 + 0 172 S Variable declared multiply. MISRA-C:2012(Ed 3 Rev 1) R.8.5 + 0 176 S Non standard escape sequence in source. MISRA-C:2012(Ed 3 Rev 1) R.1.3,R.4.1 + 0 203 S Cast on a constant value. MISRA-C:2012(Ed 3 Rev 1) R.11.8 + 0 218 S Name is used in standard libraries. MISRA-C:2012(Ed 3 Rev 1) R.21.2 + 0 219 S User name starts with underscore. MISRA-C:2012(Ed 3 Rev 1) R.21.1,R.21.2 + 0 243 S Included file not protected with #define. MISRA-C:2012(Ed 3 Rev 1) D.4.10 + 0 245 S Case statement in nested block. MISRA-C:2012(Ed 3 Rev 1) R.16.2 + 0 248 S Divide by zero in preprocessor directive. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 0 249 S Operation not appropriate to boolean type. MISRA-C:2012(Ed 3 Rev 1) R.10.1 + 0 252 S Lower case suffix to literal number. MISRA-C:2012(Ed 3 Rev 1) R.7.3 + 0 270 S For loop initialisation is not simple. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + 5 271 S * For loop incrementation is not simple. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + 0 276 S Case is not part of switch enumeration. MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 0 296 S Function declared at block scope. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 322 S Default is not last case of switch. MISRA-C:2012(Ed 3 Rev 1) R.16.5 + 0 323 S Switch has more than one default case. MISRA-C:2012(Ed 3 Rev 1) R.1.1 + 0 324 S Macro call has wrong number of parameters. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 325 S Inconsistent use of tag. MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 326 S Declaration is missing type. MISRA-C:2012(Ed 3 Rev 1) R.8.1 + 0 329 S Operation not appropriate to plain char. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2 + 5 330 S * Implicit conversion of underlying type (MR). MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + 21 331 S * Literal value requires a U suffix. MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + 0 332 S Widening cast on complex integer expression (MR). MISRA-C:2012(Ed 3 Rev 1) R.10.8 + 0 333 S Widening cast on complex float expression (MR). MISRA-C:2012(Ed 3 Rev 1) R.10.8 + 0 335 S Operator defined contains illegal items. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 336 S #if expansion contains define operator. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 337 S Undefined macro variable in #if. MISRA-C:2012(Ed 3 Rev 1) R.20.9 + 0 341 S Preprocessor construct as macro parameter. MISRA-C:2012(Ed 3 Rev 1) R.20.6 + 0 342 S Extra chars after preprocessor directive. MISRA-C:2012(Ed 3 Rev 1) R.20.13 + 0 343 S #else has no #if, etc in the same file. MISRA-C:2012(Ed 3 Rev 1) R.20.14 + 0 344 S Cast on volatile value. MISRA-C:2012(Ed 3 Rev 1) R.11.8 + 2 345 S * Bit operator with floating point operand. MISRA-C:2012(Ed 3 Rev 1) R.1.1,R.10.1 + 29 361 S * Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + 0 374 S Name conflict with typedef. MISRA-C:2012(Ed 3 Rev 1) R.5.6 + 9 382 S * (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + 0 383 S Identifier name matches macro name. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 384 S Identifier matches macro name in 31 chars. MISRA-C:2012(Ed 3 Rev 1) R.5.4,R.5.5 + 0 385 S MISRA switch statement syntax violation. MISRA-C:2012(Ed 3 Rev 1) R.16.1 + 0 387 S Enum init not integer-constant-expression. MISRA-C:2012(Ed 3 Rev 1) R.1.1 + 0 389 S Bool value incremented/decremented. MISRA-C:2012(Ed 3 Rev 1) R.10.1 + 0 397 S Array initialisation has insufficient items. MISRA-C:2012(Ed 3 Rev 1) R.9.3 + 4 403 S * Negative (or potentially negative) shift. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.12.2 + 0 404 S Array initialisation has too many items. MISRA-C:2012(Ed 3 Rev 1) R.1.1 + 0 406 S Use of ++ or -- on RHS of && or || operator. MISRA-C:2012(Ed 3 Rev 1) R.13.5 + 0 408 S Volatile variable accessed on RHS of && or ||. MISRA-C:2012(Ed 3 Rev 1) R.13.5 + 0 410 S Switch empty default has no comment (MR). MISRA-C:2012(Ed 3 Rev 1) R.16.4 + 0 411 S Inappropriate value assigned to enum. MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 0 412 S Undefined behaviour, \ before E-O-F. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 427 S Filename in #include not in < > or " ". MISRA-C:2012(Ed 3 Rev 1) R.20.3 + 0 428 S No {} for switch. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + 0 429 S Empty middle expression in for loop. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + 0 430 S Inconsistent usage of loop control variable. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + 0 431 S Char used instead of (un)signed char. MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 0 432 S Inappropriate type - should be plain char. MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 0 433 S Type conversion without cast. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.11.5 + 28 434 S * Signed/unsigned conversion without cast. MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + 4 435 S * Float/integer conversion without cast. MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + 50 436 S * Declaration does not specify an array. MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 0 437 S < > <= >= used on different object pointers. MISRA-C:2012(Ed 3 Rev 1) R.18.3 + 0 438 S Pointer subtraction not addressing one array. MISRA-C:2012(Ed 3 Rev 1) R.18.2 + 0 439 S Cast from pointer to integral type. MISRA-C:2012(Ed 3 Rev 1) R.11.2,R.11.4,R.11.6,R.11.7 + 0 440 S Cast from integral type to pointer. MISRA-C:2012(Ed 3 Rev 1) R.11.1,R.11.2,R.11.4,R.11.6,R.11.7 + 0 441 S Float cast to non-float. MISRA-C:2012(Ed 3 Rev 1) R.10.8 + 0 442 S Signed integral type cast to unsigned. MISRA-C:2012(Ed 3 Rev 1) R.10.8 + 0 443 S Unsigned integral type cast to signed. MISRA-C:2012(Ed 3 Rev 1) R.10.8 + 0 444 S Integral type cast to non-integral. MISRA-C:2012(Ed 3 Rev 1) R.10.8 + 0 445 S Narrower float conversion without cast. MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 4 446 S * Narrower int conversion without cast. MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 0 450 S Wide string and string concatenated. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 451 S No cast for widening complex float expression (MR). + MISRA-C:2012(Ed 3 Rev 1) R.10.6,R.10.7 + 1 452 S * No cast for widening complex int expression (MR). MISRA-C:2012(Ed 3 Rev 1) R.10.6,R.10.7 + 3 458 S * Implicit conversion: actual to formal param (MR). MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 0 461 S Identifier with ambiguous linkage. MISRA-C:2012(Ed 3 Rev 1) R.8.8 + 0 465 S Struct/union not completely specified. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 477 S Empty else clause following else if. MISRA-C:2012(Ed 3 Rev 1) R.15.7 + 0 481 S Array with no bounds in struct. MISRA-C:2012(Ed 3 Rev 1) R.1.1,R.18.7 + 0 482 S Incomplete structure referenced. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 486 S Incorrect number of formats in output function. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 487 S Insufficient space allocated. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 488 S Value outside range of underlying type. MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + 0 493 S Numeric overflow. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14,R.12.4 + 0 494 S Numeric underflow. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14,R.12.4 + 1 497 S * Type is incomplete in translation unit. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 506 S Use of boolean with relational operator. MISRA-C:2012(Ed 3 Rev 1) R.10.1 + 0 509 S goto label is backwards. MISRA-C:2012(Ed 3 Rev 1) R.15.2 + 1 511 S * Jump into nested block. MISRA-C:2012(Ed 3 Rev 1) R.15.3 + 0 520 S Bit field is not bool or explicit integral. MISRA-C:2012(Ed 3 Rev 1) R.6.1 + 0 531 S Literal zero used in pointer context. MISRA-C:2012(Ed 3 Rev 1) R.11.9 + 2 550 S * Unsuffixed hex or octal is unsigned, add U. MISRA-C:2012(Ed 3 Rev 1) R.7.2 + 0 553 S Function and proto should both be static. MISRA-C:2012(Ed 3 Rev 1) R.8.8 + 0 554 S Cast to an unrelated type. MISRA-C:2012(Ed 3 Rev 1) R.11.2,R.11.3 + 0 565 S Assignment to wider scope. MISRA-C:2012(Ed 3 Rev 1) R.18.6 + 4 567 S * Pointer arithmetic is not on array. MISRA-C:2012(Ed 3 Rev 1) R.18.1,R.18.4 + 0 573 S Macro concatenation of uni char names. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 575 S Linkage differs from previous declaration. MISRA-C:2012(Ed 3 Rev 1) R.8.8 + 0 576 S Function pointer is of wrong type. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 580 S Macro redefinition without using #undef. MISRA-C:2012(Ed 3 Rev 1) R.1.1,R.20.4 + 0 581 S Loop conditions are independent. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + 0 582 S const object reassigned. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 587 S Const local variable not immediately initialised. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 589 S Format is not appropriate type. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 590 S Mode fault in fopen. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 606 S Cast involving function pointer. MISRA-C:2012(Ed 3 Rev 1) R.11.1 + 0 608 S Use of explicitly undefined language feature. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 611 S Line splice used in // comment. MISRA-C:2012(Ed 3 Rev 1) R.3.2 + 0 612 S inline function should be declared static. MISRA-C:2012(Ed 3 Rev 1) R.8.10 + 0 613 S Use of restrict keyword. MISRA-C:2012(Ed 3 Rev 1) R.8.14 + 0 615 S Conditional operator has incompatible types. MISRA-C:2012(Ed 3 Rev 1) R.1.1 + 0 616 S Preprocessor result not 0 or 1. MISRA-C:2012(Ed 3 Rev 1) R.20.8 + 0 618 S Use of memcmp between structures. MISRA-C:2012(Ed 3 Rev 1) R.21.16 + 0 620 S Initialisation designator duplicated. MISRA-C:2012(Ed 3 Rev 1) R.9.4 + 1 621 S * Variable-length array declared. MISRA-C:2012(Ed 3 Rev 1) R.18.8 + 0 622 S Macro parameters are not unique within limits. MISRA-C:2012(Ed 3 Rev 1) R.5.4 + 0 623 S String assigned to non const object. MISRA-C:2012(Ed 3 Rev 1) R.7.4 + 0 626 S #define of keyword. MISRA-C:2012(Ed 3 Rev 1) R.20.4 + 0 627 S Initialiser both positional and designational. MISRA-C:2012(Ed 3 Rev 1) R.9.4 + 0 629 S Divide by zero found. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 0 630 S Duplicated enumeration value. MISRA-C:2012(Ed 3 Rev 1) R.8.12 + 0 635 S Cast from pointer to float type. MISRA-C:2012(Ed 3 Rev 1) R.11.6,R.11.7 + 0 636 S Cast from float type to pointer. MISRA-C:2012(Ed 3 Rev 1) R.11.6,R.11.7 + 0 637 S # operand followed by ##. MISRA-C:2012(Ed 3 Rev 1) R.20.11 + 0 642 S Function return type with array field. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 645 S realloc ptr type does not match target type. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 646 S Struct initialisation has too many items. MISRA-C:2012(Ed 3 Rev 1) R.1.1 + 0 649 S Use of unallocated flexible array. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 650 S Flexible array copy ignores last member. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 655 S Standard library copy/compare objects have different types. + MISRA-C:2012(Ed 3 Rev 1) R.21.15 + 0 661 S memcmp used to compare null terminated strings. MISRA-C:2012(Ed 3 Rev 1) R.21.14 + 0 662 S EOF compared with char. MISRA-C:2012(Ed 3 Rev 1) R.22.7 + 2 692 S * Array index is negative. MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 0 6 D Recursion in procedure calls found. MISRA-C:2012(Ed 3 Rev 1) R.17.2 + 2 8 D * DD data flow anomalies found. MISRA-C:2012(Ed 3 Rev 1) R.2.2 + 0 17 D Identifier not unique within 31 characters. MISRA-C:2012(Ed 3 Rev 1) R.5.1,R.5.2,R.5.3 + 0 18 D Identifier name reused. MISRA-C:2012(Ed 3 Rev 1) R.5.3 + 0 26 D Variable should be defined once in only one file. MISRA-C:2012(Ed 3 Rev 1) R.8.6 + 0 27 D Variable should be declared static. MISRA-C:2012(Ed 3 Rev 1) R.8.7,R.8.8 + 0 28 D Potentially infinite loop found. MISRA-C:2012(Ed 3 Rev 1) R.2.1 + 0 33 D No real declaration for external variable. MISRA-C:2012(Ed 3 Rev 1) R.8.6 + 0 34 D Procedure name re-used in different files. MISRA-C:2012(Ed 3 Rev 1) R.8.6 + 0 35 D Expression has side effects. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.2,R.13.5 + 0 36 D Prototype and definition name mismatch. MISRA-C:2012(Ed 3 Rev 1) R.8.3,R.8.4 + 0 42 D Local pointer returned in function result. MISRA-C:2012(Ed 3 Rev 1) R.18.6 + 0 43 D Divide by zero found. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 0 45 D Pointer not checked for null before use. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 0 49 D File pointer not closed on exit. MISRA-C:2012(Ed 3 Rev 1) R.22.1 + 0 50 D Memory not freed after last reference. MISRA-C:2012(Ed 3 Rev 1) R.22.1 + 1 55 D * Modification of loop counter in loop body. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + 0 60 D External object should be declared only once. MISRA-C:2012(Ed 3 Rev 1) R.8.5 + 0 61 D Procedure should be declared static. MISRA-C:2012(Ed 3 Rev 1) R.8.7,R.8.8 + 0 63 D No definition in system for prototyped procedure. MISRA-C:2012(Ed 3 Rev 1) R.8.6 + 0 65 D Void function has no side effects. MISRA-C:2012(Ed 3 Rev 1) R.2.2 + 0 72 D Potential side effect problem in expression. MISRA-C:2012(Ed 3 Rev 1) R.13.2 + 0 75 D Attempt to open file pointer more than once. MISRA-C:2012(Ed 3 Rev 1) R.22.1 + 0 76 D Procedure is not called or referenced in code analysed. + MISRA-C:2012(Ed 3 Rev 1) R.2.1 + 0 77 D Local structure returned in function result. MISRA-C:2012(Ed 3 Rev 1) R.18.6 + 0 82 D fsetpos values not generated by fgetpos. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 83 D Potentially repeated call to ungetc. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 84 D No fseek or flush before I/O. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 85 D Filename not verified before fopen. MISRA-C:2012(Ed 3 Rev 1) D.4.14 + 0 86 D User input not checked before use. MISRA-C:2012(Ed 3 Rev 1) D.4.14 + 0 87 D Illegal shared object in signal handler. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 89 D Illegal use of raise in signal handler. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 91 D Function return value potentially unused. MISRA-C:2012(Ed 3 Rev 1) D.4.7,R.17.7 + 0 103 D File opened both read and write. MISRA-C:2012(Ed 3 Rev 1) R.22.3 + 0 105 D DU anomaly dead code, var value is unused on all paths. + MISRA-C:2012(Ed 3 Rev 1) R.2.2 + 16 106 D * No prototype for non-static function. MISRA-C:2012(Ed 3 Rev 1) R.8.4 + 0 110 D More than one prototype for same function. MISRA-C:2012(Ed 3 Rev 1) R.8.5 + 0 111 D errno checked without having been set for errno setting fn. + MISRA-C:2012(Ed 3 Rev 1) R.22.8 + 2 115 D * Copy length parameter not checked before use. MISRA-C:2012(Ed 3 Rev 1) D.4.1 + 0 121 D errno neither set nor checked for errno setting function. + MISRA-C:2012(Ed 3 Rev 1) R.22.8,R.22.9 + 0 122 D errno not checked after being set for errno setting fn. + MISRA-C:2012(Ed 3 Rev 1) R.22.9 + 0 123 D File pointer not checked for null before use. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 1 124 D * Var set by std lib func return not checked before use. + MISRA-C:2012(Ed 3 Rev 1) D.4.7 + 0 127 D Local or member denominator not checked before use. + MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 0 128 D Global pointer not checked within this procedure. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 0 129 D Global file pointer not checked within this procedure. + MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 1 130 D * Global set by std lib func return not checked before use. + MISRA-C:2012(Ed 3 Rev 1) D.4.7 + 1 131 D * Global denominator not checked within this procedure. + MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 0 132 D errno checked after call to non-errno setting function. + MISRA-C:2012(Ed 3 Rev 1) R.22.10 + 0 134 D errno not checked before subsequent function call. + MISRA-C:2012(Ed 3 Rev 1) R.22.9 + 0 135 D Pointer assigned to NULL may be dereferenced. MISRA-C:2012(Ed 3 Rev 1) D.4.1 + 0 136 D Global pointer assigned to NULL may be dereferenced. + MISRA-C:2012(Ed 3 Rev 1) D.4.1 + 0 137 D Parameter used as denominator not checked before use. + MISRA-C:2012(Ed 3 Rev 1) D.4.1 + 0 1 X Declaration types do not match across a system. MISRA-C:2012(Ed 3 Rev 1) R.8.4 + 0 4 X Identifier reuse: struct/union tag repeated. MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 5 X Identifier reuse: struct vs union. MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 6 X Identifier reuse: struct/union tag vs enum tag. MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 7 X Identifier reuse: tag vs procedure. MISRA-C:2012(Ed 3 Rev 1) R.5.7,R.5.8,R.5.9 + 0 8 X Identifier reuse: tag vs procedure parameter. MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 9 X Identifier reuse: tag vs variable. MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 10 X Identifier reuse: tag vs label (MR). MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 11 X Identifier reuse: tag vs typedef. MISRA-C:2012(Ed 3 Rev 1) R.5.6,R.5.7 + 0 12 X Identifier reuse: tag vs macro. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 13 X Identifier reuse: tag vs component. MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 14 X Identifier reuse: tag vs enum constant. MISRA-C:2012(Ed 3 Rev 1) R.5.7 + 0 15 X Identifier reuse: persistent var vs tag. MISRA-C:2012(Ed 3 Rev 1) R.5.7,R.5.8,R.5.9 + 0 16 X Identifier reuse: typedef vs variable. MISRA-C:2012(Ed 3 Rev 1) R.5.6 + 0 17 X Identifier reuse: typedef vs label (MR). MISRA-C:2012(Ed 3 Rev 1) R.5.6 + 0 18 X Identifier reuse: typedef vs typedef. MISRA-C:2012(Ed 3 Rev 1) R.5.6 + 0 19 X Identifier reuse: typedef vs procedure parameter. MISRA-C:2012(Ed 3 Rev 1) R.5.6 + 0 20 X Identifier reuse: persistent var vs typedef. MISRA-C:2012(Ed 3 Rev 1) R.5.6,R.5.8,R.5.9 + 0 21 X Identifier reuse: typedef vs macro. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 22 X Identifier reuse: typedef vs component. MISRA-C:2012(Ed 3 Rev 1) R.5.6 + 0 23 X Identifier reuse: typedef vs enum constant. MISRA-C:2012(Ed 3 Rev 1) R.5.6 + 0 24 X Identifier reuse: typedef vs procedure. MISRA-C:2012(Ed 3 Rev 1) R.5.6,R.5.8,R.5.9 + 0 25 X Identifier reuse: procedure vs procedure param. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 26 X Identifier reuse: persistent var vs label (MR). MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 27 X Identifier reuse: persist var vs persist var. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 28 X Identifier reuse: persistent var vs var. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 29 X Identifier reuse: persistent var vs procedure. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 30 X Identifier reuse: persistent var vs proc param. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 31 X Identifier reuse: procedure vs procedure. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 32 X Identifier reuse: procedure vs var. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 33 X Identifier reuse: procedure vs label (MR). MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 34 X Identifier reuse: proc vs macro. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 35 X Identifier reuse: proc vs component. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 36 X Identifier reuse: proc vs enum constant. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 37 X Identifier reuse: persistent var vs macro. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 38 X Identifier reuse: persistent var vs component. MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 39 X Identifier reuse: persistent var vs enum constant. + MISRA-C:2012(Ed 3 Rev 1) R.5.8,R.5.9 + 0 47 X Identifier reuse: component vs macro. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 48 X Identifier reuse: label vs macro (MR). MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 50 X Identifier reuse: var vs macro. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 53 X Identifier reuse: proc param vs macro. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 57 X Identifier reuse: macro vs enum constant. MISRA-C:2012(Ed 3 Rev 1) R.5.5 + 0 61 X Identifier match in 31 chars. MISRA-C:2012(Ed 3 Rev 1) R.5.1,R.5.2,R.5.3,R.5.4,R.5.5 + 0 62 X Function prototype/defn return type mismatch (MR). + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + 0 63 X Function prototype/defn param type mismatch (MR). MISRA-C:2012(Ed 3 Rev 1) R.8.3,R.8.4 + 0 64 X Array bound exceeded at call. MISRA-C:2012(Ed 3 Rev 1) R.17.5,R.18.1 + 0 68 X Parameter indexing array too big at call. MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 0 69 X Global array bound exceeded at use. MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 0 72 X Parameter indexing array too small at call. MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 0 80 X Divide by zero found. MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + 1 1 Q * Call has execution order dependant side effects. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.2,R.13.5 + 0 5 Q File does not end with new line. MISRA-C:2012(Ed 3 Rev 1) R.1.3 + 0 1 U Inter-file recursion found. MISRA-C:2012(Ed 3 Rev 1) R.17.2 + 0 1 J Unreachable Code found. MISRA-C:2012(Ed 3 Rev 1) R.2.1 + 0 3 J All internal linkage calls unreachable. MISRA-C:2012(Ed 3 Rev 1) R.2.1 + + + + ============================================================================================================== + NUMBER OF + VIOLATIONS LDRA CODE ADVISORY STANDARDS MISRA-C:2012(ED 3 REV 1) CODE + ============================================================================================================== + 1 13 S * goto detected. MISRA-C:2012(Ed 3 Rev 1) R.15.1 + 61 49 S * Logical conjunctions need brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1 + 0 53 S Use of comma operator. MISRA-C:2012(Ed 3 Rev 1) R.12.3 + 0 68 S #undef used. MISRA-C:2012(Ed 3 Rev 1) R.20.5 + 0 74 S Union declared. MISRA-C:2012(Ed 3 Rev 1) R.19.2 + 0 75 S Executable code before an included file. MISRA-C:2012(Ed 3 Rev 1) R.20.1 + 0 80 S Pointer indirection exceeds 2 levels. MISRA-C:2012(Ed 3 Rev 1) R.18.5 + 0 81 S Use of trigraph. MISRA-C:2012(Ed 3 Rev 1) R.4.2 + 4 87 S * Use of pointer arithmetic. MISRA-C:2012(Ed 3 Rev 1) R.18.4 + 62 90 S * Basic type declaration used. MISRA-C:2012(Ed 3 Rev 1) D.4.6 + 13 110 S * Use of single line comment(s) //. MISRA-C:2012(Ed 3 Rev 1) R.1.2 + 0 143 S Curly brackets used in expression. MISRA-C:2012(Ed 3 Rev 1) R.1.2 + 2 149 S * Reference parameter to procedure is reassigned. MISRA-C:2012(Ed 3 Rev 1) R.17.8 + 0 217 S Names only differ by case. MISRA-C:2012(Ed 3 Rev 1) D.4.5 + 0 293 S Non ANSI/ISO construct used. MISRA-C:2012(Ed 3 Rev 1) R.1.2 + 0 302 S Comment possibly contains code. MISRA-C:2012(Ed 3 Rev 1) D.4.4 + 0 338 S #include preceded by non preproc directives. MISRA-C:2012(Ed 3 Rev 1) R.20.1 + 0 340 S Use of function like macro. MISRA-C:2012(Ed 3 Rev 1) D.4.9 + 0 409 S More than one break or goto statement in loop. MISRA-C:2012(Ed 3 Rev 1) R.15.4 + 0 413 S User type declared but not used in code analysed. MISRA-C:2012(Ed 3 Rev 1) R.2.3,R.2.4 + 0 426 S #undef used in a block. MISRA-C:2012(Ed 3 Rev 1) R.20.5 + 0 495 S Typedef name has no size indication. MISRA-C:2012(Ed 3 Rev 1) D.4.6 + 0 610 S Label is unused. MISRA-C:2012(Ed 3 Rev 1) R.2.6 + 0 628 S Macro not used in translation unit. MISRA-C:2012(Ed 3 Rev 1) R.2.5 + 2 632 S * Use of // comment in pre-processor directive or macro defn. + MISRA-C:2012(Ed 3 Rev 1) R.1.2 + 7 7 C * Procedure has more than one exit point. MISRA-C:2012(Ed 3 Rev 1) R.15.5 + 0 1 D Unused procedure parameter. MISRA-C:2012(Ed 3 Rev 1) R.2.7 + 1 14 D * Attempt to change parameter passed by value. MISRA-C:2012(Ed 3 Rev 1) R.17.8 + 0 15 D Unused procedural parameter. MISRA-C:2012(Ed 3 Rev 1) R.2.7 + 3 25 D * Scope of variable could be reduced. MISRA-C:2012(Ed 3 Rev 1) R.8.9 + 0 104 D Structure implementation not hidden. MISRA-C:2012(Ed 3 Rev 1) D.4.8 + 8 120 D * Pointer param should be declared pointer to const. + MISRA-C:2012(Ed 3 Rev 1) R.8.13 + 1 67 X * Identifier is typographically ambiguous. MISRA-C:2012(Ed 3 Rev 1) D.4.5 + + + + Number of Mandatory Standards checked 34 + Number of Required Standards checked 308 + Number of Advisory Standards checked 33 + Number of Document Standards checked 3 + Total Standards checked 375 + Total Standards checked including Document 378 + + + + + + + ---------------------------------------------------------------------------------------------------- + =============================== + ** OVERALL RESULT: FAIL ** + =============================== + ---------------------------------------------------------------------------------------------------- + + + Out of 17 program components, 1 (5.88 %) passes ( of which 1 conditionally passes ) + and 16 fail ( of which 0 fail only because of insufficient comments ) + + + Procedure Results + ----------------- + ============================================================================================= + CODE REVIEW RESULT PROCEDURE SOURCE FILE UNIQUE VIOLATIONS FAILURE DENSITY + (VIOLS/R.LINE %) + ============================================================================================= + Conditional Pass Global Program + FAIL mode_s_init mode-s.c 4 # 26 ### + FAIL mode_s_checksum mode-s.c 6 # 67 ####### + FAIL mode_s_msg_len_by_type + mode-s.c 3 # 48 ##### + FAIL fix_single_bit_errors + mode-s.c 5 # 47 ##### + FAIL fix_two_bits_errors mode-s.c 5 # 55 ###### + FAIL icao_cache_has_addr mode-s.c 2 # 56 ###### + FAIL add_recently_seen_icao_addr + mode-s.c 1 # 29 ### + FAIL icao_addr_was_recently_seen + mode-s.c 5 # 86 ######### + FAIL brute_force_ap mode-s.c 10 ## 98 ########## + FAIL decode_ac13_field mode-s.c 7 # 168 ########### + FAIL decode_ac12_field mode-s.c 7 # 138 ########### + FAIL mode_s_decode mode-s.c 14 ## 87 ######### + FAIL mode_s_compute_magnitude_vector + mode-s.c 6 # 75 ######## + FAIL detect_out_of_phase mode-s.c 5 # 54 ###### + FAIL apply_phase_correction + mode-s.c 4 # 50 ###### + FAIL mode_s_detect mode-s.c 14 ## 53 ###### + + + + Global Information + ------------------ + + Global Basic Information + ------------------------ + Number of procedures: 16 + Number of locally uncalled procedures: 0 + Maximum loop depth: 2 + Total Cyclomatic Complexity: 113 + Number of reformatted executable lines: 918 + Number of lines of comments: 242 + + + + + + *********************************************** + * * + * Detailed Report on all Program Components * + * * + *********************************************** + + + ********************************************************** + * * + * Globals / code outside procedures - Conditional Pass * + * * + ********************************************************** + + Standards Violation Summary + --------------------------- + =========================================================================== + CODE SRC LINE VIOLATION STANDARD + =========================================================================== + O 3 Use of // comment in pre-processor directive or macro defn. + MISRA-C:2012(Ed 3 Rev 1) R.1.2 + Source : #define MODE_S_PREAMBLE_US 8 // microseconds + + O 8 Use of // comment in pre-processor directive or macro defn. + MISRA-C:2012(Ed 3 Rev 1) R.1.2 + Source : #define MODE_S_ICAO_CACHE_TTL 60 // Time to live of cached addresses. + + O 11 Basic type declaration used. : int maglut_initialized + MISRA-C:2012(Ed 3 Rev 1) D.4.6 + Source : static int maglut_initialized = 0; + + O Use of single line comment(s) //. MISRA-C:2012(Ed 3 Rev 1) R.1.2 + O 11 Scope of variable could be reduced. : maglut_initialized + MISRA-C:2012(Ed 3 Rev 1) R.8.9 + Source : static int maglut_initialized = 0; + + O 61 Scope of variable could be reduced. : mode_s_checksum_table + MISRA-C:2012(Ed 3 Rev 1) R.8.9 + Source : uint32_t mode_s_checksum_table[] = { + + O 309 Scope of variable could be reduced. : ais_charset MISRA-C:2012(Ed 3 Rev 1) R.8.9 + Source : static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789?????? + + + + + -------------------------------------------------------------------------------- + + + ************************* + * * + * mode_s_init * + * (15 to 40 mode-s.c) * + * FAIL * + * * + ************************* + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : mode_s_init + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 24 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memset(&self->icao_cache, 0, sizeof(self->icao_cache)); + + C 32 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (!maglut_initialized) { + + C 35 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : maglut[i*129+q] = round(sqrt(i*i+q*q)*360); + + C 35 Float/integer conversion without cast. : (unsigned short and double): maglut [ i * 129 + q ] = round + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : maglut[i*129+q] = round(sqrt(i*i+q*q)*360); + + C 35 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : maglut[i*129+q] = round(sqrt(i*i+q*q)*360); + + C 35 Value is not of appropriate type. : (double and short): sqrt ( i * i + q * q ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : maglut[i*129+q] = round(sqrt(i*i+q*q)*360); + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 35 + Maximum loop depth: 2 + Cyclomatic Complexity: 4 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 0 + Number of procedures which this calls: 3 + Number of comments associated with procedure: 9 + Number of comments in procedure header: 1 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 1 (self)->icao_cache + * + 1 (self)->aggressive + * + 1 (self)->check_crc + * + 1 (self)->fix_errors + * + 1 self * + + + + -------------------------------------------------------------------------------- + + + ************************* + * * + * mode_s_checksum * + * (78 to 93 mode-s.c) * + * FAIL * + * * + ************************* + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : mode_s_checksum + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 86 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int bitmask = 1 << (7-bit); + + C 86 Implicit conversion of underlying type (MR). : (signed char and int): 1 << ( 7 - bit + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : int bitmask = 1 << (7-bit); + + C 86 Use of mixed mode arithmetic. : (signed char and int): 1 << ( 7 - bit + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : int bitmask = 1 << (7-bit); + + C 86 Negative (or potentially negative) shift. : int : ( 7 - bit ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.12.2 + Source : int bitmask = 1 << (7-bit); + + C 89 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 78 + Source : uint32_t mode_s_checksum(unsigned char *msg, int bits) { + Source : if (msg[byte] & bitmask) + + C 89 Use of bit operator on signed type. : & used with int: bitmask + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : if (msg[byte] & bitmask) + + C 89 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (msg[byte] & bitmask) + + C 89 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (msg[byte] & bitmask) + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 27 + Maximum loop depth: 1 + Cyclomatic Complexity: 4 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 4 + Number of procedures which this calls: 0 + Number of comments associated with procedure: 20 + Number of comments in procedure header: 18 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 2 bits * + 1 msg * * + + + + -------------------------------------------------------------------------------- + + + **************************** + * * + * mode_s_msg_len_by_type * + * (97 to 104 mode-s.c) * + * FAIL * + * * + **************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : mode_s_msg_len_by_type + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 100 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : type == 21) + + C 102 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : else + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 23 + Maximum loop depth: 0 + Cyclomatic Complexity: 6 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 2 + Number of procedures which this calls: 0 + Number of comments associated with procedure: 2 + Number of comments in procedure header: 2 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 1 type * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * fix_single_bit_errors * + * (109 to 134 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : fix_single_bit_errors + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 115 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int bitmask = 1 << (7-(j%8)); + + C 115 Negative (or potentially negative) shift. : int : ( 7 - ( j % 8 ) ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.12.2 + Source : int bitmask = 1 << (7-(j%8)); + + C 118 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memcpy(aux, msg, bits/8); + + C 119 Use of bit operator on signed type. : ^= used with int: bitmask + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : aux[byte] ^= bitmask; // Flip j-th bit. + + C 119 Signed/unsigned conversion without cast. : (unsigned char and int): aux [ byte ] ^= bitmask + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : aux[byte] ^= bitmask; // Flip j-th bit. + + C 129 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memcpy(msg, aux, bits/8); + + M 118 Copy source parameter not checked before use. : msg + MISRA-C:2012(Ed 3 Rev 1) R.21.17 + Source : memcpy(aux, msg, bits/8); + + M 129 Copy source parameter not checked before use. : aux + MISRA-C:2012(Ed 3 Rev 1) R.21.17 + Source : memcpy(msg, aux, bits/8); + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 38 + Maximum loop depth: 1 + Cyclomatic Complexity: 3 + Essential Cyclomatic Complexity: 3 + Number of procedures which call this one: 1 + Number of procedures which this calls: 2 + Number of comments associated with procedure: 6 + Number of comments in procedure header: 3 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 2 bits * + 1 msg * * * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * fix_two_bits_errors * + * (139 to 175 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : fix_two_bits_errors + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 145 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int bitmask1 = 1 << (7-(j%8)); + + C 145 Negative (or potentially negative) shift. : int : ( 7 - ( j % 8 ) ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.12.2 + Source : int bitmask1 = 1 << (7-(j%8)); + + C 150 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int bitmask2 = 1 << (7-(i%8)); + + C 150 Negative (or potentially negative) shift. : int : ( 7 - ( i % 8 ) ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.12.2 + Source : int bitmask2 = 1 << (7-(i%8)); + + C 153 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memcpy(aux, msg, bits/8); + + C 155 Use of bit operator on signed type. : ^= used with int: bitmask1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : aux[byte1] ^= bitmask1; // Flip j-th bit. + + C 155 Signed/unsigned conversion without cast. : (unsigned char and int): aux [ byte1 ] ^= bitmask1 + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : aux[byte1] ^= bitmask1; // Flip j-th bit. + + C 156 Use of bit operator on signed type. : ^= used with int: bitmask2 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : aux[byte2] ^= bitmask2; // Flip i-th bit. + + C 156 Signed/unsigned conversion without cast. : (unsigned char and int): aux [ byte2 ] ^= bitmask2 + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : aux[byte2] ^= bitmask2; // Flip i-th bit. + + C 166 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memcpy(msg, aux, bits/8); + + C 170 Use of bit operator on signed type. : | used with int: j + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : return j | (i<<8); + + C 170 Use of shift operator on signed type. : << used with int: i + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : return j | (i<<8); + + C 170 Use of bit operator on signed type. : | used with int: ( i << 8 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : return j | (i<<8); + + M 153 Copy source parameter not checked before use. : msg + MISRA-C:2012(Ed 3 Rev 1) R.21.17 + Source : memcpy(aux, msg, bits/8); + + M 166 Copy source parameter not checked before use. : aux + MISRA-C:2012(Ed 3 Rev 1) R.21.17 + Source : memcpy(msg, aux, bits/8); + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 49 + Maximum loop depth: 2 + Cyclomatic Complexity: 4 + Essential Cyclomatic Complexity: 4 + Number of procedures which call this one: 1 + Number of procedures which this calls: 2 + Number of comments associated with procedure: 11 + Number of comments in procedure header: 3 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 2 bits * + 1 msg * * * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * icao_cache_has_addr * + * (179 to 186 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : icao_cache_has_addr + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 182 Literal value requires a U suffix. : 0x45d9f3b + MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : a = ((a >> 16) ^ a) * 0x45d9f3b; + + C 183 Literal value requires a U suffix. : 0x45d9f3b + MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : a = ((a >> 16) ^ a) * 0x45d9f3b; + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 9 + Maximum loop depth: 0 + Cyclomatic Complexity: 1 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 2 + Number of procedures which this calls: 0 + Number of comments associated with procedure: 4 + Number of comments in procedure header: 2 + Number of comments in declarations: 2 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 1 a * * + + + + -------------------------------------------------------------------------------- + + + ********************************* + * * + * add_recently_seen_icao_addr * + * (191 to 195 mode-s.c) * + * FAIL * + * * + ********************************* + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : add_recently_seen_icao_addr + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 194 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : self->icao_cache[h*2+1] = (uint32_t) time(NULL); + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 7 + Maximum loop depth: 0 + Cyclomatic Complexity: 1 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 1 + Number of procedures which this calls: 2 + Number of comments associated with procedure: 3 + Number of comments in procedure header: 3 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 2 addr * + 1 (self)->icao_cache + * + 1 self * + + + + -------------------------------------------------------------------------------- + + + ********************************* + * * + * icao_addr_was_recently_seen * + * (200 to 206 mode-s.c) * + * FAIL * + * * + ********************************* + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : icao_addr_was_recently_seen + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 203 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : int32_t t = self->icao_cache[h*2+1]; + + C 205 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : return a && a == addr && time(NULL)-t <= MODE_S_ICAO_CACHE_TTL; + + C 205 Signed/unsigned conversion without cast. : (unsigned int and int): ) - t + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : return a && a == addr && time(NULL)-t <= MODE_S_ICAO_CACHE_TTL; + + C 205 Use of mixed mode arithmetic. : (unsigned int and int): ) - t + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : return a && a == addr && time(NULL)-t <= MODE_S_ICAO_CACHE_TTL; + + C 205 Literal value requires a U suffix. : 60 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : return a && a == addr && time(NULL)-t <= MODE_S_ICAO_CACHE_TTL; + + C 205 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : return a && a == addr && time(NULL)-t <= MODE_S_ICAO_CACHE_TTL; + + C 205 Use of mixed mode arithmetic. : (unsigned int and signed char): ) - t <= 60 + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : return a && a == addr && time(NULL)-t <= MODE_S_ICAO_CACHE_TTL; + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 14 + Maximum loop depth: 0 + Cyclomatic Complexity: 3 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 1 + Number of procedures which this calls: 2 + Number of comments associated with procedure: 3 + Number of comments in procedure header: 3 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 2 addr * + 1 (self)->icao_cache * + 1 self * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * brute_force_ap * + * (223 to 263 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : brute_force_ap + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 224 Variable-length array declared. : aux[*] + MISRA-C:2012(Ed 3 Rev 1) R.18.8 + Source : unsigned char aux[MODE_S_LONG_MSG_BYTES]; + + C 241 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memcpy(aux, msg, msgbits/8); + + C 248 Implicit conversion of underlying type (MR). : (unsigned char and unsigned int): aux [ lastbyte ] ^= crc + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : aux[lastbyte] ^= crc & 0xff; + + C 248 Narrower int conversion without cast. : (unsigned char and unsigned int): aux [ lastbyte ] ^= crc + MISRA-C:2012(Ed 3 Rev 1) R.10.3 + Source : aux[lastbyte] ^= crc & 0xff; + + C 248 Literal value requires a U suffix. : 0xff + MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : aux[lastbyte] ^= crc & 0xff; + + C 248 Use of bit operator on signed type. : & used with int: 0xff + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : aux[lastbyte] ^= crc & 0xff; + + C 249 Implicit conversion of underlying type (MR). : (unsigned char and unsigned int): aux [ lastbyte - 1 ] ^= ( crc >> 8 + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : aux[lastbyte-1] ^= (crc >> 8) & 0xff; + + C 249 Narrower int conversion without cast. : (unsigned char and unsigned int): aux [ lastbyte - 1 ] ^= ( crc >> 8 + MISRA-C:2012(Ed 3 Rev 1) R.10.3 + Source : aux[lastbyte-1] ^= (crc >> 8) & 0xff; + + C 249 Literal value requires a U suffix. : 0xff + MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : aux[lastbyte-1] ^= (crc >> 8) & 0xff; + + C 249 Use of bit operator on signed type. : & used with int: 0xff + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : aux[lastbyte-1] ^= (crc >> 8) & 0xff; + + C 250 Implicit conversion of underlying type (MR). : (unsigned char and unsigned int): aux [ lastbyte - 2 ] ^= ( crc >> 16 + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : aux[lastbyte-2] ^= (crc >> 16) & 0xff; + + C 250 Narrower int conversion without cast. : (unsigned char and unsigned int): aux [ lastbyte - 2 ] ^= ( crc >> 16 + MISRA-C:2012(Ed 3 Rev 1) R.10.3 + Source : aux[lastbyte-2] ^= (crc >> 16) & 0xff; + + C 250 Literal value requires a U suffix. : 0xff + MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : aux[lastbyte-2] ^= (crc >> 16) & 0xff; + + C 250 Use of bit operator on signed type. : & used with int: 0xff + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : aux[lastbyte-2] ^= (crc >> 16) & 0xff; + + C 254 No cast for widening complex int expression (MR). : (unsigned int and unsigned char): addr = aux + MISRA-C:2012(Ed 3 Rev 1) R.10.6,R.10.7 + Source : addr = aux[lastbyte] | (aux[lastbyte-1] << 8) | (aux[lastbyte-2] << 16); + + C 254 Shifting value too far. MISRA-C:2012(Ed 3 Rev 1) R.12.2 + Source : addr = aux[lastbyte] | (aux[lastbyte-1] << 8) | (aux[lastbyte-2] << 16); + + C 255 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (icao_addr_was_recently_seen(self, addr)) { + + C 256 Signed/unsigned conversion without cast. : (int and unsigned char): mm -> aa1 = aux + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->aa1 = aux[lastbyte-2]; + + C 257 Signed/unsigned conversion without cast. : (int and unsigned char): mm -> aa2 = aux + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->aa2 = aux[lastbyte-1]; + + C 258 Signed/unsigned conversion without cast. : (int and unsigned char): mm -> aa3 = aux + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->aa3 = aux[lastbyte]; + + C 223 Type is incomplete in translation unit. : mode_s_msg + MISRA-C:2012(Ed 3 Rev 1) R.1.3 + Source : int brute_force_ap(mode_s_t *self, unsigned char *msg, struct mode_s_msg *mm) { + + M 241 Copy source parameter not checked before use. : msg + MISRA-C:2012(Ed 3 Rev 1) R.21.17 + Source : memcpy(aux, msg, msgbits/8); + + C 241 Copy length parameter not checked before use. : msgbits + MISRA-C:2012(Ed 3 Rev 1) D.4.1 + Source : memcpy(aux, msg, msgbits/8); + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 42 + Maximum loop depth: 0 + Cyclomatic Complexity: 9 + Essential Cyclomatic Complexity: 3 + Number of procedures which call this one: 1 + Number of procedures which this calls: 3 + Number of comments associated with procedure: 23 + Number of comments in procedure header: 15 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 3 (mm)->aa3 * * + 3 (mm)->aa2 * * + 3 (mm)->aa1 * * + 3 (mm)->msgbits * + 3 (mm)->msgtype * + 3 mm * + 2 msg * * + 1 (self)->icao_cache * * + 1 self * * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * decode_ac13_field * + * (267 to 290 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : decode_ac13_field + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 268 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 267 + Source : int decode_ac13_field(unsigned char *msg, int *unit) { + Source : int m_bit = msg[3] & (1<<6); + + C 268 Signed/unsigned conversion without cast. : (int and unsigned char): msg + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : int m_bit = msg[3] & (1<<6); + + C 268 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int m_bit = msg[3] & (1<<6); + + C 268 Use of bit operator on signed type. : & used with signed char: ( 1 << 6 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int m_bit = msg[3] & (1<<6); + + C 269 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 267 + Source : int decode_ac13_field(unsigned char *msg, int *unit) { + Source : int q_bit = msg[3] & (1<<4); + + C 269 Signed/unsigned conversion without cast. : (int and unsigned char): msg + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : int q_bit = msg[3] & (1<<4); + + C 269 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int q_bit = msg[3] & (1<<4); + + C 269 Use of bit operator on signed type. : & used with signed char: ( 1 << 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int q_bit = msg[3] & (1<<4); + + C 271 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (!m_bit) { + + C 273 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (q_bit) { + + C 275 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 267 + Source : int decode_ac13_field(unsigned char *msg, int *unit) { + Source : int n = ((msg[2]&31)<<6) | + + C 275 Value is not of appropriate type. : (unsigned char and signed char): ( msg [ 2 ] & + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : int n = ((msg[2]&31)<<6) | + + C 275 Use of bit operator on signed type. : & used with int: 31 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int n = ((msg[2]&31)<<6) | + + C 275 Use of shift operator on signed type. : << used with signed char: ( msg [ 2 ] & 31 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int n = ((msg[2]&31)<<6) | + + C 275 Use of bit operator on signed type. : | used with signed char: ( ( msg [ 2 ] & 31 ) << 6 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int n = ((msg[2]&31)<<6) | + + C 276 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 267 + Source : int decode_ac13_field(unsigned char *msg, int *unit) { + Source : ((msg[3]&0x80)>>2) | + + C 276 Unsuffixed hex or octal is unsigned, add U. : 0x80 + MISRA-C:2012(Ed 3 Rev 1) R.7.2 + Source : ((msg[3]&0x80)>>2) | + + C 276 Value is not of appropriate type. : (unsigned char and signed char): ( msg [ 3 ] & + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : ((msg[3]&0x80)>>2) | + + C 276 Use of bit operator on signed type. : & used with int: 0x80 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3]&0x80)>>2) | + + C 276 Use of shift operator on signed type. : >> used with signed char: ( msg [ 3 ] & 0x80 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3]&0x80)>>2) | + + C 276 Use of bit operator on signed type. : | used with signed char: ( ( msg [ 3 ] & 0x80 ) >> 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3]&0x80)>>2) | + + C 278 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 267 + Source : int decode_ac13_field(unsigned char *msg, int *unit) { + Source : (msg[3]&15); + + C 278 Value is not of appropriate type. : (unsigned char and signed char): ( msg [ 3 ] & + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : (msg[3]&15); + + C 278 Use of bit operator on signed type. : & used with int: 0x20 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : (msg[3]&15); + + C 278 Use of shift operator on signed type. : >> used with signed char: ( msg [ 3 ] & 0x20 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : (msg[3]&15); + + C 278 Use of bit operator on signed type. : | used with signed char: ( ( msg [ 3 ] & 0x20 ) >> 1 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : (msg[3]&15); + + C 278 Signed/unsigned conversion without cast. : (signed char and unsigned char): ( msg [ 3 ] & 0x20 ) >> 1 ) | ( msg + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : (msg[3]&15); + + C 278 Value is not of appropriate type. : (unsigned char and signed char): ( msg [ 3 ] & 0x20 ) >> 1 ) | ( msg [ 3 ] & + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : (msg[3]&15); + + C 278 Use of bit operator on signed type. : & used with int: 15 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : (msg[3]&15); + + C 278 Use of bit operator on signed type. : | used with signed char: ( msg [ 3 ] & 15 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : (msg[3]&15); + + C 281 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : return n*25-1000; + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 25 + Maximum loop depth: 0 + Cyclomatic Complexity: 3 + Essential Cyclomatic Complexity: 3 + Number of procedures which call this one: 1 + Number of procedures which this calls: 0 + Number of comments associated with procedure: 7 + Number of comments in procedure header: 2 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 2 *(unit) * + 2 unit * + 1 msg * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * decode_ac12_field * + * (294 to 307 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : decode_ac12_field + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 295 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 294 + Source : int decode_ac12_field(unsigned char *msg, int *unit) { + Source : int q_bit = msg[5] & 1; + + C 295 Signed/unsigned conversion without cast. : (int and unsigned char): msg + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : int q_bit = msg[5] & 1; + + C 295 Value is not of appropriate type. : (unsigned char and signed char): msg [ 5 ] & + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : int q_bit = msg[5] & 1; + + C 295 Use of bit operator on signed type. : & used with int: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int q_bit = msg[5] & 1; + + C 297 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (q_bit) { + + C 300 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 294 + Source : int decode_ac12_field(unsigned char *msg, int *unit) { + Source : int n = ((msg[5]>>1)<<4) | ((msg[6]&0xF0) >> 4); + + C 300 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 294 + Source : int decode_ac12_field(unsigned char *msg, int *unit) { + Source : int n = ((msg[5]>>1)<<4) | ((msg[6]&0xF0) >> 4); + + C 300 Unsuffixed hex or octal is unsigned, add U. : 0xF0 + MISRA-C:2012(Ed 3 Rev 1) R.7.2 + Source : int n = ((msg[5]>>1)<<4) | ((msg[6]&0xF0) >> 4); + + C 300 Value is not of appropriate type. : (unsigned char and signed char): ( msg [ 6 ] & + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : int n = ((msg[5]>>1)<<4) | ((msg[6]&0xF0) >> 4); + + C 300 Use of bit operator on signed type. : & used with int: 0xF0 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int n = ((msg[5]>>1)<<4) | ((msg[6]&0xF0) >> 4); + + C 300 Use of shift operator on signed type. : >> used with signed char: ( msg [ 6 ] & 0xF0 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int n = ((msg[5]>>1)<<4) | ((msg[6]&0xF0) >> 4); + + C 300 Use of bit operator on signed type. : | used with signed char: ( ( msg [ 6 ] & 0xF0 ) >> 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : int n = ((msg[5]>>1)<<4) | ((msg[6]&0xF0) >> 4); + + C 303 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : return n*25-1000; + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 16 + Maximum loop depth: 0 + Cyclomatic Complexity: 2 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 1 + Number of procedures which this calls: 0 + Number of comments associated with procedure: 5 + Number of comments in procedure header: 2 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 2 *(unit) * * + 2 unit * * + 1 msg * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * mode_s_decode * + * (313 to 486 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : mode_s_decode + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + C DD data flow anomalies found. MISRA-C:2012(Ed 3 Rev 1) R.2.2 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 317 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memcpy(mm->msg, msg, MODE_S_LONG_MSG_BYTES); + + C 321 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 313 + Source : void mode_s_decode(mode_s_t *self, struct mode_s_msg *mm, unsigned char *msg) { + Source : mm->msgtype = msg[0]>>3; // Downlink Format + + C 321 Signed/unsigned conversion without cast. : (int and unsigned char): mm -> msgtype = msg + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->msgtype = msg[0]>>3; // Downlink Format + + C 325 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 313 + Source : void mode_s_decode(mode_s_t *self, struct mode_s_msg *mm, unsigned char *msg) { + Source : mm->crc = ((uint32_t)msg[(mm->msgbits/8)-3] << 16) | + + C 326 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 313 + Source : void mode_s_decode(mode_s_t *self, struct mode_s_msg *mm, unsigned char *msg) { + Source : ((uint32_t)msg[(mm->msgbits/8)-2] << 8) | + + C 326 Declaration does not specify an array. : msg + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 313 + Source : void mode_s_decode(mode_s_t *self, struct mode_s_msg *mm, unsigned char *msg) { + Source : ((uint32_t)msg[(mm->msgbits/8)-2] << 8) | + + C 334 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (!mm->crcok && self->fix_errors && (mm->msgtype == 11 || mm->msgtype == 17)) { + + C 334 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (!mm->crcok && self->fix_errors && (mm->msgtype == 11 || mm->msgtype == 17)) { + + C 335 Assignment operation in expression. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.2,R.13.4 + Source : if ((mm->errorbit = fix_single_bit_errors(msg, mm->msgbits)) != -1) { + + C 335 Assignment operator in boolean expression. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.4 + Source : if ((mm->errorbit = fix_single_bit_errors(msg, mm->msgbits)) != -1) { + + C 336 Signed/unsigned conversion without cast. : (int and unsigned int): mode_s_checksum + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->crc = mode_s_checksum(msg, mm->msgbits); + + C 338 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : } else if (self->aggressive && mm->msgtype == 17 && + + C 339 Assignment operation in expression. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.2,R.13.4 + Source : (mm->errorbit = fix_two_bits_errors(msg, mm->msgbits)) != -1) { + + C 339 Assignment operator in boolean expression. MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.4 + Source : (mm->errorbit = fix_two_bits_errors(msg, mm->msgbits)) != -1) { + + C 340 Signed/unsigned conversion without cast. : (int and unsigned int): mode_s_checksum + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->crc = mode_s_checksum(msg, mm->msgbits); + + C 342 Else alternative missing in if. MISRA-C:2012(Ed 3 Rev 1) R.15.7 + Source : } + + C 348 Use of bit operator on signed type. : & used with int: msg [ 0 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ca = msg[0] & 7; // Responder capabilities. + + C 348 Use of bit operator on signed type. : & used with int: 7 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ca = msg[0] & 7; // Responder capabilities. + + C 356 Use of shift operator on signed type. : >> used with int: msg [ 4 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->metype = msg[4] >> 3; // Extended squitter message type. + + C 357 Use of bit operator on signed type. : & used with int: msg [ 4 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->mesub = msg[4] & 7; // Extended squitter message subtype. + + C 357 Use of bit operator on signed type. : & used with int: 7 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->mesub = msg[4] & 7; // Extended squitter message subtype. + + C 360 Use of bit operator on signed type. : & used with int: msg [ 0 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->fs = msg[0] & 7; // Flight status for DF4,5,20,21 + + C 360 Use of bit operator on signed type. : & used with int: 7 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->fs = msg[0] & 7; // Flight status for DF4,5,20,21 + + C 361 Use of shift operator on signed type. : >> used with int: msg [ 1 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->dr = msg[1] >> 3 & 31; // Request extraction of downlink request. + + C 361 Use of bit operator on signed type. : & used with int: msg [ 1 ] >> 3 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->dr = msg[1] >> 3 & 31; // Request extraction of downlink request. + + C 361 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : mm->dr = msg[1] >> 3 & 31; // Request extraction of downlink request. + + C 361 Use of bit operator on signed type. : & used with int: 31 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->dr = msg[1] >> 3 & 31; // Request extraction of downlink request. + + C 362 Use of bit operator on signed type. : & used with int: msg [ 1 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->um = ((msg[1] & 7)<<3)| // Request extraction of downlink request. + + C 362 Use of bit operator on signed type. : & used with int: 7 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->um = ((msg[1] & 7)<<3)| // Request extraction of downlink request. + + C 362 Use of shift operator on signed type. : << used with int: ( msg [ 1 ] & 7 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->um = ((msg[1] & 7)<<3)| // Request extraction of downlink request. + + C 362 Use of bit operator on signed type. : | used with int: ( ( msg [ 1 ] & 7 ) << 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->um = ((msg[1] & 7)<<3)| // Request extraction of downlink request. + + C 363 Use of bit operator on signed type. : | used with int: msg [ 2 ] >> 5 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : msg[2]>>5; + + C 363 Use of shift operator on signed type. : >> used with int: msg [ 2 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : msg[2]>>5; + + C 363 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : msg[2]>>5; + + C 380 Use of bit operator on signed type. : & used with int: msg [ 3 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : a = ((msg[3] & 0x80) >> 5) | + + C 380 Use of bit operator on signed type. : & used with int: 0x80 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : a = ((msg[3] & 0x80) >> 5) | + + C 380 Use of shift operator on signed type. : >> used with int: ( msg [ 3 ] & 0x80 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : a = ((msg[3] & 0x80) >> 5) | + + C 380 Use of bit operator on signed type. : | used with int: ( ( msg [ 3 ] & 0x80 ) >> 5 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : a = ((msg[3] & 0x80) >> 5) | + + C 381 Use of bit operator on signed type. : & used with int: msg [ 2 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x02) >> 0) | + + C 381 Use of bit operator on signed type. : & used with int: 0x02 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x02) >> 0) | + + C 381 Use of shift operator on signed type. : >> used with int: ( msg [ 2 ] & 0x02 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x02) >> 0) | + + C 381 Use of bit operator on signed type. : | used with int: ( ( msg [ 2 ] & 0x02 ) >> 0 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x02) >> 0) | + + C 382 Use of bit operator on signed type. : & used with int: msg [ 2 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x08) >> 3); + + C 382 Use of bit operator on signed type. : & used with int: 0x08 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x08) >> 3); + + C 382 Use of shift operator on signed type. : >> used with int: ( msg [ 2 ] & 0x08 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x08) >> 3); + + C 382 Use of bit operator on signed type. : | used with int: ( ( msg [ 2 ] & 0x08 ) >> 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x08) >> 3); + + C 383 Use of bit operator on signed type. : & used with int: msg [ 3 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : b = ((msg[3] & 0x02) << 1) | + + C 383 Use of bit operator on signed type. : & used with int: 0x02 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : b = ((msg[3] & 0x02) << 1) | + + C 383 Use of shift operator on signed type. : << used with int: ( msg [ 3 ] & 0x02 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : b = ((msg[3] & 0x02) << 1) | + + C 383 Use of bit operator on signed type. : | used with int: ( ( msg [ 3 ] & 0x02 ) << 1 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : b = ((msg[3] & 0x02) << 1) | + + C 384 Use of bit operator on signed type. : & used with int: msg [ 3 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x08) >> 2) | + + C 384 Use of bit operator on signed type. : & used with int: 0x08 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x08) >> 2) | + + C 384 Use of shift operator on signed type. : >> used with int: ( msg [ 3 ] & 0x08 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x08) >> 2) | + + C 384 Use of bit operator on signed type. : | used with int: ( ( msg [ 3 ] & 0x08 ) >> 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x08) >> 2) | + + C 385 Use of bit operator on signed type. : & used with int: msg [ 3 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x20) >> 5); + + C 385 Use of bit operator on signed type. : & used with int: 0x20 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x20) >> 5); + + C 385 Use of shift operator on signed type. : >> used with int: ( msg [ 3 ] & 0x20 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x20) >> 5); + + C 385 Use of bit operator on signed type. : | used with int: ( ( msg [ 3 ] & 0x20 ) >> 5 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x20) >> 5); + + C 386 Use of bit operator on signed type. : & used with int: msg [ 2 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : c = ((msg[2] & 0x01) << 2) | + + C 386 Use of bit operator on signed type. : & used with int: 0x01 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : c = ((msg[2] & 0x01) << 2) | + + C 386 Use of shift operator on signed type. : << used with int: ( msg [ 2 ] & 0x01 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : c = ((msg[2] & 0x01) << 2) | + + C 386 Use of bit operator on signed type. : | used with int: ( ( msg [ 2 ] & 0x01 ) << 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : c = ((msg[2] & 0x01) << 2) | + + C 387 Use of bit operator on signed type. : & used with int: msg [ 2 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x04) >> 1) | + + C 387 Use of bit operator on signed type. : & used with int: 0x04 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x04) >> 1) | + + C 387 Use of shift operator on signed type. : >> used with int: ( msg [ 2 ] & 0x04 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x04) >> 1) | + + C 387 Use of bit operator on signed type. : | used with int: ( ( msg [ 2 ] & 0x04 ) >> 1 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x04) >> 1) | + + C 388 Use of bit operator on signed type. : & used with int: msg [ 2 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x10) >> 4); + + C 388 Use of bit operator on signed type. : & used with int: 0x10 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x10) >> 4); + + C 388 Use of shift operator on signed type. : >> used with int: ( msg [ 2 ] & 0x10 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x10) >> 4); + + C 388 Use of bit operator on signed type. : | used with int: ( ( msg [ 2 ] & 0x10 ) >> 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[2] & 0x10) >> 4); + + C 389 Use of bit operator on signed type. : & used with int: msg [ 3 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : d = ((msg[3] & 0x01) << 2) | + + C 389 Use of bit operator on signed type. : & used with int: 0x01 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : d = ((msg[3] & 0x01) << 2) | + + C 389 Use of shift operator on signed type. : << used with int: ( msg [ 3 ] & 0x01 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : d = ((msg[3] & 0x01) << 2) | + + C 389 Use of bit operator on signed type. : | used with int: ( ( msg [ 3 ] & 0x01 ) << 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : d = ((msg[3] & 0x01) << 2) | + + C 390 Use of bit operator on signed type. : & used with int: msg [ 3 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x04) >> 1) | + + C 390 Use of bit operator on signed type. : & used with int: 0x04 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x04) >> 1) | + + C 390 Use of shift operator on signed type. : >> used with int: ( msg [ 3 ] & 0x04 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x04) >> 1) | + + C 390 Use of bit operator on signed type. : | used with int: ( ( msg [ 3 ] & 0x04 ) >> 1 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x04) >> 1) | + + C 391 Use of bit operator on signed type. : & used with int: msg [ 3 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x10) >> 4); + + C 391 Use of bit operator on signed type. : & used with int: 0x10 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x10) >> 4); + + C 391 Use of shift operator on signed type. : >> used with int: ( msg [ 3 ] & 0x10 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x10) >> 4); + + C 391 Use of bit operator on signed type. : | used with int: ( ( msg [ 3 ] & 0x10 ) >> 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : ((msg[3] & 0x10) >> 4); + + C 392 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : mm->identity = a*1000 + b*100 + c*10 + d; + + C 401 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (brute_force_ap(self, msg, mm)) { + + C 410 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (mm->crcok && mm->errorbit == -1) { + + C 411 Use of shift operator on signed type. : << used with int: mm -> aa1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : uint32_t addr = (mm->aa1 << 16) | (mm->aa2 << 8) | mm->aa3; + + C 411 Use of bit operator on signed type. : | used with int: ( mm -> aa1 << 16 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : uint32_t addr = (mm->aa1 << 16) | (mm->aa2 << 8) | mm->aa3; + + C 411 Use of shift operator on signed type. : << used with int: mm -> aa2 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : uint32_t addr = (mm->aa1 << 16) | (mm->aa2 << 8) | mm->aa3; + + C 411 Use of bit operator on signed type. : | used with int: ( mm -> aa2 << 8 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : uint32_t addr = (mm->aa1 << 16) | (mm->aa2 << 8) | mm->aa3; + + C 429 Use of shift operator on signed type. : >> used with int: msg [ 5 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[0] = (ais_charset)[msg[5]>>2]; + + C 430 Declaration does not specify an array. : ais_charset + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 309 + Source : static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789?????? + Source : mm->flight[1] = ais_charset[((msg[5]&3)<<4)|(msg[6]>>4)]; + + C 430 Use of bit operator on signed type. : & used with int: msg [ 5 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[1] = ais_charset[((msg[5]&3)<<4)|(msg[6]>>4)]; + + C 430 Use of bit operator on signed type. : & used with int: 3 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[1] = ais_charset[((msg[5]&3)<<4)|(msg[6]>>4)]; + + C 430 Use of shift operator on signed type. : << used with int: ( msg [ 5 ] & 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[1] = ais_charset[((msg[5]&3)<<4)|(msg[6]>>4)]; + + C 430 Use of bit operator on signed type. : | used with int: ( ( msg [ 5 ] & 3 ) << 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[1] = ais_charset[((msg[5]&3)<<4)|(msg[6]>>4)]; + + C 430 Use of shift operator on signed type. : >> used with int: msg [ 6 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[1] = ais_charset[((msg[5]&3)<<4)|(msg[6]>>4)]; + + C 430 Use of bit operator on signed type. : | used with int: ( msg [ 6 ] >> 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[1] = ais_charset[((msg[5]&3)<<4)|(msg[6]>>4)]; + + C 431 Declaration does not specify an array. : ais_charset + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 309 + Source : static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789?????? + Source : mm->flight[2] = ais_charset[((msg[6]&15)<<2)|(msg[7]>>6)]; + + C 431 Use of bit operator on signed type. : & used with int: msg [ 6 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[2] = ais_charset[((msg[6]&15)<<2)|(msg[7]>>6)]; + + C 431 Use of bit operator on signed type. : & used with int: 15 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[2] = ais_charset[((msg[6]&15)<<2)|(msg[7]>>6)]; + + C 431 Use of shift operator on signed type. : << used with int: ( msg [ 6 ] & 15 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[2] = ais_charset[((msg[6]&15)<<2)|(msg[7]>>6)]; + + C 431 Use of bit operator on signed type. : | used with int: ( ( msg [ 6 ] & 15 ) << 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[2] = ais_charset[((msg[6]&15)<<2)|(msg[7]>>6)]; + + C 431 Use of shift operator on signed type. : >> used with int: msg [ 7 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[2] = ais_charset[((msg[6]&15)<<2)|(msg[7]>>6)]; + + C 431 Use of bit operator on signed type. : | used with int: ( msg [ 7 ] >> 6 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[2] = ais_charset[((msg[6]&15)<<2)|(msg[7]>>6)]; + + C 432 Declaration does not specify an array. : ais_charset + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 309 + Source : static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789?????? + Source : mm->flight[3] = ais_charset[msg[7]&63]; + + C 432 Use of bit operator on signed type. : & used with int: msg [ 7 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[3] = ais_charset[msg[7]&63]; + + C 432 Use of bit operator on signed type. : & used with int: 63 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[3] = ais_charset[msg[7]&63]; + + C 433 Declaration does not specify an array. : ais_charset + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 309 + Source : static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789?????? + Source : mm->flight[4] = ais_charset[msg[8]>>2]; + + C 433 Use of shift operator on signed type. : >> used with int: msg [ 8 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[4] = ais_charset[msg[8]>>2]; + + C 434 Declaration does not specify an array. : ais_charset + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 309 + Source : static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789?????? + Source : mm->flight[5] = ais_charset[((msg[8]&3)<<4)|(msg[9]>>4)]; + + C 434 Use of bit operator on signed type. : & used with int: msg [ 8 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[5] = ais_charset[((msg[8]&3)<<4)|(msg[9]>>4)]; + + C 434 Use of bit operator on signed type. : & used with int: 3 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[5] = ais_charset[((msg[8]&3)<<4)|(msg[9]>>4)]; + + C 434 Use of shift operator on signed type. : << used with int: ( msg [ 8 ] & 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[5] = ais_charset[((msg[8]&3)<<4)|(msg[9]>>4)]; + + C 434 Use of bit operator on signed type. : | used with int: ( ( msg [ 8 ] & 3 ) << 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[5] = ais_charset[((msg[8]&3)<<4)|(msg[9]>>4)]; + + C 434 Use of shift operator on signed type. : >> used with int: msg [ 9 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[5] = ais_charset[((msg[8]&3)<<4)|(msg[9]>>4)]; + + C 434 Use of bit operator on signed type. : | used with int: ( msg [ 9 ] >> 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[5] = ais_charset[((msg[8]&3)<<4)|(msg[9]>>4)]; + + C 435 Declaration does not specify an array. : ais_charset + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 309 + Source : static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789?????? + Source : mm->flight[6] = ais_charset[((msg[9]&15)<<2)|(msg[10]>>6)]; + + C 435 Use of bit operator on signed type. : & used with int: msg [ 9 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[6] = ais_charset[((msg[9]&15)<<2)|(msg[10]>>6)]; + + C 435 Use of bit operator on signed type. : & used with int: 15 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[6] = ais_charset[((msg[9]&15)<<2)|(msg[10]>>6)]; + + C 435 Use of shift operator on signed type. : << used with int: ( msg [ 9 ] & 15 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[6] = ais_charset[((msg[9]&15)<<2)|(msg[10]>>6)]; + + C 435 Use of bit operator on signed type. : | used with int: ( ( msg [ 9 ] & 15 ) << 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[6] = ais_charset[((msg[9]&15)<<2)|(msg[10]>>6)]; + + C 435 Use of shift operator on signed type. : >> used with int: msg [ 10 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[6] = ais_charset[((msg[9]&15)<<2)|(msg[10]>>6)]; + + C 435 Use of bit operator on signed type. : | used with int: ( msg [ 10 ] >> 6 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[6] = ais_charset[((msg[9]&15)<<2)|(msg[10]>>6)]; + + C 436 Declaration does not specify an array. : ais_charset + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 309 + Source : static const char *ais_charset = "?ABCDEFGHIJKLMNOPQRSTUVWXYZ????? ???????????????0123456789?????? + Source : mm->flight[7] = ais_charset[msg[10]&63]; + + C 436 Use of bit operator on signed type. : & used with int: msg [ 10 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[7] = ais_charset[msg[10]&63]; + + C 436 Use of bit operator on signed type. : & used with int: 63 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->flight[7] = ais_charset[msg[10]&63]; + + C 440 Use of bit operator on signed type. : & used with int: msg [ 6 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->fflag = msg[6] & (1<<2); + + C 440 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->fflag = msg[6] & (1<<2); + + C 440 Use of bit operator on signed type. : & used with int: ( 1 << 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->fflag = msg[6] & (1<<2); + + C 441 Use of bit operator on signed type. : & used with int: msg [ 6 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->tflag = msg[6] & (1<<3); + + C 441 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->tflag = msg[6] & (1<<3); + + C 441 Use of bit operator on signed type. : & used with int: ( 1 << 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->tflag = msg[6] & (1<<3); + + C 443 Use of bit operator on signed type. : & used with int: msg [ 6 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_latitude = ((msg[6] & 3) << 15) | + + C 443 Use of bit operator on signed type. : & used with int: 3 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_latitude = ((msg[6] & 3) << 15) | + + C 443 Use of shift operator on signed type. : << used with int: ( msg [ 6 ] & 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_latitude = ((msg[6] & 3) << 15) | + + C 443 Use of bit operator on signed type. : | used with int: ( ( msg [ 6 ] & 3 ) << 15 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_latitude = ((msg[6] & 3) << 15) | + + C 443 Use of shift operator on signed type. : << used with int: msg [ 7 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_latitude = ((msg[6] & 3) << 15) | + + C 443 Use of bit operator on signed type. : | used with int: ( msg [ 7 ] << 7 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_latitude = ((msg[6] & 3) << 15) | + + C 443 Use of shift operator on signed type. : >> used with int: msg [ 8 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_latitude = ((msg[6] & 3) << 15) | + + C 443 Use of bit operator on signed type. : | used with int: ( msg [ 8 ] >> 1 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_latitude = ((msg[6] & 3) << 15) | + + C 446 Use of bit operator on signed type. : & used with int: msg [ 8 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_longitude = ((msg[8]&1) << 16) | + + C 446 Use of bit operator on signed type. : & used with int: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_longitude = ((msg[8]&1) << 16) | + + C 446 Use of shift operator on signed type. : << used with int: ( msg [ 8 ] & 1 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_longitude = ((msg[8]&1) << 16) | + + C 446 Use of bit operator on signed type. : | used with int: ( ( msg [ 8 ] & 1 ) << 16 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_longitude = ((msg[8]&1) << 16) | + + C 446 Use of shift operator on signed type. : << used with int: msg [ 9 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_longitude = ((msg[8]&1) << 16) | + + C 446 Use of bit operator on signed type. : | used with int: ( msg [ 9 ] << 8 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_longitude = ((msg[8]&1) << 16) | + + C 446 Use of bit operator on signed type. : | used with int: msg [ 10 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->raw_longitude = ((msg[8]&1) << 16) | + + C 452 Use of bit operator on signed type. : & used with int: msg [ 5 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ew_dir = (msg[5]&4) >> 2; + + C 452 Use of bit operator on signed type. : & used with int: 4 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ew_dir = (msg[5]&4) >> 2; + + C 452 Use of shift operator on signed type. : >> used with int: ( msg [ 5 ] & 4 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ew_dir = (msg[5]&4) >> 2; + + C 453 Use of bit operator on signed type. : & used with int: msg [ 5 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ew_velocity = ((msg[5]&3) << 8) | msg[6]; + + C 453 Use of bit operator on signed type. : & used with int: 3 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ew_velocity = ((msg[5]&3) << 8) | msg[6]; + + C 453 Use of shift operator on signed type. : << used with int: ( msg [ 5 ] & 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ew_velocity = ((msg[5]&3) << 8) | msg[6]; + + C 453 Use of bit operator on signed type. : | used with int: ( ( msg [ 5 ] & 3 ) << 8 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ew_velocity = ((msg[5]&3) << 8) | msg[6]; + + C 453 Use of bit operator on signed type. : | used with int: msg [ 6 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ew_velocity = ((msg[5]&3) << 8) | msg[6]; + + C 454 Use of bit operator on signed type. : & used with int: msg [ 7 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_dir = (msg[7]&0x80) >> 7; + + C 454 Use of bit operator on signed type. : & used with int: 0x80 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_dir = (msg[7]&0x80) >> 7; + + C 454 Use of shift operator on signed type. : >> used with int: ( msg [ 7 ] & 0x80 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_dir = (msg[7]&0x80) >> 7; + + C 455 Use of bit operator on signed type. : & used with int: msg [ 7 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + + C 455 Use of bit operator on signed type. : & used with int: 0x7f + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + + C 455 Use of shift operator on signed type. : << used with int: ( msg [ 7 ] & 0x7f ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + + C 455 Use of bit operator on signed type. : | used with int: ( ( msg [ 7 ] & 0x7f ) << 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + + C 455 Use of bit operator on signed type. : & used with int: msg [ 8 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + + C 455 Use of bit operator on signed type. : & used with int: 0xe0 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + + C 455 Use of shift operator on signed type. : >> used with int: ( msg [ 8 ] & 0xe0 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + + C 455 Use of bit operator on signed type. : | used with int: ( ( msg [ 8 ] & 0xe0 ) >> 5 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->ns_velocity = ((msg[7]&0x7f) << 3) | ((msg[8]&0xe0) >> 5); + + C 456 Use of bit operator on signed type. : & used with int: msg [ 8 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate_source = (msg[8]&0x10) >> 4; + + C 456 Use of bit operator on signed type. : & used with int: 0x10 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate_source = (msg[8]&0x10) >> 4; + + C 456 Use of shift operator on signed type. : >> used with int: ( msg [ 8 ] & 0x10 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate_source = (msg[8]&0x10) >> 4; + + C 457 Use of bit operator on signed type. : & used with int: msg [ 8 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate_sign = (msg[8]&0x8) >> 3; + + C 457 Use of bit operator on signed type. : & used with int: 0x8 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate_sign = (msg[8]&0x8) >> 3; + + C 457 Use of shift operator on signed type. : >> used with int: ( msg [ 8 ] & 0x8 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate_sign = (msg[8]&0x8) >> 3; + + C 458 Use of bit operator on signed type. : & used with int: msg [ 8 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + + C 458 Use of bit operator on signed type. : & used with int: 7 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + + C 458 Use of shift operator on signed type. : << used with int: ( msg [ 8 ] & 7 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + + C 458 Use of bit operator on signed type. : | used with int: ( ( msg [ 8 ] & 7 ) << 6 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + + C 458 Use of bit operator on signed type. : & used with int: msg [ 9 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + + C 458 Use of bit operator on signed type. : & used with int: 0xfc + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + + C 458 Use of shift operator on signed type. : >> used with int: ( msg [ 9 ] & 0xfc ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + + C 458 Use of bit operator on signed type. : | used with int: ( ( msg [ 9 ] & 0xfc ) >> 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->vert_rate = ((msg[8]&7) << 6) | ((msg[9]&0xfc) >> 2); + + C 460 Float/integer conversion without cast. : (int and double): mm -> velocity = sqrt + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->velocity = sqrt(mm->ns_velocity*mm->ns_velocity+ + + C 460 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : mm->velocity = sqrt(mm->ns_velocity*mm->ns_velocity+ + + C 462 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (mm->velocity) { + + C 467 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (mm->ew_dir) ewv *= -1; + + C 467 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (mm->ew_dir) ewv *= -1; + + C 468 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (mm->ns_dir) nsv *= -1; + + C 468 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (mm->ns_dir) nsv *= -1; + + C 472 Float/integer conversion without cast. : (int and double): mm -> heading = heading + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->heading = heading * 360 / (M_PI*2); + + C 472 Value is not of appropriate type. : (double and short): mm -> heading = heading + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : mm->heading = heading * 360 / (M_PI*2); + + C 472 Value is not of appropriate type. : (double and signed char): ( M_PI + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : mm->heading = heading * 360 / (M_PI*2); + + C 474 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (mm->heading < 0) mm->heading += 360; + + C 479 Use of bit operator on signed type. : & used with int: msg [ 5 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->heading_is_valid = msg[5] & (1<<2); + + C 479 Use of shift operator on signed type. : << used with signed char: 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->heading_is_valid = msg[5] & (1<<2); + + C 479 Use of bit operator on signed type. : & used with int: ( 1 << 2 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->heading_is_valid = msg[5] & (1<<2); + + C 480 Value is not of appropriate type. : (int and double): mm -> heading = ( 360.0 / + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Value is not of appropriate type. : (double and short): mm -> heading = ( 360.0 + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Float/integer conversion without cast. : (int and double): 128 + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Use of bit operator on signed type. : & used with int: msg [ 5 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Use of bit operator on signed type. : & used with int: 3 + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Use of mixed mode arithmetic. : (double and int): ( msg [ 5 ] & 3 + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Bit operator with floating point operand. : << used with double: ( msg [ 5 ] & 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.1.1,R.10.1 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Bit operator with floating point operand. : | used with double: ( ( msg [ 5 ] & 3 ) << 5 ) + MISRA-C:2012(Ed 3 Rev 1) R.1.1,R.10.1 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Use of shift operator on signed type. : >> used with int: msg [ 6 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 480 Use of bit operator on signed type. : | used with int: ( msg [ 6 ] >> 3 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.1 + Source : mm->heading = (360.0/128) * (((msg[5] & 3) << 5) | + + C 482 Else alternative missing in if. MISRA-C:2012(Ed 3 Rev 1) R.15.7 + Source : } + + C 483 Else alternative missing in if. MISRA-C:2012(Ed 3 Rev 1) R.15.7 + Source : } + + C 401 Implicit conversion: actual to formal param (MR). : (int and unsigned char): param 2 + MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 223 + Source : int brute_force_ap(mode_s_t *self, unsigned char *msg, struct mode_s_msg *mm) { + Source : if (brute_force_ap(self, msg, mm)) { + + C 419 Implicit conversion: actual to formal param (MR). : (int and unsigned char): param 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 267 + Source : int decode_ac13_field(unsigned char *msg, int *unit) { + Source : mm->altitude = decode_ac13_field(msg, &mm->unit); + + C 442 Implicit conversion: actual to formal param (MR). : (int and unsigned char): param 1 + MISRA-C:2012(Ed 3 Rev 1) R.10.3 + 294 + Source : int decode_ac12_field(unsigned char *msg, int *unit) { + Source : mm->altitude = decode_ac12_field(msg, &mm->unit); + + C 339 Call has execution order dependant side effects. : fix_two_bits_errors + MISRA-C:2012(Ed 3 Rev 1) R.13.1,R.13.2,R.13.5 + Source : (mm->errorbit = fix_two_bits_errors(msg, mm->msgbits)) != -1) { + + M 317 Copy source parameter not checked before use. : msg + MISRA-C:2012(Ed 3 Rev 1) R.21.17 + Source : memcpy(mm->msg, msg, MODE_S_LONG_MSG_BYTES); + + C 317 Copy length parameter not checked before use. : MODE_S_LONG_MSG_BYTES + MISRA-C:2012(Ed 3 Rev 1) D.4.1 + Source : memcpy(mm->msg, msg, MODE_S_LONG_MSG_BYTES); + + C 472 Var set by std lib func return not checked before use. : heading + MISRA-C:2012(Ed 3 Rev 1) D.4.7 + 469 + Source : heading = atan2(ewv, nsv); + 465 + Source : double heading; + Source : mm->heading = heading * 360 / (M_PI*2); + + C 472 Global denominator not checked within this procedure. : M_PI + MISRA-C:2012(Ed 3 Rev 1) D.4.1,D.4.14 + Source : mm->heading = heading * 360 / (M_PI*2); + + + + + Calls to functions with side effects in unsuitable locations + ------------------------------------------------------------ + ======================================= + LINE SIDE EFFECT FUNCTION + ======================================= + 339 Parameter fix_two_bits_errors + Source: (mm->errorbit = fix_two_bits_errors(msg, mm->msgbits)) != -1) { + + + Basic Information + ----------------- + Number of executable reformatted lines: 285 + Maximum loop depth: 0 + Cyclomatic Complexity: 34 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 1 + Number of procedures which this calls: 11 + Number of comments associated with procedure: 51 + Number of comments in procedure header: 2 + Number of comments in declarations: 2 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 3 msg * * + 2 (mm)->phase_corrected + * + 2 (mm)->heading_is_valid + * * + 2 (mm)->heading * * + 2 (mm)->velocity * * + 2 (mm)->vert_rate + * * + 2 (mm)->vert_rate_sign + * * + 2 (mm)->vert_rate_source + * * + 2 (mm)->ns_velocity + * * + 2 (mm)->ns_dir * * + 2 (mm)->ew_velocity + * * + 2 (mm)->ew_dir * * + 2 (mm)->raw_longitude + * * + 2 (mm)->raw_latitude + * * + 2 (mm)->tflag * * + 2 (mm)->fflag * * + 2 (mm)->flight * * + 2 (mm)->aircraft_type + * * + 2 (mm)->unit * * + 2 (mm)->altitude * * + 2 (mm)->identity * + 2 (mm)->um * + 2 (mm)->dr * + 2 (mm)->fs * + 2 (mm)->mesub * + 2 (mm)->metype * + 2 (mm)->aa3 * + 2 (mm)->aa2 * + 2 (mm)->aa1 * + 2 (mm)->ca * + 2 (mm)->crcok * + 2 (mm)->errorbit * + 2 (mm)->crc * + 2 (mm)->msgbits * + 2 (mm)->msgtype * + 2 (mm)->msg * * + 2 mm * + 1 (self)->icao_cache + * * * + 1 (self)->aggressive * * + 1 (self)->fix_errors * * + 1 self * * + + + + -------------------------------------------------------------------------------- + + + ************************************* + * * + * mode_s_compute_magnitude_vector * + * (489 to 502 mode-s.c) * + * FAIL * + * * + ************************************* + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : mode_s_compute_magnitude_vector + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 494 Literal value requires a U suffix. : 0 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : for (j = 0; j < size; j += 2) { + + C 494 Signed/unsigned conversion without cast. : (unsigned int and int): j + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : for (j = 0; j < size; j += 2) { + + C 494 For loop incrementation is not simple. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + Source : for (j = 0; j < size; j += 2) { + + C 494 Literal value requires a U suffix. : 2 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : for (j = 0; j < size; j += 2) { + + C 495 Declaration does not specify an array. : data + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 489 + Source : void mode_s_compute_magnitude_vector(unsigned char *data, uint16_t *mag, uint32_t size) { + Source : int i = data[j]-127; + + C 495 Signed/unsigned conversion without cast. : (int and unsigned char): data + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : int i = data[j]-127; + + C 495 Use of mixed mode arithmetic. : (unsigned char and signed char): data [ j ] - 127 + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : int i = data[j]-127; + + C 496 Declaration does not specify an array. : data + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 489 + Source : void mode_s_compute_magnitude_vector(unsigned char *data, uint16_t *mag, uint32_t size) { + Source : int q = data[j+1]-127; + + C 496 Signed/unsigned conversion without cast. : (int and unsigned char): data + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : int q = data[j+1]-127; + + C 496 Use of mixed mode arithmetic. : (unsigned char and signed char): data [ j + 1 ] - 127 + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : int q = data[j+1]-127; + + C 498 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (i < 0) i = -i; + + C 499 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (q < 0) q = -q; + + C 500 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 489 + Source : void mode_s_compute_magnitude_vector(unsigned char *data, uint16_t *mag, uint32_t size) { + Source : mag[j/2] = maglut[i*129+q]; + + C 500 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : mag[j/2] = maglut[i*129+q]; + + C 500 Global set by std lib func return not checked before use. : maglut + MISRA-C:2012(Ed 3 Rev 1) D.4.7 + 10 + Source : static uint16_t maglut[129*129*2]; + Source : mag[j/2] = maglut[i*129+q]; + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 28 + Maximum loop depth: 1 + Cyclomatic Complexity: 4 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 0 + Number of procedures which this calls: 0 + Number of comments associated with procedure: 3 + Number of comments in procedure header: 1 + Number of comments in declarations: 2 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 3 size * + 2 mag * * + 1 data * * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * detect_out_of_phase * + * (510 to 516 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : detect_out_of_phase + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 511 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 510 + Source : int detect_out_of_phase(uint16_t *mag) { + Source : if (mag[3] > mag[2]/3) return 1; + + C 511 Literal value requires a U suffix. : 3 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : if (mag[3] > mag[2]/3) return 1; + + C 511 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : if (mag[3] > mag[2]/3) return 1; + + C 511 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (mag[3] > mag[2]/3) return 1; + + C 512 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 510 + Source : int detect_out_of_phase(uint16_t *mag) { + Source : if (mag[10] > mag[9]/3) return 1; + + C 512 Literal value requires a U suffix. : 3 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : if (mag[10] > mag[9]/3) return 1; + + C 512 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : if (mag[10] > mag[9]/3) return 1; + + C 512 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (mag[10] > mag[9]/3) return 1; + + C 513 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 510 + Source : int detect_out_of_phase(uint16_t *mag) { + Source : if (mag[6] > mag[7]/3) return -1; + + C 513 Literal value requires a U suffix. : 3 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : if (mag[6] > mag[7]/3) return -1; + + C 513 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : if (mag[6] > mag[7]/3) return -1; + + C 513 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (mag[6] > mag[7]/3) return -1; + + C 514 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 510 + Source : int detect_out_of_phase(uint16_t *mag) { + Source : if (mag[-1] > mag[1]/3) return -1; + + C 514 Array index is negative. : mag[*]; accessed=-1 + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + Source : if (mag[-1] > mag[1]/3) return -1; + + C 514 Literal value requires a U suffix. : 3 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : if (mag[-1] > mag[1]/3) return -1; + + C 514 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : if (mag[-1] > mag[1]/3) return -1; + + C 514 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (mag[-1] > mag[1]/3) return -1; + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 39 + Maximum loop depth: 0 + Cyclomatic Complexity: 5 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 1 + Number of procedures which this calls: 0 + Number of comments associated with procedure: 6 + Number of comments in procedure header: 6 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 1 mag * + + + + -------------------------------------------------------------------------------- + + + **************************** + * * + * apply_phase_correction * + * (544 to 557 mode-s.c) * + * FAIL * + * * + **************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : apply_phase_correction + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + C 548 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : for (j = 0; j < (MODE_S_LONG_MSG_BITS-1)*2; j += 2) { + + C 548 For loop incrementation is not simple. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + Source : for (j = 0; j < (MODE_S_LONG_MSG_BITS-1)*2; j += 2) { + + C 549 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 544 + Source : void apply_phase_correction(uint16_t *mag) { + Source : if (mag[j] > mag[j+1]) { + + C 551 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 544 + Source : void apply_phase_correction(uint16_t *mag) { + Source : mag[j+2] = (mag[j+2] * 5) / 4; + + C 551 Literal value requires a U suffix. : 5 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : mag[j+2] = (mag[j+2] * 5) / 4; + + C 551 Literal value requires a U suffix. : 4 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : mag[j+2] = (mag[j+2] * 5) / 4; + + C 554 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 544 + Source : void apply_phase_correction(uint16_t *mag) { + Source : mag[j+2] = (mag[j+2] * 4) / 5; + + C 554 Literal value requires a U suffix. : 4 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : mag[j+2] = (mag[j+2] * 4) / 5; + + C 554 Literal value requires a U suffix. : 5 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : mag[j+2] = (mag[j+2] * 4) / 5; + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 26 + Maximum loop depth: 1 + Cyclomatic Complexity: 3 + Essential Cyclomatic Complexity: 1 + Number of procedures which call this one: 1 + Number of procedures which this calls: 0 + Number of comments associated with procedure: 29 + Number of comments in procedure header: 26 + Number of comments in declarations: 0 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 1 mag * * + + + + -------------------------------------------------------------------------------- + + + *************************** + * * + * mode_s_detect * + * (562 to 740 mode-s.c) * + * FAIL * + * * + *************************** + + Standards Violation Summary + --------------------------- + ================================================================= + CODE VIOLATION STANDARD + ================================================================= + C No prototype for non-static function. : mode_s_detect + MISRA-C:2012(Ed 3 Rev 1) R.8.4 + C DD data flow anomalies found. MISRA-C:2012(Ed 3 Rev 1) R.2.2 + + + =========================================================================== + CODE LINE VIOLATION STANDARD + =========================================================================== + M 728 Function call with no prior declaration. : cb MISRA-C:2012(Ed 3 Rev 1) R.17.3 + Source : cb(self, &mm); + + C 591 Literal value requires a U suffix. : 0 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : for (j = 0; j < maglen - MODE_S_FULL_LEN*2; j++) { + + C 591 Signed/unsigned conversion without cast. : (unsigned int and int): j + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : for (j = 0; j < maglen - MODE_S_FULL_LEN*2; j++) { + + C 591 Literal value requires a U suffix. : 8 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : for (j = 0; j < maglen - MODE_S_FULL_LEN*2; j++) { + + C 591 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : for (j = 0; j < maglen - MODE_S_FULL_LEN*2; j++) { + + C 591 Value is not of appropriate type. : (unsigned int and signed char): j < maglen - ( 8 + + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : for (j = 0; j < maglen - MODE_S_FULL_LEN*2; j++) { + + C 591 Use of mixed mode arithmetic. : (unsigned int and signed char): j < maglen - ( 8 + 112 + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : for (j = 0; j < maglen - MODE_S_FULL_LEN*2; j++) { + + C 595 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (use_correction) goto good_preamble; // We already checked it. + + C 600 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : if (!(mag[j] > mag[j+1] && + + C 600 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (!(mag[j] > mag[j+1] && + + C 601 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+1] < mag[j+2] && + + C 601 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+1] < mag[j+2] && + + C 602 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+2] > mag[j+3] && + + C 602 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+2] > mag[j+3] && + + C 603 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+3] < mag[j] && + + C 603 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+3] < mag[j] && + + C 604 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+4] < mag[j] && + + C 604 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+4] < mag[j] && + + C 605 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+5] < mag[j] && + + C 605 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+5] < mag[j] && + + C 606 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+6] < mag[j] && + + C 606 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+6] < mag[j] && + + C 607 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+7] > mag[j+8] && + + C 607 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+7] > mag[j+8] && + + C 608 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+8] < mag[j+9] && + + C 608 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+8] < mag[j+9] && + + C 609 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+9] > mag[j+6])) + + C 609 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : mag[j+9] > mag[j+6])) + + C 618 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : high = (mag[j]+mag[j+2]+mag[j+7]+mag[j+9])/6; + + C 618 Signed/unsigned conversion without cast. : (int and unsigned short): high = ( mag [ j ] + mag [ j + 2 ] + mag [ j + 7 ] + mag [ j + 9 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : high = (mag[j]+mag[j+2]+mag[j+7]+mag[j+9])/6; + + C 618 Literal value requires a U suffix. : 6 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : high = (mag[j]+mag[j+2]+mag[j+7]+mag[j+9])/6; + + C 619 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : if (mag[j+4] >= high || + + C 620 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+5] >= high) + + C 628 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : if (mag[j+11] >= high || + + C 629 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+12] >= high || + + C 630 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+13] >= high || + + C 631 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : mag[j+14] >= high) + + C 640 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memcpy(aux, mag+j+MODE_S_PREAMBLE_US*2, sizeof(aux)); + + C 640 Pointer arithmetic is not on array. MISRA-C:2012(Ed 3 Rev 1) R.18.1,R.18.4 + Source : memcpy(aux, mag+j+MODE_S_PREAMBLE_US*2, sizeof(aux)); + + C 640 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : memcpy(aux, mag+j+MODE_S_PREAMBLE_US*2, sizeof(aux)); + + M 640 Use of sizeof on an array parameter. MISRA-C:2012(Ed 3 Rev 1) R.12.5 + Source : memcpy(aux, mag+j+MODE_S_PREAMBLE_US*2, sizeof(aux)); + + C 641 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (j && detect_out_of_phase(mag+j)) { + + C 641 Pointer arithmetic is not on array. MISRA-C:2012(Ed 3 Rev 1) R.18.1,R.18.4 + Source : if (j && detect_out_of_phase(mag+j)) { + + C 641 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (j && detect_out_of_phase(mag+j)) { + + C 642 Pointer arithmetic is not on array. MISRA-C:2012(Ed 3 Rev 1) R.18.1,R.18.4 + Source : apply_phase_correction(mag+j); + + C 650 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : for (i = 0; i < MODE_S_LONG_MSG_BITS*2; i += 2) { + + C 650 For loop incrementation is not simple. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + Source : for (i = 0; i < MODE_S_LONG_MSG_BITS*2; i += 2) { + + C 651 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : low = mag[j+i+MODE_S_PREAMBLE_US*2]; + + C 651 Signed/unsigned conversion without cast. : (int and unsigned short): low = mag + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : low = mag[j+i+MODE_S_PREAMBLE_US*2]; + + C 651 Signed/unsigned conversion without cast. : (unsigned int and int): low = mag [ j + i + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : low = mag[j+i+MODE_S_PREAMBLE_US*2]; + + C 651 Use of mixed mode arithmetic. : (unsigned int and int): low = mag [ j + i + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : low = mag[j+i+MODE_S_PREAMBLE_US*2]; + + C 651 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : low = mag[j+i+MODE_S_PREAMBLE_US*2]; + + C 652 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : high = mag[j+i+MODE_S_PREAMBLE_US*2+1]; + + C 652 Signed/unsigned conversion without cast. : (int and unsigned short): high = mag + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : high = mag[j+i+MODE_S_PREAMBLE_US*2+1]; + + C 652 Signed/unsigned conversion without cast. : (unsigned int and int): high = mag [ j + i + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : high = mag[j+i+MODE_S_PREAMBLE_US*2+1]; + + C 652 Use of mixed mode arithmetic. : (unsigned int and int): high = mag [ j + i + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : high = mag[j+i+MODE_S_PREAMBLE_US*2+1]; + + C 652 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : high = mag[j+i+MODE_S_PREAMBLE_US*2+1]; + + C 654 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (delta < 0) delta = -delta; + + C 657 Array index is negative. : bits[*]; accessed=-1 + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + Source : bits[i/2] = bits[i/2-1]; + + C 657 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : bits[i/2] = bits[i/2-1]; + + C 663 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : if (i < MODE_S_SHORT_MSG_BITS*2) errors++; + + C 663 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (i < MODE_S_SHORT_MSG_BITS*2) errors++; + + C 668 Literal value requires a U suffix. : 0 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : bits[i/2] = 0; + + C 668 Signed/unsigned conversion without cast. : (unsigned char and int): 2 ] + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : bits[i/2] = 0; + + C 673 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (use_correction) + + C 674 (void) missing for discarded return value. MISRA-C:2012(Ed 3 Rev 1) R.17.7 + Source : memcpy(mag+j+MODE_S_PREAMBLE_US*2, aux, sizeof(aux)); + + C 674 Pointer arithmetic is not on array. MISRA-C:2012(Ed 3 Rev 1) R.18.1,R.18.4 + Source : memcpy(mag+j+MODE_S_PREAMBLE_US*2, aux, sizeof(aux)); + + C 674 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : memcpy(mag+j+MODE_S_PREAMBLE_US*2, aux, sizeof(aux)); + + M 674 Use of sizeof on an array parameter. MISRA-C:2012(Ed 3 Rev 1) R.12.5 + Source : memcpy(mag+j+MODE_S_PREAMBLE_US*2, aux, sizeof(aux)); + + C 677 For loop incrementation is not simple. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + Source : for (i = 0; i < MODE_S_LONG_MSG_BITS; i += 8) { + + C 678 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : msg[i/8] = + + C 689 Signed/unsigned conversion without cast. : (int and unsigned char): msg + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : int msgtype = msg[0]>>3; + + C 695 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : for (i = 0; i < msglen*8*2; i += 2) { + + C 695 For loop incrementation is not simple. MISRA-C:2012(Ed 3 Rev 1) R.14.2 + Source : for (i = 0; i < msglen*8*2; i += 2) { + + C 696 Declaration does not specify an array. : mag + MISRA-C:2012(Ed 3 Rev 1) R.18.1 + 562 + Source : void mode_s_detect(mode_s_t *self, uint16_t *mag, uint32_t maglen, mode_s_callback_t cb) { + Source : delta += abs(mag[j+i+MODE_S_PREAMBLE_US*2]- + + C 696 Signed/unsigned conversion without cast. : (unsigned int and int): delta += abs ( mag [ j + i + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : delta += abs(mag[j+i+MODE_S_PREAMBLE_US*2]- + + C 696 Use of mixed mode arithmetic. : (unsigned int and int): delta += abs ( mag [ j + i + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : delta += abs(mag[j+i+MODE_S_PREAMBLE_US*2]- + + C 696 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : delta += abs(mag[j+i+MODE_S_PREAMBLE_US*2]- + + C 696 Signed/unsigned conversion without cast. : (unsigned int and int): delta += abs ( mag [ j + i + 8 * 2 ] - mag [ j + i + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : delta += abs(mag[j+i+MODE_S_PREAMBLE_US*2]- + + C 696 Use of mixed mode arithmetic. : (unsigned int and int): delta += abs ( mag [ j + i + 8 * 2 ] - mag [ j + i + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.2,R.10.3,R.10.4 + Source : delta += abs(mag[j+i+MODE_S_PREAMBLE_US*2]- + + C 704 Expression needs brackets. MISRA-C:2012(Ed 3 Rev 1) R.12.1,R.20.7 + Source : if (delta < 10*255) { + + C 712 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (errors == 0 || (self->aggressive && errors < 3)) { + + C 719 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (mm.crcok) { + + C 720 Literal value requires a U suffix. : 8 MISRA-C:2012(Ed 3 Rev 1) R.7.2,R.10.3,R.10.4 + Source : j += (MODE_S_PREAMBLE_US+(msglen*8))*2; + + C 720 Value is not of appropriate type. : (unsigned int and signed char): j += ( 8 + + MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 + Source : j += (MODE_S_PREAMBLE_US+(msglen*8))*2; + + C 720 Implicit conversion of underlying type (MR). : (signed char and int): j += ( 8 + ( + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : j += (MODE_S_PREAMBLE_US+(msglen*8))*2; + + C 720 Narrower int conversion without cast. : (signed char and int): j += ( 8 + ( + MISRA-C:2012(Ed 3 Rev 1) R.10.3 + Source : j += (MODE_S_PREAMBLE_US+(msglen*8))*2; + + C 720 Signed/unsigned conversion without cast. : (unsigned int and int): j += ( 8 + ( msglen * 8 ) + MISRA-C:2012(Ed 3 Rev 1) R.10.3,R.10.4 + Source : j += (MODE_S_PREAMBLE_US+(msglen*8))*2; + + C 722 No brackets to then/else. MISRA-C:2012(Ed 3 Rev 1) R.15.6 + Source : if (use_correction) + + C 733 Expression is not Boolean. MISRA-C:2012(Ed 3 Rev 1) R.10.1,R.14.4 + Source : if (!good_message && !use_correction) { + + C 595 Jump into nested block. MISRA-C:2012(Ed 3 Rev 1) R.15.3 + Source : if (use_correction) goto good_preamble; // We already checked it. + + M 674 Copy source parameter not checked before use. : aux + MISRA-C:2012(Ed 3 Rev 1) R.21.17 + Source : memcpy(mag+j+MODE_S_PREAMBLE_US*2, aux, sizeof(aux)); + + M 565 Procedure contains UR data flow anomalies. : aux MISRA-C:2012(Ed 3 Rev 1) R.9.1 + 674 + Source : memcpy(mag+j+MODE_S_PREAMBLE_US*2, aux, sizeof(aux)); + Source : uint16_t aux[MODE_S_LONG_MSG_BITS*2]; + + M 563 Procedure contains UR data flow anomalies. : bits MISRA-C:2012(Ed 3 Rev 1) R.9.1 + 657 + Source : bits[i/2] = bits[i/2-1]; + Source : unsigned char bits[MODE_S_LONG_MSG_BITS]; + + M 564 Procedure contains UR data flow anomalies. : msg MISRA-C:2012(Ed 3 Rev 1) R.9.1 + 716 + Source : mode_s_decode(self, &mm, msg); + Source : unsigned char msg[MODE_S_LONG_MSG_BITS/2]; + + C 734 Modification of loop counter in loop body. : j MISRA-C:2012(Ed 3 Rev 1) R.14.2 + Source : j--; + + + + + Basic Information + ----------------- + Number of executable reformatted lines: 255 + Maximum loop depth: 2 + Cyclomatic Complexity: 42 + Essential Cyclomatic Complexity: 6 + Number of procedures which call this one: 0 + Number of procedures which this calls: 7 + Number of comments associated with procedure: 60 + Number of comments in procedure header: 3 + Number of comments in declarations: 22 + The procedure is reducible + + + Parameter Analysis + ------------------ + ======================================================== + NUMBER NAME DEFINED REFERENCED CLEAR PATH + ======================================================== + 4 cb * + 3 maglen * + 2 mag * * * + 1 (self)->icao_cache + * * * + 1 (self)->fix_errors * * + 1 (self)->check_crc * * + 1 (self)->aggressive * * + 1 self * * + + + + -------------------------------------------------------------------------------- + + + ****************** + * * + * Key to Terms * + * * + ****************** + + Standards violations for procedures are printed in tables with code markers as follows: + --------------------------------------------------------------------------------------- + + ==================================================================== + CODE (LINE) VIOLATION STANDARD + ==================================================================== + M (Source line number) [Text of Mandatory standard] [Appropriate rule reference] + C [Text of Required standard] + O [Text of Advisory standard] + [Source: Text of line from Source file] + + + + Required standards are considered mandatory but individual instances may be overridden + by adding annotations to the source code + + Advisory standards provide additional quality criteria but may be violated + + For some standards violations, additional information is provided in results tables + Note that source lines do not show macro expansions + + "Off" in Summary tables indicates that a standard is switched off + in the pen.dat file + "MR" in Summary tables indicates a MISRA Restricted standard + which cannot be checked without the MISRA licence option. + + + A summary is given of the pass/fail result of each program component as follows: + -------------------------------------------------------------------------------- + + Components which pass all standards are marked: Pass + Components which fail only Advisory standards are marked: Conditional Pass + Components which fail on insufficient comments only are marked: + Comment FAIL + Components which violate Mandatory standards are marked: FAIL + + + + + Procedure Results table breakdown (Example Only) + ------------------------------------------------ + + ======================================= + UNIQUE VIOLATIONS FAILURE DENSITY + (VIOLS/R.LINE %) + ======================================= + 65 ####### 150 ########### + 35 #### 39 #### + + + + + The Violation density for a function is the number of violations per reformatted line, expressed as a percentage. + It is an indication of code quality. + + Functions with a high violation density are likely to be smaller functions with a large number of violations. + + Lower density may indicate larger functions with fewer violations. + + (nViols / nRefLines) x 100 + + where: + + nViols = number of standard violations in a function. + + and: + + nRefLines = number of reformatted lines in a function. + + The unique standards failure ratio is an indication of variety of standards violations in a module. + + Thus a function containing one instance of several different standards will have a high ratio, + while a function that has violated only one standard will have a low ratio. + + + -------------------------------------------------------------------------------- + =========================================================== + * * + * End of Code Review Report * + * * + * Copyright (C) 2019 Liverpool Data Research Associates * + * * + =========================================================== + + diff --git a/CPE455/ncursesdemo/.vscode/configurationCache.log b/CPE455/ncursesdemo/.vscode/configurationCache.log new file mode 100644 index 0000000..79e027f --- /dev/null +++ b/CPE455/ncursesdemo/.vscode/configurationCache.log @@ -0,0 +1 @@ +{"buildTargets":["clean","make","ncursesdemo"],"launchTargets":["/home/student/anw0044/CPE455/ncursesdemo>ncursesdemo()"],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":["/home/student/anw0044/CPE455/ncursesdemo"],"compilerArgs":["-g","-Wall","--pedantic","-ansi","--coverage","ncursesdemo.c","-o","ncursesdemo","-l","ncurses"],"compilerPath":"/usr/bin/gcc","windowsSdkVersion":""},"fileIndex":[["/home/student/anw0044/CPE455/ncursesdemo/ncursesdemo.c",{"uri":{"$mid":1,"fsPath":"/home/student/anw0044/CPE455/ncursesdemo/ncursesdemo.c","path":"/home/student/anw0044/CPE455/ncursesdemo/ncursesdemo.c","scheme":"file"},"configuration":{"defines":[],"includePath":[],"forcedInclude":[],"compilerPath":"/usr/bin/gcc","compilerArgs":["-g","-Wall","--pedantic","-ansi","--coverage","ncursesdemo.c","-o","ncursesdemo","-l","ncurses"],"windowsSdkVersion":""},"compileCommand":{"command":"gcc -g -Wall --pedantic -ansi --coverage ncursesdemo.c -o ncursesdemo -l ncurses","directory":"/home/student/anw0044/CPE455/ncursesdemo","file":"/home/student/anw0044/CPE455/ncursesdemo/ncursesdemo.c"}}]]}} \ No newline at end of file diff --git a/CPE455/ncursesdemo/.vscode/dryrun.log b/CPE455/ncursesdemo/.vscode/dryrun.log new file mode 100644 index 0000000..812dc9f --- /dev/null +++ b/CPE455/ncursesdemo/.vscode/dryrun.log @@ -0,0 +1,5 @@ +make --dry-run --always-make --keep-going --print-directory +make: Entering directory `/home/student/anw0044/CPE455/ncursesdemo' +gcc -g -Wall --pedantic -ansi --coverage ncursesdemo.c -o ncursesdemo -l ncurses +make: Leaving directory `/home/student/anw0044/CPE455/ncursesdemo' + diff --git a/CPE455/ncursesdemo/.vscode/settings.json b/CPE455/ncursesdemo/.vscode/settings.json new file mode 100644 index 0000000..65e1ec0 --- /dev/null +++ b/CPE455/ncursesdemo/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "makefile.extensionOutputFolder": "./.vscode" +} \ No newline at end of file diff --git a/CPE455/ncursesdemo/.vscode/targets.log b/CPE455/ncursesdemo/.vscode/targets.log new file mode 100644 index 0000000..72c79e1 --- /dev/null +++ b/CPE455/ncursesdemo/.vscode/targets.log @@ -0,0 +1,329 @@ +make all --print-data-base --no-builtin-variables --no-builtin-rules --question +# GNU Make 3.82 +# Built for x86_64-redhat-linux-gnu +# Copyright (C) 2010 Free Software Foundation, Inc. +# License GPLv3+: GNU GPL version 3 or later +# This is free software: you are free to change and redistribute it. +# There is NO WARRANTY, to the extent permitted by law. + +# Make data base, printed on Thu Apr 7 10:06:16 2022 + +# Variables + +# automatic + +#include +#include +#include + + + +int main(int argc, char* argv[ ]) +{ + WINDOW* W = 0; /* Curses Window handle */ + int rowLimit, colLimit; /* Num of rows and columns in terminal window */ + int playerRow, playerCol; /* Player row-column position */ + int deltaRow, deltaCol; /* Change in row-column position based on key input */ + + + /* Initialize ncurses -- you will want to use the following settings */ + W = initscr(); /* Determine terminal type and initialize curses data structures */ + start_color(); /* Enable use of color with ncurses */ + cbreak(); /* Disable line buffering and make char inputs immediately accessible to program */ + noecho(); /* Disable echo printing of chars type by user */ + nodelay(W, true); /* Make getch( ) a non-blocking call */ + keypad(W, true); /* Enable keypad and arrow keys */ + curs_set(0); /* Set cursor to be invisible - 0 */ + getmaxyx(W, rowLimit, colLimit); /* Query terminal dimensions */ + + /* Define color pallete foreground-background color pairs */ + /* PairID#, Foreground Color, Background Color */ + /* Foreground color == Background color ==> solid color block */ + init_pair(1, COLOR_BLACK, COLOR_BLACK); /* Black text on Black background */ + init_pair(2, COLOR_RED, COLOR_BLACK); /* Red text on Black background */ + init_pair(3, COLOR_WHITE, COLOR_BLUE); /* White text on Blue background */ + init_pair(4, COLOR_YELLOW, COLOR_YELLOW); /* Yellow text on Yellow background */ + + /* Draw some obstacle */ + attron(COLOR_PAIR(2)); /* Turn on color attribute #2 */ + wmove(W, rowLimit/2, colLimit/2); /* Position cursor in middle of terminal window */ + waddch(W, '#'); /* Draw # symbol */ + attroff(COLOR_PAIR(2)); /* Turn off color attribute #2 */ + + /* Initialize player movement variables */ + playerRow = rowLimit/4; + playerCol = colLimit/4; + deltaCol = 0; + deltaRow = 0; + + /* Player movement loop */ + do + { + int kb = wgetch(W); /* Grab keypress */ + + /* Support player movement via WASD, IJKL, and arrow keys */ + if (kb == 'a' || kb == 'j' || kb == KEY_LEFT) + { + /* Move Left */ + deltaCol = -1; + deltaRow = 0; + } + else if (kb == 'd' || kb == 'l' || kb == KEY_RIGHT) + { + /* Move Right */ + deltaCol = 1; + deltaRow = 0; + } + else if (kb == 'w' || kb == 'i' || kb == KEY_UP) + { + /* Move Up */ + deltaCol = 0; + deltaRow = -1; + } + else if (kb == 's' || kb == 'k' || kb == KEY_DOWN) + { + /* Move Down */ + deltaCol = 0; + deltaRow = 1; + } + else if (kb == 'q') + { + /* q to exit player movement loop */ + break; + }; + + /* Erase player from current position */ + /* An alternate option is to invoke clear() */ + /* which erases everything on the screen */ + /* If you comment out this code, the player will leave an onscreen trail */ + /* */ + /* Algorithm: */ + /* - Turn on color attribute #1 (solid block of background color) */ + /* - Position cursor */ + /* - Draw player symbol */ + /* - Turn off color attribute #1 */ + attron(COLOR_PAIR(1)); + wmove(W, playerRow, playerCol); + waddch(W, 'P'); + attroff(COLOR_PAIR(1)); + + /* Compute new player position without checking to see if new position is valid */ + playerRow = playerRow + deltaRow; + playerCol = playerCol + deltaCol; + + + /* Redraw player in new position */ + attron(COLOR_PAIR(3)); /* Turn on color attribute #3 */ + wmove(W, playerRow, playerCol); /* Position cursor */ + waddch(W, 'P'); /* Draw player symbol */ + attroff(COLOR_PAIR(3)); /* Turn off color attribute #3 */ + + /* Zero offsets prior to next key press */ + deltaRow = 0; + deltaCol = 0; + + wrefresh(W); /* Refresh ncurses window */ + + } while (true); /* Repeat until user selects q to quit */ + + endwin(); /* Terminate ncurses window -- very important */ + + return 0; +} + + + + diff --git a/CPE455/ncursesdemo/ncursesdemo.gcda b/CPE455/ncursesdemo/ncursesdemo.gcda new file mode 100644 index 0000000..64cee7f Binary files /dev/null and b/CPE455/ncursesdemo/ncursesdemo.gcda differ diff --git a/CPE455/ncursesdemo/ncursesdemo.gcno b/CPE455/ncursesdemo/ncursesdemo.gcno new file mode 100644 index 0000000..ba8a8fb Binary files /dev/null and b/CPE455/ncursesdemo/ncursesdemo.gcno differ diff --git a/EE203/Noah Woodlee/BasicGates/Waveform.vwf b/EE203/Noah Woodlee/BasicGates/Waveform.vwf new file mode 100644 index 0000000..3d1b8ff --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/Waveform.vwf @@ -0,0 +1,178 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off class1-21-21 -c class1-21-21 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/Waveform1.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/Waveform1.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off class1-21-21 -c class1-21-21 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/Waveform1.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/Waveform1.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/" class1-21-21 -c class1-21-21 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/" class1-21-21 -c class1-21-21 +onerror {exit -code 1} +vlib work +vlog -work work class1-21-21.vo +vlog -work work Waveform1.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.class1-21-21_vlg_vec_tst +vcd file -direction class1-21-21.msim.vcd +vcd add -internal class1-21-21_vlg_vec_tst/* +vcd add -internal class1-21-21_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work class1-21-21.vo +vlog -work work Waveform1.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.class1-21-21_vlg_vec_tst +vcd file -direction class1-21-21.msim.vcd +vcd add -internal class1-21-21_vlg_vec_tst/* +vcd add -internal class1-21-21_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("in1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("out") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("in1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 220.0; + LEVEL 0 FOR 440.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 220.0; + } +} + +TRANSITION_LIST("in2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 130.0; + LEVEL 0 FOR 380.0; + } +} + +TRANSITION_LIST("out") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "in1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "out"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/BasicGates/Waveform1.vwf b/EE203/Noah Woodlee/BasicGates/Waveform1.vwf new file mode 100644 index 0000000..3d1b8ff --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/Waveform1.vwf @@ -0,0 +1,178 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off class1-21-21 -c class1-21-21 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/Waveform1.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/Waveform1.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off class1-21-21 -c class1-21-21 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/Waveform1.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/Waveform1.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/" class1-21-21 -c class1-21-21 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/" class1-21-21 -c class1-21-21 +onerror {exit -code 1} +vlib work +vlog -work work class1-21-21.vo +vlog -work work Waveform1.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.class1-21-21_vlg_vec_tst +vcd file -direction class1-21-21.msim.vcd +vcd add -internal class1-21-21_vlg_vec_tst/* +vcd add -internal class1-21-21_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work class1-21-21.vo +vlog -work work Waveform1.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.class1-21-21_vlg_vec_tst +vcd file -direction class1-21-21.msim.vcd +vcd add -internal class1-21-21_vlg_vec_tst/* +vcd add -internal class1-21-21_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("in1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("out") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("in1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 220.0; + LEVEL 0 FOR 440.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 220.0; + } +} + +TRANSITION_LIST("in2") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 130.0; + LEVEL 0 FOR 380.0; + } +} + +TRANSITION_LIST("out") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "in1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "out"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/BasicGates/class1-21-21.bdf b/EE203/Noah Woodlee/BasicGates/class1-21-21.bdf new file mode 100644 index 0000000..42d4f9c --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/class1-21-21.bdf @@ -0,0 +1,102 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 104 264 272 280) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "in1" (rect 5 0 20 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 104 280 272 296) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "in2" (rect 5 0 20 17)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 336 272 512 288) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "out" (rect 90 0 105 17)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 272 256 336 304) + (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) + (text "inst" (rect 3 37 20 49)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 0 32) + (input) + (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 14 32)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) + (line (pt 42 24)(pt 64 24)) + ) + (drawing + (line (pt 14 12)(pt 30 12)) + (line (pt 14 37)(pt 31 37)) + (line (pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) diff --git a/EE203/Noah Woodlee/BasicGates/class1-21-21.qsf b/EE203/Noah Woodlee/BasicGates/class1-21-21.qsf new file mode 100644 index 0000000..daa93ef --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/class1-21-21.qsf @@ -0,0 +1,63 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 18:23:33 January 21, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# class1-21-21_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY class1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:23:33 JANUARY 21, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name BDF_FILE "class1-21-21.bdf" +set_location_assignment PIN_C10 -to in1 +set_location_assignment PIN_C11 -to in2 +set_location_assignment PIN_A8 -to out +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf +set_global_assignment -name BDF_FILE class1.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name BDF_FILE decoder.bdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/BasicGates/class1-21-21.qws b/EE203/Noah Woodlee/BasicGates/class1-21-21.qws new file mode 100644 index 0000000..4ff1343 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/class1-21-21.qws differ diff --git a/EE203/Noah Woodlee/BasicGates/class1-21-21_description.txt b/EE203/Noah Woodlee/BasicGates/class1-21-21_description.txt new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/BasicGates/class1.bdf b/EE203/Noah Woodlee/BasicGates/class1.bdf new file mode 100644 index 0000000..42d4f9c --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/class1.bdf @@ -0,0 +1,102 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 104 264 272 280) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "in1" (rect 5 0 20 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 104 280 272 296) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "in2" (rect 5 0 20 17)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 336 272 512 288) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "out" (rect 90 0 105 17)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 272 256 336 304) + (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) + (text "inst" (rect 3 37 20 49)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 0 32) + (input) + (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 14 32)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) + (line (pt 42 24)(pt 64 24)) + ) + (drawing + (line (pt 14 12)(pt 30 12)) + (line (pt 14 37)(pt 31 37)) + (line (pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) diff --git a/EE203/Noah Woodlee/BasicGates/class1.qpf b/EE203/Noah Woodlee/BasicGates/class1.qpf new file mode 100644 index 0000000..622ef61 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/class1.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 18:23:33 January 21, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "18:23:33 January 21, 2021" + +# Revisions + +PROJECT_REVISION = "class1-21-21" diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(0).cnf.cdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(0).cnf.cdb new file mode 100644 index 0000000..6edb417 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(0).cnf.hdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(0).cnf.hdb new file mode 100644 index 0000000..e1dd42b Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(1).cnf.cdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(1).cnf.cdb new file mode 100644 index 0000000..6edb417 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(1).cnf.cdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(1).cnf.hdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(1).cnf.hdb new file mode 100644 index 0000000..f6e91e6 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.(1).cnf.hdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm.qmsg b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm.qmsg new file mode 100644 index 0000000..ea58630 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611278980764 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611278980768 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 19:29:40 2021 " "Processing started: Thu Jan 21 19:29:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611278980768 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611278980768 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off class1 -c class1-21-21 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off class1 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611278980768 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1611278980964 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611278982209 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611278982309 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4683 " "Peak virtual memory: 4683 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611278983009 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 19:29:43 2021 " "Processing ended: Thu Jan 21 19:29:43 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611278983009 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611278983009 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611278983009 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611278983009 ""} diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm.rdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm.rdb new file mode 100644 index 0000000..03b7257 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm.rdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm_labs.ddb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm_labs.ddb new file mode 100644 index 0000000..3604a1e Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cbx.xml b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cbx.xml new file mode 100644 index 0000000..9590c50 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.bpm b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.bpm new file mode 100644 index 0000000..00df495 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.bpm differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.cdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.cdb new file mode 100644 index 0000000..c1ea79f Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.cdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.hdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.hdb new file mode 100644 index 0000000..e453bb9 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.hdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.idb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.idb new file mode 100644 index 0000000..a1c3a6b Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.idb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.logdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.logdb new file mode 100644 index 0000000..66ec905 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.logdb @@ -0,0 +1,45 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,3;0;3;0;0;3;3;0;3;3;0;1;0;0;2;0;1;2;0;0;0;1;0;0;0;0;0;3;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,0;3;0;3;3;0;0;3;0;0;3;2;3;3;1;3;2;1;3;3;3;2;3;3;3;3;3;0;3;3, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,out,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,in1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,in2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.rdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.rdb new file mode 100644 index 0000000..ffa546c Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp.rdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp_merge.kpt b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp_merge.kpt new file mode 100644 index 0000000..b42cbc6 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.db_info b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.db_info new file mode 100644 index 0000000..64bfad1 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Version_Index = 419480576 +Creation_Time = Thu Jan 21 19:27:37 2021 diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.eda.qmsg b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.eda.qmsg new file mode 100644 index 0000000..f7c8a91 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611278361946 ""} +{ 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" "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611278361946 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 19:19:21 2021 " "Processing started: Thu Jan 21 19:19:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611278361946 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611278361946 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/\" class1-21-21 -c class1-21-21 " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/\" class1-21-21 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611278361946 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1611278975898 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1611278975898 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "class1-21-21 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"class1-21-21\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611278975908 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611278975938 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611278975938 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1611278976078 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611278976088 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611278976158 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 15 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278976158 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 17 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278976158 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 19 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278976158 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 21 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278976158 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 23 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278976158 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 25 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278976158 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 27 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278976158 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 29 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278976158 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1611278976158 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611278976158 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611278976158 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611278976158 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611278976158 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1611278976158 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "class1-21-21.sdc " "Synopsys Design Constraints File file not found: 'class1-21-21.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1611278976448 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1611278976448 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1611278976448 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1611278976448 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1611278976448 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1611278976448 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1611278976448 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1611278976448 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611278976448 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611278976448 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611278976448 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611278976448 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1611278976448 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1611278976448 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1611278976448 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1611278976458 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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Woodlee/BasicGates/db/class1-21-21.sld_design_entry_dsc.sci b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sld_design_entry_dsc.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.smart_action.txt b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.smart_action.txt new file mode 100644 index 0000000..437a63e --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta.qmsg b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta.qmsg new file mode 100644 index 0000000..2275170 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta.qmsg @@ -0,0 +1,51 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611278983959 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611278983959 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 19:29:43 2021 " "Processing started: Thu Jan 21 19:29:43 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611278983959 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278983959 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta class1 -c class1-21-21 " "Command: quartus_sta class1 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278983959 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278984029 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984139 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984139 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984159 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984159 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "class1-21-21.sdc " "Synopsys Design Constraints File file not found: 'class1-21-21.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984339 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984339 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984349 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984349 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984349 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984349 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278984349 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984349 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278984349 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984349 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1611278984349 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984349 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984359 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984359 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984359 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984359 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278984369 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984379 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984379 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984549 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984579 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984579 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984579 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984579 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984579 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984579 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984579 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984579 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984589 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984589 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278984589 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278984679 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278985249 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278985249 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611278985279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 19:29:45 2021 " "Processing ended: Thu Jan 21 19:29:45 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611278985279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611278985279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611278985279 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278985279 ""} diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta.rdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta.rdb new file mode 100644 index 0000000..680819c Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta.rdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta_cmp.6_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..1ef720f Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tis_db_list.ddb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tis_db_list.ddb new file mode 100644 index 0000000..ecc3004 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..e0c85e7 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..aa59522 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..5420905 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tmw_info b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tmw_info new file mode 100644 index 0000000..3d0e97c --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:18 +start_analysis_synthesis:s:00:00:08-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:05-start_full_compilation +start_assembler:s:00:00:03-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.vpr.ammdb b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.vpr.ammdb new file mode 100644 index 0000000..0b126b6 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..d86640f Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.tt_0c_slow.hsd b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..a7cdb95 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.tt_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.tt_85c_slow.hsd b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..11019ef Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/db/class1-21-21.zippleback_io_sim_cache.tt_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/BasicGates/db/class1-21-21_partition_pins.json b/EE203/Noah Woodlee/BasicGates/db/class1-21-21_partition_pins.json new file mode 100644 index 0000000..c752463 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1-21-21_partition_pins.json @@ -0,0 +1,21 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "out", + "strict" : false + }, + { + "name" : "in1", + "strict" : false + }, + { + "name" : "in2", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/BasicGates/db/class1.map_bb.logdb b/EE203/Noah Woodlee/BasicGates/db/class1.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/class1.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/BasicGates/db/prev_cmp_class1-21-21.qmsg b/EE203/Noah Woodlee/BasicGates/db/prev_cmp_class1-21-21.qmsg new file mode 100644 index 0000000..6fa5308 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/prev_cmp_class1-21-21.qmsg @@ -0,0 +1,132 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611275653285 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611275653285 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 18:34:13 2021 " "Processing started: Thu Jan 21 18:34:13 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611275653285 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611275653285 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off class1-21-21 -c class1-21-21 " "Command: quartus_map --read_settings_files=on --write_settings_files=off class1-21-21 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611275653285 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1611275653565 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1611275653565 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "class1-21-21.bdf 1 1 " "Found 1 design units, including 1 entities, in source file class1-21-21.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 class1-21-21 " "Found entity 1: class1-21-21" { } { { "class1-21-21.bdf" "" { Schematic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/class1-21-21.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611275659683 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611275659683 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "class1-21-21 " "Elaborating entity \"class1-21-21\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1611275659721 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1611275660131 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1611275660525 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611275660525 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "4 " "Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1611275660665 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1611275660665 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1611275660665 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1611275660665 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4788 " "Peak virtual memory: 4788 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611275660695 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 18:34:20 2021 " "Processing ended: Thu Jan 21 18:34:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611275660695 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611275660695 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611275660695 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1611275660695 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1611275661982 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611275661986 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 18:34:21 2021 " "Processing started: Thu Jan 21 18:34:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611275661986 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1611275661986 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off class1-21-21 -c class1-21-21 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off class1-21-21 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1611275661986 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1611275662087 ""} +{ "Info" "0" "" "Project = class1-21-21" { } { } 0 0 "Project = class1-21-21" 0 0 "Fitter" 0 0 1611275662088 ""} +{ "Info" "0" "" "Revision = class1-21-21" { } { } 0 0 "Revision = class1-21-21" 0 0 "Fitter" 0 0 1611275662088 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1611275662161 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1611275662161 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "class1-21-21 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"class1-21-21\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611275662165 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611275662194 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611275662194 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1611275662430 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611275662448 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611275662596 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 15 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611275662615 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 17 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611275662615 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 19 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611275662615 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 21 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611275662615 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 23 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611275662615 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 25 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611275662615 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 27 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611275662615 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 29 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611275662615 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1611275662615 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611275662616 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611275662616 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611275662616 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611275662616 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1611275662620 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "3 3 " "No exact pin location assignment(s) for 3 pins of 3 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1611275662825 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "class1-21-21.sdc " "Synopsys Design Constraints File file not found: 'class1-21-21.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1611275663036 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1611275663037 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1611275663037 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1611275663038 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1611275663038 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1611275663038 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1611275663038 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1611275663044 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611275663045 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611275663045 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611275663045 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611275663046 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1611275663046 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1611275663046 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1611275663046 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1611275663046 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1611275663046 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1611275663046 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 2.5V 2 1 0 " "Number of I/O pins in group: 3 (unused VREF, 2.5V VCCIO, 2 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1611275663049 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1611275663049 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1611275663049 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 20 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 36 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 48 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 48 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 40 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 60 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 52 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 32 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611275663050 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1611275663050 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1611275663050 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611275663058 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1611275663073 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1611275663909 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611275663960 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1611275663985 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1611275664190 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611275664191 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1611275665857 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X33_Y44 X44_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y44 to location X44_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y44 to location X44_Y54"} { { 12 { 0 ""} 33 44 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1611275666788 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1611275666788 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1611275666850 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1611275666850 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1611275666850 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611275666852 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1611275667012 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611275667018 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1611275667018 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611275667184 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611275667184 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1611275667184 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611275667342 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611275667569 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1611275667769 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5900 " "Peak virtual memory: 5900 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611275668080 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 18:34:28 2021 " "Processing ended: Thu Jan 21 18:34:28 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611275668080 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611275668080 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611275668080 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1611275668080 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1611275669115 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611275669115 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 18:34:29 2021 " "Processing started: Thu Jan 21 18:34:29 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611275669115 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611275669115 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off class1-21-21 -c class1-21-21 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off class1-21-21 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611275669115 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1611275669315 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611275670584 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611275670684 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611275671471 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 18:34:31 2021 " "Processing ended: Thu Jan 21 18:34:31 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611275671471 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611275671471 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611275671471 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611275671471 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1611275672073 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1611275672554 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611275672564 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 18:34:32 2021 " "Processing started: Thu Jan 21 18:34:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611275672564 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672564 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta class1-21-21 -c class1-21-21 " "Command: quartus_sta class1-21-21 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672564 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1611275672644 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672774 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672774 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672802 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672803 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "class1-21-21.sdc " "Synopsys Design Constraints File file not found: 'class1-21-21.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672998 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672998 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672998 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672998 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672998 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672998 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1611275672998 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672998 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611275672998 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275672998 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1611275673008 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673008 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673018 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673018 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673018 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673028 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611275673028 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673048 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673048 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673939 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673969 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673969 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673969 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673969 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673970 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673977 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673981 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673985 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673989 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275673992 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611275673997 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674083 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674083 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674083 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674083 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674088 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674092 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674097 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674101 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674106 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674665 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674665 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4868 " "Peak virtual memory: 4868 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611275674705 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 18:34:34 2021 " "Processing ended: Thu Jan 21 18:34:34 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611275674705 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611275674705 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611275674705 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275674705 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 16 s " "Quartus Prime Full Compilation was successful. 0 errors, 16 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611275675348 ""} diff --git a/EE203/Noah Woodlee/BasicGates/db/prev_cmp_class1.qmsg b/EE203/Noah Woodlee/BasicGates/db/prev_cmp_class1.qmsg new file mode 100644 index 0000000..b99bcb4 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/db/prev_cmp_class1.qmsg @@ -0,0 +1,131 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611278883750 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611278883750 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 19:28:03 2021 " "Processing started: Thu Jan 21 19:28:03 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611278883750 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611278883750 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off class1 -c class1-21-21 " "Command: quartus_map --read_settings_files=on --write_settings_files=off class1 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611278883750 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1611278883990 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1611278883990 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "class1-21-21.bdf 1 1 " "Found 1 design units, including 1 entities, in source file class1-21-21.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 class1-21-21 " "Found entity 1: class1-21-21" { } { { "class1-21-21.bdf" "" { Schematic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/class1-21-21.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611278890027 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611278890027 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "class1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file class1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 class1 " "Found entity 1: class1" { } { { "class1.bdf" "" { Schematic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/class1.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611278890027 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611278890027 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Found entity 1: decoder" { } { { "decoder.bdf" "" { Schematic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/decoder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611278890027 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611278890027 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "class1 " "Elaborating entity \"class1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1611278890047 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1611278890322 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1611278890594 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611278890594 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "4 " "Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1611278890627 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1611278890627 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1611278890627 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1611278890627 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4779 " "Peak virtual memory: 4779 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611278890652 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 19:28:10 2021 " "Processing ended: Thu Jan 21 19:28:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611278890652 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611278890652 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611278890652 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1611278890652 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1611278891607 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611278891607 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 19:28:11 2021 " "Processing started: Thu Jan 21 19:28:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611278891607 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1611278891607 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off class1 -c class1-21-21 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off class1 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1611278891607 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1611278891677 ""} +{ "Info" "0" "" "Project = class1" { } { } 0 0 "Project = class1" 0 0 "Fitter" 0 0 1611278891677 ""} +{ "Info" "0" "" "Revision = class1-21-21" { } { } 0 0 "Revision = class1-21-21" 0 0 "Fitter" 0 0 1611278891677 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1611278891737 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1611278891737 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "class1-21-21 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"class1-21-21\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611278891747 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611278891767 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611278891767 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1611278891927 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611278891937 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611278892007 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 15 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278892007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 17 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278892007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 19 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278892007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 21 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278892007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 23 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278892007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 25 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278892007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 27 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278892007 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 0 { 0 ""} 0 29 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611278892007 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1611278892007 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611278892007 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611278892007 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611278892007 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611278892007 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1611278892007 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "class1-21-21.sdc " "Synopsys Design Constraints File file not found: 'class1-21-21.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611278892297 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611278892297 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611278892297 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611278892297 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1611278892297 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1611278892297 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1611278892297 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1611278892297 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1611278892297 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1611278892297 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611278892307 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1611278892307 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1611278893129 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611278893169 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1611278893179 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1611278893299 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611278893299 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1611278893589 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1611278894529 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1611278894529 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1611278894589 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1611278894589 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1611278894589 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611278894599 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1611278894749 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611278894759 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1611278894759 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611278894909 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611278894909 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1611278894909 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611278895059 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611278895289 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1611278895469 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5906 " "Peak virtual memory: 5906 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611278895749 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 19:28:15 2021 " "Processing ended: Thu Jan 21 19:28:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611278895749 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611278895749 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611278895749 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1611278895749 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1611278896599 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611278896609 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 19:28:16 2021 " "Processing started: Thu Jan 21 19:28:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611278896609 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611278896609 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off class1 -c class1-21-21 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off class1 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611278896609 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1611278896799 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611278897999 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611278898089 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4683 " "Peak virtual memory: 4683 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611278898799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 19:28:18 2021 " "Processing ended: Thu Jan 21 19:28:18 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611278898799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611278898799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611278898799 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611278898799 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1611278899489 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1611278899869 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611278899869 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 19:28:19 2021 " "Processing started: Thu Jan 21 19:28:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611278899869 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278899869 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta class1 -c class1-21-21 " "Command: quartus_sta class1 -c class1-21-21" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278899869 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278899939 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900059 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900059 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900089 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900089 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "class1-21-21.sdc " "Synopsys Design Constraints File file not found: 'class1-21-21.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900269 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900269 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900269 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900269 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900269 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900269 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278900269 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900269 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278900269 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900269 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1611278900279 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900279 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900279 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900289 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900289 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900289 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278900289 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900309 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900309 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900479 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900509 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900509 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900509 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900509 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900509 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900509 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900509 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900509 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900519 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900519 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611278900519 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900609 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900609 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900609 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900609 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900609 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900609 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900619 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900619 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278900619 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278901179 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278901179 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611278901209 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 19:28:21 2021 " "Processing ended: Thu Jan 21 19:28:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611278901209 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611278901209 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611278901209 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278901209 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus Prime Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611278901809 ""} diff --git a/EE203/Noah Woodlee/BasicGates/decoder.bdf b/EE203/Noah Woodlee/BasicGates/decoder.bdf new file mode 100644 index 0000000..39f3977 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/decoder.bdf @@ -0,0 +1,102 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 200 232 368 248) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "in1" (rect 5 0 19 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 200 248 368 264) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "in2" (rect 5 0 19 17)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 432 240 608 256) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "out" (rect 90 0 105 17)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 368 224 432 272) + (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) + (text "inst" (rect 3 37 20 49)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 0 32) + (input) + (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 14 32)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) + (line (pt 42 24)(pt 64 24)) + ) + (drawing + (line (pt 14 12)(pt 30 12)) + (line (pt 14 37)(pt 31 37)) + (line (pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) diff --git a/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..d89a873 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| George Totolos :| 08/22/2016:| Initial Revision +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a2885da --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +DE10_LITE_Golden_Top.v +platform_setup.tcl +filelist.txt diff --git a/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..d9cea11 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,435 @@ +proc ::setup_project {} { +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name SDC_FILE DE10_LITE_Golden_Top.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS + +#============================================================ +# Accelerometer +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO + +#============================================================ +# Arduino +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..1c1dfa3 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/home/gtotolos/Desktop/max10_de10_lite/Golden_Top/", + "acds_version" : "Version 16.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/BasicGates/devkits/readme.txt b/EE203/Noah Woodlee/BasicGates/devkits/readme.txt new file mode 100644 index 0000000..f6ba267 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/BasicGates/incremental_db/README b/EE203/Noah Woodlee/BasicGates/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/BasicGates/incremental_db/compiled_partitions/class1-21-21.db_info b/EE203/Noah Woodlee/BasicGates/incremental_db/compiled_partitions/class1-21-21.db_info new file mode 100644 index 0000000..613df57 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/incremental_db/compiled_partitions/class1-21-21.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Version_Index = 419480576 +Creation_Time = Thu Jan 21 18:34:19 2021 diff --git a/EE203/Noah Woodlee/BasicGates/incremental_db/compiled_partitions/class1-21-21.root_partition.cmp.ammdb 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index 0000000..d220ef7 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/incremental_db/compiled_partitions/class1-21-21.rrp.hdb differ diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.asm.rpt b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.asm.rpt new file mode 100644 index 0000000..ee671f8 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.asm.rpt @@ -0,0 +1,93 @@ +Assembler report for class1-21-21 +Thu Jan 21 19:29:42 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Jan 21 19:29:42 2021 ; +; Revision Name ; class1-21-21 ; +; Top-level Entity Name ; class1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++--------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------------------------------------------+ +; File Name ; ++--------------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.sof ; ++--------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.sof ; ++----------------+-----------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-----------------------------------------------------------------------------------------+ +; Device ; 10M50DAF484C6GES ; +; JTAG usercode ; 0x0026FD9A ; +; Checksum ; 0x0026FD9A ; ++----------------+-----------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Jan 21 19:29:40 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off class1 -c class1-21-21 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4683 megabytes + Info: Processing ended: Thu Jan 21 19:29:43 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.done b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.done new file mode 100644 index 0000000..37dacf0 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.done @@ -0,0 +1 @@ +Thu Jan 21 19:29:45 2021 diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.eda.rpt b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.eda.rpt new file mode 100644 index 0000000..94f0227 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for class1-21-21 +Thu Jan 21 19:19:22 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Jan 21 19:19:22 2021 ; +; Revision Name ; class1-21-21 ; +; Top-level Entity Name ; class1-21-21 ; +; Family ; MAX 10 ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++-----------------------------------------------------------------------------------+ +; Generated Files ; ++-----------------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim//class1-21-21.vo ; ++-----------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Jan 21 19:19:21 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim/" class1-21-21 -c class1-21-21 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file class1-21-21.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Jan 21 19:19:22 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.rpt b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.rpt new file mode 100644 index 0000000..70280db --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.rpt @@ -0,0 +1,1163 @@ +Fitter report for class1-21-21 +Thu Jan 21 19:29:39 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Jan 21 19:29:39 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; class1-21-21 ; +; Top-level Entity Name ; class1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 2 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 2 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 3 / 360 ( < 1 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.2% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ; +; -- Achieved ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ; 0.00 % ( 0 / 27 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 11 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 2 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 2 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 2 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 2 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 3 / 360 ( < 1 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 17 ; +; Average fan-out ; 0.63 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 2 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 2 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 2 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 2 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 3 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 23 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 2 ; 0 ; +; -- Output Ports ; 1 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; in1 ; C10 ; 7 ; 51 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; in2 ; C11 ; 7 ; 51 ; 54 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; out ; A8 ; 7 ; 46 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 0 / 60 ( 0 % ) ; 2.5V ; -- ; +; 7 ; 3 / 52 ( 6 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; out ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; in1 ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; in2 ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 391 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 388 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; out ; Incomplete set of assignments ; +; in1 ; Incomplete set of assignments ; +; in2 ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |class1 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 3 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |class1 ; class1 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; out ; Output ; -- ; -- ; -- ; -- ; -- ; +; in1 ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; in2 ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; in1 ; ; ; +; - inst ; 0 ; 6 ; +; in2 ; ; ; +; - inst ; 0 ; 6 ; ++---------------------+-------------------+---------+ + + ++-----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-----------------------+ +; Block interconnects ; 7 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 0 / 5,382 ( 0 % ) ; +; C4 interconnects ; 6 / 106,704 ( < 1 % ) ; +; Direct links ; 0 / 148,641 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 49,760 ( 0 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 0 / 5,406 ( 0 % ) ; +; R4 interconnects ; 3 / 147,764 ( < 1 % ) ; ++-----------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 2) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 2 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 1.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 1.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 3 ; 0 ; 3 ; 0 ; 0 ; 3 ; 3 ; 0 ; 3 ; 3 ; 0 ; 1 ; 0 ; 0 ; 2 ; 0 ; 1 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 3 ; 0 ; 3 ; 3 ; 0 ; 0 ; 3 ; 0 ; 0 ; 3 ; 2 ; 3 ; 3 ; 1 ; 3 ; 2 ; 1 ; 3 ; 3 ; 3 ; 2 ; 3 ; 3 ; 3 ; 3 ; 3 ; 0 ; 3 ; 3 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; out ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; in1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; in2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (119006): Selected device 10M50DAF484C6GES for design "class1-21-21" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'class1-21-21.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds. +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings + Info: Peak virtual memory: 5905 megabytes + Info: Processing ended: Thu Jan 21 19:29:39 2021 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:07 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg. + + diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg new file mode 100644 index 0000000..558ea95 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.summary b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.summary new file mode 100644 index 0000000..a284d87 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Thu Jan 21 19:29:39 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : class1-21-21 +Top-level Entity Name : class1 +Family : MAX 10 +Device : 10M50DAF484C6GES +Timing Models : Preliminary +Total logic elements : 2 / 49,760 ( < 1 % ) + Total combinational functions : 2 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 3 / 360 ( < 1 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.flow.rpt b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.flow.rpt new file mode 100644 index 0000000..8c98d26 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.flow.rpt @@ -0,0 +1,128 @@ +Flow report for class1-21-21 +Thu Jan 21 19:29:45 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Jan 21 19:29:42 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; class1-21-21 ; +; Top-level Entity Name ; class1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 2 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 2 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 3 / 360 ( < 1 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 01/21/2021 19:29:28 ; +; Main task ; Compilation ; +; Revision Name ; class1-21-21 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 189559947077153.161127896806632 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; class1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; class1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; class1 ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; TOP_LEVEL_ENTITY ; class1 ; class1-21-21 ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 4779 MB ; 00:00:16 ; +; Fitter ; 00:00:04 ; 1.0 ; 5905 MB ; 00:00:06 ; +; Assembler ; 00:00:02 ; 1.0 ; 4682 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4867 MB ; 00:00:01 ; +; Total ; 00:00:15 ; -- ; -- ; 00:00:25 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off class1 -c class1-21-21 +quartus_fit --read_settings_files=off --write_settings_files=off class1 -c class1-21-21 +quartus_asm --read_settings_files=off --write_settings_files=off class1 -c class1-21-21 +quartus_sta class1 -c class1-21-21 + + + diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.jdi b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.jdi new file mode 100644 index 0000000..40d1edd --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.map.rpt b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.map.rpt new file mode 100644 index 0000000..8ab380e --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.map.rpt @@ -0,0 +1,287 @@ +Analysis & Synthesis report for class1-21-21 +Thu Jan 21 19:29:34 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Jan 21 19:29:34 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; class1-21-21 ; +; Top-level Entity Name ; class1 ; +; Family ; MAX 10 ; +; Total logic elements ; 1 ; +; Total combinational functions ; 1 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 3 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Top-level entity name ; class1 ; class1-21-21 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------+---------+ +; class1.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/class1.bdf ; ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 1 ; +; ; ; +; Total combinational functions ; 1 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 1 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 3 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; inst ; +; Maximum fan-out ; 1 ; +; Total fan-out ; 6 ; +; Average fan-out ; 0.86 ; ++---------------------------------------------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |class1 ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; |class1 ; class1 ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 3 ; +; cycloneiii_lcell_comb ; 1 ; +; normal ; 1 ; +; 2 data inputs ; 1 ; +; ; ; +; Max LUT depth ; 1.00 ; +; Average LUT depth ; 1.00 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Jan 21 19:29:27 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off class1 -c class1-21-21 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file class1-21-21.bdf + Info (12023): Found entity 1: class1-21-21 +Info (12021): Found 1 design units, including 1 entities, in source file class1.bdf + Info (12023): Found entity 1: class1 +Info (12021): Found 1 design units, including 1 entities, in source file decoder.bdf + Info (12023): Found entity 1: decoder +Info (12127): Elaborating entity "class1" for the top level hierarchy +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 4 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 2 input pins + Info (21059): Implemented 1 output pins + Info (21061): Implemented 1 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4779 megabytes + Info: Processing ended: Thu Jan 21 19:29:34 2021 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:16 + + diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.map.summary b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.map.summary new file mode 100644 index 0000000..8efd95a --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Thu Jan 21 19:29:34 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : class1-21-21 +Top-level Entity Name : class1 +Family : MAX 10 +Total logic elements : 1 + Total combinational functions : 1 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 3 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.pin b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.pin new file mode 100644 index 0000000..06f5592 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2016 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel MegaCore Function License Agreement, or other + -- applicable license agreement, including, without limitation, + -- that your use is for the sole purpose of programming logic + -- devices manufactured by Intel and sold by Intel or its + -- authorized distributors. Please refer to the applicable + -- agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +CHIP "class1-21-21" ASSIGNED TO AN: 10M50DAF484C6GES + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +out : A8 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +GND : B13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +in1 : C10 : input : 2.5 V : : 7 : Y +in2 : C11 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.pof b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.pof new file mode 100644 index 0000000..dec6081 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.pof differ diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sld b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sof b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sof new file mode 100644 index 0000000..398f578 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sof differ diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sta.rpt b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sta.rpt new file mode 100644 index 0000000..87e9270 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sta.rpt @@ -0,0 +1,426 @@ +TimeQuest Timing Analyzer report for class1-21-21 +Thu Jan 21 19:29:45 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; class1-21-21 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.3% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; out ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; in1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; in2 ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; out ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; out ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0108 V ; 0.13 V ; 0.066 V ; 6.32e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0108 V ; 0.13 V ; 0.066 V ; 6.32e-10 s ; 6.45e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; out ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 2 ; 2 ; +; Unconstrained Input Port Paths ; 2 ; 2 ; +; Unconstrained Output Ports ; 1 ; 1 ; +; Unconstrained Output Port Paths ; 2 ; 2 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; in1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; in2 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; in1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; in2 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Jan 21 19:29:43 2021 +Info: Command: quartus_sta class1 -c class1-21-21 +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'class1-21-21.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 4867 megabytes + Info: Processing ended: Thu Jan 21 19:29:45 2021 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sta.summary b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/output_files/class1-21-21.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/Waveform.vwf.vt b/EE203/Noah Woodlee/BasicGates/simulation/qsim/Waveform.vwf.vt new file mode 100644 index 0000000..f72728d --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/Waveform.vwf.vt @@ -0,0 +1,78 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "01/21/2021 19:08:58" + +// Verilog Test Bench (with test vectors) for design : class1-21-21 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module class1-21-21_vlg_vec_tst(); +// constants +// general purpose registers +reg in1; +reg in2; +// wires +wire out; + +// assign statements (if any) +class1-21-21 i1 ( +// port map - connection between master ports and signals/registers + .in1(in1), + .in2(in2), + .out(out) +); +initial +begin +#200000 $finish; +end + +// in1 +initial +begin + in1 = 1'b0; + in1 = #10000 1'b1; + in1 = #10000 1'b0; + in1 = #10000 1'b1; + in1 = #10000 1'b0; + in1 = #30000 1'b1; + in1 = #20000 1'b0; + in1 = #80000 1'b1; + in1 = #10000 1'b0; +end + +// in2 +initial +begin + in2 = 1'b0; + in2 = #30000 1'b1; + in2 = #10000 1'b0; + in2 = #20000 1'b1; + in2 = #10000 1'b0; + in2 = #50000 1'b1; + in2 = #10000 1'b0; + in2 = #20000 1'b1; + in2 = #10000 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/Waveform1.vwf.vt b/EE203/Noah Woodlee/BasicGates/simulation/qsim/Waveform1.vwf.vt new file mode 100644 index 0000000..49a340a --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/Waveform1.vwf.vt @@ -0,0 +1,72 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "01/21/2021 19:19:21" + +// Verilog Test Bench (with test vectors) for design : class1-21-21 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module class1-21-21_vlg_vec_tst(); +// constants +// general purpose registers +reg in1; +reg in2; +// wires +wire out; + +// assign statements (if any) +class1-21-21 i1 ( +// port map - connection between master ports and signals/registers + .in1(in1), + .in2(in2), + .out(out) +); +initial +begin +#1000000 $finish; +end + +// in1 +initial +begin + in1 = 1'b0; + in1 = #80000 1'b1; + in1 = #220000 1'b0; + in1 = #440000 1'b1; + in1 = #40000 1'b0; +end + +// in2 +initial +begin + in2 = 1'b0; + in2 = #260000 1'b1; + in2 = #40000 1'b0; + in2 = #40000 1'b1; + in2 = #50000 1'b0; + in2 = #100000 1'b1; + in2 = #130000 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.do b/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.do new file mode 100644 index 0000000..1d463c4 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vlog -work work class1-21-21.vo +vlog -work work Waveform1.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.class1-21-21_vlg_vec_tst +vcd file -direction class1-21-21.msim.vcd +vcd add -internal class1-21-21_vlg_vec_tst/* +vcd add -internal class1-21-21_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.sft b/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.sft new file mode 100644 index 0000000..f324fea --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.vo b/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.vo new file mode 100644 index 0000000..774d4b9 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21.vo @@ -0,0 +1,272 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" + +// DATE "01/21/2021 19:19:22" + +// +// Device: Altera 10M50DAF484C6GES Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module \class1-21-21 ( + out, + in1, + in2); +output out; +input in1; +input in2; + +// Design Ports Information +// out => Location: PIN_W8, I/O Standard: 2.5 V, Current Strength: Default +// in1 => Location: PIN_AB4, I/O Standard: 2.5 V, Current Strength: Default +// in2 => Location: PIN_AA3, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \~QUARTUS_CREATED_UNVM~~busy ; +wire \~QUARTUS_CREATED_ADC1~~eoc ; +wire \~QUARTUS_CREATED_ADC2~~eoc ; +wire \out~output_o ; +wire \in1~input_o ; +wire \in2~input_o ; +wire \inst~combout ; + + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: LCCOMB_X44_Y52_N8 +fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): +// \~QUARTUS_CREATED_GND~I_combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .cout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000; +defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X24_Y0_N2 +fiftyfivenm_io_obuf \out~output ( + .i(\inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\out~output_o ), + .obar()); +// synopsys translate_off +defparam \out~output .bus_hold = "false"; +defparam \out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X26_Y0_N22 +fiftyfivenm_io_ibuf \in1~input ( + .i(in1), + .ibar(gnd), + .nsleep(vcc), + .o(\in1~input_o )); +// synopsys translate_off +defparam \in1~input .bus_hold = "false"; +defparam \in1~input .listen_to_nsleep_signal = "false"; +defparam \in1~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X26_Y0_N29 +fiftyfivenm_io_ibuf \in2~input ( + .i(in2), + .ibar(gnd), + .nsleep(vcc), + .o(\in2~input_o )); +// synopsys translate_off +defparam \in2~input .bus_hold = "false"; +defparam \in2~input .listen_to_nsleep_signal = "false"; +defparam \in2~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y1_N0 +fiftyfivenm_lcell_comb inst( +// Equation(s): +// \inst~combout = (\in1~input_o & \in2~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\in1~input_o ), + .datad(\in2~input_o ), + .cin(gnd), + .combout(\inst~combout ), + .cout()); +// synopsys translate_off +defparam inst.lut_mask = 16'hF000; +defparam inst.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: UNVM_X0_Y40_N40 +fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ ( + .arclk(vcc), + .arshft(vcc), + .drclk(vcc), + .drshft(vcc), + .drdin(vcc), + .nprogram(vcc), + .nerase(vcc), + .nosc_ena(\~QUARTUS_CREATED_GND~I_combout ), + .par_en(vcc), + .xe_ye(\~QUARTUS_CREATED_GND~I_combout ), + .se(\~QUARTUS_CREATED_GND~I_combout ), + .ardin(23'b11111111111111111111111), + .busy(\~QUARTUS_CREATED_UNVM~~busy ), + .osc(), + .bgpbusy(), + .sp_pass(), + .se_pass(), + .drdout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm"; +defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true"; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y52_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC1~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1; +defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y51_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC2~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2; +defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0; +// synopsys translate_on + +assign out = \out~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_TMS~~padout ; +wire \~ALTERA_TCK~~padout ; +wire \~ALTERA_TDI~~padout ; +wire \~ALTERA_CONFIG_SEL~~padout ; +wire \~ALTERA_nCONFIG~~padout ; +wire \~ALTERA_nSTATUS~~padout ; +wire \~ALTERA_CONF_DONE~~padout ; +wire \~ALTERA_TMS~~ibuf_o ; +wire \~ALTERA_TCK~~ibuf_o ; +wire \~ALTERA_TDI~~ibuf_o ; +wire \~ALTERA_CONFIG_SEL~~ibuf_o ; +wire \~ALTERA_nCONFIG~~ibuf_o ; +wire \~ALTERA_nSTATUS~~ibuf_o ; +wire \~ALTERA_CONF_DONE~~ibuf_o ; + + +endmodule diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21_modelsim.xrf b/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21_modelsim.xrf new file mode 100644 index 0000000..dd827fa --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/class1-21-21_modelsim.xrf @@ -0,0 +1,20 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/class1-21-21.bdf +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/Waveform.vwf +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/db/class1-21-21.cbx.xml +design_name = \class1-21-21 +instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, \class1-21-21 , 1 +instance = comp, \out~output , out~output, \class1-21-21 , 1 +instance = comp, \in1~input , in1~input, \class1-21-21 , 1 +instance = comp, \in2~input , in2~input, \class1-21-21 , 1 +instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, \class1-21-21 , 1 +instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, \class1-21-21 , 1 +instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, \class1-21-21 , 1 +design_name = hard_block +instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1 diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/transcript b/EE203/Noah Woodlee/BasicGates/simulation/qsim/transcript new file mode 100644 index 0000000..ba7acb2 --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/transcript @@ -0,0 +1,20 @@ +# do class1-21-21.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 19:19:22 on Jan 21,2021 +# vlog -work work class1-21-21.vo +# -- Compiling module \class1-21-21 +# -- Compiling module hard_block +# +# Top level modules: +# \class1-21-21 +# End time: 19:19:22 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 19:19:22 on Jan 21,2021 +# vlog -work work Waveform1.vwf.vt +# ** Error: (vlog-13069) Waveform1.vwf.vt(30): near "-": syntax error, unexpected '-', expecting "SystemVerilog keyword 'import'" or ';' or '#' or '('. +# End time: 19:19:22 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 1, Warnings: 0 +# ** Error: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/vlog failed. +# Executing ONERROR command at macro ./class1-21-21.do line 4 diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_info b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_info new file mode 100644 index 0000000..18655ac --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_info @@ -0,0 +1,53 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dC:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim +v\class1-21-21 +Z1 !s110 1611278362 +!i10b 1 +!s100 jJQkb4bY@EOnS7>4kW[N?3 +I22ORzOonmkC=^2kBCmCMe0 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +Z3 w1611278362 +Z4 8class1-21-21.vo +Z5 Fclass1-21-21.vo +L0 32 +Z6 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z7 !s108 1611278362.000000 +Z8 !s107 class1-21-21.vo| +Z9 !s90 -work|work|class1-21-21.vo| +!i113 1 +Z10 o-work work +Z11 tCvgOpt 0 +n@134class1-21-21@040 +vhard_block +R1 +!i10b 1 +!s100 M`VFZU>cQ=@9Z4Cck8KGo1 +IK8Ki:eNcRfd6F_3a<8Ff^0 +R2 +R0 +R3 +R4 +R5 +L0 228 +R6 +r1 +!s85 0 +31 +R7 +R8 +R9 +!i113 1 +R10 +R11 diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib.qdb b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib.qdb new file mode 100644 index 0000000..74c0202 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib.qdb differ diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qdb b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qdb new file mode 100644 index 0000000..5639958 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qdb differ diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qpg b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qpg new file mode 100644 index 0000000..da46133 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qpg differ diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qtl b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qtl new file mode 100644 index 0000000..7facc40 Binary files /dev/null and b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_lib1_0.qtl differ diff --git a/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_vmake b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/EE203/Noah Woodlee/BasicGates/simulation/qsim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/EE203/Noah Woodlee/Decoder/Waveform.vwf b/EE203/Noah Woodlee/Decoder/Waveform.vwf new file mode 100644 index 0000000..0c2c986 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/Waveform.vwf @@ -0,0 +1,264 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +onerror {exit -code 1} +vlib work +vlog -work work decoder.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +vcd file -direction decoder.msim.vcd +vcd add -internal decoder_vlg_vec_tst/* +vcd add -internal decoder_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work decoder.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +vcd file -direction decoder.msim.vcd +vcd add -internal decoder_vlg_vec_tst/* +vcd add -internal decoder_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 200.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Q0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("A") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } +} + +TRANSITION_LIST("B") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } +} + +TRANSITION_LIST("Q0") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 200.0; + } +} + +TRANSITION_LIST("Q1") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 200.0; + } +} + +TRANSITION_LIST("Q2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 200.0; + } +} + +TRANSITION_LIST("Q3") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 200.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.(0).cnf.cdb b/EE203/Noah Woodlee/Decoder/db/decoder.(0).cnf.cdb new file mode 100644 index 0000000..2c9c009 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.(0).cnf.hdb b/EE203/Noah Woodlee/Decoder/db/decoder.(0).cnf.hdb new file mode 100644 index 0000000..4d18a79 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.asm.qmsg b/EE203/Noah Woodlee/Decoder/db/decoder.asm.qmsg new file mode 100644 index 0000000..ebb8d5b --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611280915611 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611280915615 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:01:55 2021 " "Processing started: Thu Jan 21 20:01:55 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611280915615 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611280915615 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611280915615 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1611280915826 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611280917012 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611280917103 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611280917813 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:01:57 2021 " "Processing ended: Thu Jan 21 20:01:57 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611280917813 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611280917813 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611280917813 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611280917813 ""} diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.asm.rdb b/EE203/Noah Woodlee/Decoder/db/decoder.asm.rdb new file mode 100644 index 0000000..302f0e2 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.asm.rdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.asm_labs.ddb b/EE203/Noah Woodlee/Decoder/db/decoder.asm_labs.ddb new file mode 100644 index 0000000..9e8f3e7 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.cbx.xml b/EE203/Noah Woodlee/Decoder/db/decoder.cbx.xml new file mode 100644 index 0000000..2ab7055 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.cmp.bpm b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.bpm new file mode 100644 index 0000000..2d8072f Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.bpm differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.cmp.cdb b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.cdb new file mode 100644 index 0000000..75cc98b Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.cmp.hdb b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.hdb new file mode 100644 index 0000000..8cf0cc7 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.cmp.idb b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.idb new file mode 100644 index 0000000..c9e6185 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.idb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.cmp.logdb b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.logdb new file mode 100644 index 0000000..32f4068 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.logdb @@ -0,0 +1,48 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;6;0;0;6;6;0;4;0;0;2;0;4;2;0;0;0;4;0;0;0;0;0;6;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,6;6;6;6;6;0;6;6;0;0;6;2;6;6;4;6;2;4;6;6;6;2;6;6;6;6;6;0;6;6, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Q0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Q1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Q2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Q3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.cmp.rdb b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.rdb new file mode 100644 index 0000000..0e9a19b Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.cmp.rdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.cmp_merge.kpt b/EE203/Noah Woodlee/Decoder/db/decoder.cmp_merge.kpt new file mode 100644 index 0000000..2715191 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.db_info b/EE203/Noah Woodlee/Decoder/db/decoder.db_info new file mode 100644 index 0000000..f5fd108 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Version_Index = 419480576 +Creation_Time = Thu Jan 21 19:32:30 2021 diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.eda.qmsg b/EE203/Noah Woodlee/Decoder/db/decoder.eda.qmsg new file mode 100644 index 0000000..1d26e17 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611281531256 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2016 Intel Corporation. All rights reserved. " "Copyright (C) 2016 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic " "and other software and tools, and its AMPP partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel MegaCore Function License Agreement, or other " "the Intel MegaCore Function License Agreement, or other " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable license agreement, including, without limitation, " "applicable license agreement, including, without limitation, " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "that your use is for the sole purpose of programming logic " "that your use is for the sole purpose of programming logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "devices manufactured by Intel and sold by Intel or its " "devices manufactured by Intel and sold by Intel or its " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "authorized distributors. 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" "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:12:11 2021 " "Processing started: Thu Jan 21 20:12:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531260 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/\" decoder -c decoder " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/\" decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531261 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1611281531461 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder.vo C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim// simulation " "Generated file decoder.vo in folder \"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1611281531492 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4641 " "Peak virtual memory: 4641 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:12:11 2021 " "Processing ended: Thu Jan 21 20:12:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531521 ""} diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.fit.qmsg b/EE203/Noah Woodlee/Decoder/db/decoder.fit.qmsg new file mode 100644 index 0000000..ad0012d --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.fit.qmsg @@ -0,0 +1,53 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1611280909024 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1611280909025 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "decoder 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"decoder\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611280909028 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611280909057 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611280909057 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1611280909212 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611280909217 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611280909289 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 26 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 28 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 30 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 32 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 34 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 36 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 38 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 40 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1611280909290 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611280909290 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611280909290 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611280909290 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611280909290 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1611280909291 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "6 6 " "No exact pin location assignment(s) for 6 pins of 6 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1611280909442 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "decoder.sdc " "Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611280909603 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611280909603 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611280909603 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611280909603 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1611280909603 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1611280909603 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1611280909603 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 2.5V 2 4 0 " "Number of I/O pins in group: 6 (unused VREF, 2.5V VCCIO, 2 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 20 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 36 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 48 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 48 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 40 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 60 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 52 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 32 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1611280909603 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280909613 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1611280909613 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1611280910413 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280910449 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1611280910463 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1611280910737 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280910737 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1611280912422 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X33_Y44 X44_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y44 to location X44_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y44 to location X44_Y54"} { { 12 { 0 ""} 33 44 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1611280913340 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1611280913340 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1611280913399 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1611280913399 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1611280913399 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280913402 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1611280913546 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611280913551 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611280913709 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611280913709 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611280913928 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280914229 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1611280914419 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5902 " "Peak virtual memory: 5902 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611280914763 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:01:54 2021 " "Processing ended: Thu Jan 21 20:01:54 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611280914763 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611280914763 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611280914763 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1611280914763 ""} diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.hier_info b/EE203/Noah Woodlee/Decoder/db/decoder.hier_info new file mode 100644 index 0000000..8b8da8e --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.hier_info @@ -0,0 +1,13 @@ +|decoder +Q0 <= inst.DB_MAX_OUTPUT_PORT_TYPE +B => inst7.IN0 +B => inst1.IN1 +B => inst3.IN1 +A => inst5.IN0 +A => inst2.IN0 +A => inst3.IN0 +Q1 <= inst1.DB_MAX_OUTPUT_PORT_TYPE +Q2 <= inst2.DB_MAX_OUTPUT_PORT_TYPE +Q3 <= inst3.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.hif b/EE203/Noah Woodlee/Decoder/db/decoder.hif new file mode 100644 index 0000000..10e6590 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.hif differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.lpc.html b/EE203/Noah Woodlee/Decoder/db/decoder.lpc.html new file mode 100644 index 0000000..7d68592 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.lpc.rdb b/EE203/Noah Woodlee/Decoder/db/decoder.lpc.rdb new file mode 100644 index 0000000..c179f4d Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.lpc.rdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.lpc.txt b/EE203/Noah Woodlee/Decoder/db/decoder.lpc.txt new file mode 100644 index 0000000..dbfe520 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map.ammdb b/EE203/Noah Woodlee/Decoder/db/decoder.map.ammdb new file mode 100644 index 0000000..a4afc79 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.map.ammdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map.bpm b/EE203/Noah Woodlee/Decoder/db/decoder.map.bpm new file mode 100644 index 0000000..66a808b Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.map.bpm differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map.cdb b/EE203/Noah Woodlee/Decoder/db/decoder.map.cdb new file mode 100644 index 0000000..be9112f Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.map.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map.hdb b/EE203/Noah Woodlee/Decoder/db/decoder.map.hdb new file mode 100644 index 0000000..c60f3ec Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.map.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map.kpt b/EE203/Noah Woodlee/Decoder/db/decoder.map.kpt new file mode 100644 index 0000000..db3ed27 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.map.kpt differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map.logdb b/EE203/Noah Woodlee/Decoder/db/decoder.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map.qmsg b/EE203/Noah Woodlee/Decoder/db/decoder.map.qmsg new file mode 100644 index 0000000..3291be9 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.map.qmsg @@ -0,0 +1,11 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611280900987 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611280900991 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:01:40 2021 " "Processing started: Thu Jan 21 20:01:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611280900991 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611280900991 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611280900991 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1611280901215 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1611280901215 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Found entity 1: decoder" { } { { "decoder.bdf" "" { Schematic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611280907273 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611280907273 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "decoder " "Elaborating entity \"decoder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1611280907290 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1611280907580 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1611280907858 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611280907858 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1611280907897 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1611280907897 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1611280907897 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1611280907897 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4788 " "Peak virtual memory: 4788 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611280907912 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:01:47 2021 " "Processing ended: Thu Jan 21 20:01:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611280907912 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611280907912 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611280907912 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1611280907912 ""} diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map.rdb b/EE203/Noah Woodlee/Decoder/db/decoder.map.rdb new file mode 100644 index 0000000..989e4fe Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.map.rdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.cdb b/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.cdb new file mode 100644 index 0000000..e2e020d Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.hdb b/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.hdb new file mode 100644 index 0000000..9176267 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.logdb b/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.pre_map.hdb b/EE203/Noah Woodlee/Decoder/db/decoder.pre_map.hdb new file mode 100644 index 0000000..3f9e93f Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.pre_map.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.root_partition.map.reg_db.cdb b/EE203/Noah Woodlee/Decoder/db/decoder.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..9d09873 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.root_partition.map.reg_db.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.routing.rdb b/EE203/Noah Woodlee/Decoder/db/decoder.routing.rdb new file mode 100644 index 0000000..dc01f86 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.routing.rdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.rtlv.hdb b/EE203/Noah Woodlee/Decoder/db/decoder.rtlv.hdb new file mode 100644 index 0000000..5f74350 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.rtlv.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.rtlv_sg.cdb b/EE203/Noah Woodlee/Decoder/db/decoder.rtlv_sg.cdb new file mode 100644 index 0000000..1df38b5 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.rtlv_sg.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.rtlv_sg_swap.cdb b/EE203/Noah Woodlee/Decoder/db/decoder.rtlv_sg_swap.cdb new file mode 100644 index 0000000..0be030c Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.rtlv_sg_swap.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.sld_design_entry.sci b/EE203/Noah Woodlee/Decoder/db/decoder.sld_design_entry.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.sld_design_entry.sci differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.sld_design_entry_dsc.sci b/EE203/Noah Woodlee/Decoder/db/decoder.sld_design_entry_dsc.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.smart_action.txt b/EE203/Noah Woodlee/Decoder/db/decoder.smart_action.txt new file mode 100644 index 0000000..f1e1649 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.sta.qmsg b/EE203/Noah Woodlee/Decoder/db/decoder.sta.qmsg new file mode 100644 index 0000000..b9244ce --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.sta.qmsg @@ -0,0 +1,50 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611280918793 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611280918797 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:01:58 2021 " "Processing started: Thu Jan 21 20:01:58 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611280918797 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280918797 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta decoder -c decoder " "Command: quartus_sta decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280918797 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280918863 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280918987 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280918987 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919013 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919013 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "decoder.sdc " "Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919199 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919199 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919199 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919200 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919200 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919200 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280919200 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919202 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280919202 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919202 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1611280919202 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919215 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919219 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919223 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919227 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919230 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280919236 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919255 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920275 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920333 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920337 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920341 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920343 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920343 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280920353 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920476 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920476 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920477 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920477 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920481 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920485 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920489 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920493 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920497 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280921050 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280921050 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4872 " "Peak virtual memory: 4872 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611280921083 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:02:01 2021 " "Processing ended: Thu Jan 21 20:02:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611280921083 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611280921083 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611280921083 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280921083 ""} diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.sta.rdb b/EE203/Noah Woodlee/Decoder/db/decoder.sta.rdb new file mode 100644 index 0000000..c556dca Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.sta.rdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.sta_cmp.7_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/Decoder/db/decoder.sta_cmp.7_slow_1200mv_85c.tdb new file mode 100644 index 0000000..044c530 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.sta_cmp.7_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.tis_db_list.ddb b/EE203/Noah Woodlee/Decoder/db/decoder.tis_db_list.ddb new file mode 100644 index 0000000..eda1a82 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..185dc31 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_0c.ddb b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..d614d52 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_85c.ddb b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..ae44f6b Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..312c391 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..3473cfe Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.tmw_info b/EE203/Noah Woodlee/Decoder/db/decoder.tmw_info new file mode 100644 index 0000000..e2678c2 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder.tmw_info @@ -0,0 +1,2 @@ +start_analysis_synthesis:s:00:00:08-start_full_compilation +start_analysis_elaboration:s-start_full_compilation diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.vpr.ammdb b/EE203/Noah Woodlee/Decoder/db/decoder.vpr.ammdb new file mode 100644 index 0000000..8a7c927 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..db68b29 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ii_0c_slow.hsd b/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..d223770 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ii_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ii_85c_slow.hsd b/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..68203ec Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/db/decoder.zippleback_io_sim_cache.ii_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Decoder/db/decoder_partition_pins.json b/EE203/Noah Woodlee/Decoder/db/decoder_partition_pins.json new file mode 100644 index 0000000..14c75c7 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/db/decoder_partition_pins.json @@ -0,0 +1,33 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "Q0", + "strict" : false + }, + { + "name" : "Q1", + "strict" : false + }, + { + "name" : "Q2", + "strict" : false + }, + { + "name" : "Q3", + "strict" : false + }, + { + "name" : "B", + "strict" : false + }, + { + "name" : "A", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Decoder/decoder.bdf b/EE203/Noah Woodlee/Decoder/decoder.bdf new file mode 100644 index 0000000..2f0f752 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/decoder.bdf @@ -0,0 +1,409 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 136 272 304 288) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "A" (rect 5 0 14 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 136 400 304 416) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "B" (rect 5 0 13 17)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 632 232 808 248) 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(bold))(invisible)) + (line (pt 42 24)(pt 64 24)) + ) + (drawing + (line (pt 14 12)(pt 30 12)) + (line (pt 14 37)(pt 31 37)) + (line (pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) +(symbol + (rect 384 288 432 320) + (text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6))) + (text "inst5" (rect 3 21 25 38)(font "Intel Clear" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(symbol + (rect 384 392 432 424) + (text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6))) + (text "inst7" (rect 3 21 25 38)(font "Intel Clear" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(connector + (pt 568 248) + (pt 560 248) +) +(connector + (pt 560 248) + (pt 560 304) +) +(connector + (pt 304 280) + (pt 336 280) +) +(connector + (pt 336 304) + (pt 384 304) +) +(connector + (pt 568 232) + (pt 480 232) +) +(connector + (pt 480 232) + (pt 480 408) +) +(connector + (pt 360 512) + (pt 568 512) +) +(connector + (pt 304 408) + (pt 360 408) +) +(connector + (pt 360 408) + (pt 384 408) +) +(connector + (pt 336 280) + (pt 336 304) +) +(connector + (pt 336 304) + (pt 336 464) +) +(connector + (pt 568 464) + (pt 568 496) +) +(connector + (pt 488 464) + (pt 488 416) +) +(connector + (pt 488 416) + (pt 568 416) +) +(connector + (pt 336 464) + (pt 488 464) +) +(connector + (pt 488 464) + (pt 568 464) +) +(connector + (pt 568 432) + (pt 456 432) +) +(connector + (pt 456 432) + (pt 456 408) +) +(connector + (pt 480 408) + (pt 456 408) +) +(connector + (pt 456 408) + (pt 432 408) +) +(connector + (pt 568 320) + (pt 528 320) +) +(connector + (pt 528 320) + (pt 528 304) +) +(connector + (pt 560 304) + (pt 528 304) +) +(connector + (pt 528 304) + (pt 432 304) +) +(connector + (pt 360 336) + (pt 568 336) +) +(connector + (pt 360 336) + (pt 360 408) +) +(connector + (pt 360 408) + (pt 360 512) +) +(junction (pt 360 408)) +(junction (pt 336 304)) +(junction (pt 488 464)) +(junction (pt 456 408)) +(junction (pt 528 304)) diff --git a/EE203/Noah Woodlee/Decoder/decoder.qpf b/EE203/Noah Woodlee/Decoder/decoder.qpf new file mode 100644 index 0000000..bbf2d22 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/decoder.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 19:32:30 January 21, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "19:32:30 January 21, 2021" + +# Revisions + +PROJECT_REVISION = "decoder" diff --git a/EE203/Noah Woodlee/Decoder/decoder.qsf b/EE203/Noah Woodlee/Decoder/decoder.qsf new file mode 100644 index 0000000..c6fc31c --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/decoder.qsf @@ -0,0 +1,61 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 19:32:30 January 21, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# decoder_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY decoder +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:32:30 JANUARY 21, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name BDF_FILE decoder.bdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_C10 -to A +set_location_assignment PIN_C11 -to B +set_location_assignment PIN_A8 -to Q0 +set_location_assignment PIN_A9 -to Q1 +set_location_assignment PIN_A10 -to Q2 +set_location_assignment PIN_B10 -to Q3 +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf \ No newline at end of file diff --git a/EE203/Noah Woodlee/Decoder/decoder.qws b/EE203/Noah Woodlee/Decoder/decoder.qws new file mode 100644 index 0000000..4feb9cf Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/decoder.qws differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/README b/EE203/Noah Woodlee/Decoder/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.db_info b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.db_info new file mode 100644 index 0000000..bec5092 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Version_Index = 419480576 +Creation_Time = Thu Jan 21 20:01:47 2021 diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.ammdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.ammdb new file mode 100644 index 0000000..d9ee6c7 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.cdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.cdb new file mode 100644 index 0000000..c68e967 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.dfp b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.hdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.hdb new file mode 100644 index 0000000..d2c6fdd Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.logdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.rcfdb new file mode 100644 index 0000000..29c7d68 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.cdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.cdb new file mode 100644 index 0000000..fb72e48 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.dpi b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.dpi new file mode 100644 index 0000000..4d6717b Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..d454b85 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..212f4b7 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hdb new file mode 100644 index 0000000..0f5753f Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.kpt b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.kpt new file mode 100644 index 0000000..91bacec Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.rrp.hdb b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.rrp.hdb new file mode 100644 index 0000000..b5208b8 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/incremental_db/compiled_partitions/decoder.rrp.hdb differ diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.asm.rpt b/EE203/Noah Woodlee/Decoder/output_files/decoder.asm.rpt new file mode 100644 index 0000000..272fd0f --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.asm.rpt @@ -0,0 +1,93 @@ +Assembler report for decoder +Thu Jan 21 20:01:57 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Jan 21 20:01:57 2021 ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++------------------------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------------------------+ +; File Name ; ++------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof ; ++------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof ; ++----------------+---------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------------------------+ +; Device ; 10M50DAF484C7G ; +; JTAG usercode ; 0x0026FF7D ; +; Checksum ; 0x0026FF7D ; ++----------------+---------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Jan 21 20:01:55 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4685 megabytes + Info: Processing ended: Thu Jan 21 20:01:57 2021 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.done b/EE203/Noah Woodlee/Decoder/output_files/decoder.done new file mode 100644 index 0000000..dec96e3 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.done @@ -0,0 +1 @@ +Thu Jan 21 20:02:01 2021 diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.eda.rpt b/EE203/Noah Woodlee/Decoder/output_files/decoder.eda.rpt new file mode 100644 index 0000000..87cf935 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for decoder +Thu Jan 21 20:12:11 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Jan 21 20:12:11 2021 ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++---------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//decoder.vo ; ++---------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Jan 21 20:12:11 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file decoder.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Jan 21 20:12:11 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.rpt b/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.rpt new file mode 100644 index 0000000..8704ec1 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.rpt @@ -0,0 +1,1215 @@ +Fitter report for decoder +Thu Jan 21 20:01:54 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Jan 21 20:01:54 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 5 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 6 / 360 ( 2 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C7G ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.1% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 36 ) ; 0.00 % ( 0 / 36 ) ; 0.00 % ( 0 / 36 ) ; +; -- Achieved ; 0.00 % ( 0 / 36 ) ; 0.00 % ( 0 / 36 ) ; 0.00 % ( 0 / 36 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 20 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 5 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 5 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 5 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 6 / 360 ( 2 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 29 ; +; Average fan-out ; 0.81 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 5 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 5 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 5 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 5 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 6 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 35 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 2 ; 0 ; +; -- Output Ports ; 4 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; A ; W4 ; 3 ; 18 ; 0 ; 14 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; B ; W3 ; 3 ; 18 ; 0 ; 7 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Q0 ; Y2 ; 3 ; 16 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Q1 ; AA1 ; 3 ; 18 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Q2 ; AA2 ; 3 ; 18 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Q3 ; U7 ; 3 ; 16 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 6 / 48 ( 13 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 0 / 60 ( 0 % ) ; 2.5V ; -- ; +; 7 ; 0 / 52 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; Q1 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA2 ; 135 ; 3 ; Q2 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C12 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 391 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 388 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; Q3 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; B ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W4 ; 132 ; 3 ; A ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; Q0 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; Q0 ; Incomplete set of assignments ; +; Q1 ; Incomplete set of assignments ; +; Q2 ; Incomplete set of assignments ; +; Q3 ; Incomplete set of assignments ; +; B ; Incomplete set of assignments ; +; A ; Incomplete set of assignments ; +; Q0 ; Missing location assignment ; +; Q1 ; Missing location assignment ; +; Q2 ; Missing location assignment ; +; Q3 ; Missing location assignment ; +; B ; Missing location assignment ; +; A ; Missing location assignment ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |decoder ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 6 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; |decoder ; decoder ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Q0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Q1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Q2 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Q3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; B ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; A ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; B ; ; ; +; - inst ; 1 ; 6 ; +; - inst2~0 ; 1 ; 6 ; +; - inst2~1 ; 1 ; 6 ; +; - inst2~2 ; 1 ; 6 ; +; A ; ; ; +; - inst ; 1 ; 6 ; +; - inst2~0 ; 1 ; 6 ; +; - inst2~1 ; 1 ; 6 ; +; - inst2~2 ; 1 ; 6 ; ++---------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 10 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 0 / 5,382 ( 0 % ) ; +; C4 interconnects ; 11 / 106,704 ( < 1 % ) ; +; Direct links ; 0 / 148,641 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 49,760 ( 0 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 0 / 5,406 ( 0 % ) ; +; R4 interconnects ; 1 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 2.50) ; Number of LABs (Total = 2) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 2.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 2.50) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 1.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 6 ; 6 ; 0 ; 4 ; 0 ; 0 ; 2 ; 0 ; 4 ; 2 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 6 ; 6 ; 6 ; 6 ; 6 ; 0 ; 6 ; 6 ; 0 ; 0 ; 6 ; 2 ; 6 ; 6 ; 4 ; 6 ; 2 ; 4 ; 6 ; 6 ; 6 ; 2 ; 6 ; 6 ; 6 ; 6 ; 6 ; 0 ; 6 ; 6 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Q0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Q1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Q2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Q3 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (119006): Selected device 10M50DAF484C7G for design "decoder" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 10M08DAF484I7G is compatible + Info (176445): Device 10M16DAF484C7G is compatible + Info (176445): Device 10M16DAF484I7G is compatible + Info (176445): Device 10M25DAF484C7G is compatible + Info (176445): Device 10M25DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7P is compatible + Info (176445): Device 10M40DAF484C7G is compatible + Info (176445): Device 10M40DAF484I7G is compatible +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 6 pins of 6 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 6 (unused VREF, 2.5V VCCIO, 2 input, 4 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available + Info (176213): I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y44 to location X44_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 5902 megabytes + Info: Processing ended: Thu Jan 21 20:01:54 2021 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:08 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg. + + diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.smsg b/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.smsg new file mode 100644 index 0000000..558ea95 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.summary b/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.summary new file mode 100644 index 0000000..dda2637 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Thu Jan 21 20:01:54 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : decoder +Top-level Entity Name : decoder +Family : MAX 10 +Device : 10M50DAF484C7G +Timing Models : Final +Total logic elements : 5 / 49,760 ( < 1 % ) + Total combinational functions : 5 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 6 / 360 ( 2 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.flow.rpt b/EE203/Noah Woodlee/Decoder/output_files/decoder.flow.rpt new file mode 100644 index 0000000..6b74b48 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.flow.rpt @@ -0,0 +1,137 @@ +Flow report for decoder +Thu Jan 21 20:12:11 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Jan 21 20:12:11 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 5 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 6 / 360 ( 2 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 01/21/2021 20:01:41 ; +; Main task ; Compilation ; +; Revision Name ; decoder ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 189559947077153.161128090107632 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 4788 MB ; 00:00:16 ; +; Fitter ; 00:00:06 ; 1.0 ; 5902 MB ; 00:00:08 ; +; Assembler ; 00:00:02 ; 1.0 ; 4685 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4872 MB ; 00:00:02 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:00 ; +; Total ; 00:00:18 ; -- ; -- ; 00:00:28 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder +quartus_fit --read_settings_files=off --write_settings_files=off decoder -c decoder +quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder +quartus_sta decoder -c decoder +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder + + + diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.jdi b/EE203/Noah Woodlee/Decoder/output_files/decoder.jdi new file mode 100644 index 0000000..bb6ca07 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.map.rpt b/EE203/Noah Woodlee/Decoder/output_files/decoder.map.rpt new file mode 100644 index 0000000..ce5ece4 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.map.rpt @@ -0,0 +1,284 @@ +Analysis & Synthesis report for decoder +Thu Jan 21 20:01:47 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Jan 21 20:01:47 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Total logic elements ; 4 ; +; Total combinational functions ; 4 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 6 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C7G ; ; +; Top-level entity name ; decoder ; decoder ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+ +; decoder.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf ; ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+ + + ++-------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------+ +; Resource ; Usage ; ++---------------------------------------------+---------+ +; Estimated Total logic elements ; 4 ; +; ; ; +; Total combinational functions ; 4 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 4 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 4 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 6 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; B~input ; +; Maximum fan-out ; 4 ; +; Total fan-out ; 18 ; +; Average fan-out ; 1.13 ; ++---------------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |decoder ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; |decoder ; decoder ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 6 ; +; cycloneiii_lcell_comb ; 5 ; +; normal ; 5 ; +; 1 data inputs ; 1 ; +; 2 data inputs ; 4 ; +; ; ; +; Max LUT depth ; 2.00 ; +; Average LUT depth ; 1.57 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Jan 21 20:01:40 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file decoder.bdf + Info (12023): Found entity 1: decoder +Info (12127): Elaborating entity "decoder" for the top level hierarchy +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 10 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 2 input pins + Info (21059): Implemented 4 output pins + Info (21061): Implemented 4 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4788 megabytes + Info: Processing ended: Thu Jan 21 20:01:47 2021 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:16 + + diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.map.summary b/EE203/Noah Woodlee/Decoder/output_files/decoder.map.summary new file mode 100644 index 0000000..4fdb692 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Thu Jan 21 20:01:47 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : decoder +Top-level Entity Name : decoder +Family : MAX 10 +Total logic elements : 4 + Total combinational functions : 4 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 6 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.pin b/EE203/Noah Woodlee/Decoder/output_files/decoder.pin new file mode 100644 index 0000000..4e3679d --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2016 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel MegaCore Function License Agreement, or other + -- applicable license agreement, including, without limitation, + -- that your use is for the sole purpose of programming logic + -- devices manufactured by Intel and sold by Intel or its + -- authorized distributors. Please refer to the applicable + -- agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +CHIP "decoder" ASSIGNED TO AN: 10M50DAF484C7G + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +Q1 : AA1 : output : 2.5 V : : 3 : N +Q2 : AA2 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +GND : B13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +Q3 : U7 : output : 2.5 V : : 3 : N +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +B : W3 : input : 2.5 V : : 3 : N +A : W4 : input : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +Q0 : Y2 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.pof b/EE203/Noah Woodlee/Decoder/output_files/decoder.pof new file mode 100644 index 0000000..cfc032e Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/output_files/decoder.pof differ diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.sld b/EE203/Noah Woodlee/Decoder/output_files/decoder.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.sof b/EE203/Noah Woodlee/Decoder/output_files/decoder.sof new file mode 100644 index 0000000..ff35735 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/output_files/decoder.sof differ diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.sta.rpt b/EE203/Noah Woodlee/Decoder/output_files/decoder.sta.rpt new file mode 100644 index 0000000..4fe7c04 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.sta.rpt @@ -0,0 +1,443 @@ +TimeQuest Timing Analyzer report for decoder +Thu Jan 21 20:02:01 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; decoder ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.2% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Q0 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Q1 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Q2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Q3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; B ; 2.5 V ; 2000 ps ; 2000 ps ; +; A ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 2 ; 2 ; +; Unconstrained Input Port Paths ; 8 ; 8 ; +; Unconstrained Output Ports ; 4 ; 4 ; +; Unconstrained Output Port Paths ; 8 ; 8 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Q0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Q0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Jan 21 20:01:58 2021 +Info: Command: quartus_sta decoder -c decoder +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4872 megabytes + Info: Processing ended: Thu Jan 21 20:02:01 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/EE203/Noah Woodlee/Decoder/output_files/decoder.sta.summary b/EE203/Noah Woodlee/Decoder/output_files/decoder.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/output_files/decoder.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt b/EE203/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt new file mode 100644 index 0000000..ace2249 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt @@ -0,0 +1,80 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "01/21/2021 20:12:10" + +// Verilog Test Bench (with test vectors) for design : decoder +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module decoder_vlg_vec_tst(); +// constants +// general purpose registers +reg A; +reg B; +// wires +wire Q0; +wire Q1; +wire Q2; +wire Q3; + +// assign statements (if any) +decoder i1 ( +// port map - connection between master ports and signals/registers + .A(A), + .B(B), + .Q0(Q0), + .Q1(Q1), + .Q2(Q2), + .Q3(Q3) +); +initial +begin +#200000 $finish; +end + +// A +initial +begin + A = 1'b0; + A = #10000 1'b1; + A = #20000 1'b0; + A = #30000 1'b1; + A = #30000 1'b0; + A = #60000 1'b1; + A = #10000 1'b0; +end + +// B +initial +begin + B = 1'b0; + B = #60000 1'b1; + B = #30000 1'b0; + B = #20000 1'b1; + B = #10000 1'b0; + B = #30000 1'b1; + B = #10000 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.do b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.do new file mode 100644 index 0000000..ca3c9f7 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vlog -work work decoder.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +vcd file -direction decoder.msim.vcd +vcd add -internal decoder_vlg_vec_tst/* +vcd add -internal decoder_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.msim.vcd b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.msim.vcd new file mode 100644 index 0000000..6e01868 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.msim.vcd @@ -0,0 +1,156 @@ +$comment + File created using the following command: + vcd file decoder.msim.vcd -direction +$end +$date + Thu Jan 21 20:12:12 2021 +$end +$version + ModelSim Version 10.5b +$end +$timescale + 1ps +$end + +$scope module decoder_vlg_vec_tst $end +$var reg 1 ! A $end +$var reg 1 " B $end +$var wire 1 # Q0 $end +$var wire 1 $ Q1 $end +$var wire 1 % Q2 $end +$var wire 1 & Q3 $end + +$scope module i1 $end +$var wire 1 ' gnd $end +$var wire 1 ( vcc $end +$var wire 1 ) unknown $end +$var tri1 1 * devclrn $end +$var tri1 1 + devpor $end +$var tri1 1 , devoe $end +$var wire 1 - ~QUARTUS_CREATED_GND~I_combout $end +$var wire 1 . ~QUARTUS_CREATED_UNVM~~busy $end +$var wire 1 / ~QUARTUS_CREATED_ADC1~~eoc $end +$var wire 1 0 ~QUARTUS_CREATED_ADC2~~eoc $end +$var wire 1 1 Q0~output_o $end +$var wire 1 2 Q1~output_o $end +$var wire 1 3 Q2~output_o $end +$var wire 1 4 Q3~output_o $end +$var wire 1 5 B~input_o $end +$var wire 1 6 A~input_o $end +$var wire 1 7 inst~combout $end +$var wire 1 8 inst2~0_combout $end +$var wire 1 9 inst2~1_combout $end +$var wire 1 : inst2~2_combout $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0! +0" +1# +0$ +0% +0& +0' +1( +x) +1* +1+ +1, +0- +z. +z/ +z0 +11 +02 +03 +04 +05 +06 +07 +08 +09 +0: +$end +#10000 +1! +16 +17 +19 +13 +01 +0# +1% +#30000 +0! +06 +07 +09 +03 +11 +1# +0% +#60000 +1" +1! +16 +15 +17 +1: +14 +01 +0# +1& +#90000 +0" +0! +06 +05 +07 +0: +04 +11 +1# +0& +#110000 +1" +15 +17 +18 +12 +01 +0# +1$ +#120000 +0" +05 +07 +08 +02 +11 +1# +0$ +#150000 +1! +1" +15 +16 +17 +1: +14 +01 +0# +1& +#160000 +0! +0" +05 +06 +07 +0: +04 +11 +1# +0& +#200000 diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.sft b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.sft new file mode 100644 index 0000000..f324fea --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.vo b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.vo new file mode 100644 index 0000000..8eb8440 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.vo @@ -0,0 +1,383 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" + +// DATE "01/21/2021 20:12:11" + +// +// Device: Altera 10M50DAF484C7G Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module decoder ( + Q0, + B, + A, + Q1, + Q2, + Q3); +output Q0; +input B; +input A; +output Q1; +output Q2; +output Q3; + +// Design Ports Information +// Q0 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default +// Q1 => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default +// Q2 => Location: PIN_AA2, I/O Standard: 2.5 V, Current Strength: Default +// Q3 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default +// B => Location: PIN_W3, I/O Standard: 2.5 V, Current Strength: Default +// A => Location: PIN_W4, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \~QUARTUS_CREATED_UNVM~~busy ; +wire \~QUARTUS_CREATED_ADC1~~eoc ; +wire \~QUARTUS_CREATED_ADC2~~eoc ; +wire \Q0~output_o ; +wire \Q1~output_o ; +wire \Q2~output_o ; +wire \Q3~output_o ; +wire \B~input_o ; +wire \A~input_o ; +wire \inst~combout ; +wire \inst2~0_combout ; +wire \inst2~1_combout ; +wire \inst2~2_combout ; + + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: LCCOMB_X44_Y42_N8 +fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): +// \~QUARTUS_CREATED_GND~I_combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .cout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000; +defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +fiftyfivenm_io_obuf \Q0~output ( + .i(!\inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Q0~output_o ), + .obar()); +// synopsys translate_off +defparam \Q0~output .bus_hold = "false"; +defparam \Q0~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N30 +fiftyfivenm_io_obuf \Q1~output ( + .i(\inst2~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Q1~output_o ), + .obar()); +// synopsys translate_off +defparam \Q1~output .bus_hold = "false"; +defparam \Q1~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N23 +fiftyfivenm_io_obuf \Q2~output ( + .i(\inst2~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Q2~output_o ), + .obar()); +// synopsys translate_off +defparam \Q2~output .bus_hold = "false"; +defparam \Q2~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N2 +fiftyfivenm_io_obuf \Q3~output ( + .i(\inst2~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Q3~output_o ), + .obar()); +// synopsys translate_off +defparam \Q3~output .bus_hold = "false"; +defparam \Q3~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +fiftyfivenm_io_ibuf \B~input ( + .i(B), + .ibar(gnd), + .nsleep(vcc), + .o(\B~input_o )); +// synopsys translate_off +defparam \B~input .bus_hold = "false"; +defparam \B~input .listen_to_nsleep_signal = "false"; +defparam \B~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N15 +fiftyfivenm_io_ibuf \A~input ( + .i(A), + .ibar(gnd), + .nsleep(vcc), + .o(\A~input_o )); +// synopsys translate_off +defparam \A~input .bus_hold = "false"; +defparam \A~input .listen_to_nsleep_signal = "false"; +defparam \A~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y1_N0 +fiftyfivenm_lcell_comb inst( +// Equation(s): +// \inst~combout = (\B~input_o ) # (\A~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\B~input_o ), + .datad(\A~input_o ), + .cin(gnd), + .combout(\inst~combout ), + .cout()); +// synopsys translate_off +defparam inst.lut_mask = 16'hFFF0; +defparam inst.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y1_N2 +fiftyfivenm_lcell_comb \inst2~0 ( +// Equation(s): +// \inst2~0_combout = (\B~input_o & !\A~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\B~input_o ), + .datad(\A~input_o ), + .cin(gnd), + .combout(\inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst2~0 .lut_mask = 16'h00F0; +defparam \inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y1_N4 +fiftyfivenm_lcell_comb \inst2~1 ( +// Equation(s): +// \inst2~1_combout = (!\B~input_o & \A~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\B~input_o ), + .datad(\A~input_o ), + .cin(gnd), + .combout(\inst2~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst2~1 .lut_mask = 16'h0F00; +defparam \inst2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y1_N6 +fiftyfivenm_lcell_comb \inst2~2 ( +// Equation(s): +// \inst2~2_combout = (\B~input_o & \A~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\B~input_o ), + .datad(\A~input_o ), + .cin(gnd), + .combout(\inst2~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst2~2 .lut_mask = 16'hF000; +defparam \inst2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: UNVM_X0_Y40_N40 +fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ ( + .arclk(vcc), + .arshft(vcc), + .drclk(vcc), + .drshft(vcc), + .drdin(vcc), + .nprogram(vcc), + .nerase(vcc), + .nosc_ena(\~QUARTUS_CREATED_GND~I_combout ), + .par_en(vcc), + .xe_ye(\~QUARTUS_CREATED_GND~I_combout ), + .se(\~QUARTUS_CREATED_GND~I_combout ), + .ardin(23'b11111111111111111111111), + .busy(\~QUARTUS_CREATED_UNVM~~busy ), + .osc(), + .bgpbusy(), + .sp_pass(), + .se_pass(), + .drdout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm"; +defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true"; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y52_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC1~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1; +defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y51_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC2~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2; +defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0; +// synopsys translate_on + +assign Q0 = \Q0~output_o ; + +assign Q1 = \Q1~output_o ; + +assign Q2 = \Q2~output_o ; + +assign Q3 = \Q3~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_TMS~~padout ; +wire \~ALTERA_TCK~~padout ; +wire \~ALTERA_TDI~~padout ; +wire \~ALTERA_CONFIG_SEL~~padout ; +wire \~ALTERA_nCONFIG~~padout ; +wire \~ALTERA_nSTATUS~~padout ; +wire \~ALTERA_CONF_DONE~~padout ; +wire \~ALTERA_TMS~~ibuf_o ; +wire \~ALTERA_TCK~~ibuf_o ; +wire \~ALTERA_TDI~~ibuf_o ; +wire \~ALTERA_CONFIG_SEL~~ibuf_o ; +wire \~ALTERA_nCONFIG~~ibuf_o ; +wire \~ALTERA_nSTATUS~~ibuf_o ; +wire \~ALTERA_CONF_DONE~~ibuf_o ; + + +endmodule diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201117.sim.vwf b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201117.sim.vwf new file mode 100644 index 0000000..c6ea50f --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201117.sim.vwf @@ -0,0 +1,255 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 200.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Q0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("A") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("B") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("Q0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 40.0; + } + } +} + +TRANSITION_LIST("Q1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("Q2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 170.0; + } + } +} + +TRANSITION_LIST("Q3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf new file mode 100644 index 0000000..c0a5d1e --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf @@ -0,0 +1,261 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 200.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Q0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("A") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("B") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("Q0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 40.0; + } + } +} + +TRANSITION_LIST("Q1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 80.0; + } + } +} + +TRANSITION_LIST("Q2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 170.0; + } + } +} + +TRANSITION_LIST("Q3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_modelsim.xrf b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_modelsim.xrf new file mode 100644 index 0000000..b726119 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_modelsim.xrf @@ -0,0 +1,25 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/db/decoder.cbx.xml +design_name = decoder +instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, decoder, 1 +instance = comp, \Q0~output , Q0~output, decoder, 1 +instance = comp, \Q1~output , Q1~output, decoder, 1 +instance = comp, \Q2~output , Q2~output, decoder, 1 +instance = comp, \Q3~output , Q3~output, decoder, 1 +instance = comp, \B~input , B~input, decoder, 1 +instance = comp, \A~input , A~input, decoder, 1 +instance = comp, \inst2~0 , inst2~0, decoder, 1 +instance = comp, \inst2~1 , inst2~1, decoder, 1 +instance = comp, \inst2~2 , inst2~2, decoder, 1 +instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, decoder, 1 +instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, decoder, 1 +instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, decoder, 1 +design_name = hard_block +instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1 diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/transcript b/EE203/Noah Woodlee/Decoder/simulation/qsim/transcript new file mode 100644 index 0000000..3ffa8fc --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/transcript @@ -0,0 +1,37 @@ +# do decoder.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:12:11 on Jan 21,2021 +# vlog -work work decoder.vo +# -- Compiling module decoder +# -- Compiling module hard_block +# +# Top level modules: +# decoder +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:12:12 on Jan 21,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module decoder_vlg_vec_tst +# +# Top level modules: +# decoder_vlg_vec_tst +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +# Start time: 20:12:12 on Jan 21,2021 +# Loading work.decoder_vlg_vec_tst +# Loading work.decoder +# Loading work.hard_block +# ** Warning: (vsim-3017) decoder.vo(284): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) decoder.vo(284): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) decoder.vo(307): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) decoder.vo(307): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform.vwf.vt(53) +# Time: 200 ns Iteration: 0 Instance: /decoder_vlg_vec_tst +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4 diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/vwf_sim_transcript b/EE203/Noah Woodlee/Decoder/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..1ee67bd --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,141 @@ +Determining the location of the ModelSim executable... + +Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Jan 21 20:12:10 2021 +Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. + +Completed successfully. + +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Jan 21 20:12:11 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file decoder.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Jan 21 20:12:11 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + +Completed successfully. + +**** Generating the ModelSim .do script **** + +C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do decoder.do + +Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl + + +# 10.5b + +# do decoder.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:12:11 on Jan 21,2021 +# vlog -work work decoder.vo +# -- Compiling module decoder +# -- Compiling module hard_block +# +# Top level modules: +# decoder + +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:12:12 on Jan 21,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module decoder_vlg_vec_tst +# +# Top level modules: +# decoder_vlg_vec_tst +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +# Start time: 20:12:12 on Jan 21,2021 +# Loading work.decoder_vlg_vec_tst +# Loading work.decoder +# Loading work.hard_block +# ** Warning: (vsim-3017) decoder.vo(284): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) decoder.vo(284): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) decoder.vo(307): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) decoder.vo(307): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform.vwf.vt(53) +# Time: 200 ns Iteration: 0 Instance: /decoder_vlg_vec_tst +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4 + +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf... + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder.msim.vcd... + +Processing channel transitions... + +Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf + +Finished VCD to VWF conversion. + +Completed successfully. + +All completed. \ No newline at end of file diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_info b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_info new file mode 100644 index 0000000..8e21126 --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_info @@ -0,0 +1,73 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dC:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim +vdecoder +Z1 !s110 1611281532 +!i10b 1 +!s100 UIL90zBZg0Y19`leS`6h<2 +I?kJ^Dj<_UL0j=K>IoSLA43 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +Z3 w1611281531 +Z4 8decoder.vo +Z5 Fdecoder.vo +L0 32 +Z6 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z7 !s108 1611281531.000000 +Z8 !s107 decoder.vo| +Z9 !s90 -work|work|decoder.vo| +!i113 1 +Z10 o-work work +Z11 tCvgOpt 0 +vdecoder_vlg_vec_tst +R1 +!i10b 1 +!s100 ]Ca;=HzRX6Lo`OmRLo6W[1 +IK[F>kI[RnW?^K1G37[MAK1 +R2 +R0 +w1611281530 +8Waveform.vwf.vt +FWaveform.vwf.vt +L0 30 +R6 +r1 +!s85 0 +31 +!s108 1611281532.000000 +!s107 Waveform.vwf.vt| +!s90 -work|work|Waveform.vwf.vt| +!i113 1 +R10 +R11 +vhard_block +R1 +!i10b 1 +!s100 =YQAZHYcKj^4X8AX_30Gh2 +I`Y@_E2FIMAN_fQ3cHX1n?2 +R2 +R0 +R3 +R4 +R5 +L0 339 +R6 +r1 +!s85 0 +31 +R7 +R8 +R9 +!i113 1 +R10 +R11 diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib.qdb b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib.qdb new file mode 100644 index 0000000..d9b590a Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib.qdb differ diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qdb b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qdb new file mode 100644 index 0000000..2c2a282 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qdb differ diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qpg b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qpg new file mode 100644 index 0000000..c61b8b0 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qpg differ diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qtl b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qtl new file mode 100644 index 0000000..a3fb234 Binary files /dev/null and b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_lib1_0.qtl differ diff --git a/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_vmake b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/EE203/Noah Woodlee/Decoder/simulation/qsim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/EE203/Noah Woodlee/LAB1/Decoder/Waveform.vwf b/EE203/Noah Woodlee/LAB1/Decoder/Waveform.vwf new file mode 100644 index 0000000..0c2c986 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/Waveform.vwf @@ -0,0 +1,264 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +onerror {exit -code 1} +vlib work +vlog -work work decoder.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +vcd file -direction decoder.msim.vcd +vcd add -internal decoder_vlg_vec_tst/* +vcd add -internal decoder_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work decoder.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +vcd file -direction decoder.msim.vcd +vcd add -internal decoder_vlg_vec_tst/* +vcd add -internal decoder_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 200.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Q0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("A") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } +} + +TRANSITION_LIST("B") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } +} + +TRANSITION_LIST("Q0") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 200.0; + } +} + +TRANSITION_LIST("Q1") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 200.0; + } +} + +TRANSITION_LIST("Q2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 200.0; + } +} + +TRANSITION_LIST("Q3") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 200.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Decoder/atom_netlists/decoder.qsf b/EE203/Noah Woodlee/LAB1/Decoder/atom_netlists/decoder.qsf new file mode 100644 index 0000000..5e7f941 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/atom_netlists/decoder.qsf @@ -0,0 +1,22 @@ +set_location_assignment PIN_C10 -to A +set_location_assignment PIN_C11 -to B +set_location_assignment PIN_A8 -to Q0 +set_location_assignment PIN_A9 -to Q1 +set_location_assignment PIN_A10 -to Q2 +set_location_assignment PIN_B10 -to Q3 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY decoder +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:32:30 JANUARY 21, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name BDF_FILE decoder.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.(0).cnf.cdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.(0).cnf.cdb new file mode 100644 index 0000000..2c9c009 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.(0).cnf.hdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.(0).cnf.hdb new file mode 100644 index 0000000..4d18a79 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm.qmsg b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm.qmsg new file mode 100644 index 0000000..839e59e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614299275561 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614299275571 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 18:27:55 2021 " "Processing started: Thu Feb 25 18:27:55 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614299275571 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1614299275571 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1614299275571 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1614299275861 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1614299277691 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1614299277841 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614299278941 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 18:27:58 2021 " "Processing ended: Thu Feb 25 18:27:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614299278941 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614299278941 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614299278941 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1614299278941 ""} diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm.rdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm.rdb new file mode 100644 index 0000000..6cab62e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm_labs.ddb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm_labs.ddb new file mode 100644 index 0000000..0bb698e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cbx.xml b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cbx.xml new file mode 100644 index 0000000..2ab7055 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.bpm b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.bpm new file mode 100644 index 0000000..2d8072f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.cdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.cdb new file mode 100644 index 0000000..a18a332 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.hdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.hdb new file mode 100644 index 0000000..ced6d96 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.idb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.idb new file mode 100644 index 0000000..a2c8fc8 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.idb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.logdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.logdb new file mode 100644 index 0000000..dbed552 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.logdb @@ -0,0 +1,48 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,6;0;6;0;0;6;6;0;6;6;0;4;0;0;2;0;4;2;0;0;0;4;0;0;0;0;0;6;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,0;6;0;6;6;0;0;6;0;0;6;2;6;6;4;6;2;4;6;6;6;2;6;6;6;6;6;0;6;6, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Q0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Q1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Q2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Q3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,B,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,A,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.rdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.rdb new file mode 100644 index 0000000..e2e8c30 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp_merge.kpt b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp_merge.kpt new file mode 100644 index 0000000..2715191 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.db_info b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.db_info new file mode 100644 index 0000000..ebda375 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Thu Apr 22 15:44:18 2021 diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.eda.qmsg b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.eda.qmsg new file mode 100644 index 0000000..1d26e17 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611281531256 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2016 Intel Corporation. All rights reserved. " "Copyright (C) 2016 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic " "and other software and tools, and its AMPP partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel MegaCore Function License Agreement, or other " "the Intel MegaCore Function License Agreement, or other " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable license agreement, including, without limitation, " "applicable license agreement, including, without limitation, " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "that your use is for the sole purpose of programming logic " "that your use is for the sole purpose of programming logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "devices manufactured by Intel and sold by Intel or its " "devices manufactured by Intel and sold by Intel or its " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "authorized distributors. Please refer to the applicable " "authorized distributors. Please refer to the applicable " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement for further details. " "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:12:11 2021 " "Processing started: Thu Jan 21 20:12:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531260 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/\" decoder -c decoder " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/\" decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531261 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1611281531461 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder.vo C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim// simulation " "Generated file decoder.vo in folder \"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1611281531492 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4641 " "Peak virtual memory: 4641 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:12:11 2021 " "Processing ended: Thu Jan 21 20:12:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531521 ""} diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.fit.qmsg b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.fit.qmsg new file mode 100644 index 0000000..46d8709 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.fit.qmsg @@ -0,0 +1,50 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1614299267691 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1614299267691 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "decoder 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"decoder\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1614299267701 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1614299267731 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1614299267731 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1614299268071 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1614299268101 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1614299268301 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 26 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 28 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 30 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 32 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 34 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 36 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 38 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 40 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1614299268321 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614299268321 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614299268321 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614299268321 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614299268321 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1614299268331 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "decoder.sdc " "Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1614299268901 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1614299268901 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1614299268901 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1614299268911 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1614299268911 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1614299268911 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1614299268911 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1614299268911 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1614299268911 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1614299268911 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1614299268911 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1614299268911 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1614299268911 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1614299268911 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1614299268911 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1614299268911 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1614299268911 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1614299268911 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614299268931 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1614299268951 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1614299270111 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614299270181 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1614299270221 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1614299270401 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614299270401 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280531 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280531 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280561 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280561 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "decoder.sdc " "Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280861 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280871 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280881 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280881 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280881 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280891 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280901 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280911 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280911 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280921 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280931 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280961 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281341 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281411 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281411 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281411 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281411 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281421 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281431 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281441 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281441 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281451 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281461 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299281461 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281661 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281661 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281671 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281681 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299282471 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299282471 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614299282531 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 18:28:02 2021 " "Processing ended: Thu Feb 25 18:28:02 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614299282531 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614299282531 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614299282531 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299282531 ""} diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.sta.rdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.sta.rdb new file mode 100644 index 0000000..726571d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.sta.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.sta_cmp.7_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.sta_cmp.7_slow_1200mv_85c.tdb new file mode 100644 index 0000000..b4b5705 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.sta_cmp.7_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tis_db_list.ddb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tis_db_list.ddb new file mode 100644 index 0000000..eda1a82 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..9bda339 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..1de3a7a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..835b8a5 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..481c945 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..d0ef5c1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tmw_info b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tmw_info new file mode 100644 index 0000000..ba6a589 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.tmw_info @@ -0,0 +1,3 @@ +start_full_compilation:s +start_assembler:s-start_full_compilation +start_timing_analyzer:s-start_full_compilation diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.vpr.ammdb b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.vpr.ammdb new file mode 100644 index 0000000..329b371 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..d86640f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ii_0c_slow.hsd b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..d223770 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ii_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ii_85c_slow.hsd b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..859bd44 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder.zippleback_io_sim_cache.ii_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/db/decoder_partition_pins.json b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder_partition_pins.json new file mode 100644 index 0000000..14c75c7 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/db/decoder_partition_pins.json @@ -0,0 +1,33 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "Q0", + "strict" : false + }, + { + "name" : "Q1", + "strict" : false + }, + { + "name" : "Q2", + "strict" : false + }, + { + "name" : "Q3", + "strict" : false + }, + { + "name" : "B", + "strict" : false + }, + { + "name" : "A", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Decoder/decoder.bdf b/EE203/Noah Woodlee/LAB1/Decoder/decoder.bdf new file mode 100644 index 0000000..2f0f752 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/decoder.bdf @@ -0,0 +1,409 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 136 272 304 288) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "A" (rect 5 0 14 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 136 400 304 416) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "B" (rect 5 0 13 17)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 632 232 808 248) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "Q0" (rect 90 0 104 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 632 320 808 336) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "Q1" (rect 90 0 104 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 632 416 808 432) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "Q2" (rect 90 0 104 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 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b/EE203/Noah Woodlee/LAB1/Decoder/decoder.qpf new file mode 100644 index 0000000..bbf2d22 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/decoder.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 19:32:30 January 21, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "19:32:30 January 21, 2021" + +# Revisions + +PROJECT_REVISION = "decoder" diff --git a/EE203/Noah Woodlee/LAB1/Decoder/decoder.qsf b/EE203/Noah Woodlee/LAB1/Decoder/decoder.qsf new file mode 100644 index 0000000..19c00ca --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/decoder.qsf @@ -0,0 +1,61 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 19:32:30 January 21, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# decoder_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY decoder +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:32:30 JANUARY 21, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name BDF_FILE decoder.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_C10 -to A +set_location_assignment PIN_C11 -to B +set_location_assignment PIN_A8 -to Q0 +set_location_assignment PIN_A9 -to Q1 +set_location_assignment PIN_A10 -to Q2 +set_location_assignment PIN_B10 -to Q3 +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Decoder/decoder.qws b/EE203/Noah Woodlee/LAB1/Decoder/decoder.qws new file mode 100644 index 0000000..26186f6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/decoder.qws differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/decoder_assignment_defaults.qdf b/EE203/Noah Woodlee/LAB1/Decoder/decoder_assignment_defaults.qdf new file mode 100644 index 0000000..bb43b61 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/decoder_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 14:08:42 April 22, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. 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+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/README b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.db_info b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.db_info new file mode 100644 index 0000000..17bf08f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Thu Apr 22 14:08:42 2021 diff --git a/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.cmp.ammdb b/EE203/Noah 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Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..98831c1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hdb b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hdb new file mode 100644 index 0000000..2241cff Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.kpt b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.kpt new file mode 100644 index 0000000..91bacec Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.rrp.hdb b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.rrp.hdb new file mode 100644 index 0000000..c2e28dc Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/incremental_db/compiled_partitions/decoder.rrp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.asm.rpt b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.asm.rpt new file mode 100644 index 0000000..14a42e2 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.asm.rpt @@ -0,0 +1,93 @@ +Assembler report for decoder +Thu Feb 25 18:27:58 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Feb 25 18:27:58 2021 ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++------------------------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------------------------+ +; File Name ; ++------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof ; ++------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof ; ++----------------+---------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------------------------+ +; Device ; 10M50DAF484C7G ; +; JTAG usercode ; 0x002708D4 ; +; Checksum ; 0x002708D4 ; ++----------------+---------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Feb 25 18:27:55 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4685 megabytes + Info: Processing ended: Thu Feb 25 18:27:58 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.done b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.done new file mode 100644 index 0000000..d184ac5 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.done @@ -0,0 +1 @@ +Thu Feb 25 18:28:03 2021 diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.eda.rpt b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.eda.rpt new file mode 100644 index 0000000..87cf935 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for decoder +Thu Jan 21 20:12:11 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Jan 21 20:12:11 2021 ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++---------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//decoder.vo ; ++---------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Jan 21 20:12:11 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file decoder.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Jan 21 20:12:11 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.rpt b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.rpt new file mode 100644 index 0000000..f4ce3c8 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.rpt @@ -0,0 +1,1194 @@ +Fitter report for decoder +Thu Feb 25 18:27:53 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Feb 25 18:27:53 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 5 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 6 / 360 ( 2 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C7G ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.2% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 36 ) ; 0.00 % ( 0 / 36 ) ; 0.00 % ( 0 / 36 ) ; +; -- Achieved ; 0.00 % ( 0 / 36 ) ; 0.00 % ( 0 / 36 ) ; 0.00 % ( 0 / 36 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 20 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 5 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 5 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 5 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 6 / 360 ( 2 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 29 ; +; Average fan-out ; 0.81 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 5 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 5 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 5 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 5 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 6 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 35 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 2 ; 0 ; +; -- Output Ports ; 4 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; A ; C10 ; 7 ; 51 ; 54 ; 28 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; B ; C11 ; 7 ; 51 ; 54 ; 21 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Q0 ; A8 ; 7 ; 46 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Q1 ; A9 ; 7 ; 46 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Q2 ; A10 ; 7 ; 51 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Q3 ; B10 ; 7 ; 46 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 0 / 60 ( 0 % ) ; 2.5V ; -- ; +; 7 ; 6 / 52 ( 12 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; Q0 ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 449 ; 7 ; Q1 ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 439 ; 7 ; Q2 ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; Q3 ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; A ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; B ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 391 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 388 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; Q0 ; Incomplete set of assignments ; +; Q1 ; Incomplete set of assignments ; +; Q2 ; Incomplete set of assignments ; +; Q3 ; Incomplete set of assignments ; +; B ; Incomplete set of assignments ; +; A ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |decoder ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 6 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; |decoder ; decoder ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Q0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Q1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Q2 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Q3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; B ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; A ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; B ; ; ; +; - inst ; 0 ; 6 ; +; - inst2~0 ; 0 ; 6 ; +; - inst2~1 ; 0 ; 6 ; +; - inst2~2 ; 0 ; 6 ; +; A ; ; ; +; - inst ; 0 ; 6 ; +; - inst2~0 ; 0 ; 6 ; +; - inst2~1 ; 0 ; 6 ; +; - inst2~2 ; 0 ; 6 ; ++---------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 10 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 0 / 5,382 ( 0 % ) ; +; C4 interconnects ; 11 / 106,704 ( < 1 % ) ; +; Direct links ; 0 / 148,641 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 49,760 ( 0 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 0 / 5,406 ( 0 % ) ; +; R4 interconnects ; 3 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 2.50) ; Number of LABs (Total = 2) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 2.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 2.50) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 1.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 6 ; 0 ; 6 ; 0 ; 0 ; 6 ; 6 ; 0 ; 6 ; 6 ; 0 ; 4 ; 0 ; 0 ; 2 ; 0 ; 4 ; 2 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 6 ; 0 ; 6 ; 6 ; 0 ; 0 ; 6 ; 0 ; 0 ; 6 ; 2 ; 6 ; 6 ; 4 ; 6 ; 2 ; 4 ; 6 ; 6 ; 6 ; 2 ; 6 ; 6 ; 6 ; 6 ; 6 ; 0 ; 6 ; 6 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Q0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Q1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Q2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Q3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; B ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; A ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (119006): Selected device 10M50DAF484C7G for design "decoder" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 10M08DAF484I7G is compatible + Info (176445): Device 10M16DAF484C7G is compatible + Info (176445): Device 10M16DAF484I7G is compatible + Info (176445): Device 10M25DAF484C7G is compatible + Info (176445): Device 10M25DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7P is compatible + Info (176445): Device 10M40DAF484C7G is compatible + Info (176445): Device 10M40DAF484I7G is compatible +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 5904 megabytes + Info: Processing ended: Thu Feb 25 18:27:54 2021 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:10 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg. + + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.smsg b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.smsg new file mode 100644 index 0000000..558ea95 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.summary b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.summary new file mode 100644 index 0000000..9040add --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Thu Feb 25 18:27:53 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : decoder +Top-level Entity Name : decoder +Family : MAX 10 +Device : 10M50DAF484C7G +Timing Models : Final +Total logic elements : 5 / 49,760 ( < 1 % ) + Total combinational functions : 5 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 6 / 360 ( 2 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.flow.rpt b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.flow.rpt new file mode 100644 index 0000000..d5c6fb5 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.flow.rpt @@ -0,0 +1,125 @@ +Flow report for decoder +Thu Feb 25 18:28:02 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Feb 25 18:27:58 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 5 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 6 / 360 ( 2 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 02/25/2021 18:27:35 ; +; Main task ; Compilation ; +; Revision Name ; decoder ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 189559947077153.161429925407232 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 4781 MB ; 00:00:22 ; +; Fitter ; 00:00:08 ; 1.0 ; 5904 MB ; 00:00:09 ; +; Assembler ; 00:00:03 ; 1.0 ; 4684 MB ; 00:00:03 ; +; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4867 MB ; 00:00:02 ; +; Total ; 00:00:24 ; -- ; -- ; 00:00:36 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder +quartus_fit --read_settings_files=off --write_settings_files=off decoder -c decoder +quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder +quartus_sta decoder -c decoder + + + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.jdi b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.jdi new file mode 100644 index 0000000..bb6ca07 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.map.rpt b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.map.rpt new file mode 100644 index 0000000..dba689a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.map.rpt @@ -0,0 +1,284 @@ +Analysis & Synthesis report for decoder +Thu Feb 25 18:27:44 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Feb 25 18:27:44 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; decoder ; +; Top-level Entity Name ; decoder ; +; Family ; MAX 10 ; +; Total logic elements ; 4 ; +; Total combinational functions ; 4 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 6 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C7G ; ; +; Top-level entity name ; decoder ; decoder ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+ +; decoder.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf ; ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+ + + ++-------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------+ +; Resource ; Usage ; ++---------------------------------------------+---------+ +; Estimated Total logic elements ; 4 ; +; ; ; +; Total combinational functions ; 4 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 4 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 4 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 6 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; B~input ; +; Maximum fan-out ; 4 ; +; Total fan-out ; 18 ; +; Average fan-out ; 1.13 ; ++---------------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |decoder ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; |decoder ; decoder ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 6 ; +; cycloneiii_lcell_comb ; 5 ; +; normal ; 5 ; +; 1 data inputs ; 1 ; +; 2 data inputs ; 4 ; +; ; ; +; Max LUT depth ; 2.00 ; +; Average LUT depth ; 1.57 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Feb 25 18:27:34 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file decoder.bdf + Info (12023): Found entity 1: decoder +Info (12127): Elaborating entity "decoder" for the top level hierarchy +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 10 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 2 input pins + Info (21059): Implemented 4 output pins + Info (21061): Implemented 4 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4781 megabytes + Info: Processing ended: Thu Feb 25 18:27:44 2021 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:22 + + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.map.summary b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.map.summary new file mode 100644 index 0000000..a218c78 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Thu Feb 25 18:27:44 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : decoder +Top-level Entity Name : decoder +Family : MAX 10 +Total logic elements : 4 + Total combinational functions : 4 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 6 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.pin b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.pin new file mode 100644 index 0000000..47b55d2 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2016 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel MegaCore Function License Agreement, or other + -- applicable license agreement, including, without limitation, + -- that your use is for the sole purpose of programming logic + -- devices manufactured by Intel and sold by Intel or its + -- authorized distributors. Please refer to the applicable + -- agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +CHIP "decoder" ASSIGNED TO AN: 10M50DAF484C7G + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +Q0 : A8 : output : 2.5 V : : 7 : Y +Q1 : A9 : output : 2.5 V : : 7 : Y +Q2 : A10 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +Q3 : B10 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +GND : B13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +A : C10 : input : 2.5 V : : 7 : Y +B : C11 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.pof b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.pof new file mode 100644 index 0000000..3ecac45 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.pof differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sld b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sof b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sof new file mode 100644 index 0000000..3f793d6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sof differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sta.rpt b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sta.rpt new file mode 100644 index 0000000..d45168e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sta.rpt @@ -0,0 +1,443 @@ +TimeQuest Timing Analyzer report for decoder +Thu Feb 25 18:28:02 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; decoder ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.3% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Q0 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Q1 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Q2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Q3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; B ; 2.5 V ; 2000 ps ; 2000 ps ; +; A ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 2 ; 2 ; +; Unconstrained Input Port Paths ; 8 ; 8 ; +; Unconstrained Output Ports ; 4 ; 4 ; +; Unconstrained Output Port Paths ; 8 ; 8 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Q0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Q0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Q3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Feb 25 18:27:59 2021 +Info: Command: quartus_sta decoder -c decoder +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4867 megabytes + Info: Processing ended: Thu Feb 25 18:28:02 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sta.summary b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/output_files/decoder.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/Waveform.vwf.vt b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/Waveform.vwf.vt new file mode 100644 index 0000000..ace2249 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/Waveform.vwf.vt @@ -0,0 +1,80 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "01/21/2021 20:12:10" + +// Verilog Test Bench (with test vectors) for design : decoder +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module decoder_vlg_vec_tst(); +// constants +// general purpose registers +reg A; +reg B; +// wires +wire Q0; +wire Q1; +wire Q2; +wire Q3; + +// assign statements (if any) +decoder i1 ( +// port map - connection between master ports and signals/registers + .A(A), + .B(B), + .Q0(Q0), + .Q1(Q1), + .Q2(Q2), + .Q3(Q3) +); +initial +begin +#200000 $finish; +end + +// A +initial +begin + A = 1'b0; + A = #10000 1'b1; + A = #20000 1'b0; + A = #30000 1'b1; + A = #30000 1'b0; + A = #60000 1'b1; + A = #10000 1'b0; +end + +// B +initial +begin + B = 1'b0; + B = #60000 1'b1; + B = #30000 1'b0; + B = #20000 1'b1; + B = #10000 1'b0; + B = #30000 1'b1; + B = #10000 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.do b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.do new file mode 100644 index 0000000..ca3c9f7 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vlog -work work decoder.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +vcd file -direction decoder.msim.vcd +vcd add -internal decoder_vlg_vec_tst/* +vcd add -internal decoder_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.msim.vcd b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.msim.vcd new file mode 100644 index 0000000..6e01868 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.msim.vcd @@ -0,0 +1,156 @@ +$comment + File created using the following command: + vcd file decoder.msim.vcd -direction +$end +$date + Thu Jan 21 20:12:12 2021 +$end +$version + ModelSim Version 10.5b +$end +$timescale + 1ps +$end + +$scope module decoder_vlg_vec_tst $end +$var reg 1 ! A $end +$var reg 1 " B $end +$var wire 1 # Q0 $end +$var wire 1 $ Q1 $end +$var wire 1 % Q2 $end +$var wire 1 & Q3 $end + +$scope module i1 $end +$var wire 1 ' gnd $end +$var wire 1 ( vcc $end +$var wire 1 ) unknown $end +$var tri1 1 * devclrn $end +$var tri1 1 + devpor $end +$var tri1 1 , devoe $end +$var wire 1 - ~QUARTUS_CREATED_GND~I_combout $end +$var wire 1 . ~QUARTUS_CREATED_UNVM~~busy $end +$var wire 1 / ~QUARTUS_CREATED_ADC1~~eoc $end +$var wire 1 0 ~QUARTUS_CREATED_ADC2~~eoc $end +$var wire 1 1 Q0~output_o $end +$var wire 1 2 Q1~output_o $end +$var wire 1 3 Q2~output_o $end +$var wire 1 4 Q3~output_o $end +$var wire 1 5 B~input_o $end +$var wire 1 6 A~input_o $end +$var wire 1 7 inst~combout $end +$var wire 1 8 inst2~0_combout $end +$var wire 1 9 inst2~1_combout $end +$var wire 1 : inst2~2_combout $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0! +0" +1# +0$ +0% +0& +0' +1( +x) +1* +1+ +1, +0- +z. +z/ +z0 +11 +02 +03 +04 +05 +06 +07 +08 +09 +0: +$end +#10000 +1! +16 +17 +19 +13 +01 +0# +1% +#30000 +0! +06 +07 +09 +03 +11 +1# +0% +#60000 +1" +1! +16 +15 +17 +1: +14 +01 +0# +1& +#90000 +0" +0! +06 +05 +07 +0: +04 +11 +1# +0& +#110000 +1" +15 +17 +18 +12 +01 +0# +1$ +#120000 +0" +05 +07 +08 +02 +11 +1# +0$ +#150000 +1! +1" +15 +16 +17 +1: +14 +01 +0# +1& +#160000 +0! +0" +05 +06 +07 +0: +04 +11 +1# +0& +#200000 diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.sft b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.sft new file mode 100644 index 0000000..f324fea --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.vo b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.vo new file mode 100644 index 0000000..8eb8440 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder.vo @@ -0,0 +1,383 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" + +// DATE "01/21/2021 20:12:11" + +// +// Device: Altera 10M50DAF484C7G Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module decoder ( + Q0, + B, + A, + Q1, + Q2, + Q3); +output Q0; +input B; +input A; +output Q1; +output Q2; +output Q3; + +// Design Ports Information +// Q0 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default +// Q1 => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default +// Q2 => Location: PIN_AA2, I/O Standard: 2.5 V, Current Strength: Default +// Q3 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default +// B => Location: PIN_W3, I/O Standard: 2.5 V, Current Strength: Default +// A => Location: PIN_W4, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \~QUARTUS_CREATED_UNVM~~busy ; +wire \~QUARTUS_CREATED_ADC1~~eoc ; +wire \~QUARTUS_CREATED_ADC2~~eoc ; +wire \Q0~output_o ; +wire \Q1~output_o ; +wire \Q2~output_o ; +wire \Q3~output_o ; +wire \B~input_o ; +wire \A~input_o ; +wire \inst~combout ; +wire \inst2~0_combout ; +wire \inst2~1_combout ; +wire \inst2~2_combout ; + + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: LCCOMB_X44_Y42_N8 +fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): +// \~QUARTUS_CREATED_GND~I_combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .cout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000; +defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +fiftyfivenm_io_obuf \Q0~output ( + .i(!\inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Q0~output_o ), + .obar()); +// synopsys translate_off +defparam \Q0~output .bus_hold = "false"; +defparam \Q0~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N30 +fiftyfivenm_io_obuf \Q1~output ( + .i(\inst2~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Q1~output_o ), + .obar()); +// synopsys translate_off +defparam \Q1~output .bus_hold = "false"; +defparam \Q1~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N23 +fiftyfivenm_io_obuf \Q2~output ( + .i(\inst2~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Q2~output_o ), + .obar()); +// synopsys translate_off +defparam \Q2~output .bus_hold = "false"; +defparam \Q2~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N2 +fiftyfivenm_io_obuf \Q3~output ( + .i(\inst2~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Q3~output_o ), + .obar()); +// synopsys translate_off +defparam \Q3~output .bus_hold = "false"; +defparam \Q3~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +fiftyfivenm_io_ibuf \B~input ( + .i(B), + .ibar(gnd), + .nsleep(vcc), + .o(\B~input_o )); +// synopsys translate_off +defparam \B~input .bus_hold = "false"; +defparam \B~input .listen_to_nsleep_signal = "false"; +defparam \B~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N15 +fiftyfivenm_io_ibuf \A~input ( + .i(A), + .ibar(gnd), + .nsleep(vcc), + .o(\A~input_o )); +// synopsys translate_off +defparam \A~input .bus_hold = "false"; +defparam \A~input .listen_to_nsleep_signal = "false"; +defparam \A~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y1_N0 +fiftyfivenm_lcell_comb inst( +// Equation(s): +// \inst~combout = (\B~input_o ) # (\A~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\B~input_o ), + .datad(\A~input_o ), + .cin(gnd), + .combout(\inst~combout ), + .cout()); +// synopsys translate_off +defparam inst.lut_mask = 16'hFFF0; +defparam inst.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y1_N2 +fiftyfivenm_lcell_comb \inst2~0 ( +// Equation(s): +// \inst2~0_combout = (\B~input_o & !\A~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\B~input_o ), + .datad(\A~input_o ), + .cin(gnd), + .combout(\inst2~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst2~0 .lut_mask = 16'h00F0; +defparam \inst2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y1_N4 +fiftyfivenm_lcell_comb \inst2~1 ( +// Equation(s): +// \inst2~1_combout = (!\B~input_o & \A~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\B~input_o ), + .datad(\A~input_o ), + .cin(gnd), + .combout(\inst2~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst2~1 .lut_mask = 16'h0F00; +defparam \inst2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y1_N6 +fiftyfivenm_lcell_comb \inst2~2 ( +// Equation(s): +// \inst2~2_combout = (\B~input_o & \A~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\B~input_o ), + .datad(\A~input_o ), + .cin(gnd), + .combout(\inst2~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst2~2 .lut_mask = 16'hF000; +defparam \inst2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: UNVM_X0_Y40_N40 +fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ ( + .arclk(vcc), + .arshft(vcc), + .drclk(vcc), + .drshft(vcc), + .drdin(vcc), + .nprogram(vcc), + .nerase(vcc), + .nosc_ena(\~QUARTUS_CREATED_GND~I_combout ), + .par_en(vcc), + .xe_ye(\~QUARTUS_CREATED_GND~I_combout ), + .se(\~QUARTUS_CREATED_GND~I_combout ), + .ardin(23'b11111111111111111111111), + .busy(\~QUARTUS_CREATED_UNVM~~busy ), + .osc(), + .bgpbusy(), + .sp_pass(), + .se_pass(), + .drdout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm"; +defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true"; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y52_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC1~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1; +defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y51_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC2~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2; +defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0; +// synopsys translate_on + +assign Q0 = \Q0~output_o ; + +assign Q1 = \Q1~output_o ; + +assign Q2 = \Q2~output_o ; + +assign Q3 = \Q3~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_TMS~~padout ; +wire \~ALTERA_TCK~~padout ; +wire \~ALTERA_TDI~~padout ; +wire \~ALTERA_CONFIG_SEL~~padout ; +wire \~ALTERA_nCONFIG~~padout ; +wire \~ALTERA_nSTATUS~~padout ; +wire \~ALTERA_CONF_DONE~~padout ; +wire \~ALTERA_TMS~~ibuf_o ; +wire \~ALTERA_TCK~~ibuf_o ; +wire \~ALTERA_TDI~~ibuf_o ; +wire \~ALTERA_CONFIG_SEL~~ibuf_o ; +wire \~ALTERA_nCONFIG~~ibuf_o ; +wire \~ALTERA_nSTATUS~~ibuf_o ; +wire \~ALTERA_CONF_DONE~~ibuf_o ; + + +endmodule diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_20210121201117.sim.vwf b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_20210121201117.sim.vwf new file mode 100644 index 0000000..c6ea50f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_20210121201117.sim.vwf @@ -0,0 +1,255 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 200.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Q0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("A") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("B") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("Q0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 40.0; + } + } +} + +TRANSITION_LIST("Q1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("Q2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 170.0; + } + } +} + +TRANSITION_LIST("Q3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf new file mode 100644 index 0000000..c0a5d1e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf @@ -0,0 +1,261 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 200.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("A") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("B") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Q0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Q3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("A") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("B") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("Q0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 40.0; + } + } +} + +TRANSITION_LIST("Q1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 110.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 80.0; + } + } +} + +TRANSITION_LIST("Q2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 170.0; + } + } +} + +TRANSITION_LIST("Q3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 40.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "A"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "B"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Q3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_modelsim.xrf b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_modelsim.xrf new file mode 100644 index 0000000..b726119 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/decoder_modelsim.xrf @@ -0,0 +1,25 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/db/decoder.cbx.xml +design_name = decoder +instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, decoder, 1 +instance = comp, \Q0~output , Q0~output, decoder, 1 +instance = comp, \Q1~output , Q1~output, decoder, 1 +instance = comp, \Q2~output , Q2~output, decoder, 1 +instance = comp, \Q3~output , Q3~output, decoder, 1 +instance = comp, \B~input , B~input, decoder, 1 +instance = comp, \A~input , A~input, decoder, 1 +instance = comp, \inst2~0 , inst2~0, decoder, 1 +instance = comp, \inst2~1 , inst2~1, decoder, 1 +instance = comp, \inst2~2 , inst2~2, decoder, 1 +instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, decoder, 1 +instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, decoder, 1 +instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, decoder, 1 +design_name = hard_block +instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1 diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/transcript b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/transcript new file mode 100644 index 0000000..3ffa8fc --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/transcript @@ -0,0 +1,37 @@ +# do decoder.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:12:11 on Jan 21,2021 +# vlog -work work decoder.vo +# -- Compiling module decoder +# -- Compiling module hard_block +# +# Top level modules: +# decoder +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:12:12 on Jan 21,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module decoder_vlg_vec_tst +# +# Top level modules: +# decoder_vlg_vec_tst +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +# Start time: 20:12:12 on Jan 21,2021 +# Loading work.decoder_vlg_vec_tst +# Loading work.decoder +# Loading work.hard_block +# ** Warning: (vsim-3017) decoder.vo(284): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) decoder.vo(284): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) decoder.vo(307): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) decoder.vo(307): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform.vwf.vt(53) +# Time: 200 ns Iteration: 0 Instance: /decoder_vlg_vec_tst +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4 diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/vwf_sim_transcript b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..1ee67bd --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,141 @@ +Determining the location of the ModelSim executable... + +Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Jan 21 20:12:10 2021 +Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt" +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. + +Completed successfully. + +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Jan 21 20:12:11 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file decoder.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Jan 21 20:12:11 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + +Completed successfully. + +**** Generating the ModelSim .do script **** + +C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do decoder.do + +Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl + + +# 10.5b + +# do decoder.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:12:11 on Jan 21,2021 +# vlog -work work decoder.vo +# -- Compiling module decoder +# -- Compiling module hard_block +# +# Top level modules: +# decoder + +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:12:12 on Jan 21,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module decoder_vlg_vec_tst +# +# Top level modules: +# decoder_vlg_vec_tst +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst +# Start time: 20:12:12 on Jan 21,2021 +# Loading work.decoder_vlg_vec_tst +# Loading work.decoder +# Loading work.hard_block +# ** Warning: (vsim-3017) decoder.vo(284): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) decoder.vo(284): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) decoder.vo(307): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) decoder.vo(307): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform.vwf.vt(53) +# Time: 200 ns Iteration: 0 Instance: /decoder_vlg_vec_tst +# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4 + +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf... + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder.msim.vcd... + +Processing channel transitions... + +Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf + +Finished VCD to VWF conversion. + +Completed successfully. + +All completed. \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_info b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_info new file mode 100644 index 0000000..8e21126 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_info @@ -0,0 +1,73 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dC:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim +vdecoder +Z1 !s110 1611281532 +!i10b 1 +!s100 UIL90zBZg0Y19`leS`6h<2 +I?kJ^Dj<_UL0j=K>IoSLA43 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +Z3 w1611281531 +Z4 8decoder.vo +Z5 Fdecoder.vo +L0 32 +Z6 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z7 !s108 1611281531.000000 +Z8 !s107 decoder.vo| +Z9 !s90 -work|work|decoder.vo| +!i113 1 +Z10 o-work work +Z11 tCvgOpt 0 +vdecoder_vlg_vec_tst +R1 +!i10b 1 +!s100 ]Ca;=HzRX6Lo`OmRLo6W[1 +IK[F>kI[RnW?^K1G37[MAK1 +R2 +R0 +w1611281530 +8Waveform.vwf.vt +FWaveform.vwf.vt +L0 30 +R6 +r1 +!s85 0 +31 +!s108 1611281532.000000 +!s107 Waveform.vwf.vt| +!s90 -work|work|Waveform.vwf.vt| +!i113 1 +R10 +R11 +vhard_block +R1 +!i10b 1 +!s100 =YQAZHYcKj^4X8AX_30Gh2 +I`Y@_E2FIMAN_fQ3cHX1n?2 +R2 +R0 +R3 +R4 +R5 +L0 339 +R6 +r1 +!s85 0 +31 +R7 +R8 +R9 +!i113 1 +R10 +R11 diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib.qdb b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib.qdb new file mode 100644 index 0000000..d9b590a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib.qdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qdb b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qdb new file mode 100644 index 0000000..2c2a282 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qdb differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qpg b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qpg new file mode 100644 index 0000000..c61b8b0 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qpg differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qtl b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qtl new file mode 100644 index 0000000..a3fb234 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_lib1_0.qtl differ diff --git a/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_vmake b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qpf b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qpf new file mode 100644 index 0000000..4182cd3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 19:34:44 February 25, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "19:34:44 February 25, 2021" + +# Revisions + +PROJECT_REVISION = "Lab1Pt1" diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qsf b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qsf new file mode 100644 index 0000000..6da5ed9 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qsf @@ -0,0 +1,75 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 19:34:44 February 25, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Lab1Pt1_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY Lab1Pt1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:34:44 FEBRUARY 25, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name VERILOG_FILE Lab1Pt1.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qws b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qws new file mode 100644 index 0000000..63563b7 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.qws differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v new file mode 100644 index 0000000..5153409 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v @@ -0,0 +1,5 @@ +module Lab1Pt1 (SW,LEDR); + input [9:0]SW; + output [9:0]LEDR; + assign LEDR=SW; + endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v.bak b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v.bak new file mode 100644 index 0000000..26b8e4a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v.bak @@ -0,0 +1,5 @@ +module part1 (SW,LEDR); + input [9:0]SW; + output [9:0]LEDR; + assign LEDR=SW; + endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1_assignment_defaults.qdf b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1_assignment_defaults.qdf new file mode 100644 index 0000000..c78e727 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 14:09:45 April 22, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name 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+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value ENABLE +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf b/EE203/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf new file mode 100644 index 0000000..a24845c --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf @@ -0,0 +1,748 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1 +onerror {exit -code 1} +vlib work +vlog -work work Lab1Pt1.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst +vcd file -direction Lab1Pt1.msim.vcd +vcd add -internal Lab1Pt1_vlg_vec_tst/* +vcd add -internal Lab1Pt1_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work Lab1Pt1.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst +vcd file -direction Lab1Pt1.msim.vcd +vcd add -internal Lab1Pt1_vlg_vec_tst/* +vcd add -internal Lab1Pt1_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 740.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 700.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 660.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 310.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 630.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 610.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 350.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 590.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 370.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 570.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 390.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 550.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 410.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 530.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 510.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/atom_netlists/Lab1Pt1.qsf b/EE203/Noah Woodlee/LAB1/Lab1Part1/atom_netlists/Lab1Pt1.qsf new file mode 100644 index 0000000..c6b079b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/atom_netlists/Lab1Pt1.qsf @@ -0,0 +1,36 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY Lab1Pt1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:34:44 FEBRUARY 25, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name VERILOG_FILE Lab1Pt1.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.(0).cnf.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.(0).cnf.cdb new file mode 100644 index 0000000..1c9e4c8 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.(0).cnf.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.(0).cnf.hdb new file mode 100644 index 0000000..5810f6b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm.qmsg new file mode 100644 index 0000000..d624969 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614303379961 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614303379971 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 19:36:19 2021 " "Processing started: Thu Feb 25 19:36:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614303379971 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1614303379971 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Lab1Pt1 -c Lab1Pt1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Lab1Pt1 -c Lab1Pt1" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1614303379971 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1614303380251 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1614303382001 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1614303382141 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4686 " "Peak virtual memory: 4686 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614303383191 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 19:36:23 2021 " "Processing ended: Thu Feb 25 19:36:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614303383191 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614303383191 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614303383191 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1614303383191 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm.rdb new file mode 100644 index 0000000..9ff94aa Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm_labs.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm_labs.ddb new file mode 100644 index 0000000..806dd89 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cbx.xml b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cbx.xml new file mode 100644 index 0000000..c0760b2 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.bpm b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.bpm new file mode 100644 index 0000000..8f4e6a7 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.cdb new file mode 100644 index 0000000..b1d0b3b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.hdb new file mode 100644 index 0000000..155aa5d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.idb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.idb new file mode 100644 index 0000000..19a45d1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.idb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.logdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.logdb new file mode 100644 index 0000000..62890cb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.logdb @@ -0,0 +1,62 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;20;0;0;20;20;0;10;0;0;10;0;10;10;0;0;0;10;0;0;0;0;0;20;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,20;20;20;20;20;0;20;20;0;0;20;10;20;20;10;20;10;10;20;20;20;10;20;20;20;20;20;0;20;20, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,LEDR[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.rdb new file mode 100644 index 0000000..0654ab4 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp_merge.kpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp_merge.kpt new file mode 100644 index 0000000..7efc93b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.db_info b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.db_info new file mode 100644 index 0000000..b000342 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Thu Apr 22 15:34:31 2021 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.eda.qmsg b/EE203/Noah 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" "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614304930664 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 20:02:10 2021 " "Processing started: Thu Feb 25 20:02:10 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614304930664 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1614304930664 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/\" Lab1Pt1 -c Lab1Pt1 " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/\" Lab1Pt1 -c Lab1Pt1" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1614304930664 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. 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If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1614303370831 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 0 { 0 ""} 0 50 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614303370831 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 0 { 0 ""} 0 52 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614303370831 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 0 { 0 ""} 0 54 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614303370831 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 0 { 0 ""} 0 56 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614303370831 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 0 { 0 ""} 0 58 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614303370831 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 0 { 0 ""} 0 60 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614303370831 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 0 { 0 ""} 0 62 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614303370831 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 0 { 0 ""} 0 64 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614303370831 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1614303370831 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614303370831 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614303370831 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614303370831 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614303370831 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1614303370831 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "20 20 " "No exact pin location assignment(s) for 20 pins of 20 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1614303371061 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Lab1Pt1.sdc " "Synopsys Design Constraints File file not found: 'Lab1Pt1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1614303371281 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1614303371281 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1614303371281 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1614303371281 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1614303371281 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1614303371281 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1614303371281 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1614303371291 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1614303371291 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1614303371291 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1614303371291 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1614303371291 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1614303371291 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1614303371291 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1614303371291 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1614303371291 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1614303371291 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1614303371291 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "20 unused 2.5V 10 10 0 " "Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 10 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1614303371291 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1614303371291 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1614303371291 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 20 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 36 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 48 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 48 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 40 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 60 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 52 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 32 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1614303371291 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1614303371291 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1614303371291 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614303371321 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1614303371331 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1614303372451 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614303372501 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1614303372531 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1614303372951 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614303372951 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1614303375481 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X22_Y33 X32_Y43 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y33 to location X32_Y43" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y33 to location X32_Y43"} { { 12 { 0 ""} 22 33 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1614303376811 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1614303376811 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1614303376891 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1614303376891 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1614303376891 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614303376901 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1614303377101 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1614303377111 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1614303377351 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1614303377351 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1614303377691 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614303378171 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1614303378451 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5901 " "Peak virtual memory: 5901 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614303378951 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 19:36:18 2021 " "Processing ended: Thu Feb 25 19:36:18 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614303378951 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614303378951 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614303378951 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1614303378951 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.hier_info b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.hier_info new file mode 100644 index 0000000..479b683 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.hier_info @@ -0,0 +1,23 @@ +|Lab1Pt1 +SW[0] => LEDR[0].DATAIN +SW[1] => LEDR[1].DATAIN +SW[2] => LEDR[2].DATAIN +SW[3] => LEDR[3].DATAIN +SW[4] => LEDR[4].DATAIN +SW[5] => LEDR[5].DATAIN +SW[6] => LEDR[6].DATAIN +SW[7] => LEDR[7].DATAIN +SW[8] => LEDR[8].DATAIN +SW[9] => LEDR[9].DATAIN +LEDR[0] <= SW[0].DB_MAX_OUTPUT_PORT_TYPE +LEDR[1] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE +LEDR[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE +LEDR[3] <= SW[3].DB_MAX_OUTPUT_PORT_TYPE +LEDR[4] <= SW[4].DB_MAX_OUTPUT_PORT_TYPE +LEDR[5] <= SW[5].DB_MAX_OUTPUT_PORT_TYPE +LEDR[6] <= SW[6].DB_MAX_OUTPUT_PORT_TYPE +LEDR[7] <= SW[7].DB_MAX_OUTPUT_PORT_TYPE +LEDR[8] <= SW[8].DB_MAX_OUTPUT_PORT_TYPE +LEDR[9] <= SW[9].DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.hif b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.hif new file mode 100644 index 0000000..ae015f9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.hif differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.html b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.html new file mode 100644 index 0000000..7d68592 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.rdb new file mode 100644 index 0000000..c179f4d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.txt b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.txt new file mode 100644 index 0000000..dbfe520 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.ammdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.ammdb new file mode 100644 index 0000000..a4afc79 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.bpm b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.bpm new file mode 100644 index 0000000..e710cd7 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.cdb new file mode 100644 index 0000000..1748e5b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.hdb new file mode 100644 index 0000000..940d2ee Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.kpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.kpt new file mode 100644 index 0000000..8524d5c Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.logdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.qmsg new file mode 100644 index 0000000..d1ffded --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.qmsg @@ -0,0 +1,10 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614303360062 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614303360066 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 19:35:59 2021 " "Processing started: Thu Feb 25 19:35:59 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614303360066 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303360066 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Lab1Pt1 -c Lab1Pt1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1Pt1 -c Lab1Pt1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303360070 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1614303360421 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1614303360421 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lab1pt1.v 1 1 " "Found 1 design units, including 1 entities, in source file lab1pt1.v" { { "Info" "ISGN_ENTITY_NAME" "1 Lab1Pt1 " "Found entity 1: Lab1Pt1" { } { { "Lab1Pt1.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614303368481 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303368481 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "Lab1Pt1 " "Elaborating entity \"Lab1Pt1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1614303368511 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1614303368991 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614303368991 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "20 " "Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1614303369051 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1614303369051 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1614303369051 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4749 " "Peak virtual memory: 4749 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614303369081 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 19:36:09 2021 " "Processing ended: Thu Feb 25 19:36:09 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614303369081 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614303369081 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614303369081 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303369081 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.rdb new file mode 100644 index 0000000..fa047f8 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.cdb new file mode 100644 index 0000000..e78d428 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.hdb new file mode 100644 index 0000000..15dc265 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.logdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.pre_map.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.pre_map.hdb new file mode 100644 index 0000000..62e3fdc Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.pre_map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.quiproj.11537.rdr.flock b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.quiproj.11537.rdr.flock new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.root_partition.map.reg_db.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..4b74ddb Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.root_partition.map.reg_db.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.routing.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.routing.rdb new file mode 100644 index 0000000..a1487a7 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.routing.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv.hdb new file mode 100644 index 0000000..ca03eb5 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv_sg.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv_sg.cdb new file mode 100644 index 0000000..18319fe Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv_sg.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv_sg_swap.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv_sg_swap.cdb new file mode 100644 index 0000000..0be030c Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.rtlv_sg_swap.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sld_design_entry.sci b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sld_design_entry.sci new file mode 100644 index 0000000..7d39add Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sld_design_entry.sci differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sld_design_entry_dsc.sci b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sld_design_entry_dsc.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.smart_action.txt b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.smart_action.txt new file mode 100644 index 0000000..f1e1649 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta.qmsg new file mode 100644 index 0000000..5469568 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta.qmsg @@ -0,0 +1,50 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614303384351 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614303384361 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 19:36:24 2021 " "Processing started: Thu Feb 25 19:36:24 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614303384361 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384361 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Lab1Pt1 -c Lab1Pt1 " "Command: quartus_sta Lab1Pt1 -c Lab1Pt1" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384361 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1614303384461 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384621 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384621 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384651 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384651 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Lab1Pt1.sdc " "Synopsys Design Constraints File file not found: 'Lab1Pt1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384931 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384931 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384931 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384931 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384931 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384931 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1614303384931 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384941 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614303384941 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384941 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1614303384951 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384961 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384971 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384971 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384981 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303384991 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614303385001 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303385021 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386551 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386631 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386631 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386631 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386631 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386631 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386641 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386651 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386651 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386661 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386661 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614303386671 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386851 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386851 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386851 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386851 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386861 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386861 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386871 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386871 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303386881 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303387711 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303387711 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614303387821 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 19:36:27 2021 " "Processing ended: Thu Feb 25 19:36:27 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614303387821 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614303387821 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614303387821 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614303387821 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta.rdb new file mode 100644 index 0000000..9459a21 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta_cmp.7_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta_cmp.7_slow_1200mv_85c.tdb new file mode 100644 index 0000000..4983aff Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.sta_cmp.7_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tis_db_list.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tis_db_list.ddb new file mode 100644 index 0000000..eda1a82 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..6674911 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fastest_slow_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..dc74e53 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fastest_slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..68626b8 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..28ee79a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..e5e6b11 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.vpr.ammdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.vpr.ammdb new file mode 100644 index 0000000..b4049f0 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..db68b29 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ii_0c_slow.hsd b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..d223770 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ii_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ii_85c_slow.hsd b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..68203ec Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.zippleback_io_sim_cache.ii_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1_partition_pins.json b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1_partition_pins.json new file mode 100644 index 0000000..0425bf6 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1_partition_pins.json @@ -0,0 +1,89 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "LEDR[0]", + "strict" : false + }, + { + "name" : "LEDR[1]", + "strict" : false + }, + { + "name" : "LEDR[2]", + "strict" : false + }, + { + "name" : "LEDR[3]", + "strict" : false + }, + { + "name" : "LEDR[4]", + "strict" : false + }, + { + "name" : "LEDR[5]", + "strict" : false + }, + { + "name" : "LEDR[6]", + "strict" : false + }, + { + "name" : "LEDR[7]", + "strict" : false + }, + { + "name" : "LEDR[8]", + "strict" : false + }, + { + "name" : "LEDR[9]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[2]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + }, + { + "name" : "SW[4]", + "strict" : false + }, + { + "name" : "SW[5]", + "strict" : false + }, + { + "name" : "SW[6]", + "strict" : false + }, + { + "name" : "SW[7]", + "strict" : false + }, + { + "name" : "SW[8]", + "strict" : false + }, + { + "name" : "SW[9]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/db/prev_cmp_Lab1Pt1.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/prev_cmp_Lab1Pt1.qmsg new file mode 100644 index 0000000..86bf30a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/db/prev_cmp_Lab1Pt1.qmsg @@ -0,0 +1,9 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614303317098 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614303317098 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 19:35:16 2021 " "Processing started: Thu Feb 25 19:35:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614303317098 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303317098 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Lab1Pt1 -c Lab1Pt1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1Pt1 -c Lab1Pt1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303317098 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1614303317438 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1614303317438 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lab1pt1.v 1 1 " "Found 1 design units, including 1 entities, in source file lab1pt1.v" { { "Info" "ISGN_ENTITY_NAME" "1 part1 " "Found entity 1: part1" { } { { "Lab1Pt1.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614303325528 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303325528 ""} +{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "Lab1Pt1 " "Top-level design entity \"Lab1Pt1\" is undefined" { } { } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1614303325558 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4712 " "Peak virtual memory: 4712 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614303325658 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Feb 25 19:35:25 2021 " "Processing ended: Thu Feb 25 19:35:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614303325658 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614303325658 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614303325658 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303325658 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1 " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1614303326288 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/README b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.db_info b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.db_info new file mode 100644 index 0000000..85e6deb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Thu Apr 22 14:09:45 2021 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.ammdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.ammdb new file mode 100644 index 0000000..0b3b4a5 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.cdb new file mode 100644 index 0000000..906b66d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.dfp b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.hdb new file mode 100644 index 0000000..155ebb4 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.logdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.rcfdb new file mode 100644 index 0000000..d4261d9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.cdb new file mode 100644 index 0000000..f003aa6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.dpi b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.dpi new file mode 100644 index 0000000..ac95ae2 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..ff1f87d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..e07ce70 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hdb new file mode 100644 index 0000000..59b39a9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.kpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.kpt new file mode 100644 index 0000000..1bc92e7 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.rrp.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.rrp.hdb new file mode 100644 index 0000000..6ca12d6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/incremental_db/compiled_partitions/Lab1Pt1.rrp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.asm.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.asm.rpt new file mode 100644 index 0000000..8720ba5 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.asm.rpt @@ -0,0 +1,93 @@ +Assembler report for Lab1Pt1 +Thu Feb 25 19:36:23 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Feb 25 19:36:23 2021 ; +; Revision Name ; Lab1Pt1 ; +; Top-level Entity Name ; Lab1Pt1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------------------------------------+ +; File Name ; ++-------------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sof ; ++-------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sof ; ++----------------+----------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------------------------------------+ +; Device ; 10M50DAF484C7G ; +; JTAG usercode ; 0x002703A1 ; +; Checksum ; 0x002703A1 ; ++----------------+----------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Feb 25 19:36:19 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Lab1Pt1 -c Lab1Pt1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4686 megabytes + Info: Processing ended: Thu Feb 25 19:36:23 2021 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.done b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.done new file mode 100644 index 0000000..c531af0 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.done @@ -0,0 +1 @@ +Thu Feb 25 19:36:28 2021 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.eda.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.eda.rpt new file mode 100644 index 0000000..d6e3462 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for Lab1Pt1 +Thu Feb 25 20:02:11 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Feb 25 20:02:11 2021 ; +; Revision Name ; Lab1Pt1 ; +; Top-level Entity Name ; Lab1Pt1 ; +; Family ; MAX 10 ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++----------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++----------------------------------------------------------------------------------+ +; Generated Files ; ++----------------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim//Lab1Pt1.vo ; ++----------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Feb 25 20:02:10 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file Lab1Pt1.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Feb 25 20:02:11 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.rpt new file mode 100644 index 0000000..0c7c7a4 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.rpt @@ -0,0 +1,1277 @@ +Fitter report for Lab1Pt1 +Thu Feb 25 19:36:18 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. I/O Rules Summary + 25. I/O Rules Details + 26. I/O Rules Matrix + 27. Fitter Device Options + 28. Operating Settings and Conditions + 29. Fitter Messages + 30. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Feb 25 19:36:18 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Lab1Pt1 ; +; Top-level Entity Name ; Lab1Pt1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 1 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 1 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 20 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C7G ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.1% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 60 ) ; 0.00 % ( 0 / 60 ) ; 0.00 % ( 0 / 60 ) ; +; -- Achieved ; 0.00 % ( 0 / 60 ) ; 0.00 % ( 0 / 60 ) ; 0.00 % ( 0 / 60 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 44 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 1 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 1 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 1 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 1 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 20 / 360 ( 6 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 41 ; +; Average fan-out ; 0.68 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 1 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 1 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 1 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 1 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 20 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 47 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 10 ; 0 ; +; -- Output Ports ; 10 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; J9 ; 1A ; 0 ; 36 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[1] ; H20 ; 6 ; 78 ; 45 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[2] ; E1 ; 1B ; 0 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[3] ; R22 ; 5 ; 78 ; 21 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[4] ; W14 ; 4 ; 49 ; 0 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[5] ; L19 ; 6 ; 78 ; 37 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[6] ; R1 ; 2 ; 0 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[7] ; B2 ; 8 ; 22 ; 39 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[8] ; Y16 ; 4 ; 54 ; 0 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[9] ; AA9 ; 3 ; 34 ; 0 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; LEDR[0] ; J8 ; 1A ; 0 ; 36 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[1] ; J20 ; 6 ; 78 ; 45 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[2] ; L9 ; 1B ; 0 ; 27 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[3] ; U22 ; 5 ; 78 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[4] ; R13 ; 4 ; 49 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[5] ; M18 ; 6 ; 78 ; 37 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[6] ; T5 ; 2 ; 0 ; 3 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[7] ; D6 ; 8 ; 22 ; 39 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[8] ; W15 ; 4 ; 54 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[9] ; AB9 ; 3 ; 34 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1A ; 2 / 16 ( 13 % ) ; 2.5V ; -- ; +; 1B ; 6 / 24 ( 25 % ) ; 2.5V ; -- ; +; 2 ; 2 / 36 ( 6 % ) ; 2.5V ; -- ; +; 3 ; 2 / 48 ( 4 % ) ; 2.5V ; -- ; +; 4 ; 4 / 48 ( 8 % ) ; 2.5V ; -- ; +; 5 ; 2 / 40 ( 5 % ) ; 2.5V ; -- ; +; 6 ; 4 / 60 ( 7 % ) ; 2.5V ; -- ; +; 7 ; 0 / 52 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 6 / 36 ( 17 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; SW[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; SW[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C12 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 391 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; SW[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 388 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; LEDR[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J9 ; 6 ; 1A ; SW[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; LEDR[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; LEDR[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; LEDR[5] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; LEDR[6] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; LEDR[3] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; SW[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W15 ; 206 ; 4 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; SW[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; LEDR[0] ; Incomplete set of assignments ; +; LEDR[1] ; Incomplete set of assignments ; +; LEDR[2] ; Incomplete set of assignments ; +; LEDR[3] ; Incomplete set of assignments ; +; LEDR[4] ; Incomplete set of assignments ; +; LEDR[5] ; Incomplete set of assignments ; +; LEDR[6] ; Incomplete set of assignments ; +; LEDR[7] ; Incomplete set of assignments ; +; LEDR[8] ; Incomplete set of assignments ; +; LEDR[9] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; +; SW[8] ; Incomplete set of assignments ; +; SW[9] ; Incomplete set of assignments ; +; LEDR[0] ; Missing location assignment ; +; LEDR[1] ; Missing location assignment ; +; LEDR[2] ; Missing location assignment ; +; LEDR[3] ; Missing location assignment ; +; LEDR[4] ; Missing location assignment ; +; LEDR[5] ; Missing location assignment ; +; LEDR[6] ; Missing location assignment ; +; LEDR[7] ; Missing location assignment ; +; LEDR[8] ; Missing location assignment ; +; LEDR[9] ; Missing location assignment ; +; SW[0] ; Missing location assignment ; +; SW[1] ; Missing location assignment ; +; SW[2] ; Missing location assignment ; +; SW[3] ; Missing location assignment ; +; SW[4] ; Missing location assignment ; +; SW[5] ; Missing location assignment ; +; SW[6] ; Missing location assignment ; +; SW[7] ; Missing location assignment ; +; SW[8] ; Missing location assignment ; +; SW[9] ; Missing location assignment ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |Lab1Pt1 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 20 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; |Lab1Pt1 ; Lab1Pt1 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 873 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; -- ; (6) 873 ps ; -- ; -- ; -- ; +; SW[2] ; Input ; -- ; (6) 873 ps ; -- ; -- ; -- ; +; SW[3] ; Input ; (6) 873 ps ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; (6) 873 ps ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; -- ; (6) 873 ps ; -- ; -- ; -- ; +; SW[7] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-----------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------+-------------------+---------+ +; SW[0] ; ; ; +; - LEDR[0]~output ; 0 ; 6 ; +; SW[1] ; ; ; +; - LEDR[1]~output ; 1 ; 6 ; +; SW[2] ; ; ; +; - LEDR[2]~output ; 1 ; 6 ; +; SW[3] ; ; ; +; - LEDR[3]~output ; 0 ; 6 ; +; SW[4] ; ; ; +; - LEDR[4]~output ; 0 ; 6 ; +; SW[5] ; ; ; +; - LEDR[5]~output ; 0 ; 6 ; +; SW[6] ; ; ; +; - LEDR[6]~output ; 1 ; 6 ; +; SW[7] ; ; ; +; - LEDR[7]~output ; 0 ; 6 ; +; SW[8] ; ; ; +; - LEDR[8]~output ; 0 ; 6 ; +; SW[9] ; ; ; +; - LEDR[9]~output ; 0 ; 6 ; ++-----------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 14 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 4 / 5,382 ( < 1 % ) ; +; C4 interconnects ; 8 / 106,704 ( < 1 % ) ; +; Direct links ; 1 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 49,760 ( 0 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 0 / 5,406 ( 0 % ) ; +; R4 interconnects ; 8 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 1) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 1.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 20 ; 20 ; 0 ; 10 ; 0 ; 0 ; 10 ; 0 ; 10 ; 10 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 20 ; 20 ; 20 ; 20 ; 20 ; 0 ; 20 ; 20 ; 0 ; 0 ; 20 ; 10 ; 20 ; 20 ; 10 ; 20 ; 10 ; 10 ; 20 ; 20 ; 20 ; 10 ; 20 ; 20 ; 20 ; 20 ; 20 ; 0 ; 20 ; 20 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; LEDR[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (119006): Selected device 10M50DAF484C7G for design "Lab1Pt1" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 10M08DAF484I7G is compatible + Info (176445): Device 10M16DAF484C7G is compatible + Info (176445): Device 10M16DAF484I7G is compatible + Info (176445): Device 10M25DAF484C7G is compatible + Info (176445): Device 10M25DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7P is compatible + Info (176445): Device 10M40DAF484C7G is compatible + Info (176445): Device 10M40DAF484I7G is compatible +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 20 pins of 20 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'Lab1Pt1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 10 input, 10 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available + Info (176213): I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y33 to location X32_Y43 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 5901 megabytes + Info: Processing ended: Thu Feb 25 19:36:18 2021 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:13 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.smsg. + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.smsg b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.smsg new file mode 100644 index 0000000..558ea95 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.summary b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.summary new file mode 100644 index 0000000..77d7827 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Thu Feb 25 19:36:18 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : Lab1Pt1 +Top-level Entity Name : Lab1Pt1 +Family : MAX 10 +Device : 10M50DAF484C7G +Timing Models : Final +Total logic elements : 1 / 49,760 ( < 1 % ) + Total combinational functions : 1 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 20 / 360 ( 6 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.flow.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.flow.rpt new file mode 100644 index 0000000..4f38452 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.flow.rpt @@ -0,0 +1,131 @@ +Flow report for Lab1Pt1 +Thu Feb 25 20:02:11 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Feb 25 20:02:11 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Lab1Pt1 ; +; Top-level Entity Name ; Lab1Pt1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 1 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 1 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 20 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 02/25/2021 19:36:00 ; +; Main task ; Compilation ; +; Revision Name ; Lab1Pt1 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 189559947077153.161430336002828 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4734 MB ; 00:00:20 ; +; Fitter ; 00:00:09 ; 1.0 ; 5901 MB ; 00:00:12 ; +; Assembler ; 00:00:04 ; 1.0 ; 4685 MB ; 00:00:03 ; +; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4867 MB ; 00:00:04 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4632 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4641 MB ; 00:00:01 ; +; Total ; 00:00:27 ; -- ; -- ; 00:00:41 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off Lab1Pt1 -c Lab1Pt1 +quartus_fit --read_settings_files=off --write_settings_files=off Lab1Pt1 -c Lab1Pt1 +quartus_asm --read_settings_files=off --write_settings_files=off Lab1Pt1 -c Lab1Pt1 +quartus_sta Lab1Pt1 -c Lab1Pt1 +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1 + + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.jdi b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.jdi new file mode 100644 index 0000000..1ab2d9b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.map.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.map.rpt new file mode 100644 index 0000000..e09183e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.map.rpt @@ -0,0 +1,277 @@ +Analysis & Synthesis report for Lab1Pt1 +Thu Feb 25 19:36:09 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Feb 25 19:36:09 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Lab1Pt1 ; +; Top-level Entity Name ; Lab1Pt1 ; +; Family ; MAX 10 ; +; Total logic elements ; 0 ; +; Total combinational functions ; 0 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 20 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C7G ; ; +; Top-level entity name ; Lab1Pt1 ; Lab1Pt1 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+ +; Lab1Pt1.v ; yes ; User Verilog HDL File ; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v ; ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; ; ; +; Total combinational functions ; 0 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 0 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 20 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; LEDR[0]~output ; +; Maximum fan-out ; 1 ; +; Total fan-out ; 30 ; +; Average fan-out ; 0.75 ; ++---------------------------------------------+----------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |Lab1Pt1 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; |Lab1Pt1 ; Lab1Pt1 ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-------------------+---------------------------------+ +; Type ; Count ; ++-------------------+---------------------------------+ +; boundary_port ; 20 ; +; ; ; +; Max LUT depth ; 0.00 ; +; Average LUT depth ; 0.00 ; ++-------------------+---------------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Feb 25 19:35:59 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1Pt1 -c Lab1Pt1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file lab1pt1.v + Info (12023): Found entity 1: Lab1Pt1 File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v Line: 1 +Info (12127): Elaborating entity "Lab1Pt1" for the top level hierarchy +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 20 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 10 input pins + Info (21059): Implemented 10 output pins +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4749 megabytes + Info: Processing ended: Thu Feb 25 19:36:09 2021 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:20 + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.map.summary b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.map.summary new file mode 100644 index 0000000..aed5ba8 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Thu Feb 25 19:36:09 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : Lab1Pt1 +Top-level Entity Name : Lab1Pt1 +Family : MAX 10 +Total logic elements : 0 + Total combinational functions : 0 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 20 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.pin b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.pin new file mode 100644 index 0000000..bca194b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2016 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel MegaCore Function License Agreement, or other + -- applicable license agreement, including, without limitation, + -- that your use is for the sole purpose of programming logic + -- devices manufactured by Intel and sold by Intel or its + -- authorized distributors. Please refer to the applicable + -- agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +CHIP "Lab1Pt1" ASSIGNED TO AN: 10M50DAF484C7G + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +SW[9] : AA9 : input : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +LEDR[9] : AB9 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +SW[7] : B2 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +GND : B13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +LEDR[7] : D6 : output : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +SW[2] : E1 : input : 2.5 V : : 1B : N +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +SW[1] : H20 : input : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +LEDR[0] : J8 : output : 2.5 V : : 1A : N +SW[0] : J9 : input : 2.5 V : : 1A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +LEDR[1] : J20 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +LEDR[2] : L9 : output : 2.5 V : : 1B : N +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +SW[5] : L19 : input : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +LEDR[5] : M18 : output : 2.5 V : : 6 : N +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +SW[6] : R1 : input : 2.5 V : : 2 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +LEDR[4] : R13 : output : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +SW[3] : R22 : input : 2.5 V : : 5 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +LEDR[6] : T5 : output : 2.5 V : : 2 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +LEDR[3] : U22 : output : 2.5 V : : 5 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +SW[4] : W14 : input : 2.5 V : : 4 : N +LEDR[8] : W15 : output : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +SW[8] : Y16 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.pof b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.pof new file mode 100644 index 0000000..8929318 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.pof differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sld b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sof b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sof new file mode 100644 index 0000000..a9314b9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sof differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sta.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sta.rpt new file mode 100644 index 0000000..cf041e6 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sta.rpt @@ -0,0 +1,503 @@ +TimeQuest Timing Analyzer report for Lab1Pt1 +Thu Feb 25 19:36:27 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; Lab1Pt1 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.2% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0783 V ; 0.157 V ; 0.167 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0783 V ; 0.157 V ; 0.167 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0459 V ; 0.201 V ; 0.093 V ; 4.9e-10 s ; 5.83e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0459 V ; 0.201 V ; 0.093 V ; 4.9e-10 s ; 5.83e-10 s ; Yes ; No ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.77 V ; -0.0485 V ; 0.289 V ; 0.058 V ; 2.81e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.77 V ; -0.0485 V ; 0.289 V ; 0.058 V ; 2.81e-10 s ; 3.04e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 10 ; 10 ; +; Unconstrained Input Port Paths ; 10 ; 10 ; +; Unconstrained Output Ports ; 10 ; 10 ; +; Unconstrained Output Port Paths ; 10 ; 10 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Feb 25 19:36:24 2021 +Info: Command: quartus_sta Lab1Pt1 -c Lab1Pt1 +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'Lab1Pt1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4867 megabytes + Info: Processing ended: Thu Feb 25 19:36:27 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:04 + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sta.summary b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/output_files/Lab1Pt1.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.do b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.do new file mode 100644 index 0000000..a14bfa7 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vlog -work work Lab1Pt1.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst +vcd file -direction Lab1Pt1.msim.vcd +vcd add -internal Lab1Pt1_vlg_vec_tst/* +vcd add -internal Lab1Pt1_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.msim.vcd b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.msim.vcd new file mode 100644 index 0000000..b152709 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.msim.vcd @@ -0,0 +1,300 @@ +$comment + File created using the following command: + vcd file Lab1Pt1.msim.vcd -direction +$end +$date + Thu Feb 25 20:02:14 2021 +$end +$version + ModelSim Version 10.5b +$end +$timescale + 1ps +$end + +$scope module Lab1Pt1_vlg_vec_tst $end +$var reg 10 ! SW [9:0] $end +$var wire 1 " LEDR [9] $end +$var wire 1 # LEDR [8] $end +$var wire 1 $ LEDR [7] $end +$var wire 1 % LEDR [6] $end +$var wire 1 & LEDR [5] $end +$var wire 1 ' LEDR [4] $end +$var wire 1 ( LEDR [3] $end +$var wire 1 ) LEDR [2] $end +$var wire 1 * LEDR [1] $end +$var wire 1 + LEDR [0] $end + +$scope module i1 $end +$var wire 1 , gnd $end +$var wire 1 - vcc $end +$var wire 1 . unknown $end +$var tri1 1 / devclrn $end +$var tri1 1 0 devpor $end +$var tri1 1 1 devoe $end +$var wire 1 2 ~QUARTUS_CREATED_GND~I_combout $end +$var wire 1 3 ~QUARTUS_CREATED_UNVM~~busy $end +$var wire 1 4 ~QUARTUS_CREATED_ADC1~~eoc $end +$var wire 1 5 ~QUARTUS_CREATED_ADC2~~eoc $end +$var wire 1 6 LEDR[0]~output_o $end +$var wire 1 7 LEDR[1]~output_o $end +$var wire 1 8 LEDR[2]~output_o $end +$var wire 1 9 LEDR[3]~output_o $end +$var wire 1 : LEDR[4]~output_o $end +$var wire 1 ; LEDR[5]~output_o $end +$var wire 1 < LEDR[6]~output_o $end +$var wire 1 = LEDR[7]~output_o $end +$var wire 1 > LEDR[8]~output_o $end +$var wire 1 ? LEDR[9]~output_o $end +$var wire 1 @ SW[0]~input_o $end +$var wire 1 A SW[1]~input_o $end +$var wire 1 B SW[2]~input_o $end +$var wire 1 C SW[3]~input_o $end +$var wire 1 D SW[4]~input_o $end +$var wire 1 E SW[5]~input_o $end +$var wire 1 F SW[6]~input_o $end +$var wire 1 G SW[7]~input_o $end +$var wire 1 H SW[8]~input_o $end +$var wire 1 I SW[9]~input_o $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 ! +0+ +0* +0) +0( +0' +0& +0% +0$ +0# +0" +0, +1- +x. +1/ +10 +11 +02 +z3 +z4 +z5 +06 +07 +08 +09 +0: +0; +0< +0= +0> +0? +0@ +0A +0B +0C +0D +0E +0F +0G +0H +0I +$end +#10000 +b1000000000 ! +1I +1? +1" +#20000 +b0 ! +0I +0? +0" +#30000 +b100000000 ! +b110000000 ! +b111000000 ! +b111100000 ! +b111110000 ! +b111111000 ! +b111111100 ! +b111111110 ! +b111111111 ! +b1111111111 ! +1I +1H +1G +1F +1E +1D +1C +1B +1A +1@ +16 +17 +18 +19 +1: +1; +1< +1= +1> +1? +1" +1# +1$ +1% +1& +1' +1( +1) +1* +1+ +#40000 +b1011111111 ! +b1001111111 ! +b1000111111 ! +b1000011111 ! +b1000001111 ! +b1000000111 ! +b1000000011 ! +b1000000001 ! +b1000000000 ! +b0 ! +0I +0H +0G +0F +0E +0D +0C +0B +0A +0@ +06 +07 +08 +09 +0: +0; +0< +0= +0> +0? +0" +0# +0$ +0% +0& +0' +0( +0) +0* +0+ +#60000 +b100000 ! +1E +1; +1& +#130000 +b0 ! +0E +0; +0& +#200000 +b1000000000 ! +1I +1? +1" +#260000 +b1100000000 ! +b100000000 ! +0I +1H +1> +0? +0" +1# +#300000 +b110000000 ! +b10000000 ! +0H +1G +1= +0> +0# +1$ +#340000 +b0 ! +0G +0= +0$ +#350000 +b1000000 ! +1F +1< +1% +#370000 +b1100000 ! +b100000 ! +0F +1E +1; +0< +0% +1& +#390000 +b110000 ! +b10000 ! +0E +1D +1: +0; +0& +1' +#410000 +b11000 ! +b1000 ! +0D +1C +19 +0: +0' +1( +#430000 +b1100 ! +b100 ! +0C +1B +18 +09 +0( +1) +#450000 +b110 ! +b10 ! +0B +1A +17 +08 +0) +1* +#470000 +b11 ! +b1 ! +0A +1@ +16 +07 +0* +1+ +#490000 +b0 ! +0@ +06 +0+ +#1000000 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.sft b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.sft new file mode 100644 index 0000000..f324fea --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.vo b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.vo new file mode 100644 index 0000000..5feeb51 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.vo @@ -0,0 +1,517 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" + +// DATE "02/25/2021 20:02:11" + +// +// Device: Altera 10M50DAF484C7G Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module Lab1Pt1 ( + SW, + LEDR); +input [9:0] SW; +output [9:0] LEDR; + +// Design Ports Information +// LEDR[0] => Location: PIN_J8, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[1] => Location: PIN_J20, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[2] => Location: PIN_L9, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[3] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[4] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[5] => Location: PIN_M18, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[6] => Location: PIN_T5, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[7] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[8] => Location: PIN_W15, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[9] => Location: PIN_AB9, I/O Standard: 2.5 V, Current Strength: Default +// SW[0] => Location: PIN_J9, I/O Standard: 2.5 V, Current Strength: Default +// SW[1] => Location: PIN_H20, I/O Standard: 2.5 V, Current Strength: Default +// SW[2] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// SW[3] => Location: PIN_R22, I/O Standard: 2.5 V, Current Strength: Default +// SW[4] => Location: PIN_W14, I/O Standard: 2.5 V, Current Strength: Default +// SW[5] => Location: PIN_L19, I/O Standard: 2.5 V, Current Strength: Default +// SW[6] => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default +// SW[7] => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +// SW[8] => Location: PIN_Y16, I/O Standard: 2.5 V, Current Strength: Default +// SW[9] => Location: PIN_AA9, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \~QUARTUS_CREATED_UNVM~~busy ; +wire \~QUARTUS_CREATED_ADC1~~eoc ; +wire \~QUARTUS_CREATED_ADC2~~eoc ; +wire \LEDR[0]~output_o ; +wire \LEDR[1]~output_o ; +wire \LEDR[2]~output_o ; +wire \LEDR[3]~output_o ; +wire \LEDR[4]~output_o ; +wire \LEDR[5]~output_o ; +wire \LEDR[6]~output_o ; +wire \LEDR[7]~output_o ; +wire \LEDR[8]~output_o ; +wire \LEDR[9]~output_o ; +wire \SW[0]~input_o ; +wire \SW[1]~input_o ; +wire \SW[2]~input_o ; +wire \SW[3]~input_o ; +wire \SW[4]~input_o ; +wire \SW[5]~input_o ; +wire \SW[6]~input_o ; +wire \SW[7]~input_o ; +wire \SW[8]~input_o ; +wire \SW[9]~input_o ; + + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: LCCOMB_X44_Y51_N16 +fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): +// \~QUARTUS_CREATED_GND~I_combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .cout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000; +defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y36_N16 +fiftyfivenm_io_obuf \LEDR[0]~output ( + .i(\SW[0]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[0]~output .bus_hold = "false"; +defparam \LEDR[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X78_Y45_N9 +fiftyfivenm_io_obuf \LEDR[1]~output ( + .i(\SW[1]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[1]~output .bus_hold = "false"; +defparam \LEDR[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N23 +fiftyfivenm_io_obuf \LEDR[2]~output ( + .i(\SW[2]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[2]~output .bus_hold = "false"; +defparam \LEDR[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X78_Y21_N16 +fiftyfivenm_io_obuf \LEDR[3]~output ( + .i(\SW[3]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[3]~output .bus_hold = "false"; +defparam \LEDR[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X49_Y0_N2 +fiftyfivenm_io_obuf \LEDR[4]~output ( + .i(\SW[4]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[4]~output .bus_hold = "false"; +defparam \LEDR[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X78_Y37_N23 +fiftyfivenm_io_obuf \LEDR[5]~output ( + .i(\SW[5]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[5]~output .bus_hold = "false"; +defparam \LEDR[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y3_N16 +fiftyfivenm_io_obuf \LEDR[6]~output ( + .i(\SW[6]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[6]~output .bus_hold = "false"; +defparam \LEDR[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X22_Y39_N30 +fiftyfivenm_io_obuf \LEDR[7]~output ( + .i(\SW[7]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[7]~output .bus_hold = "false"; +defparam \LEDR[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X54_Y0_N9 +fiftyfivenm_io_obuf \LEDR[8]~output ( + .i(\SW[8]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[8]~output .bus_hold = "false"; +defparam \LEDR[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y0_N16 +fiftyfivenm_io_obuf \LEDR[9]~output ( + .i(\SW[9]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[9]~output .bus_hold = "false"; +defparam \LEDR[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y36_N22 +fiftyfivenm_io_ibuf \SW[0]~input ( + .i(SW[0]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[0]~input_o )); +// synopsys translate_off +defparam \SW[0]~input .bus_hold = "false"; +defparam \SW[0]~input .listen_to_nsleep_signal = "false"; +defparam \SW[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X78_Y45_N1 +fiftyfivenm_io_ibuf \SW[1]~input ( + .i(SW[1]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[1]~input_o )); +// synopsys translate_off +defparam \SW[1]~input .bus_hold = "false"; +defparam \SW[1]~input .listen_to_nsleep_signal = "false"; +defparam \SW[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y27_N1 +fiftyfivenm_io_ibuf \SW[2]~input ( + .i(SW[2]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[2]~input_o )); +// synopsys translate_off +defparam \SW[2]~input .bus_hold = "false"; +defparam \SW[2]~input .listen_to_nsleep_signal = "false"; +defparam \SW[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X78_Y21_N8 +fiftyfivenm_io_ibuf \SW[3]~input ( + .i(SW[3]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[3]~input_o )); +// synopsys translate_off +defparam \SW[3]~input .bus_hold = "false"; +defparam \SW[3]~input .listen_to_nsleep_signal = "false"; +defparam \SW[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X49_Y0_N22 +fiftyfivenm_io_ibuf \SW[4]~input ( + .i(SW[4]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[4]~input_o )); +// synopsys translate_off +defparam \SW[4]~input .bus_hold = "false"; +defparam \SW[4]~input .listen_to_nsleep_signal = "false"; +defparam \SW[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X78_Y37_N8 +fiftyfivenm_io_ibuf \SW[5]~input ( + .i(SW[5]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[5]~input_o )); +// synopsys translate_off +defparam \SW[5]~input .bus_hold = "false"; +defparam \SW[5]~input .listen_to_nsleep_signal = "false"; +defparam \SW[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y3_N1 +fiftyfivenm_io_ibuf \SW[6]~input ( + .i(SW[6]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[6]~input_o )); +// synopsys translate_off +defparam \SW[6]~input .bus_hold = "false"; +defparam \SW[6]~input .listen_to_nsleep_signal = "false"; +defparam \SW[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X22_Y39_N15 +fiftyfivenm_io_ibuf \SW[7]~input ( + .i(SW[7]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[7]~input_o )); +// synopsys translate_off +defparam \SW[7]~input .bus_hold = "false"; +defparam \SW[7]~input .listen_to_nsleep_signal = "false"; +defparam \SW[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X54_Y0_N22 +fiftyfivenm_io_ibuf \SW[8]~input ( + .i(SW[8]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[8]~input_o )); +// synopsys translate_off +defparam \SW[8]~input .bus_hold = "false"; +defparam \SW[8]~input .listen_to_nsleep_signal = "false"; +defparam \SW[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y0_N22 +fiftyfivenm_io_ibuf \SW[9]~input ( + .i(SW[9]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[9]~input_o )); +// synopsys translate_off +defparam \SW[9]~input .bus_hold = "false"; +defparam \SW[9]~input .listen_to_nsleep_signal = "false"; +defparam \SW[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: UNVM_X0_Y40_N40 +fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ ( + .arclk(vcc), + .arshft(vcc), + .drclk(vcc), + .drshft(vcc), + .drdin(vcc), + .nprogram(vcc), + .nerase(vcc), + .nosc_ena(\~QUARTUS_CREATED_GND~I_combout ), + .par_en(vcc), + .xe_ye(\~QUARTUS_CREATED_GND~I_combout ), + .se(\~QUARTUS_CREATED_GND~I_combout ), + .ardin(23'b11111111111111111111111), + .busy(\~QUARTUS_CREATED_UNVM~~busy ), + .osc(), + .bgpbusy(), + .sp_pass(), + .se_pass(), + .drdout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm"; +defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true"; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y52_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC1~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1; +defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y51_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC2~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2; +defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0; +// synopsys translate_on + +assign LEDR[0] = \LEDR[0]~output_o ; + +assign LEDR[1] = \LEDR[1]~output_o ; + +assign LEDR[2] = \LEDR[2]~output_o ; + +assign LEDR[3] = \LEDR[3]~output_o ; + +assign LEDR[4] = \LEDR[4]~output_o ; + +assign LEDR[5] = \LEDR[5]~output_o ; + +assign LEDR[6] = \LEDR[6]~output_o ; + +assign LEDR[7] = \LEDR[7]~output_o ; + +assign LEDR[8] = \LEDR[8]~output_o ; + +assign LEDR[9] = \LEDR[9]~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_TMS~~padout ; +wire \~ALTERA_TCK~~padout ; +wire \~ALTERA_TDI~~padout ; +wire \~ALTERA_CONFIG_SEL~~padout ; +wire \~ALTERA_nCONFIG~~padout ; +wire \~ALTERA_nSTATUS~~padout ; +wire \~ALTERA_CONF_DONE~~padout ; +wire \~ALTERA_TMS~~ibuf_o ; +wire \~ALTERA_TCK~~ibuf_o ; +wire \~ALTERA_TDI~~ibuf_o ; +wire \~ALTERA_CONFIG_SEL~~ibuf_o ; +wire \~ALTERA_nCONFIG~~ibuf_o ; +wire \~ALTERA_nSTATUS~~ibuf_o ; +wire \~ALTERA_CONF_DONE~~ibuf_o ; + + +endmodule diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_20210225200214.sim.vwf b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_20210225200214.sim.vwf new file mode 100644 index 0000000..80171a4 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_20210225200214.sim.vwf @@ -0,0 +1,829 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 740.0; + } + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 700.0; + } + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 660.0; + } + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 310.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 630.0; + } + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 610.0; + } + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 350.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 590.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 370.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 570.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 390.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 550.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 410.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 530.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 510.0; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 740.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 700.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 660.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 310.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 630.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 610.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 350.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 590.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 370.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 390.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 550.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 410.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 530.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 510.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_modelsim.xrf b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_modelsim.xrf new file mode 100644 index 0000000..1339c5a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_modelsim.xrf @@ -0,0 +1,36 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cbx.xml +design_name = Lab1Pt1 +instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, Lab1Pt1, 1 +instance = comp, \LEDR[0]~output , LEDR[0]~output, Lab1Pt1, 1 +instance = comp, \LEDR[1]~output , LEDR[1]~output, Lab1Pt1, 1 +instance = comp, \LEDR[2]~output , LEDR[2]~output, Lab1Pt1, 1 +instance = comp, \LEDR[3]~output , LEDR[3]~output, Lab1Pt1, 1 +instance = comp, \LEDR[4]~output , LEDR[4]~output, Lab1Pt1, 1 +instance = comp, \LEDR[5]~output , LEDR[5]~output, Lab1Pt1, 1 +instance = comp, \LEDR[6]~output , LEDR[6]~output, Lab1Pt1, 1 +instance = comp, \LEDR[7]~output , LEDR[7]~output, Lab1Pt1, 1 +instance = comp, \LEDR[8]~output , LEDR[8]~output, Lab1Pt1, 1 +instance = comp, \LEDR[9]~output , LEDR[9]~output, Lab1Pt1, 1 +instance = comp, \SW[0]~input , SW[0]~input, Lab1Pt1, 1 +instance = comp, \SW[1]~input , SW[1]~input, Lab1Pt1, 1 +instance = comp, \SW[2]~input , SW[2]~input, Lab1Pt1, 1 +instance = comp, \SW[3]~input , SW[3]~input, Lab1Pt1, 1 +instance = comp, \SW[4]~input , SW[4]~input, Lab1Pt1, 1 +instance = comp, \SW[5]~input , SW[5]~input, Lab1Pt1, 1 +instance = comp, \SW[6]~input , SW[6]~input, Lab1Pt1, 1 +instance = comp, \SW[7]~input , SW[7]~input, Lab1Pt1, 1 +instance = comp, \SW[8]~input , SW[8]~input, Lab1Pt1, 1 +instance = comp, \SW[9]~input , SW[9]~input, Lab1Pt1, 1 +instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, Lab1Pt1, 1 +instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, Lab1Pt1, 1 +instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, Lab1Pt1, 1 +design_name = hard_block +instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt new file mode 100644 index 0000000..c97f67a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt @@ -0,0 +1,142 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "02/25/2021 20:02:10" + +// Verilog Test Bench (with test vectors) for design : Lab1Pt1 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module Lab1Pt1_vlg_vec_tst(); +// constants +// general purpose registers +reg [9:0] SW; +// wires +wire [9:0] LEDR; + +// assign statements (if any) +Lab1Pt1 i1 ( +// port map - connection between master ports and signals/registers + .LEDR(LEDR), + .SW(SW) +); +initial +begin +#1000000 $finish; +end +// SW[ 9 ] +initial +begin + SW[9] = 1'b0; + SW[9] = #10000 1'b1; + SW[9] = #10000 1'b0; + SW[9] = #10000 1'b1; + SW[9] = #10000 1'b0; + SW[9] = #160000 1'b1; + SW[9] = #60000 1'b0; +end +// SW[ 8 ] +initial +begin + SW[8] = 1'b0; + SW[8] = #30000 1'b1; + SW[8] = #10000 1'b0; + SW[8] = #220000 1'b1; + SW[8] = #40000 1'b0; +end +// SW[ 7 ] +initial +begin + SW[7] = 1'b0; + SW[7] = #30000 1'b1; + SW[7] = #10000 1'b0; + SW[7] = #260000 1'b1; + SW[7] = #40000 1'b0; +end +// SW[ 6 ] +initial +begin + SW[6] = 1'b0; + SW[6] = #30000 1'b1; + SW[6] = #10000 1'b0; + SW[6] = #310000 1'b1; + SW[6] = #20000 1'b0; +end +// SW[ 5 ] +initial +begin + SW[5] = 1'b0; + SW[5] = #30000 1'b1; + SW[5] = #10000 1'b0; + SW[5] = #20000 1'b1; + SW[5] = #70000 1'b0; + SW[5] = #240000 1'b1; + SW[5] = #20000 1'b0; +end +// SW[ 4 ] +initial +begin + SW[4] = 1'b0; + SW[4] = #30000 1'b1; + SW[4] = #10000 1'b0; + SW[4] = #350000 1'b1; + SW[4] = #20000 1'b0; +end +// SW[ 3 ] +initial +begin + SW[3] = 1'b0; + SW[3] = #30000 1'b1; + SW[3] = #10000 1'b0; + SW[3] = #370000 1'b1; + SW[3] = #20000 1'b0; +end +// SW[ 2 ] +initial +begin + SW[2] = 1'b0; + SW[2] = #30000 1'b1; + SW[2] = #10000 1'b0; + SW[2] = #390000 1'b1; + SW[2] = #20000 1'b0; +end +// SW[ 1 ] +initial +begin + SW[1] = 1'b0; + SW[1] = #30000 1'b1; + SW[1] = #10000 1'b0; + SW[1] = #410000 1'b1; + SW[1] = #20000 1'b0; +end +// SW[ 0 ] +initial +begin + SW[0] = 1'b0; + SW[0] = #30000 1'b1; + SW[0] = #10000 1'b0; + SW[0] = #430000 1'b1; + SW[0] = #20000 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/transcript b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/transcript new file mode 100644 index 0000000..e0ae487 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/transcript @@ -0,0 +1,36 @@ +# do Lab1Pt1.do +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:02:13 on Feb 25,2021 +# vlog -work work Lab1Pt1.vo +# -- Compiling module Lab1Pt1 +# -- Compiling module hard_block +# +# Top level modules: +# Lab1Pt1 +# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:02:13 on Feb 25,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module Lab1Pt1_vlg_vec_tst +# +# Top level modules: +# Lab1Pt1_vlg_vec_tst +# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst +# Start time: 20:02:14 on Feb 25,2021 +# Loading work.Lab1Pt1_vlg_vec_tst +# Loading work.Lab1Pt1 +# Loading work.hard_block +# ** Warning: (vsim-3017) Lab1Pt1.vo(406): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) Lab1Pt1.vo(406): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) Lab1Pt1.vo(429): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) Lab1Pt1.vo(429): [TFMPC] - Missing connection for port 'clk_dft'. +# after#24 +# ** Note: $finish : Waveform.vwf.vt(45) +# Time: 1 us Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst +# End time: 20:02:14 on Feb 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/vwf_sim_transcript b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..9526fda --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,142 @@ +Determining the location of the ModelSim executable... + +Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt" + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Feb 25 20:02:09 2021 +Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt" +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. + +Completed successfully. + +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1 + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Feb 25 20:02:10 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file Lab1Pt1.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Feb 25 20:02:11 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + +Completed successfully. + +**** Generating the ModelSim .do script **** + +C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do Lab1Pt1.do + +Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl + + +# 10.5b + +# do Lab1Pt1.do + +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:02:13 on Feb 25,2021 +# vlog -work work Lab1Pt1.vo + +# -- Compiling module Lab1Pt1 +# -- Compiling module hard_block +# +# Top level modules: +# Lab1Pt1 +# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:02:13 on Feb 25,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module Lab1Pt1_vlg_vec_tst +# +# Top level modules: +# Lab1Pt1_vlg_vec_tst +# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst +# Start time: 20:02:14 on Feb 25,2021 +# Loading work.Lab1Pt1_vlg_vec_tst +# Loading work.Lab1Pt1 +# Loading work.hard_block +# ** Warning: (vsim-3017) Lab1Pt1.vo(406): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) Lab1Pt1.vo(406): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) Lab1Pt1.vo(429): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) Lab1Pt1.vo(429): [TFMPC] - Missing connection for port 'clk_dft'. +# after#24 +# ** Note: $finish : Waveform.vwf.vt(45) +# Time: 1 us Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst +# End time: 20:02:14 on Feb 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4 + +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf... + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.msim.vcd... + +Processing channel transitions... + +Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_20210225200214.sim.vwf + +Finished VCD to VWF conversion. + +Completed successfully. + +All completed. \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_info b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_info new file mode 100644 index 0000000..a5492fd --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_info @@ -0,0 +1,75 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dC:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim +vhard_block +Z1 !s110 1614304933 +!i10b 1 +!s100 DcO78?h1mRCVlg_3oDgmk0 +IoZd:WG^U6F_U:64AXFcTmd653 +R2 +R0 +R3 +R4 +R5 +L0 32 +R6 +r1 +!s85 0 +31 +R7 +R8 +R9 +!i113 1 +R10 +R11 +n@lab1@pt1 +vLab1Pt1_vlg_vec_tst +R1 +!i10b 1 +!s100 7k9eW>3G`@cPjj;45<5M71 +I6K3e5S;j5kiP]F0?jlZ612 +R2 +R0 +w1614304930 +8Waveform.vwf.vt +FWaveform.vwf.vt +L0 30 +R6 +r1 +!s85 0 +31 +R7 +!s107 Waveform.vwf.vt| +!s90 -work|work|Waveform.vwf.vt| +!i113 1 +R10 +R11 +n@lab1@pt1_vlg_vec_tst diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib.qdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib.qdb new file mode 100644 index 0000000..dcc515d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib.qdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qdb b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qdb new file mode 100644 index 0000000..81bc430 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qpg b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qpg new file mode 100644 index 0000000..23b5a5b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qpg differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qtl b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qtl new file mode 100644 index 0000000..d403149 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib1_0.qtl differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_vmake b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qpf b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qpf new file mode 100644 index 0000000..faebb31 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 18:45:00 March 11, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "18:45:00 March 11, 2021" + +# Revisions + +PROJECT_REVISION = "Lab1Part2" diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qsf b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qsf new file mode 100644 index 0000000..092b712 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qsf @@ -0,0 +1,81 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 18:45:00 March 11, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Lab1Part2_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY Lab1Part2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:45:00 MARCH 11, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name VERILOG_FILE Lab1Part2.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Lab1Part2.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE output_files/Waveform.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qsf.bak b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qsf.bak new file mode 100644 index 0000000..465cb18 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qsf.bak @@ -0,0 +1,58 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 18:45:00 March 11, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Lab1Part2_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY Lab1Part2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:45:00 MARCH 11, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name VERILOG_FILE Lab1Part2.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qws b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qws new file mode 100644 index 0000000..953e287 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.qws differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v new file mode 100644 index 0000000..9698bf0 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v @@ -0,0 +1,16 @@ +module Lab1Part2 (SW,LEDR); + input [9:0]SW; + output [9:0]LEDR; + wire sel; + wire [3:0]X,Y,M; + assign X=SW[3:0]; + assign Y=SW[7:4]; + assign sel=SW[9]; + assign M[0]=(~sel &X[0])|(sel &Y[0]); + assign M[1]=(~sel &X[1])|(sel &Y[1]); + assign M[2]=(~sel &X[2])|(sel &Y[2]); + assign M[3]=(~sel &X[3])|(sel &Y[3]); + assign LEDR[9]=sel; + assign LEDR[3:0]=M; + assign LEDR[8:4]=5`b0; + endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v.bak b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v.bak new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2_assignment_defaults.qdf b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2_assignment_defaults.qdf new file mode 100644 index 0000000..f46954a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 14:11:10 April 22, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value ENABLE +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf b/EE203/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf new file mode 100644 index 0000000..116469d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf @@ -0,0 +1,724 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Part2 -c Lab1Part2 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Part2 -c Lab1Part2 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2 +onerror {exit -code 1} +vlib work +vlog -work work Lab1Part2.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst +vcd file -direction Lab1Part2.msim.vcd +vcd add -internal Lab1Part2_vlg_vec_tst/* +vcd add -internal Lab1Part2_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work Lab1Part2.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst +vcd file -direction Lab1Part2.msim.vcd +vcd add -internal Lab1Part2_vlg_vec_tst/* +vcd add -internal Lab1Part2_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 560.0; + LEVEL 0 FOR 430.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 880.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 130.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 750.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 670.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 330.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 550.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 460.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 490.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 510.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 420.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 580.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 360.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 640.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 310.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 700.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 240.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.(0).cnf.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.(0).cnf.cdb new file mode 100644 index 0000000..3e531c9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.(0).cnf.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.(0).cnf.hdb new file mode 100644 index 0000000..7454303 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm.qmsg new file mode 100644 index 0000000..dd1802b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615514320419 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615514320419 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 19:58:40 2021 " "Processing started: Thu Mar 11 19:58:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615514320419 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1615514320419 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1615514320419 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1615514320719 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1615514322469 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1615514322609 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615514323679 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:58:43 2021 " "Processing ended: Thu Mar 11 19:58:43 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615514323679 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615514323679 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615514323679 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1615514323679 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm.rdb new file mode 100644 index 0000000..440be6b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm_labs.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm_labs.ddb new file mode 100644 index 0000000..51ff11d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cbx.xml b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cbx.xml new file mode 100644 index 0000000..7b7e934 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.bpm b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.bpm new file mode 100644 index 0000000..1f8265a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.cdb new file mode 100644 index 0000000..95a499e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.hdb new file mode 100644 index 0000000..90c10f9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.idb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.idb new file mode 100644 index 0000000..c4c0956 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.idb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.logdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.logdb new file mode 100644 index 0000000..36e4fb9 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.logdb @@ -0,0 +1,62 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,20;0;20;0;0;20;20;0;20;20;0;10;0;0;10;0;10;10;0;0;0;10;0;0;0;0;0;20;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,0;20;0;20;20;0;0;20;0;0;20;10;20;20;10;20;10;10;20;20;20;10;20;20;20;20;20;0;20;20, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 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+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cmp.rdb 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1615513952779 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "Lab1Part2.vo C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim// simulation " "Generated file Lab1Part2.vo in folder \"C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615513952829 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 26 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4641 " "Peak virtual memory: 4641 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615513952889 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:52:32 2021 " "Processing ended: Thu Mar 11 19:52:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615513952889 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615513952889 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615513952889 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1615513952889 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.fit.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.fit.qmsg new file mode 100644 index 0000000..962c875 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.fit.qmsg @@ -0,0 +1,50 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1615514313129 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1615514313129 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "Lab1Part2 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"Lab1Part2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1615514313129 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615514313169 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615514313169 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1615514313389 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1615514313399 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615514313509 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1615514313509 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 57 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 59 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 61 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 63 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 65 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 67 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 69 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615514313509 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 71 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615514313509 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1615514313509 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615514313509 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615514313509 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615514313509 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615514313509 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1615514313509 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Lab1Part2.sdc " "Synopsys Design Constraints File file not found: 'Lab1Part2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1615514313969 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1615514313969 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1615514313969 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1615514313979 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1615514313979 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1615514313979 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1615514313979 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1615514313979 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615514313979 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615514313979 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615514313979 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615514313979 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1615514313979 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1615514313979 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1615514313979 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1615514313979 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1615514313979 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1615514313979 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615514314009 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1615514314009 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1615514315139 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615514315199 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1615514315219 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1615514315459 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615514315459 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1615514315909 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1615514317249 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1615514317249 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1615514317359 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1615514317359 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1615514317359 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615514317359 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1615514317569 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615514317569 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615514317819 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615514317819 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615514318159 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615514318629 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1615514318909 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5904 " "Peak virtual memory: 5904 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615514319419 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:58:39 2021 " "Processing ended: Thu Mar 11 19:58:39 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615514319419 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615514319419 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615514319419 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1615514319419 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.hier_info b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.hier_info new file mode 100644 index 0000000..b8696d0 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.hier_info @@ -0,0 +1,31 @@ +|Lab1Part2 +SW[0] => M.IN0 +SW[1] => M.IN0 +SW[2] => M.IN0 +SW[3] => M.IN0 +SW[4] => M.IN0 +SW[5] => M.IN0 +SW[6] => M.IN0 +SW[7] => M.IN0 +SW[8] => ~NO_FANOUT~ +SW[9] => M.IN1 +SW[9] => M.IN1 +SW[9] => M.IN1 +SW[9] => M.IN1 +SW[9] => LEDR[9].DATAIN +SW[9] => M.IN1 +SW[9] => M.IN1 +SW[9] => M.IN1 +SW[9] => M.IN1 +LEDR[0] << M.DB_MAX_OUTPUT_PORT_TYPE +LEDR[1] << M.DB_MAX_OUTPUT_PORT_TYPE +LEDR[2] << M.DB_MAX_OUTPUT_PORT_TYPE +LEDR[3] << M.DB_MAX_OUTPUT_PORT_TYPE +LEDR[4] << +LEDR[5] << +LEDR[6] << +LEDR[7] << +LEDR[8] << +LEDR[9] << SW[9].DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.hif b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.hif new file mode 100644 index 0000000..9bf4e25 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.hif differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.html b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.html new file mode 100644 index 0000000..7d68592 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.rdb new file mode 100644 index 0000000..c179f4d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.txt b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.txt new file mode 100644 index 0000000..dbfe520 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.ammdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.ammdb new file mode 100644 index 0000000..a4afc79 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.bpm b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.bpm new file mode 100644 index 0000000..dae8356 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.cdb new file mode 100644 index 0000000..33ec2b4 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.hdb new file mode 100644 index 0000000..120d9e3 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.kpt b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.kpt new file mode 100644 index 0000000..5915896 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.logdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.qmsg new file mode 100644 index 0000000..4b7bcd2 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.qmsg @@ -0,0 +1,15 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615514302220 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615514302230 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 19:58:22 2021 " "Processing started: Thu Mar 11 19:58:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615514302230 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615514302230 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Lab1Part2 -c Lab1Part2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1Part2 -c Lab1Part2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615514302230 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1615514302580 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1615514302580 ""} +{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "b0 Lab1Part2.v(15) " "Verilog HDL Compiler Directive warning at Lab1Part2.v(15): text macro \"b0\" is undefined" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 15 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1615514310839 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lab1part2.v 1 1 " "Found 1 design units, including 1 entities, in source file lab1part2.v" { { "Info" "ISGN_ENTITY_NAME" "1 Lab1Part2 " "Found entity 1: Lab1Part2" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615514310839 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615514310839 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "Lab1Part2 " "Elaborating entity \"Lab1Part2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1615514310879 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] VCC " "Pin \"LEDR\[4\]\" is stuck at VCC" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] VCC " "Pin \"LEDR\[6\]\" is stuck at VCC" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[8]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1615514311209 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1615514311269 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1615514311539 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1615514311669 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615514311669 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 2 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1615514311719 "|Lab1Part2|SW[8]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1615514311719 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "24 " "Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1615514311719 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1615514311719 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1615514311719 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1615514311719 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4781 " "Peak virtual memory: 4781 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615514311769 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:58:31 2021 " "Processing ended: Thu Mar 11 19:58:31 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615514311769 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615514311769 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615514311769 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1615514311769 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.rdb new file mode 100644 index 0000000..a6d77e3 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.cdb new file mode 100644 index 0000000..9bc4d2c Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.hdb new file mode 100644 index 0000000..0d8113d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.logdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.pre_map.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.pre_map.hdb new file mode 100644 index 0000000..c560bd0 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.pre_map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.quiproj.12507.rdr.flock b/EE203/Noah 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Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sld_design_entry.sci differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sld_design_entry_dsc.sci b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sld_design_entry_dsc.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.smart_action.txt b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.smart_action.txt new file mode 100644 index 0000000..437a63e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta.qmsg new file mode 100644 index 0000000..d4774bf --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta.qmsg @@ -0,0 +1,51 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615514324969 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615514324979 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 19:58:44 2021 " "Processing started: Thu Mar 11 19:58:44 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615514324979 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514324979 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Lab1Part2 -c Lab1Part2 " "Command: quartus_sta Lab1Part2 -c Lab1Part2" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514324979 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1615514325079 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment 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was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514325109 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325109 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325249 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325249 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325279 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325279 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Lab1Part2.sdc " "Synopsys Design Constraints File file not found: 'Lab1Part2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325549 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325549 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325549 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325549 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325549 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325549 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1615514325549 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325559 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615514325559 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325559 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1615514325559 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325569 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325569 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325569 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325579 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325589 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615514325599 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325619 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514325989 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326059 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326059 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326059 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326059 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326059 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326069 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326069 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326069 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326079 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326079 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615514326079 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326269 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326269 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326269 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326269 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326269 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326269 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326269 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326279 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514326279 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514327099 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514327099 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 30 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4865 " "Peak virtual memory: 4865 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615514327149 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:58:47 2021 " "Processing ended: Thu Mar 11 19:58:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615514327149 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615514327149 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615514327149 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615514327149 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta.rdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta.rdb new file mode 100644 index 0000000..d785843 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta_cmp.7_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta_cmp.7_slow_1200mv_85c.tdb new file mode 100644 index 0000000..04b3424 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.sta_cmp.7_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tis_db_list.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tis_db_list.ddb new file mode 100644 index 0000000..eda1a82 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..72f85c3 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fastest_slow_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..775afa7 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fastest_slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..9b766bb Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..6e07aab Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..9d8b767 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tmw_info b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tmw_info new file mode 100644 index 0000000..93bfb4b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:26 +start_analysis_synthesis:s:00:00:11-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:08-start_full_compilation +start_assembler:s:00:00:04-start_full_compilation +start_timing_analyzer:s:00:00:03-start_full_compilation diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.vpr.ammdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.vpr.ammdb new file mode 100644 index 0000000..364ba7f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..d86640f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ii_0c_slow.hsd b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..d223770 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ii_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ii_85c_slow.hsd b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..859bd44 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.zippleback_io_sim_cache.ii_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2_partition_pins.json b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2_partition_pins.json new file mode 100644 index 0000000..4a2d90f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2_partition_pins.json @@ -0,0 +1,65 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "LEDR[0]", + "strict" : false + }, + { + "name" : "LEDR[1]", + "strict" : false + }, + { + "name" : "LEDR[2]", + "strict" : false + }, + { + "name" : "LEDR[3]", + "strict" : false + }, + { + "name" : "LEDR[9]", + "strict" : false + }, + { + "name" : "SW[4]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[9]", + "strict" : false + }, + { + "name" : "SW[5]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[6]", + "strict" : false + }, + { + "name" : "SW[2]", + "strict" : false + }, + { + "name" : "SW[7]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/db/prev_cmp_Lab1Part2.qmsg b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/prev_cmp_Lab1Part2.qmsg new file mode 100644 index 0000000..53ba7f1 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/db/prev_cmp_Lab1Part2.qmsg @@ -0,0 +1,131 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615512692606 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615512692616 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 19:31:32 2021 " "Processing started: Thu Mar 11 19:31:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615512692616 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615512692616 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Lab1Part2 -c Lab1Part2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1Part2 -c Lab1Part2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615512692616 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1615512692976 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1615512692976 ""} +{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "b0 Lab1Part2.v(15) " "Verilog HDL Compiler Directive warning at Lab1Part2.v(15): text macro \"b0\" is undefined" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 15 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1615512701103 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lab1part2.v 1 1 " "Found 1 design units, including 1 entities, in source file lab1part2.v" { { "Info" "ISGN_ENTITY_NAME" "1 Lab1Part2 " "Found entity 1: Lab1Part2" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615512701103 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615512701103 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "Lab1Part2 " "Elaborating entity \"Lab1Part2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1615512701133 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] VCC " "Pin \"LEDR\[4\]\" is stuck at VCC" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615512701443 "|Lab1Part2|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615512701443 "|Lab1Part2|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] VCC " "Pin \"LEDR\[6\]\" is stuck at VCC" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615512701443 "|Lab1Part2|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615512701443 "|Lab1Part2|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615512701443 "|Lab1Part2|LEDR[8]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1615512701443 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1615512701503 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512701773 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1615512701773 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1615512701913 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615512701913 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" { } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 2 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1615512701963 "|Lab1Part2|SW[8]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1615512701963 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "24 " "Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1615512701963 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1615512701963 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1615512701963 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1615512701963 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4780 " "Peak virtual memory: 4780 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615512702003 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:31:42 2021 " "Processing ended: Thu Mar 11 19:31:42 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615512702003 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615512702003 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615512702003 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1615512702003 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1615512703173 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615512703183 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 19:31:42 2021 " "Processing started: Thu Mar 11 19:31:42 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615512703183 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1615512703183 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1615512703183 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1615512703283 ""} +{ "Info" "0" "" "Project = Lab1Part2" { } { } 0 0 "Project = Lab1Part2" 0 0 "Fitter" 0 0 1615512703283 ""} +{ "Info" "0" "" "Revision = Lab1Part2" { } { } 0 0 "Revision = Lab1Part2" 0 0 "Fitter" 0 0 1615512703283 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1615512703373 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1615512703373 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "Lab1Part2 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"Lab1Part2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1615512703373 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615512703413 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615512703413 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1615512703643 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1615512703643 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615512703753 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1615512703753 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 57 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 59 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 61 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 63 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 65 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 67 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 69 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615512703753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 0 { 0 ""} 0 71 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615512703753 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1615512703753 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615512703753 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615512703753 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615512703753 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615512703753 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1615512703753 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Lab1Part2.sdc " "Synopsys Design Constraints File file not found: 'Lab1Part2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1615512704213 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1615512704213 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1615512704213 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1615512704213 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1615512704213 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1615512704213 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1615512704213 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1615512704213 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615512704213 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615512704213 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615512704213 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615512704213 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1615512704223 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1615512704223 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1615512704223 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1615512704223 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1615512704223 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1615512704223 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615512704243 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1615512704253 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1615512705373 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615512705423 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1615512705453 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1615512705683 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615512705683 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1615512706133 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1615512707473 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1615512707473 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1615512707573 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1615512707573 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1615512707573 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615512707573 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1615512707783 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615512707793 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615512708033 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615512708033 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615512708373 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615512708843 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1615512709123 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5905 " "Peak virtual memory: 5905 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615512709623 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:31:49 2021 " "Processing ended: Thu Mar 11 19:31:49 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615512709623 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615512709623 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615512709623 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1615512709623 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1615512710623 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615512710633 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 19:31:50 2021 " "Processing started: Thu Mar 11 19:31:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615512710633 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1615512710633 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1615512710633 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1615512710913 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1615512712673 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1615512712803 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615512713873 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:31:53 2021 " "Processing ended: Thu Mar 11 19:31:53 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615512713873 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615512713873 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615512713873 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1615512713873 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1615512714613 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1615512715173 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615512715183 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 19:31:54 2021 " "Processing started: Thu Mar 11 19:31:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615512715183 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715183 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Lab1Part2 -c Lab1Part2 " "Command: quartus_sta Lab1Part2 -c Lab1Part2" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715183 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1615512715283 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615512715313 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715313 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715443 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715443 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715483 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715483 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Lab1Part2.sdc " "Synopsys Design Constraints File file not found: 'Lab1Part2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715763 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715763 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715763 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715763 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715763 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715763 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1615512715763 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715773 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615512715773 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715773 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1615512715773 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715783 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715783 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715793 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715793 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715793 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615512715803 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512715823 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716193 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716263 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716263 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716263 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716263 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716263 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716263 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716263 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716273 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716273 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716273 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615512716273 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716463 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716463 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716463 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716463 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716463 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716463 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716473 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716473 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512716473 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512717283 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512717283 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 30 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4865 " "Peak virtual memory: 4865 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615512717343 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:31:57 2021 " "Processing ended: Thu Mar 11 19:31:57 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615512717343 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615512717343 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615512717343 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512717343 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 71 s " "Quartus Prime Full Compilation was successful. 0 errors, 71 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615512717983 ""} diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/README b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.db_info b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.db_info new file mode 100644 index 0000000..711f5cb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Thu Apr 22 14:11:10 2021 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.ammdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.ammdb new file mode 100644 index 0000000..d1bec11 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.cdb new file mode 100644 index 0000000..697e8db Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.dfp b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.hdb new file mode 100644 index 0000000..0fd4ab9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.logdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.rcfdb new file mode 100644 index 0000000..ab9c317 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.cdb new file mode 100644 index 0000000..09c22fc Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.dpi b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.dpi new file mode 100644 index 0000000..f22bd75 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..6f9deab Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..b4c5546 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hdb new file mode 100644 index 0000000..a4c7d4a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.kpt b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.kpt new file mode 100644 index 0000000..7930ac1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.rrp.hdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.rrp.hdb new file mode 100644 index 0000000..66755a2 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/incremental_db/compiled_partitions/Lab1Part2.rrp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.asm.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.asm.rpt new file mode 100644 index 0000000..99d4429 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.asm.rpt @@ -0,0 +1,93 @@ +Assembler report for Lab1Part2 +Thu Mar 11 19:58:43 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Mar 11 19:58:43 2021 ; +; Revision Name ; Lab1Part2 ; +; Top-level Entity Name ; Lab1Part2 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++---------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++---------------------------------------------------------------------------------+ +; File Name ; ++---------------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sof ; ++---------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sof ; ++----------------+------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+------------------------------------------------------------------------------------------+ +; Device ; 10M50DAF484C7G ; +; JTAG usercode ; 0x00270F49 ; +; Checksum ; 0x00270F49 ; ++----------------+------------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Mar 11 19:58:40 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4684 megabytes + Info: Processing ended: Thu Mar 11 19:58:43 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.done b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.done new file mode 100644 index 0000000..4ff9e18 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.done @@ -0,0 +1 @@ +Thu Mar 11 19:58:47 2021 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.eda.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.eda.rpt new file mode 100644 index 0000000..1e985bb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.eda.rpt @@ -0,0 +1,133 @@ +EDA Netlist Writer report for Lab1Part2 +Thu Mar 11 19:52:32 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Mar 11 19:52:32 2021 ; +; Revision Name ; Lab1Part2 ; +; Top-level Entity Name ; Lab1Part2 ; +; Family ; MAX 10 ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++------------------------------------------------------------------------------------+ +; Generated Files ; ++------------------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim//Lab1Part2.vo ; ++------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Mar 11 19:52:32 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file Lab1Part2.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 26 warnings + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Mar 11 19:52:32 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.rpt new file mode 100644 index 0000000..dd5e736 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.rpt @@ -0,0 +1,1262 @@ +Fitter report for Lab1Part2 +Thu Mar 11 19:58:38 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Mar 11 19:58:38 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Lab1Part2 ; +; Top-level Entity Name ; Lab1Part2 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 5 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 20 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C7G ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.2% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; +; -- Achieved ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 48 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 5 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 4 ; +; -- <=2 input functions ; 1 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 5 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 4 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 20 / 360 ( 6 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.3% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 48 ; +; Average fan-out ; 0.75 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 5 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 5 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 4 ; 0 ; +; -- <=2 input functions ; 1 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 5 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 4 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 20 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 54 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 10 ; 0 ; +; -- Output Ports ; 10 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; C10 ; 7 ; 51 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[2] ; D12 ; 7 ; 51 ; 54 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[3] ; C12 ; 7 ; 54 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[4] ; A12 ; 7 ; 54 ; 54 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[5] ; B12 ; 7 ; 49 ; 54 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[6] ; A13 ; 7 ; 54 ; 54 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[7] ; A14 ; 7 ; 58 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[8] ; B14 ; 7 ; 56 ; 54 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[9] ; F15 ; 7 ; 69 ; 54 ; 0 ; 5 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; LEDR[0] ; A8 ; 7 ; 46 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[1] ; A9 ; 7 ; 46 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[2] ; A10 ; 7 ; 51 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[3] ; B10 ; 7 ; 46 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[4] ; D13 ; 7 ; 56 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[5] ; C13 ; 7 ; 58 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[6] ; E14 ; 7 ; 66 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[7] ; D14 ; 7 ; 56 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[8] ; A11 ; 7 ; 51 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[9] ; B11 ; 7 ; 49 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 0 / 60 ( 0 % ) ; 2.5V ; -- ; +; 7 ; 20 / 52 ( 38 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 449 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 439 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 437 ; 7 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A12 ; 435 ; 7 ; SW[4] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 433 ; 7 ; SW[6] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 425 ; 7 ; SW[7] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 443 ; 7 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B12 ; 441 ; 7 ; SW[5] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; SW[8] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; SW[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C13 ; 426 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C14 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 391 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D13 ; 431 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D14 ; 428 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E15 ; 390 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 388 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; SW[9] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; SW[8] ; Incomplete set of assignments ; +; LEDR[0] ; Incomplete set of assignments ; +; LEDR[1] ; Incomplete set of assignments ; +; LEDR[2] ; Incomplete set of assignments ; +; LEDR[3] ; Incomplete set of assignments ; +; LEDR[4] ; Incomplete set of assignments ; +; LEDR[5] ; Incomplete set of assignments ; +; LEDR[6] ; Incomplete set of assignments ; +; LEDR[7] ; Incomplete set of assignments ; +; LEDR[8] ; Incomplete set of assignments ; +; LEDR[9] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[9] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |Lab1Part2 ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 20 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; |Lab1Part2 ; Lab1Part2 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; SW[8] ; Input ; -- ; -- ; -- ; -- ; -- ; +; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[3] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-----------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------+-------------------+---------+ +; SW[8] ; ; ; +; SW[4] ; ; ; +; - M~0 ; 0 ; 6 ; +; SW[0] ; ; ; +; - M~0 ; 0 ; 6 ; +; SW[9] ; ; ; +; - M~0 ; 0 ; 6 ; +; - M~1 ; 0 ; 6 ; +; - M~2 ; 0 ; 6 ; +; - M~3 ; 0 ; 6 ; +; - LEDR[9]~output ; 0 ; 6 ; +; SW[5] ; ; ; +; - M~1 ; 0 ; 6 ; +; SW[1] ; ; ; +; - M~1 ; 0 ; 6 ; +; SW[6] ; ; ; +; - M~2 ; 0 ; 6 ; +; SW[2] ; ; ; +; - M~2 ; 0 ; 6 ; +; SW[7] ; ; ; +; - M~3 ; 1 ; 6 ; +; SW[3] ; ; ; +; - M~3 ; 0 ; 6 ; ++-----------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 20 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 1 / 5,382 ( < 1 % ) ; +; C4 interconnects ; 19 / 106,704 ( < 1 % ) ; +; Direct links ; 1 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 49,760 ( 0 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 1 / 5,406 ( < 1 % ) ; +; R4 interconnects ; 7 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 1.25) ; Number of LABs (Total = 4) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 3 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 1.25) ; Number of LABs (Total = 4) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 3 ; +; 2 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 1.25) ; Number of LABs (Total = 4) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 3 ; +; 2 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 2.75) ; Number of LABs (Total = 4) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 2 ; +; 4 ; 0 ; +; 5 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 20 ; 0 ; 20 ; 0 ; 0 ; 20 ; 20 ; 0 ; 20 ; 20 ; 0 ; 10 ; 0 ; 0 ; 10 ; 0 ; 10 ; 10 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 20 ; 0 ; 20 ; 20 ; 0 ; 0 ; 20 ; 0 ; 0 ; 20 ; 10 ; 20 ; 20 ; 10 ; 20 ; 10 ; 10 ; 20 ; 20 ; 20 ; 10 ; 20 ; 20 ; 20 ; 20 ; 20 ; 0 ; 20 ; 20 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (119006): Selected device 10M50DAF484C7G for design "Lab1Part2" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 10M08DAF484I7G is compatible + Info (176445): Device 10M16DAF484C7G is compatible + Info (176445): Device 10M16DAF484I7G is compatible + Info (176445): Device 10M25DAF484C7G is compatible + Info (176445): Device 10M25DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7P is compatible + Info (176445): Device 10M40DAF484C7G is compatible + Info (176445): Device 10M40DAF484I7G is compatible +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'Lab1Part2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 5904 megabytes + Info: Processing ended: Thu Mar 11 19:58:39 2021 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:10 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg. + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg new file mode 100644 index 0000000..558ea95 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.summary b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.summary new file mode 100644 index 0000000..2cbb5fd --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Thu Mar 11 19:58:38 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : Lab1Part2 +Top-level Entity Name : Lab1Part2 +Family : MAX 10 +Device : 10M50DAF484C7G +Timing Models : Final +Total logic elements : 5 / 49,760 ( < 1 % ) + Total combinational functions : 5 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 20 / 360 ( 6 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.flow.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.flow.rpt new file mode 100644 index 0000000..801ad1a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.flow.rpt @@ -0,0 +1,128 @@ +Flow report for Lab1Part2 +Thu Mar 11 19:58:47 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Mar 11 19:58:43 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Lab1Part2 ; +; Top-level Entity Name ; Lab1Part2 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 5 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 5 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 20 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/11/2021 19:58:22 ; +; Main task ; Compilation ; +; Revision Name ; Lab1Part2 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 189559947077153.161551430207988 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4781 MB ; 00:00:23 ; +; Fitter ; 00:00:06 ; 1.0 ; 5904 MB ; 00:00:09 ; +; Assembler ; 00:00:03 ; 1.0 ; 4684 MB ; 00:00:03 ; +; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4865 MB ; 00:00:02 ; +; Total ; 00:00:21 ; -- ; -- ; 00:00:37 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off Lab1Part2 -c Lab1Part2 +quartus_fit --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2 +quartus_asm --read_settings_files=off --write_settings_files=off Lab1Part2 -c Lab1Part2 +quartus_sta Lab1Part2 -c Lab1Part2 + + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.jdi b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.jdi new file mode 100644 index 0000000..6ae5de1 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.map.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.map.rpt new file mode 100644 index 0000000..c27c81f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.map.rpt @@ -0,0 +1,318 @@ +Analysis & Synthesis report for Lab1Part2 +Thu Mar 11 19:58:31 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Mar 11 19:58:31 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Lab1Part2 ; +; Top-level Entity Name ; Lab1Part2 ; +; Family ; MAX 10 ; +; Total logic elements ; 4 ; +; Total combinational functions ; 4 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 20 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C7G ; ; +; Top-level entity name ; Lab1Part2 ; Lab1Part2 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+------------------------------------------------------------------+---------+ +; Lab1Part2.v ; yes ; User Verilog HDL File ; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v ; ; ++----------------------------------+-----------------+------------------------+------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimated Total logic elements ; 4 ; +; ; ; +; Total combinational functions ; 4 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 4 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 4 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 20 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; SW[9]~input ; +; Maximum fan-out ; 5 ; +; Total fan-out ; 37 ; +; Average fan-out ; 0.84 ; ++---------------------------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |Lab1Part2 ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; |Lab1Part2 ; Lab1Part2 ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 20 ; +; cycloneiii_lcell_comb ; 6 ; +; normal ; 6 ; +; 0 data inputs ; 2 ; +; 3 data inputs ; 4 ; +; ; ; +; Max LUT depth ; 1.00 ; +; Average LUT depth ; 0.87 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Mar 11 19:58:22 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1Part2 -c Lab1Part2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Critical Warning (10191): Verilog HDL Compiler Directive warning at Lab1Part2.v(15): text macro "b0" is undefined File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v Line: 15 +Info (12021): Found 1 design units, including 1 entities, in source file lab1part2.v + Info (12023): Found entity 1: Lab1Part2 File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v Line: 1 +Info (12127): Elaborating entity "Lab1Part2" for the top level hierarchy +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "LEDR[4]" is stuck at VCC File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v Line: 3 + Warning (13410): Pin "LEDR[5]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v Line: 3 + Warning (13410): Pin "LEDR[6]" is stuck at VCC File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v Line: 3 + Warning (13410): Pin "LEDR[7]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v Line: 3 + Warning (13410): Pin "LEDR[8]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v Line: 3 +Info (286030): Timing-Driven Synthesis is running +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 1 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "SW[8]" File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v Line: 2 +Info (21057): Implemented 24 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 10 input pins + Info (21059): Implemented 10 output pins + Info (21061): Implemented 4 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings + Info: Peak virtual memory: 4781 megabytes + Info: Processing ended: Thu Mar 11 19:58:31 2021 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:23 + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.map.summary b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.map.summary new file mode 100644 index 0000000..bf3c329 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Thu Mar 11 19:58:31 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : Lab1Part2 +Top-level Entity Name : Lab1Part2 +Family : MAX 10 +Total logic elements : 4 + Total combinational functions : 4 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 20 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.pin b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.pin new file mode 100644 index 0000000..5b38c2f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2016 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel MegaCore Function License Agreement, or other + -- applicable license agreement, including, without limitation, + -- that your use is for the sole purpose of programming logic + -- devices manufactured by Intel and sold by Intel or its + -- authorized distributors. Please refer to the applicable + -- agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +CHIP "Lab1Part2" ASSIGNED TO AN: 10M50DAF484C7G + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +LEDR[0] : A8 : output : 2.5 V : : 7 : Y +LEDR[1] : A9 : output : 2.5 V : : 7 : Y +LEDR[2] : A10 : output : 2.5 V : : 7 : Y +LEDR[8] : A11 : output : 2.5 V : : 7 : Y +SW[4] : A12 : input : 2.5 V : : 7 : Y +SW[6] : A13 : input : 2.5 V : : 7 : Y +SW[7] : A14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +LEDR[3] : B10 : output : 2.5 V : : 7 : Y +LEDR[9] : B11 : output : 2.5 V : : 7 : Y +SW[5] : B12 : input : 2.5 V : : 7 : Y +GND : B13 : gnd : : : : +SW[8] : B14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[0] : C10 : input : 2.5 V : : 7 : Y +SW[1] : C11 : input : 2.5 V : : 7 : Y +SW[3] : C12 : input : 2.5 V : : 7 : Y +LEDR[5] : C13 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +SW[2] : D12 : input : 2.5 V : : 7 : Y +LEDR[4] : D13 : output : 2.5 V : : 7 : Y +LEDR[7] : D14 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +LEDR[6] : E14 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +SW[9] : F15 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.pof b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.pof new file mode 100644 index 0000000..73d7d3a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.pof differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sld b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sof b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sof new file mode 100644 index 0000000..f2d8f02 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sof differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sta.rpt b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sta.rpt new file mode 100644 index 0000000..4d8d27c --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sta.rpt @@ -0,0 +1,516 @@ +TimeQuest Timing Analyzer report for Lab1Part2 +Thu Mar 11 19:58:47 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; Lab1Part2 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.03 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.4% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 9 ; 9 ; +; Unconstrained Input Port Paths ; 13 ; 13 ; +; Unconstrained Output Ports ; 5 ; 5 ; +; Unconstrained Output Port Paths ; 13 ; 13 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Mar 11 19:58:44 2021 +Info: Command: quartus_sta Lab1Part2 -c Lab1Part2 +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'Lab1Part2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 30 warnings + Info: Peak virtual memory: 4865 megabytes + Info: Processing ended: Thu Mar 11 19:58:47 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sta.summary b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/output_files/Lab1Part2.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.do b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.do new file mode 100644 index 0000000..afb7a31 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vlog -work work Lab1Part2.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst +vcd file -direction Lab1Part2.msim.vcd +vcd add -internal Lab1Part2_vlg_vec_tst/* +vcd add -internal Lab1Part2_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.msim.vcd b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.msim.vcd new file mode 100644 index 0000000..e207964 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.msim.vcd @@ -0,0 +1,222 @@ +$comment + File created using the following command: + vcd file Lab1Part2.msim.vcd -direction +$end +$date + Thu Mar 11 19:52:33 2021 +$end +$version + ModelSim Version 10.5b +$end +$timescale + 1ps +$end + +$scope module Lab1Part2_vlg_vec_tst $end +$var reg 10 ! SW [9:0] $end +$var wire 1 " LEDR [9] $end +$var wire 1 # LEDR [8] $end +$var wire 1 $ LEDR [7] $end +$var wire 1 % LEDR [6] $end +$var wire 1 & LEDR [5] $end +$var wire 1 ' LEDR [4] $end +$var wire 1 ( LEDR [3] $end +$var wire 1 ) LEDR [2] $end +$var wire 1 * LEDR [1] $end +$var wire 1 + LEDR [0] $end + +$scope module i1 $end +$var wire 1 , gnd $end +$var wire 1 - vcc $end +$var wire 1 . unknown $end +$var tri1 1 / devclrn $end +$var tri1 1 0 devpor $end +$var tri1 1 1 devoe $end +$var wire 1 2 SW[8]~input_o $end +$var wire 1 3 ~QUARTUS_CREATED_GND~I_combout $end +$var wire 1 4 ~QUARTUS_CREATED_UNVM~~busy $end +$var wire 1 5 ~QUARTUS_CREATED_ADC1~~eoc $end +$var wire 1 6 ~QUARTUS_CREATED_ADC2~~eoc $end +$var wire 1 7 LEDR[0]~output_o $end +$var wire 1 8 LEDR[1]~output_o $end +$var wire 1 9 LEDR[2]~output_o $end +$var wire 1 : LEDR[3]~output_o $end +$var wire 1 ; LEDR[4]~output_o $end +$var wire 1 < LEDR[5]~output_o $end +$var wire 1 = LEDR[6]~output_o $end +$var wire 1 > LEDR[7]~output_o $end +$var wire 1 ? LEDR[8]~output_o $end +$var wire 1 @ LEDR[9]~output_o $end +$var wire 1 A SW[4]~input_o $end +$var wire 1 B SW[0]~input_o $end +$var wire 1 C SW[9]~input_o $end +$var wire 1 D M~0_combout $end +$var wire 1 E SW[5]~input_o $end +$var wire 1 F SW[1]~input_o $end +$var wire 1 G M~1_combout $end +$var wire 1 H SW[6]~input_o $end +$var wire 1 I SW[2]~input_o $end +$var wire 1 J M~2_combout $end +$var wire 1 K SW[3]~input_o $end +$var wire 1 L SW[7]~input_o $end +$var wire 1 M M~3_combout $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 ! +0+ +0* +0) +0( +1' +0& +1% +0$ +0# +0" +0, +1- +x. +1/ +10 +11 +02 +03 +z4 +z5 +z6 +07 +08 +09 +0: +1; +0< +1= +0> +0? +0@ +0A +0B +0C +0D +0E +0F +0G +0H +0I +0J +0K +0L +0M +$end +#10000 +b1000000000 ! +1C +1@ +1" +#30000 +b1100000000 ! +12 +#120000 +b1000000000 ! +02 +#130000 +b1010000000 ! +1L +1M +1: +1( +#250000 +b1000000000 ! +0L +0M +0: +0( +#260000 +b1001000000 ! +1H +1J +19 +1) +#330000 +b1001100000 ! +b1000100000 ! +0H +1E +0J +1G +18 +09 +0) +1* +#450000 +b1000000000 ! +0E +0G +08 +0* +#460000 +b1000010000 ! +1A +1D +17 +1+ +#510000 +b1000011000 ! +b1000001000 ! +0A +1K +0D +07 +0+ +#570000 +b1000 ! +0C +0@ +0" +1M +1: +1( +#580000 +b1100 ! +b100 ! +0K +1I +0M +1J +19 +0: +0( +1) +#640000 +b110 ! +b10 ! +0I +1F +0J +1G +18 +09 +0) +1* +#690000 +b0 ! +0F +0G +08 +0* +#700000 +b1 ! +1B +1D +17 +1+ +#760000 +b0 ! +0B +0D +07 +0+ +#1000000 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.sft b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.sft new file mode 100644 index 0000000..f324fea --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.vo b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.vo new file mode 100644 index 0000000..6f82d05 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.vo @@ -0,0 +1,589 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" + +// DATE "03/11/2021 19:52:32" + +// +// Device: Altera 10M50DAF484C7G Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module Lab1Part2 ( + SW, + LEDR); +input [9:0] SW; +output [9:0] LEDR; + +// Design Ports Information +// SW[8] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[0] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[2] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[3] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[4] => Location: PIN_D13, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[5] => Location: PIN_C13, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[6] => Location: PIN_E14, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[7] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[8] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[9] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// SW[4] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// SW[0] => Location: PIN_C10, I/O Standard: 2.5 V, Current Strength: Default +// SW[9] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// SW[5] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// SW[1] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// SW[6] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// SW[2] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default +// SW[7] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// SW[3] => Location: PIN_C12, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \SW[8]~input_o ; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \~QUARTUS_CREATED_UNVM~~busy ; +wire \~QUARTUS_CREATED_ADC1~~eoc ; +wire \~QUARTUS_CREATED_ADC2~~eoc ; +wire \LEDR[0]~output_o ; +wire \LEDR[1]~output_o ; +wire \LEDR[2]~output_o ; +wire \LEDR[3]~output_o ; +wire \LEDR[4]~output_o ; +wire \LEDR[5]~output_o ; +wire \LEDR[6]~output_o ; +wire \LEDR[7]~output_o ; +wire \LEDR[8]~output_o ; +wire \LEDR[9]~output_o ; +wire \SW[4]~input_o ; +wire \SW[0]~input_o ; +wire \SW[9]~input_o ; +wire \M~0_combout ; +wire \SW[5]~input_o ; +wire \SW[1]~input_o ; +wire \M~1_combout ; +wire \SW[6]~input_o ; +wire \SW[2]~input_o ; +wire \M~2_combout ; +wire \SW[3]~input_o ; +wire \SW[7]~input_o ; +wire \M~3_combout ; + + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: LCCOMB_X44_Y41_N8 +fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): +// \~QUARTUS_CREATED_GND~I_combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .cout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000; +defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X46_Y54_N2 +fiftyfivenm_io_obuf \LEDR[0]~output ( + .i(\M~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[0]~output .bus_hold = "false"; +defparam \LEDR[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X46_Y54_N23 +fiftyfivenm_io_obuf \LEDR[1]~output ( + .i(\M~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[1]~output .bus_hold = "false"; +defparam \LEDR[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y54_N16 +fiftyfivenm_io_obuf \LEDR[2]~output ( + .i(\M~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[2]~output .bus_hold = "false"; +defparam \LEDR[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X46_Y54_N9 +fiftyfivenm_io_obuf \LEDR[3]~output ( + .i(\M~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[3]~output .bus_hold = "false"; +defparam \LEDR[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X56_Y54_N30 +fiftyfivenm_io_obuf \LEDR[4]~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[4]~output .bus_hold = "false"; +defparam \LEDR[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X58_Y54_N23 +fiftyfivenm_io_obuf \LEDR[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[5]~output .bus_hold = "false"; +defparam \LEDR[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X66_Y54_N23 +fiftyfivenm_io_obuf \LEDR[6]~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[6]~output .bus_hold = "false"; +defparam \LEDR[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X56_Y54_N9 +fiftyfivenm_io_obuf \LEDR[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[7]~output .bus_hold = "false"; +defparam \LEDR[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y54_N9 +fiftyfivenm_io_obuf \LEDR[8]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[8]~output .bus_hold = "false"; +defparam \LEDR[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X49_Y54_N9 +fiftyfivenm_io_obuf \LEDR[9]~output ( + .i(\SW[9]~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[9]~output .bus_hold = "false"; +defparam \LEDR[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X54_Y54_N22 +fiftyfivenm_io_ibuf \SW[4]~input ( + .i(SW[4]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[4]~input_o )); +// synopsys translate_off +defparam \SW[4]~input .bus_hold = "false"; +defparam \SW[4]~input .listen_to_nsleep_signal = "false"; +defparam \SW[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N29 +fiftyfivenm_io_ibuf \SW[0]~input ( + .i(SW[0]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[0]~input_o )); +// synopsys translate_off +defparam \SW[0]~input .bus_hold = "false"; +defparam \SW[0]~input .listen_to_nsleep_signal = "false"; +defparam \SW[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X69_Y54_N1 +fiftyfivenm_io_ibuf \SW[9]~input ( + .i(SW[9]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[9]~input_o )); +// synopsys translate_off +defparam \SW[9]~input .bus_hold = "false"; +defparam \SW[9]~input .listen_to_nsleep_signal = "false"; +defparam \SW[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N24 +fiftyfivenm_lcell_comb \M~0 ( +// Equation(s): +// \M~0_combout = (\SW[9]~input_o & (\SW[4]~input_o )) # (!\SW[9]~input_o & ((\SW[0]~input_o ))) + + .dataa(\SW[4]~input_o ), + .datab(\SW[0]~input_o ), + .datac(gnd), + .datad(\SW[9]~input_o ), + .cin(gnd), + .combout(\M~0_combout ), + .cout()); +// synopsys translate_off +defparam \M~0 .lut_mask = 16'hAACC; +defparam \M~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X49_Y54_N1 +fiftyfivenm_io_ibuf \SW[5]~input ( + .i(SW[5]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[5]~input_o )); +// synopsys translate_off +defparam \SW[5]~input .bus_hold = "false"; +defparam \SW[5]~input .listen_to_nsleep_signal = "false"; +defparam \SW[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N22 +fiftyfivenm_io_ibuf \SW[1]~input ( + .i(SW[1]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[1]~input_o )); +// synopsys translate_off +defparam \SW[1]~input .bus_hold = "false"; +defparam \SW[1]~input .listen_to_nsleep_signal = "false"; +defparam \SW[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X50_Y53_N16 +fiftyfivenm_lcell_comb \M~1 ( +// Equation(s): +// \M~1_combout = (\SW[9]~input_o & (\SW[5]~input_o )) # (!\SW[9]~input_o & ((\SW[1]~input_o ))) + + .dataa(\SW[5]~input_o ), + .datab(gnd), + .datac(\SW[9]~input_o ), + .datad(\SW[1]~input_o ), + .cin(gnd), + .combout(\M~1_combout ), + .cout()); +// synopsys translate_off +defparam \M~1 .lut_mask = 16'hAFA0; +defparam \M~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X54_Y54_N15 +fiftyfivenm_io_ibuf \SW[6]~input ( + .i(SW[6]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[6]~input_o )); +// synopsys translate_off +defparam \SW[6]~input .bus_hold = "false"; +defparam \SW[6]~input .listen_to_nsleep_signal = "false"; +defparam \SW[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N1 +fiftyfivenm_io_ibuf \SW[2]~input ( + .i(SW[2]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[2]~input_o )); +// synopsys translate_off +defparam \SW[2]~input .bus_hold = "false"; +defparam \SW[2]~input .listen_to_nsleep_signal = "false"; +defparam \SW[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N26 +fiftyfivenm_lcell_comb \M~2 ( +// Equation(s): +// \M~2_combout = (\SW[9]~input_o & (\SW[6]~input_o )) # (!\SW[9]~input_o & ((\SW[2]~input_o ))) + + .dataa(gnd), + .datab(\SW[6]~input_o ), + .datac(\SW[2]~input_o ), + .datad(\SW[9]~input_o ), + .cin(gnd), + .combout(\M~2_combout ), + .cout()); +// synopsys translate_off +defparam \M~2 .lut_mask = 16'hCCF0; +defparam \M~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X54_Y54_N29 +fiftyfivenm_io_ibuf \SW[3]~input ( + .i(SW[3]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[3]~input_o )); +// synopsys translate_off +defparam \SW[3]~input .bus_hold = "false"; +defparam \SW[3]~input .listen_to_nsleep_signal = "false"; +defparam \SW[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X58_Y54_N29 +fiftyfivenm_io_ibuf \SW[7]~input ( + .i(SW[7]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[7]~input_o )); +// synopsys translate_off +defparam \SW[7]~input .bus_hold = "false"; +defparam \SW[7]~input .listen_to_nsleep_signal = "false"; +defparam \SW[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X54_Y53_N8 +fiftyfivenm_lcell_comb \M~3 ( +// Equation(s): +// \M~3_combout = (\SW[9]~input_o & ((\SW[7]~input_o ))) # (!\SW[9]~input_o & (\SW[3]~input_o )) + + .dataa(gnd), + .datab(\SW[3]~input_o ), + .datac(\SW[9]~input_o ), + .datad(\SW[7]~input_o ), + .cin(gnd), + .combout(\M~3_combout ), + .cout()); +// synopsys translate_off +defparam \M~3 .lut_mask = 16'hFC0C; +defparam \M~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X56_Y54_N1 +fiftyfivenm_io_ibuf \SW[8]~input ( + .i(SW[8]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[8]~input_o )); +// synopsys translate_off +defparam \SW[8]~input .bus_hold = "false"; +defparam \SW[8]~input .listen_to_nsleep_signal = "false"; +defparam \SW[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: UNVM_X0_Y40_N40 +fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ ( + .arclk(vcc), + .arshft(vcc), + .drclk(vcc), + .drshft(vcc), + .drdin(vcc), + .nprogram(vcc), + .nerase(vcc), + .nosc_ena(\~QUARTUS_CREATED_GND~I_combout ), + .par_en(vcc), + .xe_ye(\~QUARTUS_CREATED_GND~I_combout ), + .se(\~QUARTUS_CREATED_GND~I_combout ), + .ardin(23'b11111111111111111111111), + .busy(\~QUARTUS_CREATED_UNVM~~busy ), + .osc(), + .bgpbusy(), + .sp_pass(), + .se_pass(), + .drdout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm"; +defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true"; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y52_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC1~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1; +defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y51_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC2~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2; +defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0; +// synopsys translate_on + +assign LEDR[0] = \LEDR[0]~output_o ; + +assign LEDR[1] = \LEDR[1]~output_o ; + +assign LEDR[2] = \LEDR[2]~output_o ; + +assign LEDR[3] = \LEDR[3]~output_o ; + +assign LEDR[4] = \LEDR[4]~output_o ; + +assign LEDR[5] = \LEDR[5]~output_o ; + +assign LEDR[6] = \LEDR[6]~output_o ; + +assign LEDR[7] = \LEDR[7]~output_o ; + +assign LEDR[8] = \LEDR[8]~output_o ; + +assign LEDR[9] = \LEDR[9]~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_TMS~~padout ; +wire \~ALTERA_TCK~~padout ; +wire \~ALTERA_TDI~~padout ; +wire \~ALTERA_CONFIG_SEL~~padout ; +wire \~ALTERA_nCONFIG~~padout ; +wire \~ALTERA_nSTATUS~~padout ; +wire \~ALTERA_CONF_DONE~~padout ; +wire \~ALTERA_TMS~~ibuf_o ; +wire \~ALTERA_TCK~~ibuf_o ; +wire \~ALTERA_TDI~~ibuf_o ; +wire \~ALTERA_CONFIG_SEL~~ibuf_o ; +wire \~ALTERA_nCONFIG~~ibuf_o ; +wire \~ALTERA_nSTATUS~~ibuf_o ; +wire \~ALTERA_CONF_DONE~~ibuf_o ; + + +endmodule diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_20210311193454.sim.vwf b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_20210311193454.sim.vwf new file mode 100644 index 0000000..a336b23 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_20210311193454.sim.vwf @@ -0,0 +1,771 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 920.0; + } + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 490.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 510.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 420.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 590.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 350.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 660.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 290.0; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 920.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 850.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 780.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 690.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 320.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 620.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 390.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 490.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 510.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 420.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 590.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 350.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 660.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 290.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_20210311195234.sim.vwf b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_20210311195234.sim.vwf new file mode 100644 index 0000000..1992dd8 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_20210311195234.sim.vwf @@ -0,0 +1,779 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 560.0; + LEVEL 0 FOR 430.0; + } + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 130.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 320.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 420.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 250.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 360.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 330.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 190.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 310.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 460.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 190.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 240.0; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 560.0; + LEVEL 0 FOR 430.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 880.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 130.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 750.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 670.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 330.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 550.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 460.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 490.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 510.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 420.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 580.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 360.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 640.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 310.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 700.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 240.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_modelsim.xrf b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_modelsim.xrf new file mode 100644 index 0000000..f279693 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_modelsim.xrf @@ -0,0 +1,43 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v +source_file = 1, Lab1Part2.vwf +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf +source_file = 1, output_files/Waveform.vwf +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/db/Lab1Part2.cbx.xml +design_name = Lab1Part2 +instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, Lab1Part2, 1 +instance = comp, \LEDR[0]~output , LEDR[0]~output, Lab1Part2, 1 +instance = comp, \LEDR[1]~output , LEDR[1]~output, Lab1Part2, 1 +instance = comp, \LEDR[2]~output , LEDR[2]~output, Lab1Part2, 1 +instance = comp, \LEDR[3]~output , LEDR[3]~output, Lab1Part2, 1 +instance = comp, \LEDR[4]~output , LEDR[4]~output, Lab1Part2, 1 +instance = comp, \LEDR[5]~output , LEDR[5]~output, Lab1Part2, 1 +instance = comp, \LEDR[6]~output , LEDR[6]~output, Lab1Part2, 1 +instance = comp, \LEDR[7]~output , LEDR[7]~output, Lab1Part2, 1 +instance = comp, \LEDR[8]~output , LEDR[8]~output, Lab1Part2, 1 +instance = comp, \LEDR[9]~output , LEDR[9]~output, Lab1Part2, 1 +instance = comp, \SW[4]~input , SW[4]~input, Lab1Part2, 1 +instance = comp, \SW[0]~input , SW[0]~input, Lab1Part2, 1 +instance = comp, \SW[9]~input , SW[9]~input, Lab1Part2, 1 +instance = comp, \M~0 , M~0, Lab1Part2, 1 +instance = comp, \SW[5]~input , SW[5]~input, Lab1Part2, 1 +instance = comp, \SW[1]~input , SW[1]~input, Lab1Part2, 1 +instance = comp, \M~1 , M~1, Lab1Part2, 1 +instance = comp, \SW[6]~input , SW[6]~input, Lab1Part2, 1 +instance = comp, \SW[2]~input , SW[2]~input, Lab1Part2, 1 +instance = comp, \M~2 , M~2, Lab1Part2, 1 +instance = comp, \SW[3]~input , SW[3]~input, Lab1Part2, 1 +instance = comp, \SW[7]~input , SW[7]~input, Lab1Part2, 1 +instance = comp, \M~3 , M~3, Lab1Part2, 1 +instance = comp, \SW[8]~input , SW[8]~input, Lab1Part2, 1 +instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, Lab1Part2, 1 +instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, Lab1Part2, 1 +instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, Lab1Part2, 1 +design_name = hard_block +instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt new file mode 100644 index 0000000..4fe6f88 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt @@ -0,0 +1,118 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "03/11/2021 19:52:31" + +// Verilog Test Bench (with test vectors) for design : Lab1Part2 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module Lab1Part2_vlg_vec_tst(); +// constants +// general purpose registers +reg [9:0] SW; +// wires +wire [9:0] LEDR; + +// assign statements (if any) +Lab1Part2 i1 ( +// port map - connection between master ports and signals/registers + .LEDR(LEDR), + .SW(SW) +); +initial +begin +#1000000 $finish; +end +// SW[ 9 ] +initial +begin + SW[9] = 1'b0; + SW[9] = #10000 1'b1; + SW[9] = #560000 1'b0; +end +// SW[ 8 ] +initial +begin + SW[8] = 1'b0; + SW[8] = #30000 1'b1; + SW[8] = #90000 1'b0; +end +// SW[ 7 ] +initial +begin + SW[7] = 1'b0; + SW[7] = #130000 1'b1; + SW[7] = #120000 1'b0; +end +// SW[ 6 ] +initial +begin + SW[6] = 1'b0; + SW[6] = #260000 1'b1; + SW[6] = #70000 1'b0; +end +// SW[ 5 ] +initial +begin + SW[5] = 1'b0; + SW[5] = #330000 1'b1; + SW[5] = #120000 1'b0; +end +// SW[ 4 ] +initial +begin + SW[4] = 1'b0; + SW[4] = #460000 1'b1; + SW[4] = #50000 1'b0; +end +// SW[ 3 ] +initial +begin + SW[3] = 1'b0; + SW[3] = #510000 1'b1; + SW[3] = #70000 1'b0; +end +// SW[ 2 ] +initial +begin + SW[2] = 1'b0; + SW[2] = #580000 1'b1; + SW[2] = #60000 1'b0; +end +// SW[ 1 ] +initial +begin + SW[1] = 1'b0; + SW[1] = #640000 1'b1; + SW[1] = #50000 1'b0; +end +// SW[ 0 ] +initial +begin + SW[0] = 1'b0; + SW[0] = #700000 1'b1; + SW[0] = #60000 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/transcript b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/transcript new file mode 100644 index 0000000..ca98828 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/transcript @@ -0,0 +1,37 @@ +# do Lab1Part2.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 19:52:33 on Mar 11,2021 +# vlog -work work Lab1Part2.vo +# -- Compiling module Lab1Part2 +# -- Compiling module hard_block +# +# Top level modules: +# Lab1Part2 +# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 19:52:33 on Mar 11,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module Lab1Part2_vlg_vec_tst +# +# Top level modules: +# Lab1Part2_vlg_vec_tst +# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst +# Start time: 19:52:33 on Mar 11,2021 +# Loading work.Lab1Part2_vlg_vec_tst +# Loading work.Lab1Part2 +# Loading work.hard_block +# ** Warning: (vsim-3017) Lab1Part2.vo(478): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) Lab1Part2.vo(478): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) Lab1Part2.vo(501): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) Lab1Part2.vo(501): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform.vwf.vt(45) +# Time: 1 us Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst +# End time: 19:52:34 on Mar 11,2021, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 4 diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/vwf_sim_transcript b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..1085c54 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,193 @@ +Determining the location of the ModelSim executable... + +Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Part2 -c Lab1Part2 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt" + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Mar 11 19:52:31 2021 +Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Part2 -c Lab1Part2 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt" +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignm +ent for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. + +Completed successfully. + +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2 + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Mar 11 19:52:32 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANT +S_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file Lab1Part2.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 26 warnings + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Mar 11 19:52:32 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + +Completed successfully. + +**** Generating the ModelSim .do script **** + +C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do Lab1Part2.do + +Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl + +# 10.5b + + +# do Lab1Part2.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 19:52:33 on Mar 11,2021 +# vlog -work work Lab1Part2.vo +# -- Compiling module Lab1Part2 +# -- Compiling module hard_block +# +# Top level modules: +# Lab1Part2 + +# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 19:52:33 on Mar 11,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module Lab1Part2_vlg_vec_tst +# +# Top level modules: +# Lab1Part2_vlg_vec_tst +# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst +# Start time: 19:52:33 on Mar 11,2021 +# Loading work.Lab1Part2_vlg_vec_tst +# Loading work.Lab1Part2 +# Loading work.hard_block +# ** Warning: (vsim-3017) Lab1Part2.vo(478): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) Lab1Part2.vo(478): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) Lab1Part2.vo(501): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) Lab1Part2.vo(501): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform.vwf.vt(45) +# Time: 1 us Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst +# End time: 19:52:34 on Mar 11,2021, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 4 + +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf... + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.msim.vcd... + +Processing channel transitions... + +Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_20210311195234.sim.vwf + +Finished VCD to VWF conversion. + +Completed successfully. + +All completed. \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_info b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_info new file mode 100644 index 0000000..b8dfa3a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_info @@ -0,0 +1,75 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dC:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim +vhard_block +Z1 !s110 1615513953 +!i10b 1 +!s100 `I[^S=]:E30g]kVK?:Wed2 +IzC13RVdQF6GNhaHk4ie@U1 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +Z3 w1615513952 +Z4 8Lab1Part2.vo +Z5 FLab1Part2.vo +L0 545 +Z6 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z7 !s108 1615513953.000000 +Z8 !s107 Lab1Part2.vo| +Z9 !s90 -work|work|Lab1Part2.vo| +!i113 1 +Z10 o-work work +Z11 tCvgOpt 0 +vLab1Part2 +R1 +!i10b 1 +!s100 LAgT30]T[89E2af=Bh04DG3 +IP3I8MRaL:QICAAF?T[PoW3 +R2 +R0 +R3 +8Waveform.vwf.vt +FWaveform.vwf.vt +L0 30 +R6 +r1 +!s85 0 +31 +R7 +!s107 Waveform.vwf.vt| +!s90 -work|work|Waveform.vwf.vt| +!i113 1 +R10 +R11 +n@lab1@part2_vlg_vec_tst diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib.qdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib.qdb new file mode 100644 index 0000000..7cbbfd2 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib.qdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qdb b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qdb new file mode 100644 index 0000000..f48851b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qdb differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qpg b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qpg new file mode 100644 index 0000000..eea303e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qpg differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qtl b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qtl new file mode 100644 index 0000000..668682b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_lib1_0.qtl differ diff --git a/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_vmake b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/EE203/Noah Woodlee/LAB1/Part 4/atom_netlists/part4.qsf b/EE203/Noah Woodlee/LAB1/Part 4/atom_netlists/part4.qsf new file mode 100644 index 0000000..8597799 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/atom_netlists/part4.qsf @@ -0,0 +1,46 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part4 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:21:59 APRIL 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part4.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.(0).cnf.cdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.(0).cnf.cdb new file mode 100644 index 0000000..1d793fc Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.(0).cnf.hdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.(0).cnf.hdb new file mode 100644 index 0000000..21b4ca0 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm.qmsg b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm.qmsg new file mode 100644 index 0000000..2276a57 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1617927284535 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617927284535 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 19:14:44 2021 " "Processing started: Thu Apr 08 19:14:44 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617927284535 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1617927284535 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1617927284535 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1617927284815 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1617927286555 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1617927286705 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4682 " "Peak virtual memory: 4682 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617927287765 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 19:14:47 2021 " "Processing ended: Thu Apr 08 19:14:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617927287765 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617927287765 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617927287765 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1617927287765 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm.rdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm.rdb new file mode 100644 index 0000000..14a16f4 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm_labs.ddb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm_labs.ddb new file mode 100644 index 0000000..c8c85e7 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cbx.xml b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cbx.xml new file mode 100644 index 0000000..d130db6 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.bpm b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.bpm new file mode 100644 index 0000000..8ce3623 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.cdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.cdb new file mode 100644 index 0000000..7c521be Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.hdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.hdb new file mode 100644 index 0000000..c0f1c20 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.idb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.idb new file mode 100644 index 0000000..7ba9aa9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.idb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.logdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.logdb new file mode 100644 index 0000000..674383a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.logdb @@ -0,0 +1,61 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,19;0;19;0;0;19;19;0;19;19;0;17;0;0;2;0;17;2;0;0;0;17;0;0;0;0;0;19;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,0;19;0;19;19;0;0;19;0;0;19;2;19;19;17;19;2;17;19;19;19;2;19;19;19;19;19;0;19;19, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.rdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.rdb new file mode 100644 index 0000000..d55d30c Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp_merge.kpt b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp_merge.kpt new file mode 100644 index 0000000..c96e62f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.db_info b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.db_info new file mode 100644 index 0000000..6198f6c --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Version_Index = 419480576 +Creation_Time = Fri Apr 16 19:44:32 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.fit.qmsg b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.fit.qmsg new file mode 100644 index 0000000..35aae95 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.fit.qmsg @@ -0,0 +1,54 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1617927277435 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1617927277435 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part4 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part4\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1617927277445 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1617927277475 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1617927277475 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1617927277695 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1617927277705 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1617927277815 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 61 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617927277815 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 63 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617927277815 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 65 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617927277815 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 67 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617927277815 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 69 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617927277815 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 71 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617927277815 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 73 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617927277815 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 75 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617927277815 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1617927277815 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617927277815 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617927277815 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617927277815 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617927277815 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1617927277815 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1617927278275 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1617927278275 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1617927278275 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1617927278275 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1617927278285 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1617927278285 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1617927278285 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1617927278285 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1617927278285 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1617927278285 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1617927278285 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1617927278285 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1617927278285 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1617927278285 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1617927278285 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1617927278285 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1617927278285 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1617927278285 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617927278315 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617927278315 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617927278315 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617927278315 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617927278315 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617927278315 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617927278315 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617927278315 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1617927278315 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617927278315 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1617927278325 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1617927279445 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617927279495 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1617927279515 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1617927279735 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617927279735 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1617927280225 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X67_Y44 X78_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y44 to location X78_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y44 to location X78_Y54"} { { 12 { 0 ""} 67 44 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1617927281545 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1617927281545 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1617927281645 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1617927281645 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1617927281645 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617927281645 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1617927281875 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1617927281875 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1617927281875 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1617927282135 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1617927282135 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1617927282135 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1617927282395 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617927282785 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1617927283015 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1617927283065 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 17 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5905 " "Peak virtual memory: 5905 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617927283495 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 19:14:43 2021 " "Processing ended: Thu Apr 08 19:14:43 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617927283495 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617927283495 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617927283495 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1617927283495 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.hier_info b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.hier_info new file mode 100644 index 0000000..63f0dd4 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.hier_info @@ -0,0 +1,33 @@ +|part4 +SW[0] => HEX0.IN0 +SW[0] => HEX0.IN0 +SW[0] => LEDR[0].DATAIN +SW[0] => HEX0.IN0 +SW[0] => HEX0.IN0 +SW[0] => HEX0[0].DATAIN +SW[0] => HEX0[5].DATAIN +SW[1] => HEX0.IN1 +SW[1] => HEX0.IN1 +SW[1] => LEDR[1].DATAIN +SW[1] => HEX0[6].DATAIN +SW[1] => HEX0.IN1 +SW[1] => HEX0.IN1 +LEDR[0] << SW[0].DB_MAX_OUTPUT_PORT_TYPE +LEDR[1] << SW[1].DB_MAX_OUTPUT_PORT_TYPE +LEDR[2] << +LEDR[3] << +LEDR[4] << +LEDR[5] << +LEDR[6] << +LEDR[7] << +LEDR[8] << +LEDR[9] << +HEX0[6] << SW[1].DB_MAX_OUTPUT_PORT_TYPE +HEX0[5] << SW[0].DB_MAX_OUTPUT_PORT_TYPE +HEX0[4] << HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[3] << HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[2] << HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[1] << HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[0] << SW[0].DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.hif b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.hif new file mode 100644 index 0000000..a523cca Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.hif differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.html b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.html new file mode 100644 index 0000000..7d68592 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.rdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.rdb new file mode 100644 index 0000000..c179f4d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.txt b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.txt new file mode 100644 index 0000000..dbfe520 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.ammdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.ammdb new file mode 100644 index 0000000..a4afc79 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.bpm b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.bpm new file mode 100644 index 0000000..ce63aec Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.cdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.cdb new file mode 100644 index 0000000..5fefa26 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.hdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.hdb new file mode 100644 index 0000000..4f2d129 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.kpt b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.kpt new file mode 100644 index 0000000..e7f8f93 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.logdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.qmsg b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.qmsg new file mode 100644 index 0000000..17a878a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1617927266644 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617927266644 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 19:14:26 2021 " "Processing started: Thu Apr 08 19:14:26 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617927266644 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617927266644 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617927266644 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1617927267004 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1617927267004 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part4.v 1 1 " "Found 1 design units, including 1 entities, in source file part4.v" { { "Info" "ISGN_ENTITY_NAME" "1 part4 " "Found entity 1: part4" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617927275215 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617927275215 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part4 " "Elaborating entity \"part4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1617927275245 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[2\] GND " "Pin \"LEDR\[2\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617927275565 "|part4|LEDR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[3\] GND " "Pin \"LEDR\[3\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617927275565 "|part4|LEDR[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] GND " "Pin \"LEDR\[4\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617927275565 "|part4|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617927275565 "|part4|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617927275565 "|part4|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617927275565 "|part4|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617927275565 "|part4|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617927275565 "|part4|LEDR[9]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1617927275565 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1617927275615 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927275875 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1617927275875 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1617927276005 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617927276005 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1617927276055 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1617927276055 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Implemented 2 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1617927276055 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1617927276055 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4781 " "Peak virtual memory: 4781 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617927276085 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 19:14:36 2021 " "Processing ended: Thu Apr 08 19:14:36 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617927276085 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617927276085 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617927276085 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1617927276085 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.rdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.rdb new file mode 100644 index 0000000..5b6735f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.cdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.cdb new file mode 100644 index 0000000..f69cc01 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.hdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.hdb new file mode 100644 index 0000000..9cd052b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.logdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.pplq.rdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.pplq.rdb new file mode 100644 index 0000000..0d2f962 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.pplq.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.pre_map.hdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.pre_map.hdb new file mode 100644 index 0000000..1acc1ef Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.pre_map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.root_partition.map.reg_db.cdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..69e4ca9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.root_partition.map.reg_db.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.routing.rdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.routing.rdb new file mode 100644 index 0000000..316f15d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.routing.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv.hdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv.hdb new file mode 100644 index 0000000..9ae8acb Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv_sg.cdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv_sg.cdb new file mode 100644 index 0000000..47c511f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv_sg.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv_sg_swap.cdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv_sg_swap.cdb new file mode 100644 index 0000000..0be030c Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.rtlv_sg_swap.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sld_design_entry.sci b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sld_design_entry.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sld_design_entry.sci differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sld_design_entry_dsc.sci b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sld_design_entry_dsc.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.smart_action.txt b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.smart_action.txt new file mode 100644 index 0000000..437a63e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta.qmsg b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta.qmsg new file mode 100644 index 0000000..8f0920e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta.qmsg @@ -0,0 +1,52 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1617927288945 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617927288945 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 19:14:48 2021 " "Processing started: Thu Apr 08 19:14:48 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617927288945 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927288945 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta part4 -c part4 " "Command: quartus_sta part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927288945 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1617927289055 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617927289085 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289085 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289215 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289215 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289255 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289255 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289525 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289525 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289525 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289525 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289525 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289525 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1617927289525 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289535 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617927289535 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289535 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1617927289535 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289545 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289545 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289545 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289545 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289555 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617927289565 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289585 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289585 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289865 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289895 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289895 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289895 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289895 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289895 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289905 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289905 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289905 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289905 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927289905 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617927289915 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290035 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290035 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290035 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290035 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290035 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290045 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290045 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290055 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290055 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290955 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927290955 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 31 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4869 " "Peak virtual memory: 4869 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617927291015 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 19:14:51 2021 " "Processing ended: Thu Apr 08 19:14:51 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617927291015 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617927291015 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617927291015 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617927291015 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta.rdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta.rdb new file mode 100644 index 0000000..6ba88dc Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta_cmp.6_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..c2dd792 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tis_db_list.ddb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tis_db_list.ddb new file mode 100644 index 0000000..ecc3004 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..b90f513 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..6ebaacd Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..4600992 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tmw_info b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tmw_info new file mode 100644 index 0000000..ba6a589 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.tmw_info @@ -0,0 +1,3 @@ +start_full_compilation:s +start_assembler:s-start_full_compilation +start_timing_analyzer:s-start_full_compilation diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.vpr.ammdb b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.vpr.ammdb new file mode 100644 index 0000000..a2a8e83 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..db68b29 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.tt_0c_slow.hsd b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..a7cdb95 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.tt_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.tt_85c_slow.hsd b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..82f5601 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/db/part4.zippleback_io_sim_cache.tt_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/part4_partition_pins.json b/EE203/Noah Woodlee/LAB1/Part 4/db/part4_partition_pins.json new file mode 100644 index 0000000..f13b40a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/part4_partition_pins.json @@ -0,0 +1,53 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "LEDR[0]", + "strict" : false + }, + { + "name" : "LEDR[1]", + "strict" : false + }, + { + "name" : "HEX0[6]", + "strict" : false + }, + { + "name" : "HEX0[5]", + "strict" : false + }, + { + "name" : "HEX0[4]", + "strict" : false + }, + { + "name" : "HEX0[3]", + "strict" : false + }, + { + "name" : "HEX0[2]", + "strict" : false + }, + { + "name" : "HEX0[1]", + "strict" : false + }, + { + "name" : "HEX0[0]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 4/db/prev_cmp_part4.qmsg b/EE203/Noah Woodlee/LAB1/Part 4/db/prev_cmp_part4.qmsg new file mode 100644 index 0000000..5685451 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/db/prev_cmp_part4.qmsg @@ -0,0 +1,137 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1617926007721 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617926007721 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 18:53:27 2021 " "Processing started: Thu Apr 08 18:53:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617926007721 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617926007721 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617926007721 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1617926008071 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1617926008071 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part4.v 1 1 " "Found 1 design units, including 1 entities, in source file part4.v" { { "Info" "ISGN_ENTITY_NAME" "1 part4 " "Found entity 1: part4" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617926016271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617926016271 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part4 " "Elaborating entity \"part4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1617926016301 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[2\] GND " "Pin \"LEDR\[2\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[3\] GND " "Pin \"LEDR\[3\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] GND " "Pin \"LEDR\[4\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[9]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1617926016631 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1617926016681 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1617926016951 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1617926017071 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617926017071 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1617926017111 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1617926017111 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Implemented 2 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1617926017111 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1617926017111 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4779 " "Peak virtual memory: 4779 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617926017141 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 18:53:37 2021 " "Processing ended: Thu Apr 08 18:53:37 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617926017141 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617926017141 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617926017141 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1617926017141 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1617926018321 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617926018331 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 18:53:37 2021 " "Processing started: Thu Apr 08 18:53:37 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617926018331 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1617926018331 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off part4 -c part4 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1617926018331 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1617926018431 ""} +{ "Info" "0" "" "Project = part4" { } { } 0 0 "Project = part4" 0 0 "Fitter" 0 0 1617926018431 ""} +{ "Info" "0" "" "Revision = part4" { } { } 0 0 "Revision = part4" 0 0 "Fitter" 0 0 1617926018431 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1617926018531 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1617926018531 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part4 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part4\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1617926018531 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1617926018571 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1617926018571 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1617926018791 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1617926018801 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1617926018911 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 61 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 63 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 65 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 67 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 69 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 71 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 73 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 75 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1617926018911 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617926018911 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617926018911 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617926018911 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617926018911 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1617926018911 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 19 " "No exact pin location assignment(s) for 7 pins of 19 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1617926019151 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1617926019381 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1617926019381 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1617926019381 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1617926019381 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1617926019381 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1617926019381 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1617926019381 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1617926019381 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 2.5V 0 7 0 " "Number of I/O pins in group: 7 (unused VREF, 2.5V VCCIO, 0 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1617926019381 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1617926019381 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1617926019381 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 20 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 36 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 48 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 48 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 40 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 60 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 12 40 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 12 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 32 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1617926019391 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1617926019391 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1617926019411 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926019411 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1617926019411 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1617926020531 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926020581 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1617926020611 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1617926021221 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926021221 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1617926021711 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1617926023051 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1617926023051 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1617926023151 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1617926023151 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1617926023151 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926023151 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1617926023371 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1617926023381 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1617926023381 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1617926023631 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1617926023631 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1617926023631 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1617926023891 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926024281 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1617926024511 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1617926024561 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 18 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5903 " "Peak virtual memory: 5903 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617926024991 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 18:53:44 2021 " "Processing ended: Thu Apr 08 18:53:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617926024991 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617926024991 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617926024991 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1617926024991 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1617926026011 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617926026011 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 18:53:45 2021 " "Processing started: Thu Apr 08 18:53:45 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617926026011 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1617926026011 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1617926026011 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1617926026311 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1617926028061 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1617926028201 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4682 " "Peak virtual memory: 4682 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617926029251 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 18:53:49 2021 " "Processing ended: Thu Apr 08 18:53:49 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617926029251 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617926029251 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617926029251 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1617926029251 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1617926029851 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1617926030411 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617926030411 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 18:53:50 2021 " "Processing started: Thu Apr 08 18:53:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617926030411 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030411 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta part4 -c part4 " "Command: quartus_sta part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030411 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926030521 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030541 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030681 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030681 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030721 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030721 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926030981 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030991 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926030991 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030991 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1617926031001 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031001 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031001 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031001 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031011 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031011 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926031021 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031041 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031041 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031321 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031361 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031361 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031371 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031371 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926031371 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031511 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031511 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926032391 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926032391 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 31 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4864 " "Peak virtual memory: 4864 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617926032451 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 18:53:52 2021 " "Processing ended: Thu Apr 08 18:53:52 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617926032451 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617926032451 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617926032451 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926032451 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 85 s " "Quartus Prime Full Compilation was successful. 0 errors, 85 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926033081 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..d89a873 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| George Totolos :| 08/22/2016:| Initial Revision +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a2885da --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +DE10_LITE_Golden_Top.v +platform_setup.tcl +filelist.txt diff --git a/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..d9cea11 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,435 @@ +proc ::setup_project {} { +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name SDC_FILE DE10_LITE_Golden_Top.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS + +#============================================================ +# Accelerometer +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO + +#============================================================ +# Arduino +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..1c1dfa3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/home/gtotolos/Desktop/max10_de10_lite/Golden_Top/", + "acds_version" : "Version 16.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 4/devkits/readme.txt b/EE203/Noah Woodlee/LAB1/Part 4/devkits/readme.txt new file mode 100644 index 0000000..f6ba267 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/README b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.db_info b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.db_info new file mode 100644 index 0000000..3b1dcca --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Version_Index = 419480576 +Creation_Time = Thu Apr 08 18:40:40 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.ammdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.ammdb new file mode 100644 index 0000000..faf251e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.cdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.cdb new file mode 100644 index 0000000..ea01336 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.dfp b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.hdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.hdb new file mode 100644 index 0000000..a0b4754 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.logdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.rcfdb new file mode 100644 index 0000000..f735b36 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.cdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.cdb new file mode 100644 index 0000000..f264182 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.dpi b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.dpi new file mode 100644 index 0000000..714ced4 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..196a2fd Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..905402d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hdb new file mode 100644 index 0000000..7f01fab Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.kpt b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.kpt new file mode 100644 index 0000000..a6689e5 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.rrp.hdb b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.rrp.hdb new file mode 100644 index 0000000..c705369 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/incremental_db/compiled_partitions/part4.rrp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.asm.rpt b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.asm.rpt new file mode 100644 index 0000000..8ef8789 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.asm.rpt @@ -0,0 +1,93 @@ +Assembler report for part4 +Thu Apr 08 19:14:47 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Apr 08 19:14:47 2021 ; +; Revision Name ; part4 ; +; Top-level Entity Name ; part4 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++--------------------------------------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------------------------------------+ +; File Name ; ++--------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.sof ; ++--------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.sof ; ++----------------+-----------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-----------------------------------------------------------------------------------+ +; Device ; 10M50DAF484C6GES ; +; JTAG usercode ; 0x00270A1C ; +; Checksum ; 0x00270A1C ; ++----------------+-----------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Apr 08 19:14:44 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4682 megabytes + Info: Processing ended: Thu Apr 08 19:14:47 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.done b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.done new file mode 100644 index 0000000..b1f3928 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.done @@ -0,0 +1 @@ +Thu Apr 08 19:14:51 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.rpt b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.rpt new file mode 100644 index 0000000..0d8bd51 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.rpt @@ -0,0 +1,1263 @@ +Fitter report for part4 +Thu Apr 08 19:14:43 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Apr 08 19:14:43 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; part4 ; +; Top-level Entity Name ; part4 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 3 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 3 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 19 / 360 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.2% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; SW[2] ; PIN_D12 ; QSF Assignment ; +; Location ; ; ; SW[3] ; PIN_C12 ; QSF Assignment ; +; Location ; ; ; SW[4] ; PIN_A12 ; QSF Assignment ; +; Location ; ; ; SW[5] ; PIN_B12 ; QSF Assignment ; +; Location ; ; ; SW[6] ; PIN_A13 ; QSF Assignment ; +; Location ; ; ; SW[7] ; PIN_A14 ; QSF Assignment ; +; Location ; ; ; SW[8] ; PIN_B14 ; QSF Assignment ; +; Location ; ; ; SW[9] ; PIN_F15 ; QSF Assignment ; ++----------+----------------+--------------+------------+---------------+----------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 60 ) ; 0.00 % ( 0 / 60 ) ; 0.00 % ( 0 / 60 ) ; +; -- Achieved ; 0.00 % ( 0 / 60 ) ; 0.00 % ( 0 / 60 ) ; 0.00 % ( 0 / 60 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 44 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 3 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 3 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 3 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 3 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 19 / 360 ( 5 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.1% / 0.2% / 0.1% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 43 ; +; Average fan-out ; 0.72 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 3 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 3 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 3 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 3 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 19 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 49 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 2 ; 0 ; +; -- Output Ports ; 17 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; C10 ; 7 ; 51 ; 54 ; 28 ; 5 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; HEX0[0] ; C14 ; 7 ; 58 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[1] ; E15 ; 7 ; 74 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[2] ; C15 ; 7 ; 60 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[3] ; C16 ; 7 ; 62 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[4] ; E16 ; 7 ; 74 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[5] ; D17 ; 7 ; 74 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[6] ; C17 ; 7 ; 74 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[0] ; A8 ; 7 ; 46 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[1] ; A9 ; 7 ; 46 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[2] ; A10 ; 7 ; 51 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[3] ; B10 ; 7 ; 46 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[4] ; D13 ; 7 ; 56 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[5] ; C13 ; 7 ; 58 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[6] ; E14 ; 7 ; 66 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[7] ; D14 ; 7 ; 56 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[8] ; A11 ; 7 ; 51 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[9] ; B11 ; 7 ; 49 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 0 / 60 ( 0 % ) ; 2.5V ; -- ; +; 7 ; 19 / 52 ( 37 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 449 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 439 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 437 ; 7 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A12 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 443 ; 7 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B12 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 426 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C14 ; 424 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C15 ; 418 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C16 ; 416 ; 7 ; HEX0[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C17 ; 391 ; 7 ; HEX0[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C18 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 431 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D14 ; 428 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; HEX0[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D18 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E15 ; 390 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 388 ; 7 ; HEX0[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; LEDR[0] ; Incomplete set of assignments ; +; LEDR[1] ; Incomplete set of assignments ; +; LEDR[2] ; Incomplete set of assignments ; +; LEDR[3] ; Incomplete set of assignments ; +; LEDR[4] ; Incomplete set of assignments ; +; LEDR[5] ; Incomplete set of assignments ; +; LEDR[6] ; Incomplete set of assignments ; +; LEDR[7] ; Incomplete set of assignments ; +; LEDR[8] ; Incomplete set of assignments ; +; LEDR[9] ; Incomplete set of assignments ; +; HEX0[6] ; Incomplete set of assignments ; +; HEX0[5] ; Incomplete set of assignments ; +; HEX0[4] ; Incomplete set of assignments ; +; HEX0[3] ; Incomplete set of assignments ; +; HEX0[2] ; Incomplete set of assignments ; +; HEX0[1] ; Incomplete set of assignments ; +; HEX0[0] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |part4 ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 19 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; |part4 ; part4 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-----------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------+-------------------+---------+ +; SW[0] ; ; ; +; - HEX0~0 ; 0 ; 6 ; +; - HEX0~1 ; 0 ; 6 ; +; - LEDR[0]~output ; 0 ; 6 ; +; - HEX0[0]~output ; 0 ; 6 ; +; - HEX0[5]~output ; 0 ; 6 ; +; SW[1] ; ; ; +; - HEX0~0 ; 0 ; 6 ; +; - HEX0~1 ; 0 ; 6 ; +; - LEDR[1]~output ; 0 ; 6 ; +; - HEX0[6]~output ; 0 ; 6 ; ++-----------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 15 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 2 / 5,382 ( < 1 % ) ; +; C4 interconnects ; 16 / 106,704 ( < 1 % ) ; +; Direct links ; 1 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 49,760 ( 0 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 2 / 5,406 ( < 1 % ) ; +; R4 interconnects ; 12 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 1.50) ; Number of LABs (Total = 2) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 1.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 1.50) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 1.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 19 ; 0 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 19 ; 19 ; 0 ; 17 ; 0 ; 0 ; 2 ; 0 ; 17 ; 2 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 19 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 0 ; 0 ; 19 ; 2 ; 19 ; 19 ; 17 ; 19 ; 2 ; 17 ; 19 ; 19 ; 19 ; 2 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 19 ; 19 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; LEDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (119006): Selected device 10M50DAF484C6GES for design "part4" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y44 to location X78_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 17 warnings + Info: Peak virtual memory: 5905 megabytes + Info: Processing ended: Thu Apr 08 19:14:43 2021 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:09 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg. + + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg new file mode 100644 index 0000000..558ea95 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.summary b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.summary new file mode 100644 index 0000000..f754bc0 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Thu Apr 08 19:14:43 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : part4 +Top-level Entity Name : part4 +Family : MAX 10 +Device : 10M50DAF484C6GES +Timing Models : Preliminary +Total logic elements : 3 / 49,760 ( < 1 % ) + Total combinational functions : 3 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 19 / 360 ( 5 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.flow.rpt b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.flow.rpt new file mode 100644 index 0000000..3765265 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.flow.rpt @@ -0,0 +1,128 @@ +Flow report for part4 +Thu Apr 08 19:14:50 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Apr 08 19:14:47 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; part4 ; +; Top-level Entity Name ; part4 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 3 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 3 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 19 / 360 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/08/2021 19:14:26 ; +; Main task ; Compilation ; +; Revision Name ; part4 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 189559947077153.161792726611824 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4781 MB ; 00:00:22 ; +; Fitter ; 00:00:07 ; 1.0 ; 5905 MB ; 00:00:09 ; +; Assembler ; 00:00:03 ; 1.0 ; 4681 MB ; 00:00:03 ; +; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4869 MB ; 00:00:02 ; +; Total ; 00:00:21 ; -- ; -- ; 00:00:36 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 +quartus_fit --read_settings_files=off --write_settings_files=off part4 -c part4 +quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4 +quartus_sta part4 -c part4 + + + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.jdi b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.jdi new file mode 100644 index 0000000..459d00c --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.map.rpt b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.map.rpt new file mode 100644 index 0000000..1c9dd35 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.map.rpt @@ -0,0 +1,319 @@ +Analysis & Synthesis report for part4 +Thu Apr 08 19:14:36 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Apr 08 19:14:36 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; part4 ; +; Top-level Entity Name ; part4 ; +; Family ; MAX 10 ; +; Total logic elements ; 2 ; +; Total combinational functions ; 2 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 19 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Top-level entity name ; part4 ; part4 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+-----------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+-----------------------------------------------------------+---------+ +; part4.v ; yes ; User Verilog HDL File ; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v ; ; ++----------------------------------+-----------------+------------------------+-----------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimated Total logic elements ; 2 ; +; ; ; +; Total combinational functions ; 2 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 2 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 2 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 19 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; SW[0]~input ; +; Maximum fan-out ; 5 ; +; Total fan-out ; 32 ; +; Average fan-out ; 0.80 ; ++---------------------------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |part4 ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 0 ; |part4 ; part4 ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 19 ; +; cycloneiii_lcell_comb ; 4 ; +; normal ; 4 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 1 ; +; 2 data inputs ; 2 ; +; ; ; +; Max LUT depth ; 1.00 ; +; Average LUT depth ; 0.83 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Apr 08 19:14:26 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file part4.v + Info (12023): Found entity 1: part4 File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 1 +Info (12127): Elaborating entity "part4" for the top level hierarchy +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "LEDR[2]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 3 + Warning (13410): Pin "LEDR[3]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 3 + Warning (13410): Pin "LEDR[4]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 3 + Warning (13410): Pin "LEDR[5]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 3 + Warning (13410): Pin "LEDR[6]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 3 + Warning (13410): Pin "LEDR[7]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 3 + Warning (13410): Pin "LEDR[8]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 3 + Warning (13410): Pin "LEDR[9]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v Line: 3 +Info (286030): Timing-Driven Synthesis is running +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 2 input pins + Info (21059): Implemented 17 output pins + Info (21061): Implemented 2 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings + Info: Peak virtual memory: 4781 megabytes + Info: Processing ended: Thu Apr 08 19:14:36 2021 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:22 + + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.map.summary b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.map.summary new file mode 100644 index 0000000..ff2ed3a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Thu Apr 08 19:14:36 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : part4 +Top-level Entity Name : part4 +Family : MAX 10 +Total logic elements : 2 + Total combinational functions : 2 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 19 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.pin b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.pin new file mode 100644 index 0000000..897b7bd --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2016 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel MegaCore Function License Agreement, or other + -- applicable license agreement, including, without limitation, + -- that your use is for the sole purpose of programming logic + -- devices manufactured by Intel and sold by Intel or its + -- authorized distributors. Please refer to the applicable + -- agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +CHIP "part4" ASSIGNED TO AN: 10M50DAF484C6GES + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +LEDR[0] : A8 : output : 2.5 V : : 7 : Y +LEDR[1] : A9 : output : 2.5 V : : 7 : Y +LEDR[2] : A10 : output : 2.5 V : : 7 : Y +LEDR[8] : A11 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +LEDR[3] : B10 : output : 2.5 V : : 7 : Y +LEDR[9] : B11 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +GND : B13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[0] : C10 : input : 2.5 V : : 7 : Y +SW[1] : C11 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 : +LEDR[5] : C13 : output : 2.5 V : : 7 : Y +HEX0[0] : C14 : output : 2.5 V : : 7 : Y +HEX0[2] : C15 : output : 2.5 V : : 7 : Y +HEX0[3] : C16 : output : 2.5 V : : 7 : Y +HEX0[6] : C17 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +LEDR[4] : D13 : output : 2.5 V : : 7 : Y +LEDR[7] : D14 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +HEX0[5] : D17 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +LEDR[6] : E14 : output : 2.5 V : : 7 : Y +HEX0[1] : E15 : output : 2.5 V : : 7 : Y +HEX0[4] : E16 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.pof b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.pof new file mode 100644 index 0000000..aaa417e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.pof differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sld b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sof b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sof new file mode 100644 index 0000000..b3820f4 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sof differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sta.rpt b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sta.rpt new file mode 100644 index 0000000..51b1244 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sta.rpt @@ -0,0 +1,531 @@ +TimeQuest Timing Analyzer report for part4 +Thu Apr 08 19:14:51 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; part4 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.3% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0108 V ; 0.13 V ; 0.066 V ; 6.32e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0108 V ; 0.13 V ; 0.066 V ; 6.32e-10 s ; 6.45e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 2 ; 2 ; +; Unconstrained Input Port Paths ; 13 ; 13 ; +; Unconstrained Output Ports ; 9 ; 9 ; +; Unconstrained Output Port Paths ; 13 ; 13 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Apr 08 19:14:48 2021 +Info: Command: quartus_sta part4 -c part4 +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 31 warnings + Info: Peak virtual memory: 4869 megabytes + Info: Processing ended: Thu Apr 08 19:14:51 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sta.summary b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/output_files/part4.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/part4.qpf b/EE203/Noah Woodlee/LAB1/Part 4/part4.qpf new file mode 100644 index 0000000..5224208 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/part4.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 18:21:59 April 08, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "18:21:59 April 08, 2021" + +# Revisions + +PROJECT_REVISION = "part4" diff --git a/EE203/Noah Woodlee/LAB1/Part 4/part4.qsf b/EE203/Noah Woodlee/LAB1/Part 4/part4.qsf new file mode 100644 index 0000000..708b4d9 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/part4.qsf @@ -0,0 +1,85 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 18:21:59 April 08, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part4_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part4 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:21:59 APRIL 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part4.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 4/part4.qsf.bak b/EE203/Noah Woodlee/LAB1/Part 4/part4.qsf.bak new file mode 100644 index 0000000..50aed6b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/part4.qsf.bak @@ -0,0 +1,49 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 18:21:59 April 08, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part4_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part4 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:21:59 APRIL 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 4/part4.qws b/EE203/Noah Woodlee/LAB1/Part 4/part4.qws new file mode 100644 index 0000000..3a7f336 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 4/part4.qws differ diff --git a/EE203/Noah Woodlee/LAB1/Part 4/part4.v b/EE203/Noah Woodlee/LAB1/Part 4/part4.v new file mode 100644 index 0000000..3a87bea --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 4/part4.v @@ -0,0 +1,20 @@ +module part4 (SW, LEDR, HEX0); + input[1:0] SW; + output[9:0] LEDR; + output[0:6] HEX0; + + wire[1:0] C; + + assign LEDR[1:0]=SW; + assign LEDR[9:2]=8'b0; + + assign C=SW; + + assign HEX0[0]=~C[0]; + assign HEX0[1]=~C[1] & C[0]; + assign HEX0[2]=~C[1] & C[0]; + assign HEX0[3]=C[1] & ~C[0]; + assign HEX0[4]=C[1] & ~C[0]; + assign HEX0[5]=~C[0]; + assign HEX0[6]=C[1]; +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 4/part4.v.bak b/EE203/Noah Woodlee/LAB1/Part 4/part4.v.bak new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/LAB1/Part 5/atom_netlists/part5.qsf b/EE203/Noah Woodlee/LAB1/Part 5/atom_netlists/part5.qsf new file mode 100644 index 0000000..43eac59 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/atom_netlists/part5.qsf @@ -0,0 +1,71 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:34:56 APRIL 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part5.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(0).cnf.cdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(0).cnf.cdb new file mode 100644 index 0000000..ef1dfa0 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(0).cnf.hdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(0).cnf.hdb new file mode 100644 index 0000000..1d47305 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(1).cnf.cdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(1).cnf.cdb new file mode 100644 index 0000000..1fbed96 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(1).cnf.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(1).cnf.hdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(1).cnf.hdb new file mode 100644 index 0000000..35d96eb Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(1).cnf.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(2).cnf.cdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(2).cnf.cdb new file mode 100644 index 0000000..97d8f32 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(2).cnf.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(2).cnf.hdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(2).cnf.hdb new file mode 100644 index 0000000..e900611 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.(2).cnf.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.analyze_file.qmsg b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.analyze_file.qmsg new file mode 100644 index 0000000..29148b5 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.analyze_file.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1618979349968 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1618979349970 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 23:29:09 2021 " "Processing started: Tue Apr 20 23:29:09 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1618979349970 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1618979349970 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 --analyze_file=\"/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 --analyze_file=\"/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v\"" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1618979349970 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1618979350282 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1618979350283 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1 Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1618979363251 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 23:29:23 2021 " "Processing ended: Tue Apr 20 23:29:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1618979363251 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1618979363251 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Total CPU time (on all processors): 00:00:30" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1618979363251 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1618979363251 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm.qmsg b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm.qmsg new file mode 100644 index 0000000..d5f27ae --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1618979428878 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1618979428879 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 23:30:28 2021 " "Processing started: Tue Apr 20 23:30:28 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1618979428879 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618979428879 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part5 -c part5 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part5 -c part5" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618979428879 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1618979429256 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618979432104 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618979432210 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "356 " "Peak virtual memory: 356 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1618979433491 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 23:30:33 2021 " "Processing ended: Tue Apr 20 23:30:33 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1618979433491 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1618979433491 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1618979433491 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618979433491 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm.rdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm.rdb new file mode 100644 index 0000000..e8f51ab Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm_labs.ddb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm_labs.ddb new file mode 100644 index 0000000..61d2a26 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cbx.xml b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cbx.xml new file mode 100644 index 0000000..70328de --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.bpm b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.bpm new file mode 100644 index 0000000..671572d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.cdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.cdb new file mode 100644 index 0000000..9515a4e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.hdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.hdb new file mode 100644 index 0000000..0158579 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.idb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.idb new file mode 100644 index 0000000..4638698 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.idb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.logdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.logdb new file mode 100644 index 0000000..44314f0 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.logdb @@ -0,0 +1,90 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;48;48;0;0;48;48;0;0;0;0;0;0;38;0;0;0;10;38;0;10;0;0;38;0;48;48;48;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,48;0;0;48;48;0;0;48;48;48;48;48;48;10;48;48;48;38;10;48;38;48;48;10;48;0;0;0;48;48, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX2[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX2[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX2[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX2[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX2[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX2[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX3[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX3[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX3[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX3[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX3[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX3[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX3[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.rdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.rdb new file mode 100644 index 0000000..2820ed9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp_merge.kpt b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp_merge.kpt new file mode 100644 index 0000000..76d26a1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.db_info b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.db_info new file mode 100644 index 0000000..ea9a48e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Tue Apr 20 23:27:08 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.fit.qmsg b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.fit.qmsg new file mode 100644 index 0000000..6ac2052 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.fit.qmsg @@ -0,0 +1,52 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1618979406655 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618979406655 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part5 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part5\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618979406664 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618979406752 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618979406752 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1618979407169 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618979407182 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618979407354 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 0 { 0 ""} 0 158 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618979407371 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 0 { 0 ""} 0 160 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618979407371 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 0 { 0 ""} 0 162 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618979407371 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 0 { 0 ""} 0 164 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618979407371 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 0 { 0 ""} 0 166 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618979407371 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 0 { 0 ""} 0 168 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618979407371 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 0 { 0 ""} 0 170 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618979407371 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 0 { 0 ""} 0 172 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618979407371 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1618979407371 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1618979407373 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1618979407373 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1618979407373 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1618979407373 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1618979407378 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part5.sdc " "Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618979408200 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618979408201 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1618979408201 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1618979408202 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1618979408207 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1618979408208 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1618979408210 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1618979408223 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618979408223 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618979408224 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1618979408225 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1618979408227 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1618979408228 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1618979408228 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1618979408228 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1618979408228 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1618979408229 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618979408229 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618979408316 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1618979408333 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618979411673 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618979411823 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618979411882 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618979412495 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618979412496 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618979419494 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X67_Y44 X78_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y44 to location X78_Y54" { } { { "loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y44 to location X78_Y54"} { { 12 { 0 ""} 67 44 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1618979423251 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618979423251 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1618979423478 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1618979423478 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1618979423478 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618979423481 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.06 " "Total time spent on timing analysis during the Fitter is 0.06 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1618979423799 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1618979423813 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1618979423814 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1618979424402 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1618979424402 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1618979424402 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1618979424960 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618979425804 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.smsg " "Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618979426112 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1082 " "Peak virtual memory: 1082 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1618979426605 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 23:30:26 2021 " "Processing ended: Tue Apr 20 23:30:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1618979426605 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1618979426605 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1618979426605 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618979426605 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.hier_info b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.hier_info new file mode 100644 index 0000000..4e690c5 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.hier_info @@ -0,0 +1,179 @@ +|part5 +SW[0] => SW[0].IN4 +SW[1] => SW[1].IN4 +SW[2] => SW[2].IN4 +SW[3] => SW[3].IN4 +SW[4] => SW[4].IN4 +SW[5] => SW[5].IN4 +SW[6] => SW[6].IN4 +SW[7] => SW[7].IN4 +SW[8] => SW[8].IN4 +SW[9] => SW[9].IN4 +LEDR[0] <= SW[0].DB_MAX_OUTPUT_PORT_TYPE +LEDR[1] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE +LEDR[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE +LEDR[3] <= SW[3].DB_MAX_OUTPUT_PORT_TYPE +LEDR[4] <= SW[4].DB_MAX_OUTPUT_PORT_TYPE +LEDR[5] <= SW[5].DB_MAX_OUTPUT_PORT_TYPE +LEDR[6] <= SW[6].DB_MAX_OUTPUT_PORT_TYPE +LEDR[7] <= SW[7].DB_MAX_OUTPUT_PORT_TYPE +LEDR[8] <= SW[8].DB_MAX_OUTPUT_PORT_TYPE +LEDR[9] <= SW[9].DB_MAX_OUTPUT_PORT_TYPE +HEX0[0] <= sevenSegment:S0.port1 +HEX0[1] <= sevenSegment:S0.port1 +HEX0[2] <= sevenSegment:S0.port1 +HEX0[3] <= sevenSegment:S0.port1 +HEX0[4] <= sevenSegment:S0.port1 +HEX0[5] <= sevenSegment:S0.port1 +HEX0[6] <= sevenSegment:S0.port1 +HEX1[0] <= sevenSegment:S1.port1 +HEX1[1] <= sevenSegment:S1.port1 +HEX1[2] <= sevenSegment:S1.port1 +HEX1[3] <= sevenSegment:S1.port1 +HEX1[4] <= sevenSegment:S1.port1 +HEX1[5] <= sevenSegment:S1.port1 +HEX1[6] <= sevenSegment:S1.port1 +HEX2[0] <= sevenSegment:S2.port1 +HEX2[1] <= sevenSegment:S2.port1 +HEX2[2] <= sevenSegment:S2.port1 +HEX2[3] <= sevenSegment:S2.port1 +HEX2[4] <= sevenSegment:S2.port1 +HEX2[5] <= sevenSegment:S2.port1 +HEX2[6] <= sevenSegment:S2.port1 +HEX3[0] <= sevenSegment:S3.port1 +HEX3[1] <= sevenSegment:S3.port1 +HEX3[2] <= sevenSegment:S3.port1 +HEX3[3] <= sevenSegment:S3.port1 +HEX3[4] <= sevenSegment:S3.port1 +HEX3[5] <= sevenSegment:S3.port1 +HEX3[6] <= sevenSegment:S3.port1 + + +|part5|Mux_4to1:comb_3 +IN1[0] => Mux1.IN0 +IN1[1] => Mux0.IN0 +IN2[0] => Mux1.IN1 +IN2[1] => Mux0.IN1 +IN3[0] => Mux1.IN2 +IN3[1] => Mux0.IN2 +IN4[0] => Mux1.IN3 +IN4[1] => Mux0.IN3 +SEL[0] => Mux0.IN5 +SEL[0] => Mux1.IN5 +SEL[1] => Mux0.IN4 +SEL[1] => Mux1.IN4 +M[0] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +M[1] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE + + +|part5|Mux_4to1:comb_4 +IN1[0] => Mux1.IN0 +IN1[1] => Mux0.IN0 +IN2[0] => Mux1.IN1 +IN2[1] => Mux0.IN1 +IN3[0] => Mux1.IN2 +IN3[1] => Mux0.IN2 +IN4[0] => Mux1.IN3 +IN4[1] => Mux0.IN3 +SEL[0] => Mux0.IN5 +SEL[0] => Mux1.IN5 +SEL[1] => Mux0.IN4 +SEL[1] => Mux1.IN4 +M[0] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +M[1] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE + + +|part5|Mux_4to1:comb_5 +IN1[0] => Mux1.IN0 +IN1[1] => Mux0.IN0 +IN2[0] => Mux1.IN1 +IN2[1] => Mux0.IN1 +IN3[0] => Mux1.IN2 +IN3[1] => Mux0.IN2 +IN4[0] => Mux1.IN3 +IN4[1] => Mux0.IN3 +SEL[0] => Mux0.IN5 +SEL[0] => Mux1.IN5 +SEL[1] => Mux0.IN4 +SEL[1] => Mux1.IN4 +M[0] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +M[1] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE + + +|part5|Mux_4to1:comb_6 +IN1[0] => Mux1.IN0 +IN1[1] => Mux0.IN0 +IN2[0] => Mux1.IN1 +IN2[1] => Mux0.IN1 +IN3[0] => Mux1.IN2 +IN3[1] => Mux0.IN2 +IN4[0] => Mux1.IN3 +IN4[1] => Mux0.IN3 +SEL[0] => Mux0.IN5 +SEL[0] => Mux1.IN5 +SEL[1] => Mux0.IN4 +SEL[1] => Mux1.IN4 +M[0] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +M[1] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE + + +|part5|sevenSegment:S0 +IN[0] => Decoder0.IN1 +IN[0] => OUT[5].DATAIN +IN[0] => OUT[0].DATAIN +IN[1] => Decoder0.IN0 +IN[1] => OUT[6].DATAIN +OUT[0] <= IN[0].DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[4] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[5] <= IN[0].DB_MAX_OUTPUT_PORT_TYPE +OUT[6] <= IN[1].DB_MAX_OUTPUT_PORT_TYPE + + +|part5|sevenSegment:S1 +IN[0] => Decoder0.IN1 +IN[0] => OUT[5].DATAIN +IN[0] => OUT[0].DATAIN +IN[1] => Decoder0.IN0 +IN[1] => OUT[6].DATAIN +OUT[0] <= IN[0].DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[4] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[5] <= IN[0].DB_MAX_OUTPUT_PORT_TYPE +OUT[6] <= IN[1].DB_MAX_OUTPUT_PORT_TYPE + + +|part5|sevenSegment:S2 +IN[0] => Decoder0.IN1 +IN[0] => OUT[5].DATAIN +IN[0] => OUT[0].DATAIN +IN[1] => Decoder0.IN0 +IN[1] => OUT[6].DATAIN +OUT[0] <= IN[0].DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[4] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[5] <= IN[0].DB_MAX_OUTPUT_PORT_TYPE +OUT[6] <= IN[1].DB_MAX_OUTPUT_PORT_TYPE + + +|part5|sevenSegment:S3 +IN[0] => Decoder0.IN1 +IN[0] => OUT[5].DATAIN +IN[0] => OUT[0].DATAIN +IN[1] => Decoder0.IN0 +IN[1] => OUT[6].DATAIN +OUT[0] <= IN[0].DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[4] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE +OUT[5] <= IN[0].DB_MAX_OUTPUT_PORT_TYPE +OUT[6] <= IN[1].DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.hif b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.hif new file mode 100644 index 0000000..d1e57c8 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.hif differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.html b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.html new file mode 100644 index 0000000..2ab7c67 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.html @@ -0,0 +1,146 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
S32000700000000
S22000700000000
S12000700000000
S02000700000000
comb_610000200000000
comb_510000200000000
comb_410000200000000
comb_310000200000000
diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.rdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.rdb new file mode 100644 index 0000000..465a460 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.txt b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.txt new file mode 100644 index 0000000..8fe2bb7 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.lpc.txt @@ -0,0 +1,14 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; S3 ; 2 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; S2 ; 2 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; S1 ; 2 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; S0 ; 2 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; comb_6 ; 10 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; comb_5 ; 10 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; comb_4 ; 10 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; comb_3 ; 10 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.ammdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.ammdb new file mode 100644 index 0000000..790b913 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.bpm b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.bpm new file mode 100644 index 0000000..6b55322 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.cdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.cdb new file mode 100644 index 0000000..843d37b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.hdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.hdb new file mode 100644 index 0000000..3fbd8d8 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.kpt b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.kpt new file mode 100644 index 0000000..4e0283a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.logdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.qmsg b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.qmsg new file mode 100644 index 0000000..adfd866 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.qmsg @@ -0,0 +1,19 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1618979388699 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1618979388700 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 23:29:48 2021 " "Processing started: Tue Apr 20 23:29:48 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1618979388700 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1618979388700 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1618979388700 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1618979389048 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1618979389048 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part5.v 3 3 " "Found 3 design units, including 3 entities, in source file part5.v" { { "Info" "ISGN_ENTITY_NAME" "1 sevenSegment " "Found entity 1: sevenSegment" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618979402481 ""} { "Info" "ISGN_ENTITY_NAME" "2 Mux_4to1 " "Found entity 2: Mux_4to1" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 16 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618979402481 ""} { "Info" "ISGN_ENTITY_NAME" "3 part5 " "Found entity 3: part5" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618979402481 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1618979402481 ""} +{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "part5.v(41) " "Verilog HDL Instantiation warning at part5.v(41): instance has no name" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 41 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1618979402483 ""} +{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "part5.v(43) " "Verilog HDL Instantiation warning at part5.v(43): instance has no name" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 43 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1618979402483 ""} +{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "part5.v(45) " "Verilog HDL Instantiation warning at part5.v(45): instance has no name" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 45 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1618979402483 ""} +{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "part5.v(47) " "Verilog HDL Instantiation warning at part5.v(47): instance has no name" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 47 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1618979402483 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part5 " "Elaborating entity \"part5\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1618979402554 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux_4to1 Mux_4to1:comb_3 " "Elaborating entity \"Mux_4to1\" for hierarchy \"Mux_4to1:comb_3\"" { } { { "part5.v" "comb_3" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1618979402586 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sevenSegment sevenSegment:S0 " "Elaborating entity \"sevenSegment\" for hierarchy \"sevenSegment:S0\"" { } { { "part5.v" "S0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v" 49 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1618979402594 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1618979403477 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404119 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1618979404121 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404121 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979404121 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1618979404121 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! 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Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 55 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "396 " "Peak virtual memory: 396 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1618979404435 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 23:30:04 2021 " "Processing ended: Tue Apr 20 23:30:04 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1618979404435 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1618979404435 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1618979404435 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1618979404435 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.map.rdb b/EE203/Noah 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REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979435440 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979435440 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979435440 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979435440 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979435440 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618979435440 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1618979435440 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1618979435570 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1618979435571 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1618979435655 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1618979435655 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part5.sdc " "Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1618979436124 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1618979436124 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1618979436125 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1618979436125 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1618979436126 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1618979436126 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1618979436127 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1618979436135 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1618979436136 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979436139 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1618979436140 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979436141 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979436142 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979436143 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979436145 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979436145 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1618979436150 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1618979436192 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Timing Analyzer" 0 -1 1618979436193 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1618979439856 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1618979439910 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1618979439910 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1618979439911 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1618979439911 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979439912 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979439915 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979439916 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979439917 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979439917 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979439918 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1618979439920 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1618979440094 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1618979440094 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1618979440094 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1618979440095 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979440096 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979440097 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979440098 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979440100 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1618979440101 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1618979441635 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1618979441637 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 56 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 56 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "507 " "Peak virtual memory: 507 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1618979441679 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 23:30:41 2021 " "Processing ended: Tue Apr 20 23:30:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1618979441679 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1618979441679 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1618979441679 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1618979441679 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.sta.rdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.sta.rdb new file mode 100644 index 0000000..5465fea Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.sta.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.sta_cmp.6_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..1d3cfa6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tis_db_list.ddb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tis_db_list.ddb new file mode 100644 index 0000000..73e5ec9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..aa554ab Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..e0f5ba2 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..d423978 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tmw_info b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tmw_info new file mode 100644 index 0000000..7a9403d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:55 +start_analysis_synthesis:s:00:00:18-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:22-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:08-start_full_compilation diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.vpr.ammdb b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.vpr.ammdb new file mode 100644 index 0000000..9f9daa7 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..0259d60 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.tt_0c_slow.hsd b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..090de61 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.tt_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.tt_85c_slow.hsd b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..09ac6ef Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/db/part5.zippleback_io_sim_cache.tt_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/part5_partition_pins.json b/EE203/Noah Woodlee/LAB1/Part 5/db/part5_partition_pins.json new file mode 100644 index 0000000..cf7c7ef --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/part5_partition_pins.json @@ -0,0 +1,201 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "LEDR[0]", + "strict" : false + }, + { + "name" : "LEDR[1]", + "strict" : false + }, + { + "name" : "LEDR[2]", + "strict" : false + }, + { + "name" : "LEDR[3]", + "strict" : false + }, + { + "name" : "LEDR[4]", + "strict" : false + }, + { + "name" : "LEDR[5]", + "strict" : false + }, + { + "name" : "LEDR[6]", + "strict" : false + }, + { + "name" : "LEDR[7]", + "strict" : false + }, + { + "name" : "LEDR[8]", + "strict" : false + }, + { + "name" : "LEDR[9]", + "strict" : false + }, + { + "name" : "HEX0[0]", + "strict" : false + }, + { + "name" : "HEX0[1]", + "strict" : false + }, + { + "name" : "HEX0[2]", + "strict" : false + }, + { + "name" : "HEX0[3]", + "strict" : false + }, + { + "name" : "HEX0[4]", + "strict" : false + }, + { + "name" : "HEX0[5]", + "strict" : false + }, + { + "name" : "HEX0[6]", + "strict" : false + }, + { + "name" : "HEX1[0]", + "strict" : false + }, + { + "name" : "HEX1[1]", + "strict" : false + }, + { + "name" : "HEX1[2]", + "strict" : false + }, + { + "name" : "HEX1[3]", + "strict" : false + }, + { + "name" : "HEX1[4]", + "strict" : false + }, + { + "name" : "HEX1[5]", + "strict" : false + }, + { + "name" : "HEX1[6]", + "strict" : false + }, + { + "name" : "HEX2[0]", + "strict" : false + }, + { + "name" : "HEX2[1]", + "strict" : false + }, + { + "name" : "HEX2[2]", + "strict" : false + }, + { + "name" : "HEX2[3]", + "strict" : false + }, + { + "name" : "HEX2[4]", + "strict" : false + }, + { + "name" : "HEX2[5]", + "strict" : false + }, + { + "name" : "HEX2[6]", + "strict" : false + }, + { + "name" : "HEX3[0]", + "strict" : false + }, + { + "name" : "HEX3[1]", + "strict" : false + }, + { + "name" : "HEX3[2]", + "strict" : false + }, + { + "name" : "HEX3[3]", + "strict" : false + }, + { + "name" : "HEX3[4]", + "strict" : false + }, + { + "name" : "HEX3[5]", + "strict" : false + }, + { + "name" : "HEX3[6]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[2]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + }, + { + "name" : "SW[4]", + "strict" : false + }, + { + "name" : "SW[5]", + "strict" : false + }, + { + "name" : "SW[6]", + "strict" : false + }, + { + "name" : "SW[7]", + "strict" : false + }, + { + "name" : "SW[8]", + "strict" : false + }, + { + "name" : "SW[9]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 5/db/prev_cmp_part5.qmsg b/EE203/Noah Woodlee/LAB1/Part 5/db/prev_cmp_part5.qmsg new file mode 100644 index 0000000..29148b5 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/db/prev_cmp_part5.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1618979349968 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1618979349970 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 23:29:09 2021 " "Processing started: Tue Apr 20 23:29:09 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1618979349970 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1618979349970 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 --analyze_file=\"/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 --analyze_file=\"/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v\"" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1618979349970 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1618979350282 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1618979350283 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1 Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1618979363251 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 23:29:23 2021 " "Processing ended: Tue Apr 20 23:29:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1618979363251 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1618979363251 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Total CPU time (on all processors): 00:00:30" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1618979363251 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1618979363251 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..d89a873 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| George Totolos :| 08/22/2016:| Initial Revision +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a2885da --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +DE10_LITE_Golden_Top.v +platform_setup.tcl +filelist.txt diff --git a/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..d9cea11 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,435 @@ +proc ::setup_project {} { +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name SDC_FILE DE10_LITE_Golden_Top.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS + +#============================================================ +# Accelerometer +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO + +#============================================================ +# Arduino +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..1c1dfa3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/home/gtotolos/Desktop/max10_de10_lite/Golden_Top/", + "acds_version" : "Version 16.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 5/devkits/readme.txt b/EE203/Noah Woodlee/LAB1/Part 5/devkits/readme.txt new file mode 100644 index 0000000..f6ba267 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/README b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.db_info b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.db_info new file mode 100644 index 0000000..ea9a48e --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Tue Apr 20 23:27:08 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.ammdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.ammdb new file mode 100644 index 0000000..025663b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.cdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.cdb new file mode 100644 index 0000000..7747d91 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.dfp b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.hdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.hdb new file mode 100644 index 0000000..ff2824e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.logdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.rcfdb new file mode 100644 index 0000000..15487da Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.cdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.cdb new file mode 100644 index 0000000..3810a18 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.dpi b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.dpi new file mode 100644 index 0000000..18e099f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..6e8874b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..ffa4ff2 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hdb new file mode 100644 index 0000000..8ca4645 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.kpt b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.kpt new file mode 100644 index 0000000..c974172 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.rrp.hdb b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.rrp.hdb new file mode 100644 index 0000000..b7ffc1c Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/incremental_db/compiled_partitions/part5.rrp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.asm.rpt b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.asm.rpt new file mode 100644 index 0000000..7e479f0 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for part5 +Tue Apr 20 23:30:33 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: part5.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Tue Apr 20 23:30:33 2021 ; +; Revision Name ; part5 ; +; Top-level Entity Name ; part5 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++------------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------------------------------------------------+ +; File Name ; ++------------------------------------------------------------------------------------------------+ +; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/output_files/part5.sof ; ++------------------------------------------------------------------------------------------------+ + + ++-------------------------------------+ +; Assembler Device Options: part5.sof ; ++----------------+--------------------+ +; Option ; Setting ; ++----------------+--------------------+ +; JTAG usercode ; 0x00276AA9 ; +; Checksum ; 0x00276AA9 ; ++----------------+--------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Tue Apr 20 23:30:28 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off part5 -c part5 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 356 megabytes + Info: Processing ended: Tue Apr 20 23:30:33 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.done b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.done new file mode 100644 index 0000000..72c7366 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.done @@ -0,0 +1 @@ +Tue Apr 20 23:30:41 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.rpt b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.rpt new file mode 100644 index 0000000..6943aa0 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.rpt @@ -0,0 +1,1440 @@ +Fitter report for part5 +Tue Apr 20 23:30:26 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Tue Apr 20 23:30:26 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part5 ; +; Top-level Entity Name ; part5 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 25 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 25 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 48 / 360 ( 13 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.5% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 140 ) ; 0.00 % ( 0 / 140 ) ; 0.00 % ( 0 / 140 ) ; +; -- Achieved ; 0.00 % ( 0 / 140 ) ; 0.00 % ( 0 / 140 ) ; 0.00 % ( 0 / 140 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 124 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/output_files/part5.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 25 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 25 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 8 ; +; -- 3 input functions ; 16 ; +; -- <=2 input functions ; 1 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 25 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 3 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 48 / 360 ( 13 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; +; Peak interconnect usage (total/H/V) ; 0.9% / 1.0% / 0.8% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 177 ; +; Average fan-out ; 1.26 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 25 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 25 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 8 ; 0 ; +; -- 3 input functions ; 16 ; 0 ; +; -- <=2 input functions ; 1 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 25 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 3 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 48 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 183 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 10 ; 0 ; +; -- Output Ports ; 38 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; C10 ; 7 ; 51 ; 54 ; 28 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[2] ; D12 ; 7 ; 51 ; 54 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[3] ; C12 ; 7 ; 54 ; 54 ; 28 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[4] ; A12 ; 7 ; 54 ; 54 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[5] ; B12 ; 7 ; 49 ; 54 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[6] ; A13 ; 7 ; 54 ; 54 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[7] ; A14 ; 7 ; 58 ; 54 ; 28 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[8] ; B14 ; 7 ; 56 ; 54 ; 0 ; 17 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[9] ; F15 ; 7 ; 69 ; 54 ; 0 ; 9 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; HEX0[0] ; C14 ; 7 ; 58 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[1] ; E15 ; 7 ; 74 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[2] ; C15 ; 7 ; 60 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[3] ; C16 ; 7 ; 62 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[4] ; E16 ; 7 ; 74 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[5] ; D17 ; 7 ; 74 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[6] ; C17 ; 7 ; 74 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[0] ; C18 ; 7 ; 69 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[1] ; D18 ; 6 ; 78 ; 49 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[2] ; E18 ; 6 ; 78 ; 49 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[3] ; B16 ; 7 ; 60 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[4] ; A17 ; 7 ; 64 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[5] ; A18 ; 7 ; 66 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[6] ; B17 ; 7 ; 69 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[0] ; B20 ; 6 ; 78 ; 44 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[1] ; A20 ; 7 ; 66 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[2] ; B19 ; 7 ; 69 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[3] ; A21 ; 6 ; 78 ; 44 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[4] ; B21 ; 6 ; 78 ; 43 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[5] ; C22 ; 6 ; 78 ; 35 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[6] ; B22 ; 6 ; 78 ; 43 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[0] ; F21 ; 6 ; 78 ; 35 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[1] ; E22 ; 6 ; 78 ; 33 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[2] ; E21 ; 6 ; 78 ; 33 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[3] ; C19 ; 7 ; 69 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[4] ; C20 ; 6 ; 78 ; 41 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[5] ; D19 ; 6 ; 78 ; 41 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[6] ; E17 ; 6 ; 78 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[0] ; A8 ; 7 ; 46 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[1] ; A9 ; 7 ; 46 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[2] ; A10 ; 7 ; 51 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[3] ; B10 ; 7 ; 46 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[4] ; D13 ; 7 ; 56 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[5] ; C13 ; 7 ; 58 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[6] ; E14 ; 7 ; 66 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[7] ; D14 ; 7 ; 56 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[8] ; A11 ; 7 ; 51 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[9] ; B11 ; 7 ; 49 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 13 / 60 ( 22 % ) ; 2.5V ; -- ; +; 7 ; 35 / 52 ( 67 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 449 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 439 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 437 ; 7 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A12 ; 435 ; 7 ; SW[4] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 433 ; 7 ; SW[6] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 425 ; 7 ; SW[7] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; HEX1[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A18 ; 405 ; 7 ; HEX1[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; HEX2[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A21 ; 371 ; 6 ; HEX2[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 443 ; 7 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B12 ; 441 ; 7 ; SW[5] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; SW[8] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; HEX1[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B17 ; 402 ; 7 ; HEX1[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; HEX2[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B20 ; 369 ; 6 ; HEX2[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B21 ; 367 ; 6 ; HEX2[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B22 ; 365 ; 6 ; HEX2[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; SW[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C13 ; 426 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C14 ; 424 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C15 ; 418 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C16 ; 416 ; 7 ; HEX0[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C17 ; 391 ; 7 ; HEX0[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C18 ; 400 ; 7 ; HEX1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C19 ; 397 ; 7 ; HEX3[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C20 ; 357 ; 6 ; HEX3[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; HEX2[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D13 ; 431 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D14 ; 428 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; HEX0[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D18 ; 385 ; 6 ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D19 ; 359 ; 6 ; HEX3[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E15 ; 390 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 388 ; 7 ; HEX0[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E17 ; 366 ; 6 ; HEX3[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E18 ; 387 ; 6 ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; HEX3[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E22 ; 333 ; 6 ; HEX3[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; SW[9] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; HEX3[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; LEDR[0] ; Incomplete set of assignments ; +; LEDR[1] ; Incomplete set of assignments ; +; LEDR[2] ; Incomplete set of assignments ; +; LEDR[3] ; Incomplete set of assignments ; +; LEDR[4] ; Incomplete set of assignments ; +; LEDR[5] ; Incomplete set of assignments ; +; LEDR[6] ; Incomplete set of assignments ; +; LEDR[7] ; Incomplete set of assignments ; +; LEDR[8] ; Incomplete set of assignments ; +; LEDR[9] ; Incomplete set of assignments ; +; HEX0[0] ; Incomplete set of assignments ; +; HEX0[1] ; Incomplete set of assignments ; +; HEX0[2] ; Incomplete set of assignments ; +; HEX0[3] ; Incomplete set of assignments ; +; HEX0[4] ; Incomplete set of assignments ; +; HEX0[5] ; Incomplete set of assignments ; +; HEX0[6] ; Incomplete set of assignments ; +; HEX1[0] ; Incomplete set of assignments ; +; HEX1[1] ; Incomplete set of assignments ; +; HEX1[2] ; Incomplete set of assignments ; +; HEX1[3] ; Incomplete set of assignments ; +; HEX1[4] ; Incomplete set of assignments ; +; HEX1[5] ; Incomplete set of assignments ; +; HEX1[6] ; Incomplete set of assignments ; +; HEX2[0] ; Incomplete set of assignments ; +; HEX2[1] ; Incomplete set of assignments ; +; HEX2[2] ; Incomplete set of assignments ; +; HEX2[3] ; Incomplete set of assignments ; +; HEX2[4] ; Incomplete set of assignments ; +; HEX2[5] ; Incomplete set of assignments ; +; HEX2[6] ; Incomplete set of assignments ; +; HEX3[0] ; Incomplete set of assignments ; +; HEX3[1] ; Incomplete set of assignments ; +; HEX3[2] ; Incomplete set of assignments ; +; HEX3[3] ; Incomplete set of assignments ; +; HEX3[4] ; Incomplete set of assignments ; +; HEX3[5] ; Incomplete set of assignments ; +; HEX3[6] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; +; SW[8] ; Incomplete set of assignments ; +; SW[9] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+------------------------+--------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+------------------------+--------------+--------------+ +; |part5 ; 25 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 48 ; 0 ; 25 (1) ; 0 (0) ; 0 (0) ; 0 ; |part5 ; part5 ; work ; +; |Mux_4to1:comb_3| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; |part5|Mux_4to1:comb_3 ; Mux_4to1 ; work ; +; |Mux_4to1:comb_4| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part5|Mux_4to1:comb_4 ; Mux_4to1 ; work ; +; |Mux_4to1:comb_5| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; |part5|Mux_4to1:comb_5 ; Mux_4to1 ; work ; +; |Mux_4to1:comb_6| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; |part5|Mux_4to1:comb_6 ; Mux_4to1 ; work ; +; |sevenSegment:S0| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part5|sevenSegment:S0 ; sevenSegment ; work ; +; |sevenSegment:S1| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part5|sevenSegment:S1 ; sevenSegment ; work ; +; |sevenSegment:S2| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part5|sevenSegment:S2 ; sevenSegment ; work ; +; |sevenSegment:S3| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part5|sevenSegment:S3 ; sevenSegment ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+------------------------+--------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[5] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-----------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------+-------------------+---------+ +; SW[0] ; ; ; +; - Mux_4to1:comb_5|Mux1~0 ; 0 ; 6 ; +; - Mux_4to1:comb_3|Mux1~0 ; 0 ; 6 ; +; - LEDR[0]~output ; 0 ; 6 ; +; SW[1] ; ; ; +; - Mux_4to1:comb_5|Mux0~0 ; 0 ; 6 ; +; - Mux_4to1:comb_3|Mux0~0 ; 0 ; 6 ; +; - LEDR[1]~output ; 0 ; 6 ; +; SW[2] ; ; ; +; - Mux_4to1:comb_6|Mux1~0 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux1~1 ; 0 ; 6 ; +; - LEDR[2]~output ; 0 ; 6 ; +; SW[3] ; ; ; +; - Mux_4to1:comb_6|Mux0~0 ; 1 ; 6 ; +; - Mux_4to1:comb_5|Mux0~1 ; 1 ; 6 ; +; - LEDR[3]~output ; 1 ; 6 ; +; SW[4] ; ; ; +; - Mux_4to1:comb_5|Mux1~0 ; 1 ; 6 ; +; - Mux_4to1:comb_3|Mux1~0 ; 1 ; 6 ; +; - LEDR[4]~output ; 1 ; 6 ; +; SW[5] ; ; ; +; - Mux_4to1:comb_5|Mux0~0 ; 0 ; 6 ; +; - Mux_4to1:comb_3|Mux0~0 ; 0 ; 6 ; +; - LEDR[5]~output ; 0 ; 6 ; +; SW[6] ; ; ; +; - Mux_4to1:comb_6|Mux1~0 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux1~1 ; 0 ; 6 ; +; - LEDR[6]~output ; 0 ; 6 ; +; SW[7] ; ; ; +; - Mux_4to1:comb_6|Mux0~0 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux0~1 ; 0 ; 6 ; +; - LEDR[7]~output ; 0 ; 6 ; +; SW[8] ; ; ; +; - Mux_4to1:comb_6|Mux1~1 ; 0 ; 6 ; +; - Mux_4to1:comb_6|Mux0~1 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux1~2 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux0~2 ; 0 ; 6 ; +; - Mux_4to1:comb_4|Mux1~0 ; 0 ; 6 ; +; - Mux_4to1:comb_4|Mux0~0 ; 0 ; 6 ; +; - Mux_4to1:comb_3|Mux1~1 ; 0 ; 6 ; +; - Mux_4to1:comb_3|Mux0~1 ; 0 ; 6 ; +; - sevenSegment:S0|Decoder0~8 ; 0 ; 6 ; +; - sevenSegment:S0|Decoder0~9 ; 0 ; 6 ; +; - sevenSegment:S1|Decoder0~8 ; 0 ; 6 ; +; - sevenSegment:S1|Decoder0~9 ; 0 ; 6 ; +; - sevenSegment:S2|Decoder0~8 ; 0 ; 6 ; +; - sevenSegment:S2|Decoder0~9 ; 0 ; 6 ; +; - sevenSegment:S3|Decoder0~8 ; 0 ; 6 ; +; - sevenSegment:S3|Decoder0~9 ; 0 ; 6 ; +; - LEDR[8]~output ; 0 ; 6 ; +; SW[9] ; ; ; +; - Mux_4to1:comb_6|Mux1~0 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux1~0 ; 0 ; 6 ; +; - Mux_4to1:comb_6|Mux0~0 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux0~0 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux1~1 ; 0 ; 6 ; +; - Mux_4to1:comb_5|Mux0~1 ; 0 ; 6 ; +; - Mux_4to1:comb_3|Mux1~0 ; 0 ; 6 ; +; - Mux_4to1:comb_3|Mux0~0 ; 0 ; 6 ; +; - LEDR[9]~output ; 0 ; 6 ; ++-----------------------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 65 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 10 / 5,382 ( < 1 % ) ; +; C4 interconnects ; 66 / 106,704 ( < 1 % ) ; +; Direct links ; 10 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 12 / 49,760 ( < 1 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 10 / 5,406 ( < 1 % ) ; +; R4 interconnects ; 54 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 8.33) ; Number of LABs (Total = 3) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 8.33) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 3) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 7.33) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 48 ; 48 ; 0 ; 0 ; 48 ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 38 ; 0 ; 0 ; 0 ; 10 ; 38 ; 0 ; 10 ; 0 ; 0 ; 38 ; 0 ; 48 ; 48 ; 48 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 48 ; 0 ; 0 ; 48 ; 48 ; 0 ; 0 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 10 ; 48 ; 48 ; 48 ; 38 ; 10 ; 48 ; 38 ; 48 ; 48 ; 10 ; 48 ; 0 ; 0 ; 0 ; 48 ; 48 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device 10M50DAF484C6GES for design "part5" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y44 to location X78_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.06 seconds. +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Info (144001): Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings + Info: Peak virtual memory: 1082 megabytes + Info: Processing ended: Tue Apr 20 23:30:26 2021 + Info: Elapsed time: 00:00:21 + Info: Total CPU time (on all processors): 00:00:24 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.smsg. + + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.smsg b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.summary b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.summary new file mode 100644 index 0000000..7a07bb2 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Tue Apr 20 23:30:26 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part5 +Top-level Entity Name : part5 +Family : MAX 10 +Device : 10M50DAF484C6GES +Timing Models : Preliminary +Total logic elements : 25 / 49,760 ( < 1 % ) + Total combinational functions : 25 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 48 / 360 ( 13 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.flow.rpt b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.flow.rpt new file mode 100644 index 0000000..486fc8f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.flow.rpt @@ -0,0 +1,131 @@ +Flow report for part5 +Tue Apr 20 23:30:41 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Tue Apr 20 23:30:33 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part5 ; +; Top-level Entity Name ; part5 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 25 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 25 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 48 / 360 ( 13 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/20/2021 23:29:48 ; +; Main task ; Compilation ; +; Revision Name ; part5 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 146063716074696.161897938829626 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:16 ; 1.0 ; 390 MB ; 00:00:32 ; +; Fitter ; 00:00:21 ; 1.0 ; 1082 MB ; 00:00:24 ; +; Assembler ; 00:00:05 ; 1.0 ; 356 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:07 ; 1.0 ; 507 MB ; 00:00:07 ; +; Total ; 00:00:49 ; -- ; -- ; 00:01:08 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+-------------------+------------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+-------------------+------------------+------------+----------------+ +; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; ++----------------------+-------------------+------------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 +quartus_fit --read_settings_files=off --write_settings_files=off part5 -c part5 +quartus_asm --read_settings_files=off --write_settings_files=off part5 -c part5 +quartus_sta part5 -c part5 + + + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.jdi b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.jdi new file mode 100644 index 0000000..7d5463d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.map.rpt b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.map.rpt new file mode 100644 index 0000000..62e48bb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.map.rpt @@ -0,0 +1,351 @@ +Analysis & Synthesis report for part5 +Tue Apr 20 23:30:04 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Tue Apr 20 23:30:04 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part5 ; +; Top-level Entity Name ; part5 ; +; Family ; MAX 10 ; +; Total logic elements ; 24 ; +; Total combinational functions ; 24 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 48 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Top-level entity name ; part5 ; part5 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------+---------+ +; part5.v ; yes ; User Verilog HDL File ; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v ; ; ++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimated Total logic elements ; 24 ; +; ; ; +; Total combinational functions ; 24 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 8 ; +; -- 3 input functions ; 16 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 24 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 48 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; SW[8]~input ; +; Maximum fan-out ; 17 ; +; Total fan-out ; 166 ; +; Average fan-out ; 1.38 ; ++---------------------------------------------+-------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+------------------------+--------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+------------------------+--------------+--------------+ +; |part5 ; 24 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 48 ; 0 ; 0 ; |part5 ; part5 ; work ; +; |Mux_4to1:comb_3| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|Mux_4to1:comb_3 ; Mux_4to1 ; work ; +; |Mux_4to1:comb_4| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|Mux_4to1:comb_4 ; Mux_4to1 ; work ; +; |Mux_4to1:comb_5| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|Mux_4to1:comb_5 ; Mux_4to1 ; work ; +; |Mux_4to1:comb_6| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|Mux_4to1:comb_6 ; Mux_4to1 ; work ; +; |sevenSegment:S0| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|sevenSegment:S0 ; sevenSegment ; work ; +; |sevenSegment:S1| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|sevenSegment:S1 ; sevenSegment ; work ; +; |sevenSegment:S2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|sevenSegment:S2 ; sevenSegment ; work ; +; |sevenSegment:S3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|sevenSegment:S3 ; sevenSegment ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+------------------------+--------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 48 ; +; cycloneiii_lcell_comb ; 28 ; +; normal ; 28 ; +; 1 data inputs ; 4 ; +; 3 data inputs ; 16 ; +; 4 data inputs ; 8 ; +; ; ; +; Max LUT depth ; 3.00 ; +; Average LUT depth ; 2.97 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Tue Apr 20 23:29:48 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 3 design units, including 3 entities, in source file part5.v + Info (12023): Found entity 1: sevenSegment File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 1 + Info (12023): Found entity 2: Mux_4to1 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 16 + Info (12023): Found entity 3: part5 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 33 +Critical Warning (10846): Verilog HDL Instantiation warning at part5.v(41): instance has no name File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 41 +Critical Warning (10846): Verilog HDL Instantiation warning at part5.v(43): instance has no name File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 43 +Critical Warning (10846): Verilog HDL Instantiation warning at part5.v(45): instance has no name File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 45 +Critical Warning (10846): Verilog HDL Instantiation warning at part5.v(47): instance has no name File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 47 +Info (12127): Elaborating entity "part5" for the top level hierarchy +Info (12128): Elaborating entity "Mux_4to1" for hierarchy "Mux_4to1:comb_3" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 41 +Info (12128): Elaborating entity "sevenSegment" for hierarchy "sevenSegment:S0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/LAB1/Part 5/part5.v Line: 49 +Info (286030): Timing-Driven Synthesis is running +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 72 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 10 input pins + Info (21059): Implemented 38 output pins + Info (21061): Implemented 24 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 55 warnings + Info: Peak virtual memory: 396 megabytes + Info: Processing ended: Tue Apr 20 23:30:04 2021 + Info: Elapsed time: 00:00:16 + Info: Total CPU time (on all processors): 00:00:32 + + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.map.summary b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.map.summary new file mode 100644 index 0000000..f903155 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Tue Apr 20 23:30:04 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part5 +Top-level Entity Name : part5 +Family : MAX 10 +Total logic elements : 24 + Total combinational functions : 24 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 48 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.pin b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.pin new file mode 100644 index 0000000..bf8fc4d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2020 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +CHIP "part5" ASSIGNED TO AN: 10M50DAF484C6GES + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +LEDR[0] : A8 : output : 2.5 V : : 7 : Y +LEDR[1] : A9 : output : 2.5 V : : 7 : Y +LEDR[2] : A10 : output : 2.5 V : : 7 : Y +LEDR[8] : A11 : output : 2.5 V : : 7 : Y +SW[4] : A12 : input : 2.5 V : : 7 : Y +SW[6] : A13 : input : 2.5 V : : 7 : Y +SW[7] : A14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +HEX1[4] : A17 : output : 2.5 V : : 7 : Y +HEX1[5] : A18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +HEX2[1] : A20 : output : 2.5 V : : 7 : Y +HEX2[3] : A21 : output : 2.5 V : : 6 : Y +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +LEDR[3] : B10 : output : 2.5 V : : 7 : Y +LEDR[9] : B11 : output : 2.5 V : : 7 : Y +SW[5] : B12 : input : 2.5 V : : 7 : Y +GND : B13 : gnd : : : : +SW[8] : B14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +HEX1[3] : B16 : output : 2.5 V : : 7 : Y +HEX1[6] : B17 : output : 2.5 V : : 7 : Y +GND : B18 : gnd : : : : +HEX2[2] : B19 : output : 2.5 V : : 7 : Y +HEX2[0] : B20 : output : 2.5 V : : 6 : Y +HEX2[4] : B21 : output : 2.5 V : : 6 : Y +HEX2[6] : B22 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[0] : C10 : input : 2.5 V : : 7 : Y +SW[1] : C11 : input : 2.5 V : : 7 : Y +SW[3] : C12 : input : 2.5 V : : 7 : Y +LEDR[5] : C13 : output : 2.5 V : : 7 : Y +HEX0[0] : C14 : output : 2.5 V : : 7 : Y +HEX0[2] : C15 : output : 2.5 V : : 7 : Y +HEX0[3] : C16 : output : 2.5 V : : 7 : Y +HEX0[6] : C17 : output : 2.5 V : : 7 : Y +HEX1[0] : C18 : output : 2.5 V : : 7 : Y +HEX3[3] : C19 : output : 2.5 V : : 7 : Y +HEX3[4] : C20 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +HEX2[5] : C22 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +SW[2] : D12 : input : 2.5 V : : 7 : Y +LEDR[4] : D13 : output : 2.5 V : : 7 : Y +LEDR[7] : D14 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +HEX0[5] : D17 : output : 2.5 V : : 7 : Y +HEX1[1] : D18 : output : 2.5 V : : 6 : Y +HEX3[5] : D19 : output : 2.5 V : : 6 : Y +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +LEDR[6] : E14 : output : 2.5 V : : 7 : Y +HEX0[1] : E15 : output : 2.5 V : : 7 : Y +HEX0[4] : E16 : output : 2.5 V : : 7 : Y +HEX3[6] : E17 : output : 2.5 V : : 6 : Y +HEX1[2] : E18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +HEX3[2] : E21 : output : 2.5 V : : 6 : Y +HEX3[1] : E22 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +SW[9] : F15 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +HEX3[0] : F21 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.pof b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.pof new file mode 100644 index 0000000..a334abc Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.pof differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sld b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sof b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sof new file mode 100644 index 0000000..5a5de64 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sof differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sta.rpt b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sta.rpt new file mode 100644 index 0000000..86d5537 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sta.rpt @@ -0,0 +1,722 @@ +Timing Analyzer report for part5 +Tue Apr 20 23:30:41 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; part5 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.7% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX3[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX3[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX3[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX3[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX3[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX3[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX3[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX3[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX3[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX3[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX3[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 10 ; 10 ; +; Unconstrained Input Port Paths ; 242 ; 242 ; +; Unconstrained Output Ports ; 38 ; 38 ; +; Unconstrained Output Port Paths ; 242 ; 242 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Tue Apr 20 23:30:34 2021 +Info: Command: quartus_sta part5 -c part5 +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 56 warnings + Info: Peak virtual memory: 507 megabytes + Info: Processing ended: Tue Apr 20 23:30:41 2021 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:07 + + diff --git a/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sta.summary b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/output_files/part5.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/part5.qpf b/EE203/Noah Woodlee/LAB1/Part 5/part5.qpf new file mode 100644 index 0000000..ba2db1d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/part5.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:34:56 April 08, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "20:34:56 April 08, 2021" + +# Revisions + +PROJECT_REVISION = "part5" diff --git a/EE203/Noah Woodlee/LAB1/Part 5/part5.qsf b/EE203/Noah Woodlee/LAB1/Part 5/part5.qsf new file mode 100644 index 0000000..e08d605 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/part5.qsf @@ -0,0 +1,110 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:34:56 April 08, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part5_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:34:56 APRIL 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part5.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 5/part5.qsf.bak b/EE203/Noah Woodlee/LAB1/Part 5/part5.qsf.bak new file mode 100644 index 0000000..5a48b2b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/part5.qsf.bak @@ -0,0 +1,54 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:34:56 April 08, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part5_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:34:56 APRIL 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part5.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 5/part5.qws b/EE203/Noah Woodlee/LAB1/Part 5/part5.qws new file mode 100644 index 0000000..07c67da Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part 5/part5.qws differ diff --git a/EE203/Noah Woodlee/LAB1/Part 5/part5.v b/EE203/Noah Woodlee/LAB1/Part 5/part5.v new file mode 100644 index 0000000..f2ee1f1 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/part5.v @@ -0,0 +1,56 @@ +module sevenSegment (IN, OUT); + input [1:0]IN; + output reg [6:0]OUT; + + always @ (*) + begin + case (IN[1:0]) + 2'b00: OUT=7'b010_0001; + 2'b01: OUT=7'b000_0110; + 2'b10: OUT=7'b111_1001; + 2'b11: OUT=7'b100_0000; + endcase + end +endmodule + +module Mux_4to1 (IN1, IN2, IN3, IN4, SEL, M); + input [1:0] IN1, IN2, IN3, IN4; + input [1:0] SEL; + output reg[1:0] M; + + always@(*) + begin + case(SEL[1:0]) + 2'b00: M=IN1; + 2'b01: M=IN2; + 2'b10: M=IN3; + 2'b11: M=IN4; + endcase + end + +endmodule + +module part5 (SW, LEDR, HEX0, HEX1, HEX2, HEX3); + input [9:0]SW; + output [6:0]HEX0, HEX1, HEX2, HEX3; + output [9:0]LEDR; + + wire[1:0] M1, M2, M3, M0; + + // Chooses 'd' when SW[9:8] is 00 + Mux_4to1 (SW[7:6], SW[5:4], SW[3:2], SW[1:0], SW[9:8], M3); + // Chooses 'E' when SW[9:8] is 00 + Mux_4to1 (SW[5:4], SW[3:2], SW[1:0], SW[7:6], SW[9:8], M2); + // Chooses '1' when SW[9:8] is 00 + Mux_4to1 (SW[3:2], SW[1:0], SW[7:6], SW[5:4], SW[9:8], M1); + // Chooses '0' when SW[9:8] is 00 + Mux_4to1 (SW[1:0], SW[7:6], SW[5:4], SW[3:2], SW[9:8], M0); + + sevenSegment S0(M0, HEX0); + sevenSegment S1(M1, HEX1); + sevenSegment S2(M2, HEX2); + sevenSegment S3(M3, HEX3); + + assign LEDR=SW; + +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part 5/part5_assignment_defaults.qdf b/EE203/Noah Woodlee/LAB1/Part 5/part5_assignment_defaults.qdf new file mode 100644 index 0000000..93cd12b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part 5/part5_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 23:27:08 April 20, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value ENABLE +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 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SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/EE203/Noah Woodlee/LAB1/Part3/Part3.qpf b/EE203/Noah Woodlee/LAB1/Part3/Part3.qpf new file mode 100644 index 0000000..ebdd84a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/Part3.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:04:10 March 11, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "20:04:10 March 11, 2021" + +# Revisions + +PROJECT_REVISION = "Part3" diff --git a/EE203/Noah Woodlee/LAB1/Part3/Part3.qsf b/EE203/Noah Woodlee/LAB1/Part3/Part3.qsf new file mode 100644 index 0000000..6cdeed1 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/Part3.qsf @@ -0,0 +1,54 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:04:10 March 11, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Part3_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY Part3 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:04:10 MARCH 11, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE Part3.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/Part3.qws b/EE203/Noah Woodlee/LAB1/Part3/Part3.qws new file mode 100644 index 0000000..6bc29fe Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/Part3.qws differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/Part3.v b/EE203/Noah Woodlee/LAB1/Part3/Part3.v new file mode 100644 index 0000000..4669482 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/Part3.v @@ -0,0 +1,19 @@ +module Part3 (SW,LEDR); + input [9:0]SW; + output [9:0]LEDR; + wire [1:0] S, U, V, W, X, M; + wire [1:0] U_V, W_X; + assign S[1:0]=SW[9:8]; + assign U=SW[1:0]; + assign V=SW[3:2]; + assign W=SW[5:4]; + assign X=SW[7:6]; + assign U_V[0]=(~S[0] & U[0])|(S[0] & V[0]); + assign U_V[1]=(~S[0] & U[1])|(S[0] & V[1]); + assign W_X[0]=(~S[0] & W[0])|(S[0] & X[0]); + assign W_X[1]=(~S[0] & W[1])|(S[0] & X[1]); + assign M[0]=(~S[0] & U_V[0])|(S[0] & W_X[0]); + assign M[1]=(~S[1] & U_V[1])|(S[1] & W_X[1]); + assign LEDR[1:0]=M; + assign LEDR[9:2]=8`b0; + endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/Part3.v.bak b/EE203/Noah Woodlee/LAB1/Part3/Part3.v.bak new file mode 100644 index 0000000..d6238a5 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/Part3.v.bak @@ -0,0 +1,15 @@ +module Part3 (SW,LEDR); + input [9:0]SW; + output [9:0]LEDR; + wire [1:0] S, U, V, W, X, M; + wire S[1:0] = U_v, W_X; + assign U=SW[1:0]; + assign V=SW[3:2]; + assign W=SW[5:4]; + assign X=SW[4:6]; + assign U_V[0]=(~S[0] & U[0])|(~S[0] & V[0]); + assign U_V[1]=(~S[0] & U[1])|(~S[0] & V[1]); + assign W_X[0]=(~S[0] & W[0])|(~S[0] & X[0]); + assign W_X[1]=(~S[0] & W[1])|(~S[0] & X[1]); + assign M[0]=(~S[0] & U_V[0])|(~S[0] & W_X[0]); + assign M[1]=(~S[1] & U_V[1])|(~S[1] & W_X[1]); \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/Waveform.vwf b/EE203/Noah Woodlee/LAB1/Part3/Waveform.vwf new file mode 100644 index 0000000..a015de5 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/Waveform.vwf @@ -0,0 +1,740 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3 +onerror {exit -code 1} +vlib work +vlog -work work Part3.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Part3_vlg_vec_tst +vcd file -direction Part3.msim.vcd +vcd add -internal Part3_vlg_vec_tst/* +vcd add -internal Part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + + +onerror {exit -code 1} +vlib work +vlog -work work Part3.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Part3_vlg_vec_tst +vcd file -direction Part3.msim.vcd +vcd add -internal Part3_vlg_vec_tst/* +vcd add -internal Part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 470.0; + LEVEL 1 FOR 530.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 230.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 270.0; + LEVEL 1 FOR 260.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 740.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 740.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 470.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + LEVEL X FOR 260.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 470.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + LEVEL X FOR 260.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 230.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL X FOR 530.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 230.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL X FOR 530.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL X FOR 770.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL X FOR 770.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.(0).cnf.cdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.(0).cnf.cdb new file mode 100644 index 0000000..3ed5f85 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.(0).cnf.hdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.(0).cnf.hdb new file mode 100644 index 0000000..0c02d17 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm.qmsg b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm.qmsg new file mode 100644 index 0000000..2b8d0db --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615517021969 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615517021979 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 20:43:41 2021 " "Processing started: Thu Mar 11 20:43:41 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615517021979 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1615517021979 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Part3 -c Part3 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Part3 -c Part3" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1615517021979 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1615517022269 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1615517024039 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1615517024189 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615517025249 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 20:43:45 2021 " "Processing ended: Thu Mar 11 20:43:45 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615517025249 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615517025249 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615517025249 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1615517025249 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm.rdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm.rdb new file mode 100644 index 0000000..61cedbb Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm_labs.ddb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm_labs.ddb new file mode 100644 index 0000000..93131b8 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cbx.xml b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cbx.xml new file mode 100644 index 0000000..aca5124 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.bpm b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.bpm new file mode 100644 index 0000000..fd4e935 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.cdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.cdb new file mode 100644 index 0000000..6f72c6a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.hdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.hdb new file mode 100644 index 0000000..cfcf6bb Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.idb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.idb new file mode 100644 index 0000000..90eeba9 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.idb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.logdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.logdb new file mode 100644 index 0000000..9b49f25 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.logdb @@ -0,0 +1,62 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;20;0;0;20;20;0;10;0;0;10;0;10;10;0;0;0;10;0;0;0;0;0;20;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,20;20;20;20;20;0;20;20;0;0;20;10;20;20;10;20;10;10;20;20;20;10;20;20;20;20;20;0;20;20, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,SW[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.rdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.rdb new file mode 100644 index 0000000..1be7f73 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp_merge.kpt b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp_merge.kpt new file mode 100644 index 0000000..64511c1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.db_info b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.db_info new file mode 100644 index 0000000..022c677 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Version_Index = 419480576 +Creation_Time = Thu Mar 11 20:40:28 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.eda.qmsg b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.eda.qmsg new file mode 100644 index 0000000..04147b9 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615517258442 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615517258442 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2016 Intel Corporation. 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" "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615517258442 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 20:47:38 2021 " "Processing started: Thu Mar 11 20:47:38 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615517258442 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1615517258442 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/\" Part3 -c Part3 " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/\" Part3 -c Part3" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1615517258442 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1615517011405 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1615517011405 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "Part3 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"Part3\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1615517011415 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615517011455 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615517011455 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1615517011685 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1615517011685 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615517011795 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1615517011795 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 56 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 58 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 60 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 62 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 64 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 66 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 68 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615517011795 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 70 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615517011795 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1615517011795 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615517011795 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615517011795 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615517011795 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615517011795 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1615517011795 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "20 20 " "No exact pin location assignment(s) for 20 pins of 20 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1615517012035 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Part3.sdc " "Synopsys Design Constraints File file not found: 'Part3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1615517012245 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1615517012245 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1615517012245 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1615517012245 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1615517012245 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1615517012245 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1615517012245 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1615517012255 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615517012255 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615517012255 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615517012255 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615517012255 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1615517012255 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1615517012255 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1615517012255 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1615517012255 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1615517012255 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1615517012255 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "20 unused 2.5V 10 10 0 " "Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 10 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1615517012255 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1615517012255 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1615517012255 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 20 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 36 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 48 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 48 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 40 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 60 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 52 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 32 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615517012255 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1615517012255 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1615517012255 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615517012285 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1615517012285 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1615517013445 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615517013495 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1615517013525 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1615517013915 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615517013915 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1615517014375 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1615517015785 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1615517015785 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1615517015885 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1615517015885 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1615517015885 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615517015885 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1615517016106 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615517016112 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615517016353 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615517016353 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615517016703 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615517017193 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1615517017473 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5904 " "Peak virtual memory: 5904 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615517017983 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 20:43:37 2021 " "Processing ended: Thu Mar 11 20:43:37 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615517017983 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615517017983 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615517017983 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1615517017983 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.hier_info b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.hier_info new file mode 100644 index 0000000..7d5dfe8 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.hier_info @@ -0,0 +1,33 @@ +|Part3 +SW[0] => U_V.IN0 +SW[1] => U_V.IN0 +SW[2] => U_V.IN0 +SW[3] => U_V.IN0 +SW[4] => W_X.IN0 +SW[5] => W_X.IN0 +SW[6] => W_X.IN0 +SW[7] => W_X.IN0 +SW[8] => U_V.IN1 +SW[8] => U_V.IN1 +SW[8] => W_X.IN1 +SW[8] => W_X.IN1 +SW[8] => M.IN1 +SW[8] => W_X.IN1 +SW[8] => U_V.IN1 +SW[8] => W_X.IN1 +SW[8] => U_V.IN1 +SW[8] => M.IN1 +SW[9] => M.IN1 +SW[9] => M.IN1 +LEDR[0] << M.DB_MAX_OUTPUT_PORT_TYPE +LEDR[1] << M.DB_MAX_OUTPUT_PORT_TYPE +LEDR[2] << +LEDR[3] << +LEDR[4] << +LEDR[5] << +LEDR[6] << +LEDR[7] << +LEDR[8] << +LEDR[9] << + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.hif b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.hif new file mode 100644 index 0000000..13afcda Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.hif differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.html b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.html new file mode 100644 index 0000000..7d68592 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.rdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.rdb new file mode 100644 index 0000000..c179f4d Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.txt b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.txt new file mode 100644 index 0000000..dbfe520 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.ammdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.ammdb new file mode 100644 index 0000000..a4afc79 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.bpm b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.bpm new file mode 100644 index 0000000..6dfff06 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.bpm differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.cdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.cdb new file mode 100644 index 0000000..3146154 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.hdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.hdb new file mode 100644 index 0000000..8eb9601 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.kpt b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.kpt new file mode 100644 index 0000000..1e09325 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.logdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.qmsg b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.qmsg new file mode 100644 index 0000000..dcce57b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.qmsg @@ -0,0 +1,14 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615517000565 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615517000565 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 20:43:20 2021 " "Processing started: Thu Mar 11 20:43:20 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615517000565 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615517000565 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Part3 -c Part3 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Part3 -c Part3" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615517000565 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1615517000915 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1615517000915 ""} +{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "b0 Part3.v(18) " "Verilog HDL Compiler Directive warning at Part3.v(18): text macro \"b0\" is undefined" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 18 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1615517009145 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part3.v 1 1 " "Found 1 design units, including 1 entities, in source file part3.v" { { "Info" "ISGN_ENTITY_NAME" "1 Part3 " "Found entity 1: Part3" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615517009145 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615517009145 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "Part3 " "Elaborating entity \"Part3\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1615517009175 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[2\] GND " "Pin \"LEDR\[2\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615517009505 "|Part3|LEDR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[3\] GND " "Pin \"LEDR\[3\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615517009505 "|Part3|LEDR[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] GND " "Pin \"LEDR\[4\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615517009505 "|Part3|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] VCC " "Pin \"LEDR\[5\]\" is stuck at VCC" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615517009505 "|Part3|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615517009505 "|Part3|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615517009505 "|Part3|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615517009505 "|Part3|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615517009505 "|Part3|LEDR[9]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1615517009505 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1615517009555 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1615517009955 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615517009955 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 2 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1615517010005 "|Part3|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 2 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1615517010005 "|Part3|SW[4]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1615517010005 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "23 " "Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1615517010005 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1615517010005 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1615517010005 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1615517010005 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4781 " "Peak virtual memory: 4781 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615517010035 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 20:43:30 2021 " "Processing ended: Thu Mar 11 20:43:30 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615517010035 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615517010035 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615517010035 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1615517010035 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.rdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.rdb new file mode 100644 index 0000000..d5f08fe Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.cdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.cdb new file mode 100644 index 0000000..08e0bbf Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.hdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.hdb new file mode 100644 index 0000000..1de4ce1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.logdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.pre_map.hdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.pre_map.hdb new file mode 100644 index 0000000..e7b32c0 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.pre_map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.root_partition.map.reg_db.cdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..1490d4e Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.root_partition.map.reg_db.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.routing.rdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.routing.rdb new file mode 100644 index 0000000..296825f Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.routing.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv.hdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv.hdb new file mode 100644 index 0000000..6b25e5a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv_sg.cdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv_sg.cdb new file mode 100644 index 0000000..ea01cfb Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv_sg.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv_sg_swap.cdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv_sg_swap.cdb new file mode 100644 index 0000000..0be030c Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.rtlv_sg_swap.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sld_design_entry.sci b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sld_design_entry.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sld_design_entry.sci differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sld_design_entry_dsc.sci b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sld_design_entry_dsc.sci new file mode 100644 index 0000000..1bd84ed Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.smart_action.txt b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.smart_action.txt new file mode 100644 index 0000000..f1e1649 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta.qmsg b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta.qmsg new file mode 100644 index 0000000..8e08b13 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta.qmsg @@ -0,0 +1,50 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615517027899 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615517027899 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 20:43:47 2021 " "Processing started: Thu Mar 11 20:43:47 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615517027899 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517027899 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Part3 -c Part3 " "Command: quartus_sta Part3 -c Part3" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517027899 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1615517028009 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028159 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028159 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028199 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028199 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Part3.sdc " "Synopsys Design Constraints File file not found: 'Part3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028469 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028469 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028469 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028469 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028469 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028469 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1615517028469 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028469 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615517028479 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028479 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1615517028479 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028479 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028479 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028489 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028499 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028509 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615517028509 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028529 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028899 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028969 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028969 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028969 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028969 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028969 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028979 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028979 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028979 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028979 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517028989 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615517028999 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029179 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029179 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029179 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029179 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029179 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029179 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029189 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029189 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029189 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517029999 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517030009 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615517030069 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 20:43:50 2021 " "Processing ended: Thu Mar 11 20:43:50 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615517030069 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615517030069 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615517030069 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615517030069 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta.rdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta.rdb new file mode 100644 index 0000000..af2511c Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta.rdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta_cmp.7_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta_cmp.7_slow_1200mv_85c.tdb new file mode 100644 index 0000000..a0c954b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.sta_cmp.7_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tis_db_list.ddb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tis_db_list.ddb new file mode 100644 index 0000000..eda1a82 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..4046b12 Binary files /dev/null and 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--git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..014f918 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tmw_info b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tmw_info new file mode 100644 index 0000000..13b4dfb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:30 +start_analysis_synthesis:s:00:00:10-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:11-start_full_compilation +start_assembler:s:00:00:06-start_full_compilation +start_timing_analyzer:s:00:00:03-start_full_compilation diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.vpr.ammdb b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.vpr.ammdb new file mode 100644 index 0000000..7963d6a Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..db68b29 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ii_0c_slow.hsd b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..d223770 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ii_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ii_85c_slow.hsd b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..68203ec Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/db/Part3.zippleback_io_sim_cache.ii_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/Part3_partition_pins.json b/EE203/Noah Woodlee/LAB1/Part3/db/Part3_partition_pins.json new file mode 100644 index 0000000..14273a6 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/Part3_partition_pins.json @@ -0,0 +1,49 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "LEDR[0]", + "strict" : false + }, + { + "name" : "LEDR[1]", + "strict" : false + }, + { + "name" : "SW[6]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[8]", + "strict" : false + }, + { + "name" : "SW[5]", + "strict" : false + }, + { + "name" : "SW[9]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[7]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/db/prev_cmp_Part3.qmsg b/EE203/Noah Woodlee/LAB1/Part3/db/prev_cmp_Part3.qmsg new file mode 100644 index 0000000..cc9770d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/db/prev_cmp_Part3.qmsg @@ -0,0 +1,132 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615516876157 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615516876157 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 20:41:16 2021 " "Processing started: Thu Mar 11 20:41:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615516876157 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615516876157 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Part3 -c Part3 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Part3 -c Part3" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615516876157 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1615516876509 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1615516876509 ""} +{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "b0 Part3.v(18) " "Verilog HDL Compiler Directive warning at Part3.v(18): text macro \"b0\" is undefined" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 18 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1615516884892 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part3.v 1 1 " "Found 1 design units, including 1 entities, in source file part3.v" { { "Info" "ISGN_ENTITY_NAME" "1 Part3 " "Found entity 1: Part3" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615516884892 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615516884892 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "Part3 " "Elaborating entity \"Part3\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1615516884922 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[2\] GND " "Pin \"LEDR\[2\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615516885252 "|Part3|LEDR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[3\] GND " "Pin \"LEDR\[3\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615516885252 "|Part3|LEDR[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] GND " "Pin \"LEDR\[4\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615516885252 "|Part3|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] VCC " "Pin \"LEDR\[5\]\" is stuck at VCC" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615516885252 "|Part3|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615516885252 "|Part3|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615516885252 "|Part3|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615516885252 "|Part3|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615516885252 "|Part3|LEDR[9]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1615516885252 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1615516885312 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1615516885702 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615516885702 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 2 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1615516885762 "|Part3|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" { } { { "Part3.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v" 2 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1615516885762 "|Part3|SW[4]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1615516885762 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "23 " "Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1615516885762 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1615516885762 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1615516885762 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1615516885762 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4781 " "Peak virtual memory: 4781 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615516885792 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 20:41:25 2021 " "Processing ended: Thu Mar 11 20:41:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615516885792 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615516885792 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615516885792 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1615516885792 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1615516889012 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615516889022 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 20:41:28 2021 " "Processing started: Thu Mar 11 20:41:28 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615516889022 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1615516889022 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Part3 -c Part3 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off Part3 -c Part3" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1615516889022 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1615516889122 ""} +{ "Info" "0" "" "Project = Part3" { } { } 0 0 "Project = Part3" 0 0 "Fitter" 0 0 1615516889122 ""} +{ "Info" "0" "" "Revision = Part3" { } { } 0 0 "Revision = Part3" 0 0 "Fitter" 0 0 1615516889122 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1615516889212 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1615516889212 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "Part3 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"Part3\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1615516889212 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615516889262 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615516889262 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1615516889482 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1615516889482 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615516889592 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1615516889592 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 56 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 58 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 60 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 62 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 64 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 66 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 68 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615516889592 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 0 { 0 ""} 0 70 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615516889592 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1615516889592 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615516889592 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615516889592 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615516889592 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1615516889592 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1615516889592 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "20 20 " "No exact pin location assignment(s) for 20 pins of 20 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1615516889832 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Part3.sdc " "Synopsys Design Constraints File file not found: 'Part3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615516890042 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615516890042 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615516890042 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615516890042 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1615516890042 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1615516890042 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1615516890042 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1615516890042 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1615516890042 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1615516890042 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "20 unused 2.5V 10 10 0 " "Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 10 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1615516890052 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1615516890052 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1615516890052 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 20 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 36 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 48 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 48 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 40 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 60 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 52 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 32 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1615516890052 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1615516890052 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1615516890052 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615516890072 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1615516890082 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1615516891202 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615516891252 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1615516891282 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1615516891673 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615516891673 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1615516892133 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1615516893463 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1615516893463 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1615516893563 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1615516893563 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1615516893563 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615516893573 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1615516893773 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615516893783 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615516894033 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615516894033 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615516894373 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615516894843 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1615516895123 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5903 " "Peak virtual memory: 5903 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615516895643 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 20:41:35 2021 " "Processing ended: Thu Mar 11 20:41:35 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615516895643 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615516895643 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615516895643 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1615516895643 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1615516896653 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615516896663 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 20:41:36 2021 " "Processing started: Thu Mar 11 20:41:36 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615516896663 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1615516896663 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Part3 -c Part3 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Part3 -c Part3" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1615516896663 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1615516896953 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1615516898723 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1615516898863 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615516899922 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 20:41:39 2021 " "Processing ended: Thu Mar 11 20:41:39 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615516899922 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615516899922 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615516899922 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1615516899922 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1615516900525 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1615516901085 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615516901085 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 20:41:40 2021 " "Processing started: Thu Mar 11 20:41:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615516901085 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901085 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Part3 -c Part3 " "Command: quartus_sta Part3 -c Part3" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901085 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1615516901195 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901355 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901355 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901385 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901385 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Part3.sdc " "Synopsys Design Constraints File file not found: 'Part3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901655 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901655 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901655 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901655 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901655 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901655 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1615516901655 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901665 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615516901665 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901665 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1615516901665 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901675 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901675 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901685 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901695 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901695 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615516901705 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516901725 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902105 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902165 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902165 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902165 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902165 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902165 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902175 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902175 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902175 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902175 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902185 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1615516902185 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902365 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902365 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902365 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902365 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902375 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902375 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902375 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902375 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516902385 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516903195 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516903195 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4868 " "Peak virtual memory: 4868 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615516903255 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 20:41:43 2021 " "Processing ended: Thu Mar 11 20:41:43 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615516903255 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615516903255 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615516903255 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516903255 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 26 s " "Quartus Prime Full Compilation was successful. 0 errors, 26 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1615516903895 ""} diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..d89a873 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| George Totolos :| 08/22/2016:| Initial Revision +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a2885da --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +DE10_LITE_Golden_Top.v +platform_setup.tcl +filelist.txt diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..d9cea11 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,435 @@ +proc ::setup_project {} { +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name SDC_FILE DE10_LITE_Golden_Top.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS + +#============================================================ +# Accelerometer +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO + +#============================================================ +# Arduino +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..1c1dfa3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/home/gtotolos/Desktop/max10_de10_lite/Golden_Top/", + "acds_version" : "Version 16.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/de0_nano_soc_baseline.v b/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/de0_nano_soc_baseline.v new file mode 100644 index 0000000..2c2b670 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/de0_nano_soc_baseline.v @@ -0,0 +1,147 @@ +//--------------------------------------------------------------------------// +// Title: de0_nano_soc_baseline.v // +// Rev: Rev 0.1 // +// Last Revised: 09/14/2015 // +//--------------------------------------------------------------------------// +// Description: Baseline design file contains DE0 Nano SoC // +// Board pins and I/O Standards. // +//--------------------------------------------------------------------------// +//Copyright 2015 Altera Corporation. All rights reserved. Altera products +//are protected under numerous U.S. and foreign patents, maskwork rights, +//copyrights and other intellectual property laws. +// +//This reference design file, and your use thereof, is subject to and +//governed by the terms and conditions of the applicable Altera Reference +//Design License Agreement. By using this reference design file, you +//indicate your acceptance of such terms and conditions between you and +//Altera Corporation. In the event that you do not agree with such terms and +//conditions, you may not use the reference design file. Please promptly +//destroy any copies you have made. +// +//This reference design file being provided on an "as-is" basis and as an +//accommodation and therefore all warranties, representations or guarantees +//of any kind (whether express, implied or statutory) including, without +//limitation, warranties of merchantability, non-infringement, or fitness for +//a particular purpose, are specifically disclaimed. By making this +//reference design file available, Altera expressly does not recommend, +//suggest or require that this reference design file be used in combination +//with any other product not provided by Altera +//---------------------------------------------------------------------------- + +//Group Enable Definitions +//This lists every pinout group +//Users can enable any group by uncommenting the corresponding line below: +//`define enable_ADC +//`define enable_ARDUINO +//`define enable_GPIO0 +//`define enable_GPIO1 +//`define enable_HPS + +module de0_nano_soc_baseline( + + + //////////// CLOCK ////////// + input FPGA_CLK_50, + input FPGA_CLK2_50, + input FPGA_CLK3_50, + +`ifdef enable_ADC + //////////// ADC ////////// + /* 3.3-V LVTTL */ + output ADC_CONVST, + output ADC_SCLK, + output ADC_SDI, + input ADC_SDO, +`endif + +`ifdef enable_ARDUINO + //////////// ARDUINO //////////// + /* 3.3-V LVTTL */ + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + +`ifdef enable_GPIO0 + //////////// GPIO 0 //////////// + /* 3.3-V LVTTL */ + inout [35:0] GPIO_0, +`endif + +`ifdef enable_GPIO1 + //////////// GPIO 1 //////////// + /* 3.3-V LVTTL */ + inout [35:0] GPIO_1, +`endif + +`ifdef enable_HPS + //////////// HPS ////////// + /* 3.3-V LVTTL */ + inout HPS_CONV_USB_N, + + /* SSTL-15 Class I */ + output [14:0] HPS_DDR3_ADDR, + output [2:0] HPS_DDR3_BA, + output HPS_DDR3_CAS_N, + output HPS_DDR3_CKE, + output HPS_DDR3_CS_N, + output [3:0] HPS_DDR3_DM, + inout [31:0] HPS_DDR3_DQ, + output HPS_DDR3_ODT, + output HPS_DDR3_RAS_N, + output HPS_DDR3_RESET_N, + input HPS_DDR3_RZQ, + output HPS_DDR3_WE_N, + /* DIFFERENTIAL 1.5-V SSTL CLASS I */ + output HPS_DDR3_CK_N, + output HPS_DDR3_CK_P, + inout [3:0] HPS_DDR3_DQS_N, + inout [3:0] HPS_DDR3_DQS_P, + + /* 3.3-V LVTTL */ + output HPS_ENET_GTX_CLK, + inout HPS_ENET_INT_N, + output HPS_ENET_MDC, + inout HPS_ENET_MDIO, + input HPS_ENET_RX_CLK, + input [3:0] HPS_ENET_RX_DATA, + input HPS_ENET_RX_DV, + output [3:0] HPS_ENET_TX_DATA, + output HPS_ENET_TX_EN, + inout HPS_GSENSOR_INT, + inout HPS_I2C0_SCLK, + inout HPS_I2C0_SDAT, + inout HPS_I2C1_SCLK, + inout HPS_I2C1_SDAT, + inout HPS_KEY, + inout HPS_LED, + inout HPS_LTC_GPIO, + output HPS_SD_CLK, + inout HPS_SD_CMD, + inout [3:0] HPS_SD_DATA, + output HPS_SPIM_CLK, + input HPS_SPIM_MISO, + output HPS_SPIM_MOSI, + inout HPS_SPIM_SS, + input HPS_UART_RX, + output HPS_UART_TX, + input HPS_USB_CLKOUT, + inout [7:0] HPS_USB_DATA, + input HPS_USB_DIR, + input HPS_USB_NXT, + output HPS_USB_STP, +`endif + + //////////// KEY //////////// + /* 3.3-V LVTTL */ + input [1:0] KEY, + + //////////// LED //////////// + /* 3.3-V LVTTL */ + output [7:0] LED, + + //////////// SW //////////// + /* 3.3-V LVTTL */ + input [3:0] SW + +); +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/filelist.txt b/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/filelist.txt new file mode 100644 index 0000000..90052fb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/filelist.txt @@ -0,0 +1,3 @@ +filelist.txt +platform_setup.tcl +de0_nano_soc_baseline.v \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/platform_setup.tcl b/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/platform_setup.tcl new file mode 100644 index 0000000..2d0bcc6 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/platform_setup.tcl @@ -0,0 +1,582 @@ +proc ::setup_project {} { +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Full Version +# Date created = 11:02:36 September 14, 2015 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA4U23C6 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:02:36 SEPTEMBER 14, 2015" +set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name VERILOG_FILE de0_nano_soc_baseline.v +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCLK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO +set_location_assignment PIN_AG13 -to ARDUINO_IO[0] +set_location_assignment PIN_AF13 -to ARDUINO_IO[1] +set_location_assignment PIN_AG10 -to ARDUINO_IO[2] +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_location_assignment PIN_V11 -to CLOCK_50 +set_location_assignment PIN_Y13 -to CLOCK2_50 +set_location_assignment PIN_E11 -to CLOCK3_50 +set_location_assignment PIN_V12 -to GPIO_0[0] +set_location_assignment PIN_AF7 -to GPIO_0[1] +set_location_assignment PIN_W12 -to GPIO_0[2] +set_location_assignment PIN_AF8 -to GPIO_0[3] +set_location_assignment PIN_Y8 -to GPIO_0[4] +set_location_assignment PIN_AB4 -to GPIO_0[5] +set_location_assignment PIN_W8 -to GPIO_0[6] +set_location_assignment PIN_Y4 -to GPIO_0[7] +set_location_assignment PIN_Y5 -to GPIO_0[8] +set_location_assignment PIN_U11 -to GPIO_0[9] +set_location_assignment PIN_T8 -to GPIO_0[10] +set_location_assignment PIN_T12 -to GPIO_0[11] +set_location_assignment PIN_AH5 -to GPIO_0[12] +set_location_assignment PIN_AH6 -to GPIO_0[13] +set_location_assignment PIN_AH4 -to GPIO_0[14] +set_location_assignment PIN_AG5 -to GPIO_0[15] +set_location_assignment PIN_AH3 -to GPIO_0[16] +set_location_assignment PIN_AH2 -to GPIO_0[17] +set_location_assignment PIN_AF4 -to GPIO_0[18] +set_location_assignment PIN_AG6 -to GPIO_0[19] +set_location_assignment PIN_AF5 -to GPIO_0[20] +set_location_assignment PIN_AE4 -to GPIO_0[21] +set_location_assignment PIN_T13 -to GPIO_0[22] +set_location_assignment PIN_T11 -to GPIO_0[23] +set_location_assignment PIN_AE7 -to GPIO_0[24] +set_location_assignment PIN_AF6 -to GPIO_0[25] +set_location_assignment PIN_AF9 -to GPIO_0[26] +set_location_assignment PIN_AE8 -to GPIO_0[27] +set_location_assignment PIN_AD10 -to GPIO_0[28] +set_location_assignment PIN_AE9 -to GPIO_0[29] +set_location_assignment PIN_AD11 -to GPIO_0[30] +set_location_assignment PIN_AF10 -to GPIO_0[31] +set_location_assignment PIN_AD12 -to GPIO_0[32] +set_location_assignment PIN_AE11 -to GPIO_0[33] +set_location_assignment PIN_AF11 -to GPIO_0[34] +set_location_assignment PIN_AE12 -to GPIO_0[35] +set_location_assignment PIN_Y15 -to GPIO_1[0] +set_location_assignment PIN_AG28 -to GPIO_1[1] +set_location_assignment PIN_AA15 -to GPIO_1[2] +set_location_assignment PIN_AH27 -to GPIO_1[3] +set_location_assignment PIN_AG26 -to GPIO_1[4] +set_location_assignment PIN_AH24 -to GPIO_1[5] +set_location_assignment PIN_AF23 -to GPIO_1[6] +set_location_assignment PIN_AE22 -to GPIO_1[7] +set_location_assignment PIN_AF21 -to GPIO_1[8] +set_location_assignment PIN_AG20 -to GPIO_1[9] +set_location_assignment PIN_AG19 -to GPIO_1[10] +set_location_assignment PIN_AF20 -to GPIO_1[11] +set_location_assignment PIN_AC23 -to GPIO_1[12] +set_location_assignment PIN_AG18 -to GPIO_1[13] +set_location_assignment PIN_AH26 -to GPIO_1[14] +set_location_assignment PIN_AA19 -to GPIO_1[15] +set_location_assignment PIN_AG24 -to GPIO_1[16] +set_location_assignment PIN_AF25 -to GPIO_1[17] +set_location_assignment PIN_AH23 -to GPIO_1[18] +set_location_assignment PIN_AG23 -to GPIO_1[19] +set_location_assignment PIN_AE19 -to GPIO_1[20] +set_location_assignment PIN_AF18 -to GPIO_1[21] +set_location_assignment PIN_AD19 -to GPIO_1[22] +set_location_assignment PIN_AE20 -to GPIO_1[23] +set_location_assignment PIN_AE24 -to GPIO_1[24] +set_location_assignment PIN_AD20 -to GPIO_1[25] +set_location_assignment PIN_AF22 -to GPIO_1[26] +set_location_assignment PIN_AH22 -to GPIO_1[27] +set_location_assignment PIN_AH19 -to GPIO_1[28] +set_location_assignment PIN_AH21 -to GPIO_1[29] +set_location_assignment PIN_AG21 -to GPIO_1[30] +set_location_assignment PIN_AH18 -to GPIO_1[31] +set_location_assignment PIN_AD23 -to GPIO_1[32] +set_location_assignment PIN_AE23 -to GPIO_1[33] +set_location_assignment PIN_AA18 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_L10 -to SW[0] +set_location_assignment PIN_L9 -to SW[1] +set_location_assignment PIN_H6 -to SW[2] +set_location_assignment PIN_H5 -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_P +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_P +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_N +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CAS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ODT +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RAS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_WE_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RESET_N +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[14] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[15] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[16] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[17] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[18] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[19] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[20] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[21] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[22] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[23] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[24] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[25] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[26] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[27] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[28] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[29] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[30] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[31] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[14] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CAS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CKE +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ODT +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RAS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_WE_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RESET_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_P +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_N +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/qar_info.json b/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/qar_info.json new file mode 100644 index 0000000..6524796 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/de0_nano_soc_baseline/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/data/smeer/16.0/atlas_soc_pinout/atlas_soc_pinout_baseline/de0_nano_soc_baseline/", + "acds_version" : "Version 16.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/devkits/readme.txt b/EE203/Noah Woodlee/LAB1/Part3/devkits/readme.txt new file mode 100644 index 0000000..f6ba267 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/README b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.db_info b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.db_info new file mode 100644 index 0000000..937f61d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Version_Index = 419480576 +Creation_Time = Thu Mar 11 20:26:27 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.ammdb b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.ammdb new file mode 100644 index 0000000..befd0be Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.cdb b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.cdb new file mode 100644 index 0000000..cff8c63 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.dfp b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.hdb b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.hdb new file mode 100644 index 0000000..1f29269 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.logdb b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.rcfdb new file mode 100644 index 0000000..57fd5f1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.cdb b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.cdb new file mode 100644 index 0000000..45fe584 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.dpi b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.dpi new file mode 100644 index 0000000..25f04bb Binary files /dev/null and b/EE203/Noah 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b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..4467283 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.hdb b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.hdb new file mode 100644 index 0000000..d36aa91 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.kpt b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.kpt new file mode 100644 index 0000000..a9bea23 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.rrp.hdb b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.rrp.hdb new file mode 100644 index 0000000..936834b Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/incremental_db/compiled_partitions/Part3.rrp.hdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.asm.rpt b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.asm.rpt new file mode 100644 index 0000000..5e04db6 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.asm.rpt @@ -0,0 +1,93 @@ +Assembler report for Part3 +Thu Mar 11 20:43:45 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Mar 11 20:43:45 2021 ; +; Revision Name ; Part3 ; +; Top-level Entity Name ; Part3 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------------------------------+ +; File Name ; ++-------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.sof ; ++-------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.sof ; ++----------------+----------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------------------------------+ +; Device ; 10M50DAF484C7G ; +; JTAG usercode ; 0x00270861 ; +; Checksum ; 0x00270861 ; ++----------------+----------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Mar 11 20:43:41 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Part3 -c Part3 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4685 megabytes + Info: Processing ended: Thu Mar 11 20:43:45 2021 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.done b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.done new file mode 100644 index 0000000..03aa28d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.done @@ -0,0 +1 @@ +Thu Mar 11 20:43:50 2021 diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.eda.rpt b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.eda.rpt new file mode 100644 index 0000000..76fd44f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for Part3 +Thu Mar 11 20:47:38 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Mar 11 20:47:38 2021 ; +; Revision Name ; Part3 ; +; Top-level Entity Name ; Part3 ; +; Family ; MAX 10 ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++----------------------------------------------------------------------------+ +; Simulation Generated Files ; ++----------------------------------------------------------------------------+ +; Generated Files ; ++----------------------------------------------------------------------------+ +; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim//Part3.vo ; ++----------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Mar 11 20:47:38 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file Part3.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Mar 11 20:47:38 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.rpt b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.rpt new file mode 100644 index 0000000..34c7685 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.rpt @@ -0,0 +1,1294 @@ +Fitter report for Part3 +Thu Mar 11 20:43:37 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Mar 11 20:43:37 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Part3 ; +; Top-level Entity Name ; Part3 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 4 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 4 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 20 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C7G ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.2% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 63 ) ; 0.00 % ( 0 / 63 ) ; 0.00 % ( 0 / 63 ) ; +; -- Achieved ; 0.00 % ( 0 / 63 ) ; 0.00 % ( 0 / 63 ) ; 0.00 % ( 0 / 63 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 47 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 4 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 4 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 2 ; +; -- 3 input functions ; 1 ; +; -- <=2 input functions ; 1 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 4 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 3 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 20 / 360 ( 6 % ) ; +; -- Clock pins ; 2 / 8 ( 25 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.3% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 44 ; +; Average fan-out ; 0.70 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 4 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 4 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 2 ; 0 ; +; -- 3 input functions ; 1 ; 0 ; +; -- <=2 input functions ; 1 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 4 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 3 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 20 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 50 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 10 ; 0 ; +; -- Output Ports ; 10 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; D12 ; 7 ; 51 ; 54 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[2] ; W8 ; 3 ; 24 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[3] ; A7 ; 7 ; 49 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[4] ; V5 ; 3 ; 14 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[5] ; A11 ; 7 ; 51 ; 54 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[6] ; C10 ; 7 ; 51 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[7] ; A10 ; 7 ; 51 ; 54 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[8] ; H12 ; 7 ; 49 ; 54 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; +; SW[9] ; J11 ; 7 ; 49 ; 54 ; 21 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; LEDR[0] ; B11 ; 7 ; 49 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[1] ; B12 ; 7 ; 49 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[2] ; H21 ; 6 ; 78 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[3] ; L8 ; 1B ; 0 ; 27 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[4] ; N14 ; 6 ; 78 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[5] ; E11 ; 8 ; 36 ; 39 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[6] ; Y17 ; 4 ; 58 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[7] ; AA17 ; 4 ; 58 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[8] ; W6 ; 3 ; 16 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; LEDR[9] ; E18 ; 6 ; 78 ; 49 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 5 / 24 ( 21 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 3 / 48 ( 6 % ) ; 2.5V ; -- ; +; 4 ; 2 / 48 ( 4 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 3 / 60 ( 5 % ) ; 2.5V ; -- ; +; 7 ; 10 / 52 ( 19 % ) ; 2.5V ; -- ; +; 8 ; 5 / 36 ( 14 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; SW[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A8 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 439 ; 7 ; SW[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A11 ; 437 ; 7 ; SW[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A12 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 443 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B12 ; 441 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C12 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 391 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 388 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; LEDR[9] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; SW[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; LEDR[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; SW[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; LEDR[3] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; LEDR[4] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; SW[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; SW[2] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; LEDR[0] ; Incomplete set of assignments ; +; LEDR[1] ; Incomplete set of assignments ; +; LEDR[2] ; Incomplete set of assignments ; +; LEDR[3] ; Incomplete set of assignments ; +; LEDR[4] ; Incomplete set of assignments ; +; LEDR[5] ; Incomplete set of assignments ; +; LEDR[6] ; Incomplete set of assignments ; +; LEDR[7] ; Incomplete set of assignments ; +; LEDR[8] ; Incomplete set of assignments ; +; LEDR[9] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[8] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[9] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; +; SW[2] ; Missing location assignment ; +; SW[4] ; Missing location assignment ; +; LEDR[0] ; Missing location assignment ; +; LEDR[1] ; Missing location assignment ; +; LEDR[2] ; Missing location assignment ; +; LEDR[3] ; Missing location assignment ; +; LEDR[4] ; Missing location assignment ; +; LEDR[5] ; Missing location assignment ; +; LEDR[6] ; Missing location assignment ; +; LEDR[7] ; Missing location assignment ; +; LEDR[8] ; Missing location assignment ; +; LEDR[9] ; Missing location assignment ; +; SW[6] ; Missing location assignment ; +; SW[0] ; Missing location assignment ; +; SW[8] ; Missing location assignment ; +; SW[5] ; Missing location assignment ; +; SW[9] ; Missing location assignment ; +; SW[3] ; Missing location assignment ; +; SW[1] ; Missing location assignment ; +; SW[7] ; Missing location assignment ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |Part3 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 20 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; |Part3 ; Part3 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; SW[2] ; Input ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; -- ; -- ; -- ; -- ; +; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[0] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[8] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; SW[2] ; ; ; +; SW[4] ; ; ; +; SW[6] ; ; ; +; - M~0 ; 1 ; 6 ; +; SW[0] ; ; ; +; - M~0 ; 1 ; 6 ; +; SW[8] ; ; ; +; - M~0 ; 0 ; 6 ; +; - M~1 ; 0 ; 6 ; +; SW[5] ; ; ; +; - M~2 ; 0 ; 6 ; +; SW[9] ; ; ; +; - M~1 ; 0 ; 6 ; +; - M~2 ; 0 ; 6 ; +; SW[3] ; ; ; +; - M~1 ; 1 ; 6 ; +; SW[1] ; ; ; +; - M~1 ; 0 ; 6 ; +; SW[7] ; ; ; +; - M~2 ; 0 ; 6 ; ++---------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 15 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 0 / 5,382 ( 0 % ) ; +; C4 interconnects ; 15 / 106,704 ( < 1 % ) ; +; Direct links ; 1 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 1 / 49,760 ( < 1 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 0 / 5,406 ( 0 % ) ; +; R4 interconnects ; 0 / 147,764 ( 0 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 1.33) ; Number of LABs (Total = 3) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 1.33) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 3) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 3 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 20 ; 20 ; 0 ; 10 ; 0 ; 0 ; 10 ; 0 ; 10 ; 10 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 20 ; 20 ; 20 ; 20 ; 20 ; 0 ; 20 ; 20 ; 0 ; 0 ; 20 ; 10 ; 20 ; 20 ; 10 ; 20 ; 10 ; 10 ; 20 ; 20 ; 20 ; 10 ; 20 ; 20 ; 20 ; 20 ; 20 ; 0 ; 20 ; 20 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; SW[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (119006): Selected device 10M50DAF484C7G for design "Part3" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 10M08DAF484I7G is compatible + Info (176445): Device 10M16DAF484C7G is compatible + Info (176445): Device 10M16DAF484I7G is compatible + Info (176445): Device 10M25DAF484C7G is compatible + Info (176445): Device 10M25DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7P is compatible + Info (176445): Device 10M40DAF484C7G is compatible + Info (176445): Device 10M40DAF484I7G is compatible +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 20 pins of 20 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'Part3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 10 input, 10 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available + Info (176213): I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 5904 megabytes + Info: Processing ended: Thu Mar 11 20:43:37 2021 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:11 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg. + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg new file mode 100644 index 0000000..558ea95 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.summary b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.summary new file mode 100644 index 0000000..e4c9581 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Thu Mar 11 20:43:37 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : Part3 +Top-level Entity Name : Part3 +Family : MAX 10 +Device : 10M50DAF484C7G +Timing Models : Final +Total logic elements : 4 / 49,760 ( < 1 % ) + Total combinational functions : 4 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 20 / 360 ( 6 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.flow.rpt b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.flow.rpt new file mode 100644 index 0000000..a4da2fa --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.flow.rpt @@ -0,0 +1,134 @@ +Flow report for Part3 +Thu Mar 11 20:47:38 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Mar 11 20:47:38 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Part3 ; +; Top-level Entity Name ; Part3 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 4 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 4 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 20 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/11/2021 20:43:20 ; +; Main task ; Compilation ; +; Revision Name ; Part3 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 189559947077153.161551700008156 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4781 MB ; 00:00:22 ; +; Fitter ; 00:00:07 ; 1.0 ; 5904 MB ; 00:00:10 ; +; Assembler ; 00:00:04 ; 1.0 ; 4684 MB ; 00:00:03 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:01 ; +; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4867 MB ; 00:00:02 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:01 ; +; Total ; 00:00:23 ; -- ; -- ; 00:00:40 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off Part3 -c Part3 +quartus_fit --read_settings_files=off --write_settings_files=off Part3 -c Part3 +quartus_asm --read_settings_files=off --write_settings_files=off Part3 -c Part3 +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3 +quartus_sta Part3 -c Part3 +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3 + + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.jdi b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.jdi new file mode 100644 index 0000000..85579ba --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.map.rpt b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.map.rpt new file mode 100644 index 0000000..63f5412 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.map.rpt @@ -0,0 +1,298 @@ +Analysis & Synthesis report for Part3 +Thu Mar 11 20:43:30 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Mar 11 20:43:29 2021 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; Part3 ; +; Top-level Entity Name ; Part3 ; +; Family ; MAX 10 ; +; Total logic elements ; 3 ; +; Total combinational functions ; 3 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 20 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C7G ; ; +; Top-level entity name ; Part3 ; Part3 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; OpenCore Plus hardware evaluation ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------------+---------+ +; Part3.v ; yes ; User Verilog HDL File ; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v ; ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimated Total logic elements ; 3 ; +; ; ; +; Total combinational functions ; 3 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 2 ; +; -- 3 input functions ; 1 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 3 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 20 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; SW[8]~input ; +; Maximum fan-out ; 2 ; +; Total fan-out ; 33 ; +; Average fan-out ; 0.77 ; ++---------------------------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |Part3 ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; |Part3 ; Part3 ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 20 ; +; cycloneiii_lcell_comb ; 5 ; +; normal ; 5 ; +; 0 data inputs ; 2 ; +; 3 data inputs ; 1 ; +; 4 data inputs ; 2 ; +; ; ; +; Max LUT depth ; 2.00 ; +; Average LUT depth ; 1.31 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Mar 11 20:43:20 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Part3 -c Part3 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Critical Warning (10191): Verilog HDL Compiler Directive warning at Part3.v(18): text macro "b0" is undefined File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 18 +Info (12021): Found 1 design units, including 1 entities, in source file part3.v + Info (12023): Found entity 1: Part3 File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 1 +Info (12127): Elaborating entity "Part3" for the top level hierarchy +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "LEDR[2]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 3 + Warning (13410): Pin "LEDR[3]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 3 + Warning (13410): Pin "LEDR[4]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 3 + Warning (13410): Pin "LEDR[5]" is stuck at VCC File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 3 + Warning (13410): Pin "LEDR[6]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 3 + Warning (13410): Pin "LEDR[7]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 3 + Warning (13410): Pin "LEDR[8]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 3 + Warning (13410): Pin "LEDR[9]" is stuck at GND File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 3 +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 2 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "SW[2]" File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 2 + Warning (15610): No output dependent on input pin "SW[4]" File: C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v Line: 2 +Info (21057): Implemented 23 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 10 input pins + Info (21059): Implemented 10 output pins + Info (21061): Implemented 3 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings + Info: Peak virtual memory: 4781 megabytes + Info: Processing ended: Thu Mar 11 20:43:30 2021 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:23 + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.map.summary b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.map.summary new file mode 100644 index 0000000..8b5c15b --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Thu Mar 11 20:43:29 2021 +Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition +Revision Name : Part3 +Top-level Entity Name : Part3 +Family : MAX 10 +Total logic elements : 3 + Total combinational functions : 3 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 20 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.pin b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.pin new file mode 100644 index 0000000..45f1c5d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2016 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel MegaCore Function License Agreement, or other + -- applicable license agreement, including, without limitation, + -- that your use is for the sole purpose of programming logic + -- devices manufactured by Intel and sold by Intel or its + -- authorized distributors. Please refer to the applicable + -- agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +CHIP "Part3" ASSIGNED TO AN: 10M50DAF484C7G + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +SW[3] : A7 : input : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +SW[7] : A10 : input : 2.5 V : : 7 : N +SW[5] : A11 : input : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +LEDR[7] : AA17 : output : 2.5 V : : 4 : N +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +LEDR[0] : B11 : output : 2.5 V : : 7 : N +LEDR[1] : B12 : output : 2.5 V : : 7 : N +GND : B13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[6] : C10 : input : 2.5 V : : 7 : N +SW[1] : C11 : input : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +SW[0] : D12 : input : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +LEDR[5] : E11 : output : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +LEDR[9] : E18 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +SW[8] : H12 : input : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +LEDR[2] : H21 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +SW[9] : J11 : input : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +LEDR[3] : L8 : output : 2.5 V : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +LEDR[4] : N14 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +SW[4] : V5 : input : 2.5 V : : 3 : N +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +LEDR[8] : W6 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +SW[2] : W8 : input : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +LEDR[6] : Y17 : output : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.pof b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.pof new file mode 100644 index 0000000..36cc633 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.pof differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sld b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sof b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sof new file mode 100644 index 0000000..e6c8fcc Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sof differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sta.rpt b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sta.rpt new file mode 100644 index 0000000..028d15d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sta.rpt @@ -0,0 +1,483 @@ +TimeQuest Timing Analyzer report for Part3 +Thu Mar 11 20:43:50 2021 +Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; Part3 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 8 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 8 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.3% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0783 V ; 0.157 V ; 0.167 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0783 V ; 0.157 V ; 0.167 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0459 V ; 0.201 V ; 0.093 V ; 4.9e-10 s ; 5.83e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0459 V ; 0.201 V ; 0.093 V ; 4.9e-10 s ; 5.83e-10 s ; Yes ; No ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.77 V ; -0.0485 V ; 0.289 V ; 0.058 V ; 2.81e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.77 V ; -0.0485 V ; 0.289 V ; 0.058 V ; 2.81e-10 s ; 3.04e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 8 ; 8 ; +; Unconstrained Input Port Paths ; 9 ; 9 ; +; Unconstrained Output Ports ; 2 ; 2 ; +; Unconstrained Output Port Paths ; 9 ; 9 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Processing started: Thu Mar 11 20:43:47 2021 +Info: Command: quartus_sta Part3 -c Part3 +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'Part3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4867 megabytes + Info: Processing ended: Thu Mar 11 20:43:50 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sta.summary b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.do b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.do new file mode 100644 index 0000000..8e66582 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.do @@ -0,0 +1,18 @@ +onerror {exit -code 1} +vlib work +vlog -work work Part3.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Part3_vlg_vec_tst +vcd file -direction Part3.msim.vcd +vcd add -internal Part3_vlg_vec_tst/* +vcd add -internal Part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.msim.vcd b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.msim.vcd new file mode 100644 index 0000000..2b09a5f --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.msim.vcd @@ -0,0 +1,259 @@ +$comment + File created using the following command: + vcd file Part3.msim.vcd -direction +$end +$date + Thu Mar 11 20:47:39 2021 +$end +$version + ModelSim Version 10.5b +$end +$timescale + 1ps +$end + +$scope module Part3_vlg_vec_tst $end +$var reg 10 ! SW [9:0] $end +$var wire 1 " LEDR [9] $end +$var wire 1 # LEDR [8] $end +$var wire 1 $ LEDR [7] $end +$var wire 1 % LEDR [6] $end +$var wire 1 & LEDR [5] $end +$var wire 1 ' LEDR [4] $end +$var wire 1 ( LEDR [3] $end +$var wire 1 ) LEDR [2] $end +$var wire 1 * LEDR [1] $end +$var wire 1 + LEDR [0] $end + +$scope module i1 $end +$var wire 1 , gnd $end +$var wire 1 - vcc $end +$var wire 1 . unknown $end +$var tri1 1 / devclrn $end +$var tri1 1 0 devpor $end +$var tri1 1 1 devoe $end +$var wire 1 2 SW[2]~input_o $end +$var wire 1 3 SW[4]~input_o $end +$var wire 1 4 ~QUARTUS_CREATED_GND~I_combout $end +$var wire 1 5 ~QUARTUS_CREATED_UNVM~~busy $end +$var wire 1 6 ~QUARTUS_CREATED_ADC1~~eoc $end +$var wire 1 7 ~QUARTUS_CREATED_ADC2~~eoc $end +$var wire 1 8 LEDR[0]~output_o $end +$var wire 1 9 LEDR[1]~output_o $end +$var wire 1 : LEDR[2]~output_o $end +$var wire 1 ; LEDR[3]~output_o $end +$var wire 1 < LEDR[4]~output_o $end +$var wire 1 = LEDR[5]~output_o $end +$var wire 1 > LEDR[6]~output_o $end +$var wire 1 ? LEDR[7]~output_o $end +$var wire 1 @ LEDR[8]~output_o $end +$var wire 1 A LEDR[9]~output_o $end +$var wire 1 B SW[0]~input_o $end +$var wire 1 C SW[8]~input_o $end +$var wire 1 D SW[6]~input_o $end +$var wire 1 E M~0_combout $end +$var wire 1 F SW[5]~input_o $end +$var wire 1 G SW[9]~input_o $end +$var wire 1 H SW[3]~input_o $end +$var wire 1 I SW[1]~input_o $end +$var wire 1 J M~1_combout $end +$var wire 1 K SW[7]~input_o $end +$var wire 1 L M~2_combout $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0xxxxxx00 ! +0+ +0* +0) +0( +0' +1& +0% +0$ +0# +0" +0, +1- +x. +1/ +10 +11 +x2 +x3 +04 +z5 +z6 +z7 +08 +09 +0: +0; +0< +1= +0> +0? +0@ +0A +0B +0C +xD +0E +xF +0G +xH +0I +0J +xK +0L +$end +#40000 +b0xxxxxx10 ! +b0xxxxxx11 ! +1I +1B +1J +1E +18 +1+ +1L +19 +1* +#100000 +b0xxxxxx01 ! +b0xxxxxx00 ! +0I +0B +0J +0E +08 +0+ +0L +09 +0* +#180000 +b0xxxxxx10 ! +b0xxxxxx11 ! +1I +1B +1J +1E +18 +1+ +1L +19 +1* +#230000 +b1xxxxxx11 ! +b1xxxx0x11 ! +b1xxxx0011 ! +b1xxxx00x1 ! +b1xxxx00xx ! +1C +0H +02 +xI +xB +0J +xE +x8 +x+ +0L +09 +0* +#310000 +b1xxxx10xx ! +b1xxxx11xx ! +1H +12 +1J +1L +19 +1* +#390000 +b1xxxx01xx ! +b1xxxx00xx ! +0H +02 +0J +0L +09 +0* +#470000 +b11xxxx00xx ! +b11xx1x00xx ! +b11xx1100xx ! +b10xx1100xx ! +b10xx11x0xx ! +b10xx11xxxx ! +1G +0C +1F +13 +xH +x2 +1L +19 +1* +#550000 +b10xx01xxxx ! +b10xx00xxxx ! +0F +03 +0L +09 +0* +#640000 +b10xx10xxxx ! +b10xx11xxxx ! +1F +13 +1L +19 +1* +#740000 +b101x11xxxx ! +b101111xxxx ! +b111111xxxx ! +b1111x1xxxx ! +b1111xxxxxx ! +1C +1K +1D +xF +x3 +1J +1E +xL +x9 +18 +1+ +x* +1L +19 +1* +#810000 +b1101xxxxxx ! +b1100xxxxxx ! +0K +0D +0L +0E +08 +09 +0* +0+ +#900000 +b1110xxxxxx ! +b1111xxxxxx ! +1K +1D +1L +1E +18 +19 +1* +1+ +#1000000 diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.sft b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.sft new file mode 100644 index 0000000..f324fea --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.vo b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.vo new file mode 100644 index 0000000..6e30d8d --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.vo @@ -0,0 +1,571 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" + +// DATE "03/11/2021 20:47:38" + +// +// Device: Altera 10M50DAF484C7G Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module Part3 ( + SW, + LEDR); +input [9:0] SW; +output [9:0] LEDR; + +// Design Ports Information +// SW[2] => Location: PIN_W8, I/O Standard: 2.5 V, Current Strength: Default +// SW[4] => Location: PIN_V5, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[0] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[1] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[2] => Location: PIN_H21, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[3] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[4] => Location: PIN_N14, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[5] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[6] => Location: PIN_Y17, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[7] => Location: PIN_AA17, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[8] => Location: PIN_W6, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[9] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default +// SW[6] => Location: PIN_C10, I/O Standard: 2.5 V, Current Strength: Default +// SW[0] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default +// SW[8] => Location: PIN_H12, I/O Standard: 2.5 V, Current Strength: Default +// SW[5] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// SW[9] => Location: PIN_J11, I/O Standard: 2.5 V, Current Strength: Default +// SW[3] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// SW[1] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// SW[7] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \SW[2]~input_o ; +wire \SW[4]~input_o ; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \~QUARTUS_CREATED_UNVM~~busy ; +wire \~QUARTUS_CREATED_ADC1~~eoc ; +wire \~QUARTUS_CREATED_ADC2~~eoc ; +wire \LEDR[0]~output_o ; +wire \LEDR[1]~output_o ; +wire \LEDR[2]~output_o ; +wire \LEDR[3]~output_o ; +wire \LEDR[4]~output_o ; +wire \LEDR[5]~output_o ; +wire \LEDR[6]~output_o ; +wire \LEDR[7]~output_o ; +wire \LEDR[8]~output_o ; +wire \LEDR[9]~output_o ; +wire \SW[0]~input_o ; +wire \SW[8]~input_o ; +wire \SW[6]~input_o ; +wire \M~0_combout ; +wire \SW[5]~input_o ; +wire \SW[9]~input_o ; +wire \SW[3]~input_o ; +wire \SW[1]~input_o ; +wire \M~1_combout ; +wire \SW[7]~input_o ; +wire \M~2_combout ; + + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: LCCOMB_X44_Y41_N8 +fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): +// \~QUARTUS_CREATED_GND~I_combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .cout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000; +defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X49_Y54_N9 +fiftyfivenm_io_obuf \LEDR[0]~output ( + .i(\M~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[0]~output .bus_hold = "false"; +defparam \LEDR[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X49_Y54_N2 +fiftyfivenm_io_obuf \LEDR[1]~output ( + .i(\M~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[1]~output .bus_hold = "false"; +defparam \LEDR[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X78_Y29_N2 +fiftyfivenm_io_obuf \LEDR[2]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[2]~output .bus_hold = "false"; +defparam \LEDR[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N16 +fiftyfivenm_io_obuf \LEDR[3]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[3]~output .bus_hold = "false"; +defparam \LEDR[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X78_Y29_N23 +fiftyfivenm_io_obuf \LEDR[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[4]~output .bus_hold = "false"; +defparam \LEDR[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X36_Y39_N16 +fiftyfivenm_io_obuf \LEDR[5]~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[5]~output .bus_hold = "false"; +defparam \LEDR[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X58_Y0_N23 +fiftyfivenm_io_obuf \LEDR[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[6]~output .bus_hold = "false"; +defparam \LEDR[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X58_Y0_N30 +fiftyfivenm_io_obuf \LEDR[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[7]~output .bus_hold = "false"; +defparam \LEDR[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N30 +fiftyfivenm_io_obuf \LEDR[8]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[8]~output .bus_hold = "false"; +defparam \LEDR[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X78_Y49_N2 +fiftyfivenm_io_obuf \LEDR[9]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[9]~output .bus_hold = "false"; +defparam \LEDR[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N1 +fiftyfivenm_io_ibuf \SW[0]~input ( + .i(SW[0]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[0]~input_o )); +// synopsys translate_off +defparam \SW[0]~input .bus_hold = "false"; +defparam \SW[0]~input .listen_to_nsleep_signal = "false"; +defparam \SW[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X49_Y54_N15 +fiftyfivenm_io_ibuf \SW[8]~input ( + .i(SW[8]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[8]~input_o )); +// synopsys translate_off +defparam \SW[8]~input .bus_hold = "false"; +defparam \SW[8]~input .listen_to_nsleep_signal = "false"; +defparam \SW[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N29 +fiftyfivenm_io_ibuf \SW[6]~input ( + .i(SW[6]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[6]~input_o )); +// synopsys translate_off +defparam \SW[6]~input .bus_hold = "false"; +defparam \SW[6]~input .listen_to_nsleep_signal = "false"; +defparam \SW[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X50_Y53_N24 +fiftyfivenm_lcell_comb \M~0 ( +// Equation(s): +// \M~0_combout = (\SW[8]~input_o & ((\SW[6]~input_o ))) # (!\SW[8]~input_o & (\SW[0]~input_o )) + + .dataa(\SW[0]~input_o ), + .datab(gnd), + .datac(\SW[8]~input_o ), + .datad(\SW[6]~input_o ), + .cin(gnd), + .combout(\M~0_combout ), + .cout()); +// synopsys translate_off +defparam \M~0 .lut_mask = 16'hFA0A; +defparam \M~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N8 +fiftyfivenm_io_ibuf \SW[5]~input ( + .i(SW[5]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[5]~input_o )); +// synopsys translate_off +defparam \SW[5]~input .bus_hold = "false"; +defparam \SW[5]~input .listen_to_nsleep_signal = "false"; +defparam \SW[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X49_Y54_N22 +fiftyfivenm_io_ibuf \SW[9]~input ( + .i(SW[9]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[9]~input_o )); +// synopsys translate_off +defparam \SW[9]~input .bus_hold = "false"; +defparam \SW[9]~input .listen_to_nsleep_signal = "false"; +defparam \SW[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X49_Y54_N29 +fiftyfivenm_io_ibuf \SW[3]~input ( + .i(SW[3]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[3]~input_o )); +// synopsys translate_off +defparam \SW[3]~input .bus_hold = "false"; +defparam \SW[3]~input .listen_to_nsleep_signal = "false"; +defparam \SW[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N22 +fiftyfivenm_io_ibuf \SW[1]~input ( + .i(SW[1]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[1]~input_o )); +// synopsys translate_off +defparam \SW[1]~input .bus_hold = "false"; +defparam \SW[1]~input .listen_to_nsleep_signal = "false"; +defparam \SW[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X50_Y52_N24 +fiftyfivenm_lcell_comb \M~1 ( +// Equation(s): +// \M~1_combout = (\SW[8]~input_o & ((\SW[9]~input_o ) # ((\SW[3]~input_o )))) # (!\SW[8]~input_o & (!\SW[9]~input_o & ((\SW[1]~input_o )))) + + .dataa(\SW[8]~input_o ), + .datab(\SW[9]~input_o ), + .datac(\SW[3]~input_o ), + .datad(\SW[1]~input_o ), + .cin(gnd), + .combout(\M~1_combout ), + .cout()); +// synopsys translate_off +defparam \M~1 .lut_mask = 16'hB9A8; +defparam \M~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N15 +fiftyfivenm_io_ibuf \SW[7]~input ( + .i(SW[7]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[7]~input_o )); +// synopsys translate_off +defparam \SW[7]~input .bus_hold = "false"; +defparam \SW[7]~input .listen_to_nsleep_signal = "false"; +defparam \SW[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X50_Y52_N2 +fiftyfivenm_lcell_comb \M~2 ( +// Equation(s): +// \M~2_combout = (\M~1_combout & (((\SW[7]~input_o ) # (!\SW[9]~input_o )))) # (!\M~1_combout & (\SW[5]~input_o & (\SW[9]~input_o ))) + + .dataa(\SW[5]~input_o ), + .datab(\M~1_combout ), + .datac(\SW[9]~input_o ), + .datad(\SW[7]~input_o ), + .cin(gnd), + .combout(\M~2_combout ), + .cout()); +// synopsys translate_off +defparam \M~2 .lut_mask = 16'hEC2C; +defparam \M~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X24_Y0_N1 +fiftyfivenm_io_ibuf \SW[2]~input ( + .i(SW[2]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[2]~input_o )); +// synopsys translate_off +defparam \SW[2]~input .bus_hold = "false"; +defparam \SW[2]~input .listen_to_nsleep_signal = "false"; +defparam \SW[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N8 +fiftyfivenm_io_ibuf \SW[4]~input ( + .i(SW[4]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[4]~input_o )); +// synopsys translate_off +defparam \SW[4]~input .bus_hold = "false"; +defparam \SW[4]~input .listen_to_nsleep_signal = "false"; +defparam \SW[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: UNVM_X0_Y40_N40 +fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ ( + .arclk(vcc), + .arshft(vcc), + .drclk(vcc), + .drshft(vcc), + .drdin(vcc), + .nprogram(vcc), + .nerase(vcc), + .nosc_ena(\~QUARTUS_CREATED_GND~I_combout ), + .par_en(vcc), + .xe_ye(\~QUARTUS_CREATED_GND~I_combout ), + .se(\~QUARTUS_CREATED_GND~I_combout ), + .ardin(23'b11111111111111111111111), + .busy(\~QUARTUS_CREATED_UNVM~~busy ), + .osc(), + .bgpbusy(), + .sp_pass(), + .se_pass(), + .drdout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm"; +defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true"; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y52_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC1~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1; +defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y51_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC2~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2; +defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0; +// synopsys translate_on + +assign LEDR[0] = \LEDR[0]~output_o ; + +assign LEDR[1] = \LEDR[1]~output_o ; + +assign LEDR[2] = \LEDR[2]~output_o ; + +assign LEDR[3] = \LEDR[3]~output_o ; + +assign LEDR[4] = \LEDR[4]~output_o ; + +assign LEDR[5] = \LEDR[5]~output_o ; + +assign LEDR[6] = \LEDR[6]~output_o ; + +assign LEDR[7] = \LEDR[7]~output_o ; + +assign LEDR[8] = \LEDR[8]~output_o ; + +assign LEDR[9] = \LEDR[9]~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_TMS~~padout ; +wire \~ALTERA_TCK~~padout ; +wire \~ALTERA_TDI~~padout ; +wire \~ALTERA_CONFIG_SEL~~padout ; +wire \~ALTERA_nCONFIG~~padout ; +wire \~ALTERA_nSTATUS~~padout ; +wire \~ALTERA_CONF_DONE~~padout ; +wire \~ALTERA_TMS~~ibuf_o ; +wire \~ALTERA_TCK~~ibuf_o ; +wire \~ALTERA_TDI~~ibuf_o ; +wire \~ALTERA_CONFIG_SEL~~ibuf_o ; +wire \~ALTERA_nCONFIG~~ibuf_o ; +wire \~ALTERA_nSTATUS~~ibuf_o ; +wire \~ALTERA_CONF_DONE~~ibuf_o ; + + +endmodule diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311202943.sim.vwf b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311202943.sim.vwf new file mode 100644 index 0000000..4dec002 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311202943.sim.vwf @@ -0,0 +1,793 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 70.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 590.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 460.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 340.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 370.0; + LEVEL 0 FOR 280.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 310.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 340.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 290.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 360.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 260.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 500.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 220.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 180.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 140.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 230.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 100.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 550.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 70.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 590.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 40.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311203557.sim.vwf b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311203557.sim.vwf new file mode 100644 index 0000000..69b5c90 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311203557.sim.vwf @@ -0,0 +1,789 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 380.0; + LEVEL X FOR 400.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL X FOR 180.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 10.0; + LEVEL X FOR 400.0; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 250.0; + LEVEL 1 FOR 350.0; + LEVEL 0 FOR 400.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 170.0; + LEVEL 0 FOR 400.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 750.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 410.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 250.0; + LEVEL 0 FOR 180.0; + LEVEL X FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 250.0; + LEVEL 0 FOR 180.0; + LEVEL X FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 250.0; + LEVEL 0 FOR 180.0; + LEVEL X FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 250.0; + LEVEL 0 FOR 180.0; + LEVEL X FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL X FOR 750.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL X FOR 750.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311204347.sim.vwf b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311204347.sim.vwf new file mode 100644 index 0000000..69b5c90 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311204347.sim.vwf @@ -0,0 +1,789 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 380.0; + LEVEL X FOR 400.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL X FOR 180.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 10.0; + LEVEL X FOR 400.0; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 250.0; + LEVEL 1 FOR 350.0; + LEVEL 0 FOR 400.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 170.0; + LEVEL 0 FOR 400.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 750.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 430.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 410.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 250.0; + LEVEL 0 FOR 180.0; + LEVEL X FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 250.0; + LEVEL 0 FOR 180.0; + LEVEL X FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 250.0; + LEVEL 0 FOR 180.0; + LEVEL X FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 250.0; + LEVEL 0 FOR 180.0; + LEVEL X FOR 570.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL X FOR 750.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL X FOR 750.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311204740.sim.vwf b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311204740.sim.vwf new file mode 100644 index 0000000..aa6da8c --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311204740.sim.vwf @@ -0,0 +1,793 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 10; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 170.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL X FOR 510.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 470.0; + LEVEL 1 FOR 530.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 230.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 270.0; + LEVEL 1 FOR 260.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 740.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 740.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 470.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + LEVEL X FOR 260.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 470.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 100.0; + LEVEL X FOR 260.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 230.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL X FOR 530.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL X FOR 230.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL X FOR 530.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL X FOR 770.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL X FOR 770.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_modelsim.xrf b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_modelsim.xrf new file mode 100644 index 0000000..61c0bcb --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_modelsim.xrf @@ -0,0 +1,40 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Part3.v +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf +source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/db/Part3.cbx.xml +design_name = Part3 +instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, Part3, 1 +instance = comp, \LEDR[0]~output , LEDR[0]~output, Part3, 1 +instance = comp, \LEDR[1]~output , LEDR[1]~output, Part3, 1 +instance = comp, \LEDR[2]~output , LEDR[2]~output, Part3, 1 +instance = comp, \LEDR[3]~output , LEDR[3]~output, Part3, 1 +instance = comp, \LEDR[4]~output , LEDR[4]~output, Part3, 1 +instance = comp, \LEDR[5]~output , LEDR[5]~output, Part3, 1 +instance = comp, \LEDR[6]~output , LEDR[6]~output, Part3, 1 +instance = comp, \LEDR[7]~output , LEDR[7]~output, Part3, 1 +instance = comp, \LEDR[8]~output , LEDR[8]~output, Part3, 1 +instance = comp, \LEDR[9]~output , LEDR[9]~output, Part3, 1 +instance = comp, \SW[0]~input , SW[0]~input, Part3, 1 +instance = comp, \SW[8]~input , SW[8]~input, Part3, 1 +instance = comp, \SW[6]~input , SW[6]~input, Part3, 1 +instance = comp, \M~0 , M~0, Part3, 1 +instance = comp, \SW[5]~input , SW[5]~input, Part3, 1 +instance = comp, \SW[9]~input , SW[9]~input, Part3, 1 +instance = comp, \SW[3]~input , SW[3]~input, Part3, 1 +instance = comp, \SW[1]~input , SW[1]~input, Part3, 1 +instance = comp, \M~1 , M~1, Part3, 1 +instance = comp, \SW[7]~input , SW[7]~input, Part3, 1 +instance = comp, \M~2 , M~2, Part3, 1 +instance = comp, \SW[2]~input , SW[2]~input, Part3, 1 +instance = comp, \SW[4]~input , SW[4]~input, Part3, 1 +instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, Part3, 1 +instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, Part3, 1 +instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, Part3, 1 +design_name = hard_block +instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1 diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt new file mode 100644 index 0000000..964e5a7 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt @@ -0,0 +1,132 @@ +// Copyright (C) 2016 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel MegaCore Function License Agreement, or other +// applicable license agreement, including, without limitation, +// that your use is for the sole purpose of programming logic +// devices manufactured by Intel and sold by Intel or its +// authorized distributors. Please refer to the applicable +// agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "03/11/2021 20:47:37" + +// Verilog Test Bench (with test vectors) for design : Part3 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module Part3_vlg_vec_tst(); +// constants +// general purpose registers +reg [9:0] SW; +// wires +wire [9:0] LEDR; + +// assign statements (if any) +Part3 i1 ( +// port map - connection between master ports and signals/registers + .LEDR(LEDR), + .SW(SW) +); +initial +begin +#1000000 $finish; +end +// SW[ 9 ] +initial +begin + SW[9] = 1'b0; + SW[9] = #470000 1'b1; +end +// SW[ 8 ] +initial +begin + SW[8] = 1'b0; + SW[8] = #230000 1'b1; + SW[8] = #240000 1'b0; + SW[8] = #270000 1'b1; +end +// SW[ 7 ] +initial +begin + SW[7] = 1'bX; + SW[7] = #740000 1'b1; + SW[7] = #70000 1'b0; + SW[7] = #90000 1'b1; +end +// SW[ 6 ] +initial +begin + SW[6] = 1'bX; + SW[6] = #740000 1'b1; + SW[6] = #70000 1'b0; + SW[6] = #90000 1'b1; +end +// SW[ 5 ] +initial +begin + SW[5] = 1'bX; + SW[5] = #470000 1'b1; + SW[5] = #80000 1'b0; + SW[5] = #90000 1'b1; + SW[5] = #100000 1'bX; +end +// SW[ 4 ] +initial +begin + SW[4] = 1'bX; + SW[4] = #470000 1'b1; + SW[4] = #80000 1'b0; + SW[4] = #90000 1'b1; + SW[4] = #100000 1'bX; +end +// SW[ 3 ] +initial +begin + SW[3] = 1'bX; + SW[3] = #230000 1'b0; + SW[3] = #80000 1'b1; + SW[3] = #80000 1'b0; + SW[3] = #80000 1'bX; +end +// SW[ 2 ] +initial +begin + SW[2] = 1'bX; + SW[2] = #230000 1'b0; + SW[2] = #80000 1'b1; + SW[2] = #80000 1'b0; + SW[2] = #80000 1'bX; +end +// SW[ 1 ] +initial +begin + SW[1] = 1'b0; + SW[1] = #40000 1'b1; + SW[1] = #60000 1'b0; + SW[1] = #80000 1'b1; + SW[1] = #50000 1'bX; +end +// SW[ 0 ] +initial +begin + SW[0] = 1'b0; + SW[0] = #40000 1'b1; + SW[0] = #60000 1'b0; + SW[0] = #80000 1'b1; + SW[0] = #50000 1'bX; +end +endmodule + diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/transcript b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/transcript new file mode 100644 index 0000000..07c8547 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/transcript @@ -0,0 +1,37 @@ +# do Part3.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:47:39 on Mar 11,2021 +# vlog -work work Part3.vo +# -- Compiling module Part3 +# -- Compiling module hard_block +# +# Top level modules: +# Part3 +# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:47:39 on Mar 11,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module Part3_vlg_vec_tst +# +# Top level modules: +# Part3_vlg_vec_tst +# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Part3_vlg_vec_tst +# Start time: 20:47:39 on Mar 11,2021 +# Loading work.Part3_vlg_vec_tst +# Loading work.Part3 +# Loading work.hard_block +# ** Warning: (vsim-3017) Part3.vo(460): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) Part3.vo(460): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) Part3.vo(483): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) Part3.vo(483): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform.vwf.vt(45) +# Time: 1 us Iteration: 0 Instance: /Part3_vlg_vec_tst +# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4 diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/vwf_sim_transcript b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..f7be827 --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,141 @@ +Determining the location of the ModelSim executable... + +Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt" + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Mar 11 20:47:37 2021 +Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt" +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. + +Completed successfully. + +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3 + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition + Info: Copyright (C) 2016 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel MegaCore Function License Agreement, or other + Info: applicable license agreement, including, without limitation, + Info: that your use is for the sole purpose of programming logic + Info: devices manufactured by Intel and sold by Intel or its + Info: authorized distributors. Please refer to the applicable + Info: agreement for further details. + Info: Processing started: Thu Mar 11 20:47:38 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file Part3.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4641 megabytes + Info: Processing ended: Thu Mar 11 20:47:38 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + +Completed successfully. + +**** Generating the ModelSim .do script **** + +C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do Part3.do + +Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl + +# 10.5b + +# do Part3.do + +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:47:39 on Mar 11,2021 +# vlog -work work Part3.vo +# -- Compiling module Part3 +# -- Compiling module hard_block +# +# Top level modules: +# Part3 +# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 20:47:39 on Mar 11,2021 +# vlog -work work Waveform.vwf.vt +# -- Compiling module Part3_vlg_vec_tst +# +# Top level modules: +# Part3_vlg_vec_tst +# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Part3_vlg_vec_tst +# Start time: 20:47:39 on Mar 11,2021 +# Loading work.Part3_vlg_vec_tst +# Loading work.Part3 +# Loading work.hard_block +# ** Warning: (vsim-3017) Part3.vo(460): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile +# ** Warning: (vsim-3722) Part3.vo(460): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-3017) Part3.vo(483): [TFMPC] - Too few port connections. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /Part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile +# ** Warning: (vsim-3722) Part3.vo(483): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform.vwf.vt(45) +# Time: 1 us Iteration: 0 Instance: /Part3_vlg_vec_tst +# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4 + +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf... + +Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.msim.vcd... + +Processing channel transitions... + +Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311204740.sim.vwf + +Finished VCD to VWF conversion. + +Completed successfully. + +All completed. \ No newline at end of file diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_info b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_info new file mode 100644 index 0000000..50aa9fd --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_info @@ -0,0 +1,75 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dC:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim +vhard_block +Z1 !s110 1615517259 +!i10b 1 +!s100 e7=3kHekOD8I3N7oj>GK72 +I?42glZN^bC433Wj_<7@?Y2 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +Z3 w1615517258 +Z4 8Part3.vo +Z5 FPart3.vo +L0 527 +Z6 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z7 !s108 1615517259.000000 +Z8 !s107 Part3.vo| +Z9 !s90 -work|work|Part3.vo| +!i113 1 +Z10 o-work work +Z11 tCvgOpt 0 +vPart3 +R1 +!i10b 1 +!s100 ^_@B^R5k@b0 +I8OFPdcW`A[FXoVII54SD72 +R2 +R0 +w1615517257 +8Waveform.vwf.vt +FWaveform.vwf.vt +L0 30 +R6 +r1 +!s85 0 +31 +R7 +!s107 Waveform.vwf.vt| +!s90 -work|work|Waveform.vwf.vt| +!i113 1 +R10 +R11 +n@part3_vlg_vec_tst diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib.qdb b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib.qdb new file mode 100644 index 0000000..db374e1 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib.qdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qdb b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qdb new file mode 100644 index 0000000..4c9c786 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qdb differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qpg b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qpg new file mode 100644 index 0000000..7d51996 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qpg differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qtl b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qtl new file mode 100644 index 0000000..6be9ec2 Binary files /dev/null and b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_lib1_0.qtl differ diff --git a/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_vmake b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/EE203/Noah Woodlee/Lab2/part1/atom_netlists/part1.qsf b/EE203/Noah Woodlee/Lab2/part1/atom_netlists/part1.qsf new file mode 100644 index 0000000..d8b7603 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/atom_netlists/part1.qsf @@ -0,0 +1,65 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:13:22 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top 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b/EE203/Noah Woodlee/Lab2/part1/db/part1.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.(0).cnf.hdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.(0).cnf.hdb new file mode 100644 index 0000000..f236aa3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.asm.qmsg b/EE203/Noah Woodlee/Lab2/part1/db/part1.asm.qmsg new file mode 100644 index 0000000..c0a29be --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619301714813 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619301715159 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619301717941 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619301718038 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "355 " "Peak virtual memory: 355 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619301719290 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 17:01:59 2021 " "Processing ended: Sat Apr 24 17:01:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619301719290 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619301719290 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619301719290 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619301719290 ""} diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.asm.rdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.asm.rdb new file mode 100644 index 0000000..e5f78af Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.asm.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.asm_labs.ddb b/EE203/Noah Woodlee/Lab2/part1/db/part1.asm_labs.ddb new file mode 100644 index 0000000..40d0f64 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.cbx.xml b/EE203/Noah Woodlee/Lab2/part1/db/part1.cbx.xml new file mode 100644 index 0000000..09ec8a8 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.bpm b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.bpm new file mode 100644 index 0000000..d8ce2c7 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.cdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.cdb new file mode 100644 index 0000000..e5168cf Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.hdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.hdb new file mode 100644 index 0000000..22b5d51 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.idb b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.idb new file mode 100644 index 0000000..cb28b37 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.idb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.logdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.logdb new file mode 100644 index 0000000..f82715d --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.logdb @@ -0,0 +1,64 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;22;22;0;0;22;22;0;0;0;0;0;0;14;0;0;0;8;14;0;8;0;0;14;0;22;22;22;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,22;0;0;22;22;0;0;22;22;22;22;22;22;8;22;22;22;14;8;22;14;22;22;8;22;0;0;0;22;22, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.rdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.rdb new file mode 100644 index 0000000..bfd8aff Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp_merge.kpt b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp_merge.kpt new file mode 100644 index 0000000..e0a9f98 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.db_info b/EE203/Noah Woodlee/Lab2/part1/db/part1.db_info new file mode 100644 index 0000000..94e84ee --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sat Apr 24 16:59:18 2021 diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.fit.qmsg b/EE203/Noah Woodlee/Lab2/part1/db/part1.fit.qmsg new file mode 100644 index 0000000..6282198 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.fit.qmsg @@ -0,0 +1,54 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1619301694676 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619301694677 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part1 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part1\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619301694689 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619301694769 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619301694769 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1619301695169 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619301695181 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619301695352 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619301695367 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 0 { 0 ""} 0 86 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619301695367 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 0 { 0 ""} 0 88 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619301695367 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 0 { 0 ""} 0 90 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619301695367 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 0 { 0 ""} 0 92 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619301695367 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 0 { 0 ""} 0 94 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619301695367 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 0 { 0 ""} 0 96 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619301695367 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 0 { 0 ""} 0 98 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619301695367 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1619301695367 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619301695368 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619301695368 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619301695369 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619301695369 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1619301695372 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part1.sdc " "Synopsys Design Constraints File file not found: 'part1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1619301696038 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1619301696039 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1619301696040 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1619301696040 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1619301696043 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1619301696044 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1619301696045 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1619301696053 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619301696053 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619301696053 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619301696055 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619301696056 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1619301696056 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1619301696057 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1619301696057 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1619301696057 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1619301696057 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619301696057 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619301696102 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1619301696102 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619301696103 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1619301696117 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619301698910 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619301699036 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619301699093 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619301699586 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619301699587 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619301706277 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X56_Y44 X66_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54" { } { { "loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54"} { { 12 { 0 ""} 56 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1619301709800 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619301709800 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1619301709986 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1619301709986 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1619301709986 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619301709988 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.04 " "Total time spent on timing analysis during the Fitter is 0.04 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1619301710317 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619301710328 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1619301710328 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619301710778 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619301710778 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1619301710778 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619301711217 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619301711852 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1619301712046 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/output_files/part1.fit.smsg " "Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/output_files/part1.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619301712105 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 21 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1087 " "Peak virtual memory: 1087 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619301712562 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 17:01:52 2021 " "Processing ended: Sat Apr 24 17:01:52 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619301712562 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619301712562 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619301712562 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619301712562 ""} diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.hier_info b/EE203/Noah Woodlee/Lab2/part1/db/part1.hier_info new file mode 100644 index 0000000..773bb20 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.hier_info @@ -0,0 +1,87 @@ +|part1 +SW[0] => HEX0.DATAB +SW[0] => HEX0.DATAB +SW[0] => HEX0.DATAB +SW[0] => HEX0.DATAB +SW[0] => HEX0.DATAA +SW[0] => HEX0.DATAA +SW[0] => HEX0.DATAA +SW[0] => HEX0.DATAA +SW[0] => HEX0.DATAA +SW[0] => HEX0.DATAB +SW[0] => HEX0.DATAB +SW[0] => HEX0.DATAA +SW[1] => HEX0.OUTPUTSELECT +SW[1] => HEX0.OUTPUTSELECT +SW[1] => HEX0.OUTPUTSELECT +SW[1] => HEX0.OUTPUTSELECT +SW[1] => HEX0.OUTPUTSELECT +SW[1] => HEX0.OUTPUTSELECT +SW[1] => HEX0.OUTPUTSELECT +SW[1] => HEX0.OUTPUTSELECT +SW[1] => HEX0.DATAA +SW[2] => HEX0.OUTPUTSELECT +SW[2] => HEX0.OUTPUTSELECT +SW[2] => HEX0.OUTPUTSELECT +SW[2] => HEX0.OUTPUTSELECT +SW[2] => HEX0.OUTPUTSELECT +SW[2] => HEX0.OUTPUTSELECT +SW[2] => HEX0.OUTPUTSELECT +SW[3] => HEX0.OUTPUTSELECT +SW[3] => HEX0.OUTPUTSELECT +SW[3] => HEX0.OUTPUTSELECT +SW[3] => HEX0.OUTPUTSELECT +SW[3] => HEX0.OUTPUTSELECT +SW[3] => HEX0.OUTPUTSELECT +SW[3] => HEX0.OUTPUTSELECT +SW[4] => HEX1.DATAB +SW[4] => HEX1.DATAB +SW[4] => HEX1.DATAB +SW[4] => HEX1.DATAB +SW[4] => HEX1.DATAA +SW[4] => HEX1.DATAA +SW[4] => HEX1.DATAA +SW[4] => HEX1.DATAA +SW[4] => HEX1.DATAA +SW[4] => HEX1.DATAB +SW[4] => HEX1.DATAB +SW[4] => HEX1.DATAA +SW[5] => HEX1.OUTPUTSELECT +SW[5] => HEX1.OUTPUTSELECT +SW[5] => HEX1.OUTPUTSELECT +SW[5] => HEX1.OUTPUTSELECT +SW[5] => HEX1.OUTPUTSELECT +SW[5] => HEX1.OUTPUTSELECT +SW[5] => HEX1.OUTPUTSELECT +SW[5] => HEX1.OUTPUTSELECT +SW[5] => HEX1.DATAA +SW[6] => HEX1.OUTPUTSELECT +SW[6] => HEX1.OUTPUTSELECT +SW[6] => HEX1.OUTPUTSELECT +SW[6] => HEX1.OUTPUTSELECT +SW[6] => HEX1.OUTPUTSELECT +SW[6] => HEX1.OUTPUTSELECT +SW[6] => HEX1.OUTPUTSELECT +SW[7] => HEX1.OUTPUTSELECT +SW[7] => HEX1.OUTPUTSELECT +SW[7] => HEX1.OUTPUTSELECT +SW[7] => HEX1.OUTPUTSELECT +SW[7] => HEX1.OUTPUTSELECT +SW[7] => HEX1.OUTPUTSELECT +SW[7] => HEX1.OUTPUTSELECT +HEX0[0] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[1] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[2] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[3] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[4] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[5] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX0[6] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE +HEX1[0] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE +HEX1[1] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE +HEX1[2] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE +HEX1[3] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE +HEX1[4] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE +HEX1[5] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE +HEX1[6] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.hif b/EE203/Noah Woodlee/Lab2/part1/db/part1.hif new file mode 100644 index 0000000..0390611 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.hif differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.html b/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.html new file mode 100644 index 0000000..fbc5ab5 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.rdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.rdb new file mode 100644 index 0000000..b1e0351 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.txt b/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.txt new file mode 100644 index 0000000..a463804 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.map.ammdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.ammdb new file mode 100644 index 0000000..790b913 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.map.bpm b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.bpm new file mode 100644 index 0000000..8bddd10 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.map.cdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.cdb new file mode 100644 index 0000000..52eaae3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.map.hdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.hdb new file mode 100644 index 0000000..25a52f7 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.map.kpt b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.kpt new file mode 100644 index 0000000..c918867 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.map.logdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.map.qmsg b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.qmsg new file mode 100644 index 0000000..fb344da --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.map.qmsg @@ -0,0 +1,15 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619301678340 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619301678341 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 17:01:18 2021 " "Processing started: Sat Apr 24 17:01:18 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619301678341 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619301678341 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619301678341 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619301678687 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619301678688 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part1.v 1 1 " "Found 1 design units, including 1 entities, in source file part1.v" { { "Info" "ISGN_ENTITY_NAME" "1 part1 " "Found entity 1: part1" { } { { "part1.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/part1.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619301690612 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619301690612 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part1 " "Elaborating entity \"part1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619301690685 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619301691517 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301692100 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301692100 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301692100 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619301692100 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301692100 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301692100 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! 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Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 101 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "394 " "Peak virtual memory: 394 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619301692418 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 17:01:32 2021 " "Processing ended: Sat Apr 24 17:01:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619301692418 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619301692418 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619301692418 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619301692418 ""} diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.map.rdb b/EE203/Noah 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"Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619301721039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 17:02:00 2021 " "Processing started: Sat Apr 24 17:02:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619301721039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1619301721039 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta part1 -c part1 " "Command: quartus_sta part1 -c part1" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1619301721039 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1619301721105 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " 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"set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721172 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619301721172 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part1_bcd 24 " "Ignored 24 assignments for entity \"part1_bcd\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1_bcd -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was 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"Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721173 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721173 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721173 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721173 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721173 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name 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"WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721174 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619301721174 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part5 24 " "Ignored 24 assignments for entity \"part5\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619301721175 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619301721175 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619301721300 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619301721301 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619301721381 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619301721381 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part1.sdc " "Synopsys Design Constraints File file not found: 'part1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619301721828 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619301721829 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619301721829 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619301721830 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619301721830 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619301721830 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619301721831 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1619301721838 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619301721839 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301721841 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1619301721842 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301721843 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301721844 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301721845 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301721846 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301721847 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619301721852 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619301721891 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Timing Analyzer" 0 -1 1619301721892 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619301725418 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619301725461 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619301725461 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619301725461 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619301725462 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725463 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725464 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725465 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725466 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725467 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725468 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619301725470 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619301725643 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619301725643 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619301725643 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619301725643 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725645 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725646 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725647 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725648 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619301725648 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619301726934 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619301726935 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 106 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 106 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "509 " "Peak virtual memory: 509 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619301726966 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 17:02:06 2021 " "Processing ended: Sat Apr 24 17:02:06 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619301726966 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619301726966 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619301726966 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619301726966 ""} diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.sta.rdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.sta.rdb new file mode 100644 index 0000000..d3172a1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.sta.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.sta_cmp.6_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..c7d1fcf Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.tis_db_list.ddb b/EE203/Noah Woodlee/Lab2/part1/db/part1.tis_db_list.ddb new file mode 100644 index 0000000..73e5ec9 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..cebed4e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..3b76680 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..5f10dc4 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.tmw_info b/EE203/Noah Woodlee/Lab2/part1/db/part1.tmw_info new file mode 100644 index 0000000..0847ca4 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:52 +start_analysis_synthesis:s:00:00:17-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:20-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:08-start_full_compilation diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.vpr.ammdb b/EE203/Noah Woodlee/Lab2/part1/db/part1.vpr.ammdb new file mode 100644 index 0000000..5b49efb Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..0259d60 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.tt_0c_slow.hsd b/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..090de61 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.tt_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.tt_85c_slow.hsd b/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..09ac6ef Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/db/part1.zippleback_io_sim_cache.tt_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part1/db/part1_partition_pins.json b/EE203/Noah Woodlee/Lab2/part1/db/part1_partition_pins.json new file mode 100644 index 0000000..e5c0077 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/db/part1_partition_pins.json @@ -0,0 +1,97 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "HEX0[0]", + "strict" : false + }, + { + "name" : "HEX0[1]", + "strict" : false + }, + { + "name" : "HEX0[2]", + "strict" : false + }, + { + "name" : "HEX0[3]", + "strict" : false + }, + { + "name" : "HEX0[4]", + "strict" : false + }, + { + "name" : "HEX0[5]", + "strict" : false + }, + { + "name" : "HEX0[6]", + "strict" : false + }, + { + "name" : "HEX1[0]", + "strict" : false + }, + { + "name" : "HEX1[1]", + "strict" : false + }, + { + "name" : "HEX1[2]", + "strict" : false + }, + { + "name" : "HEX1[3]", + "strict" : false + }, + { + "name" : "HEX1[4]", + "strict" : false + }, + { + "name" : "HEX1[5]", + "strict" : false + }, + { + "name" : "HEX1[6]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[2]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + }, + { + "name" : "SW[4]", + "strict" : false + }, + { + "name" : "SW[6]", + "strict" : false + }, + { + "name" : "SW[5]", + "strict" : false + }, + { + "name" : "SW[7]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..d89a873 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| George Totolos :| 08/22/2016:| Initial Revision +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a2885da --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +DE10_LITE_Golden_Top.v +platform_setup.tcl +filelist.txt diff --git a/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..d9cea11 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,435 @@ +proc ::setup_project {} { +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name SDC_FILE DE10_LITE_Golden_Top.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS + +#============================================================ +# Accelerometer +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO + +#============================================================ +# Arduino +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..1c1dfa3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/home/gtotolos/Desktop/max10_de10_lite/Golden_Top/", + "acds_version" : "Version 16.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part1/devkits/readme.txt b/EE203/Noah Woodlee/Lab2/part1/devkits/readme.txt new file mode 100644 index 0000000..f6ba267 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/README b/EE203/Noah Woodlee/Lab2/part1/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.db_info b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.db_info new file mode 100644 index 0000000..94e84ee --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sat Apr 24 16:59:18 2021 diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.ammdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.ammdb new file mode 100644 index 0000000..d476d63 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.cdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.cdb new file mode 100644 index 0000000..08f1cfc Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.dfp b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.hdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.hdb new file mode 100644 index 0000000..454b78d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.logdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.rcfdb new file mode 100644 index 0000000..7820268 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.cdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.cdb new file mode 100644 index 0000000..785eee6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.dpi b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.dpi new file mode 100644 index 0000000..a60125d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..c4de05d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..fe40073 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hdb new file mode 100644 index 0000000..9e36796 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.kpt b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.kpt new file mode 100644 index 0000000..1a82a52 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.rrp.hdb b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.rrp.hdb new file mode 100644 index 0000000..ff0a6e5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.rrp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.asm.rpt b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.asm.rpt new file mode 100644 index 0000000..b55f468 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for part1 +Sat Apr 24 17:01:59 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: part1.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Apr 24 17:01:59 2021 ; +; Revision Name ; part1 ; +; Top-level Entity Name ; part1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------------------------+ +; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/output_files/part1.sof ; ++-----------------------------------------------------------------------------------------------+ + + ++-------------------------------------+ +; Assembler Device Options: part1.sof ; ++----------------+--------------------+ +; Option ; Setting ; ++----------------+--------------------+ +; JTAG usercode ; 0x002731F7 ; +; Checksum ; 0x002731F7 ; ++----------------+--------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 17:01:54 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off part1 -c part1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 355 megabytes + Info: Processing ended: Sat Apr 24 17:01:59 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.done b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.done new file mode 100644 index 0000000..96e92d2 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.done @@ -0,0 +1 @@ +Sat Apr 24 17:02:07 2021 diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.rpt b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.rpt new file mode 100644 index 0000000..e3a2d67 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.rpt @@ -0,0 +1,1348 @@ +Fitter report for part1 +Sat Apr 24 17:01:52 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sat Apr 24 17:01:52 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part1 ; +; Top-level Entity Name ; part1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 15 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 15 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 22 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.3% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; LEDR[0] ; PIN_A8 ; QSF Assignment ; +; Location ; ; ; LEDR[1] ; PIN_A9 ; QSF Assignment ; +; Location ; ; ; LEDR[2] ; PIN_A10 ; QSF Assignment ; +; Location ; ; ; LEDR[3] ; PIN_B10 ; QSF Assignment ; +; Location ; ; ; LEDR[4] ; PIN_D13 ; QSF Assignment ; +; Location ; ; ; LEDR[5] ; PIN_C13 ; QSF Assignment ; +; Location ; ; ; LEDR[6] ; PIN_E14 ; QSF Assignment ; +; Location ; ; ; LEDR[7] ; PIN_D14 ; QSF Assignment ; +; Location ; ; ; LEDR[8] ; PIN_A11 ; QSF Assignment ; +; Location ; ; ; LEDR[9] ; PIN_B11 ; QSF Assignment ; +; Location ; ; ; SW[8] ; PIN_B14 ; QSF Assignment ; +; Location ; ; ; SW[9] ; PIN_F15 ; QSF Assignment ; ++----------+----------------+--------------+------------+---------------+----------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 78 ) ; 0.00 % ( 0 / 78 ) ; 0.00 % ( 0 / 78 ) ; +; -- Achieved ; 0.00 % ( 0 / 78 ) ; 0.00 % ( 0 / 78 ) ; 0.00 % ( 0 / 78 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 62 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/output_files/part1.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 15 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 15 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 14 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 1 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 15 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 3 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 22 / 360 ( 6 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.4% / 0.6% / 0.2% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 103 ; +; Average fan-out ; 1.32 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 15 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 15 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 14 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 1 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 15 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 3 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 22 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 109 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 8 ; 0 ; +; -- Output Ports ; 14 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; C10 ; 7 ; 51 ; 54 ; 28 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[2] ; D12 ; 7 ; 51 ; 54 ; 0 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[3] ; C12 ; 7 ; 54 ; 54 ; 28 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[4] ; A12 ; 7 ; 54 ; 54 ; 21 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[5] ; B12 ; 7 ; 49 ; 54 ; 0 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[6] ; A13 ; 7 ; 54 ; 54 ; 14 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[7] ; A14 ; 7 ; 58 ; 54 ; 28 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; HEX0[0] ; C14 ; 7 ; 58 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[1] ; E15 ; 7 ; 74 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[2] ; C15 ; 7 ; 60 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[3] ; C16 ; 7 ; 62 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[4] ; E16 ; 7 ; 74 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[5] ; D17 ; 7 ; 74 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[6] ; C17 ; 7 ; 74 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[0] ; C18 ; 7 ; 69 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[1] ; D18 ; 6 ; 78 ; 49 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[2] ; E18 ; 6 ; 78 ; 49 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[3] ; B16 ; 7 ; 60 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[4] ; A17 ; 7 ; 64 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[5] ; A18 ; 7 ; 66 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[6] ; B17 ; 7 ; 69 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 2 / 60 ( 3 % ) ; 2.5V ; -- ; +; 7 ; 20 / 52 ( 38 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; SW[4] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 433 ; 7 ; SW[6] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 425 ; 7 ; SW[7] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; HEX1[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A18 ; 405 ; 7 ; HEX1[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; SW[5] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; HEX1[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B17 ; 402 ; 7 ; HEX1[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; SW[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C15 ; 418 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C16 ; 416 ; 7 ; HEX0[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C17 ; 391 ; 7 ; HEX0[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C18 ; 400 ; 7 ; HEX1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; HEX0[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D18 ; 385 ; 6 ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 388 ; 7 ; HEX0[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; HEX0[0] ; Incomplete set of assignments ; +; HEX0[1] ; Incomplete set of assignments ; +; HEX0[2] ; Incomplete set of assignments ; +; HEX0[3] ; Incomplete set of assignments ; +; HEX0[4] ; Incomplete set of assignments ; +; HEX0[5] ; Incomplete set of assignments ; +; HEX0[6] ; Incomplete set of assignments ; +; HEX1[0] ; Incomplete set of assignments ; +; HEX1[1] ; Incomplete set of assignments ; +; HEX1[2] ; Incomplete set of assignments ; +; HEX1[3] ; Incomplete set of assignments ; +; HEX1[4] ; Incomplete set of assignments ; +; HEX1[5] ; Incomplete set of assignments ; +; HEX1[6] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |part1 ; 15 (15) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 22 ; 0 ; 15 (15) ; 0 (0) ; 0 (0) ; 0 ; |part1 ; part1 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; SW[0] ; ; ; +; - HEX0~0 ; 0 ; 6 ; +; - HEX0~1 ; 0 ; 6 ; +; - HEX0~2 ; 0 ; 6 ; +; - HEX0~3 ; 0 ; 6 ; +; - HEX0~4 ; 0 ; 6 ; +; - HEX0~5 ; 0 ; 6 ; +; - HEX0~6 ; 0 ; 6 ; +; SW[2] ; ; ; +; - HEX0~0 ; 0 ; 6 ; +; - HEX0~1 ; 0 ; 6 ; +; - HEX0~2 ; 0 ; 6 ; +; - HEX0~3 ; 0 ; 6 ; +; - HEX0~4 ; 0 ; 6 ; +; - HEX0~5 ; 0 ; 6 ; +; - HEX0~6 ; 0 ; 6 ; +; SW[1] ; ; ; +; - HEX0~0 ; 0 ; 6 ; +; - HEX0~1 ; 0 ; 6 ; +; - HEX0~2 ; 0 ; 6 ; +; - HEX0~3 ; 0 ; 6 ; +; - HEX0~4 ; 0 ; 6 ; +; - HEX0~5 ; 0 ; 6 ; +; - HEX0~6 ; 0 ; 6 ; +; SW[3] ; ; ; +; - HEX0~0 ; 0 ; 6 ; +; - HEX0~1 ; 0 ; 6 ; +; - HEX0~2 ; 0 ; 6 ; +; - HEX0~3 ; 0 ; 6 ; +; - HEX0~4 ; 0 ; 6 ; +; - HEX0~5 ; 0 ; 6 ; +; - HEX0~6 ; 0 ; 6 ; +; SW[4] ; ; ; +; - HEX1~0 ; 0 ; 6 ; +; - HEX1~1 ; 0 ; 6 ; +; - HEX1~2 ; 0 ; 6 ; +; - HEX1~3 ; 0 ; 6 ; +; - HEX1~4 ; 0 ; 6 ; +; - HEX1~5 ; 0 ; 6 ; +; - HEX1~6 ; 0 ; 6 ; +; SW[6] ; ; ; +; - HEX1~0 ; 0 ; 6 ; +; - HEX1~1 ; 0 ; 6 ; +; - HEX1~2 ; 0 ; 6 ; +; - HEX1~3 ; 0 ; 6 ; +; - HEX1~4 ; 0 ; 6 ; +; - HEX1~5 ; 0 ; 6 ; +; - HEX1~6 ; 0 ; 6 ; +; SW[5] ; ; ; +; - HEX1~0 ; 0 ; 6 ; +; - HEX1~1 ; 0 ; 6 ; +; - HEX1~2 ; 0 ; 6 ; +; - HEX1~3 ; 0 ; 6 ; +; - HEX1~4 ; 0 ; 6 ; +; - HEX1~5 ; 0 ; 6 ; +; - HEX1~6 ; 0 ; 6 ; +; SW[7] ; ; ; +; - HEX1~0 ; 0 ; 6 ; +; - HEX1~1 ; 0 ; 6 ; +; - HEX1~2 ; 0 ; 6 ; +; - HEX1~3 ; 0 ; 6 ; +; - HEX1~4 ; 0 ; 6 ; +; - HEX1~5 ; 0 ; 6 ; +; - HEX1~6 ; 0 ; 6 ; ++---------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 26 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 1 / 5,382 ( < 1 % ) ; +; C4 interconnects ; 25 / 106,704 ( < 1 % ) ; +; Direct links ; 1 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 49,760 ( 0 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 5 / 5,406 ( < 1 % ) ; +; R4 interconnects ; 39 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 5.00) ; Number of LABs (Total = 3) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 2 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 5.00) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 2 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 3) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 2 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 2.67) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 2 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 22 ; 22 ; 0 ; 0 ; 22 ; 22 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 8 ; 14 ; 0 ; 8 ; 0 ; 0 ; 14 ; 0 ; 22 ; 22 ; 22 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 22 ; 0 ; 0 ; 22 ; 22 ; 0 ; 0 ; 22 ; 22 ; 22 ; 22 ; 22 ; 22 ; 8 ; 22 ; 22 ; 22 ; 14 ; 8 ; 22 ; 14 ; 22 ; 22 ; 8 ; 22 ; 0 ; 0 ; 0 ; 22 ; 22 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device 10M50DAF484C6GES for design "part1" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds. +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/output_files/part1.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 21 warnings + Info: Peak virtual memory: 1087 megabytes + Info: Processing ended: Sat Apr 24 17:01:52 2021 + Info: Elapsed time: 00:00:19 + Info: Total CPU time (on all processors): 00:00:22 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/output_files/part1.fit.smsg. + + diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.smsg b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.summary b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.summary new file mode 100644 index 0000000..3c0919e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Sat Apr 24 17:01:52 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part1 +Top-level Entity Name : part1 +Family : MAX 10 +Device : 10M50DAF484C6GES +Timing Models : Preliminary +Total logic elements : 15 / 49,760 ( < 1 % ) + Total combinational functions : 15 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 22 / 360 ( 6 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.flow.rpt b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.flow.rpt new file mode 100644 index 0000000..f3939d5 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.flow.rpt @@ -0,0 +1,137 @@ +Flow report for part1 +Sat Apr 24 17:02:06 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sat Apr 24 17:01:59 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part1 ; +; Top-level Entity Name ; part1 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 15 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 15 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 22 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/24/2021 17:01:18 ; +; Main task ; Compilation ; +; Revision Name ; part1 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 164639278517.161930167805732 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 393 MB ; 00:00:32 ; +; Fitter ; 00:00:19 ; 1.0 ; 1087 MB ; 00:00:22 ; +; Assembler ; 00:00:05 ; 1.0 ; 355 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:06 ; 1.0 ; 509 MB ; 00:00:06 ; +; Total ; 00:00:44 ; -- ; -- ; 00:01:05 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+-------------------+------------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+-------------------+------------------+------------+----------------+ +; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; ++----------------------+-------------------+------------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1 +quartus_fit --read_settings_files=off --write_settings_files=off part1 -c part1 +quartus_asm --read_settings_files=off --write_settings_files=off part1 -c part1 +quartus_sta part1 -c part1 + + + diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.jdi b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.jdi new file mode 100644 index 0000000..351273c --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.map.rpt b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.map.rpt new file mode 100644 index 0000000..1830eaa --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.map.rpt @@ -0,0 +1,384 @@ +Analysis & Synthesis report for part1 +Sat Apr 24 17:01:32 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Apr 24 17:01:32 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part1 ; +; Top-level Entity Name ; part1 ; +; Family ; MAX 10 ; +; Total logic elements ; 14 ; +; Total combinational functions ; 14 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 22 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Top-level entity name ; part1 ; part1 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; part1.v ; yes ; User Verilog HDL File ; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/part1.v ; ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimated Total logic elements ; 14 ; +; ; ; +; Total combinational functions ; 14 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 14 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 14 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 22 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; SW[0]~input ; +; Maximum fan-out ; 7 ; +; Total fan-out ; 92 ; +; Average fan-out ; 1.59 ; ++---------------------------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |part1 ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 ; 0 ; 0 ; |part1 ; part1 ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 22 ; +; cycloneiii_lcell_comb ; 16 ; +; normal ; 16 ; +; 1 data inputs ; 2 ; +; 4 data inputs ; 14 ; +; ; ; +; Max LUT depth ; 2.00 ; +; Average LUT depth ; 1.50 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 17:01:18 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file part1.v + Info (12023): Found entity 1: part1 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/part1.v Line: 1 +Info (12127): Elaborating entity "part1" for the top level hierarchy +Info (286030): Timing-Driven Synthesis is running +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 36 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 8 input pins + Info (21059): Implemented 14 output pins + Info (21061): Implemented 14 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 101 warnings + Info: Peak virtual memory: 394 megabytes + Info: Processing ended: Sat Apr 24 17:01:32 2021 + Info: Elapsed time: 00:00:14 + Info: Total CPU time (on all processors): 00:00:32 + + diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.map.summary b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.map.summary new file mode 100644 index 0000000..7190490 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Sat Apr 24 17:01:32 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part1 +Top-level Entity Name : part1 +Family : MAX 10 +Total logic elements : 14 + Total combinational functions : 14 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 22 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.pin b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.pin new file mode 100644 index 0000000..58269e0 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2020 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +CHIP "part1" ASSIGNED TO AN: 10M50DAF484C6GES + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +SW[4] : A12 : input : 2.5 V : : 7 : Y +SW[6] : A13 : input : 2.5 V : : 7 : Y +SW[7] : A14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +HEX1[4] : A17 : output : 2.5 V : : 7 : Y +HEX1[5] : A18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +SW[5] : B12 : input : 2.5 V : : 7 : Y +GND : B13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +HEX1[3] : B16 : output : 2.5 V : : 7 : Y +HEX1[6] : B17 : output : 2.5 V : : 7 : Y +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[0] : C10 : input : 2.5 V : : 7 : Y +SW[1] : C11 : input : 2.5 V : : 7 : Y +SW[3] : C12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +HEX0[0] : C14 : output : 2.5 V : : 7 : Y +HEX0[2] : C15 : output : 2.5 V : : 7 : Y +HEX0[3] : C16 : output : 2.5 V : : 7 : Y +HEX0[6] : C17 : output : 2.5 V : : 7 : Y +HEX1[0] : C18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +SW[2] : D12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +HEX0[5] : D17 : output : 2.5 V : : 7 : Y +HEX1[1] : D18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +HEX0[1] : E15 : output : 2.5 V : : 7 : Y +HEX0[4] : E16 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +HEX1[2] : E18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.pof b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.pof new file mode 100644 index 0000000..3d77bcb Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.pof differ diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sld b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sof b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sof new file mode 100644 index 0000000..979febe Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sof differ diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sta.rpt b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sta.rpt new file mode 100644 index 0000000..d5c9202 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sta.rpt @@ -0,0 +1,622 @@ +Timing Analyzer report for part1 +Sat Apr 24 17:02:06 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; part1 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.5% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 8 ; 8 ; +; Unconstrained Input Port Paths ; 56 ; 56 ; +; Unconstrained Output Ports ; 14 ; 14 ; +; Unconstrained Output Port Paths ; 56 ; 56 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 17:02:00 2021 +Info: Command: quartus_sta part1 -c part1 +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 106 warnings + Info: Peak virtual memory: 509 megabytes + Info: Processing ended: Sat Apr 24 17:02:06 2021 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 + + diff --git a/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sta.summary b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/output_files/part1.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/Lab2/part1/part1.qpf b/EE203/Noah Woodlee/Lab2/part1/part1.qpf new file mode 100644 index 0000000..d078438 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/part1.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:13:22 April 16, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "20:13:22 April 16, 2021" + +# Revisions + +PROJECT_REVISION = "part1" diff --git a/EE203/Noah Woodlee/Lab2/part1/part1.qsf b/EE203/Noah Woodlee/Lab2/part1/part1.qsf new file mode 100644 index 0000000..6c53ec1 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/part1.qsf @@ -0,0 +1,104 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:13:23 April 16, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part1_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:13:22 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top +set_global_assignment -name VERILOG_FILE part1.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part1/part1.qsf.bak b/EE203/Noah Woodlee/Lab2/part1/part1.qsf.bak new file mode 100644 index 0000000..09b9aea --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/part1.qsf.bak @@ -0,0 +1,49 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:13:23 April 16, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part1_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:13:22 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part1/part1.qws b/EE203/Noah Woodlee/Lab2/part1/part1.qws new file mode 100644 index 0000000..f0f5014 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part1/part1.qws differ diff --git a/EE203/Noah Woodlee/Lab2/part1/part1.v b/EE203/Noah Woodlee/Lab2/part1/part1.v new file mode 100644 index 0000000..93f5fdc --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/part1.v @@ -0,0 +1,17 @@ +module part1(SW, HEX0, HEX1); + input [7:0] SW; + output [6:0] HEX0, HEX1; + + assign HEX0=SW[3]? (SW[0]? 7'b0010_000:7'b0000_000): + (SW[2]? (SW[1]? (SW[0]? 7'b1111_000:7'b0000_010): + (SW[0]? 7'b0010_010:7'b0011_001)): + (SW[1]? (SW[0]? 7'b0110_000:7'b0100_100): + (SW[0]? 7'b1111_001:7'b1000_000))); + + assign HEX1=SW[7]? (SW[4]? 7'b0010_000:7'b0000_000): + (SW[6]? (SW[5]? (SW[4]? 7'b1111_000:7'b0000_010): + (SW[4]? 7'b0010_010:7'b0011_001)): + (SW[5]? (SW[4]? 7'b0110_000:7'b0100_100): + (SW[4]? 7'b1111_001:7'b1000_000))); + +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part1/part1.v.bak b/EE203/Noah Woodlee/Lab2/part1/part1.v.bak new file mode 100644 index 0000000..be9ca57 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/part1.v.bak @@ -0,0 +1,17 @@ +module part1_bcd(SW, HEX0, HEX1); + input [7:0] SW; + output [6:0] HEX0, HEX1; + + assign HEX0=SW[3]? (SW[0]? 7'b0010_000:7'b0000_000): + (SW[2]? (SW[1]? (SW[0]? 7'b1111_000:7'b0000_010): + (SW[0]? 7'b0010_010:7'b0011_001)): + (SW[1]? (SW[0]? 7'b0110_000:7'b0100_100): + (SW[0]? 7'b1111_001:7'b1000_000))); + + assign HEX1=SW[7]? (SW[4]? 7'b0010_000:7'b0000_000): + (SW[6]? (SW[5]? (SW[4]? 7'b1111_000:7'b0000_010): + (SW[4]? 7'b0010_010:7'b0011_001)): + (SW[5]? (SW[4]? 7'b0110_000:7'b0100_100): + (SW[4]? 7'b1111_001:7'b1000_000))); + +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part1/part1_assignment_defaults.qdf b/EE203/Noah Woodlee/Lab2/part1/part1_assignment_defaults.qdf new file mode 100644 index 0000000..a7817df --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part1/part1_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 16:59:18 April 24, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value ENABLE +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/EE203/Noah Woodlee/Lab2/part2/atom_netlists/part2.qsf b/EE203/Noah Woodlee/Lab2/part2/atom_netlists/part2.qsf new file mode 100644 index 0000000..b37df22 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/atom_netlists/part2.qsf @@ -0,0 +1,69 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:26:21 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part2.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top diff --git a/EE203/Noah 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Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619309990763 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 19:19:50 2021 " "Processing started: Sat Apr 24 19:19:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619309990763 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619309990763 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part2 -c part2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part2 -c part2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619309990763 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619309991112 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619309993884 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619309993983 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "358 " "Peak virtual memory: 358 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619309995221 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 19:19:55 2021 " "Processing ended: Sat Apr 24 19:19:55 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619309995221 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619309995221 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619309995221 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619309995221 ""} diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.asm.rdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.asm.rdb new file mode 100644 index 0000000..79e8c78 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.asm.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.asm_labs.ddb b/EE203/Noah Woodlee/Lab2/part2/db/part2.asm_labs.ddb new file mode 100644 index 0000000..11bf451 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.cbx.xml b/EE203/Noah Woodlee/Lab2/part2/db/part2.cbx.xml new file mode 100644 index 0000000..3442f78 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.bpm b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.bpm new file mode 100644 index 0000000..ecba5d2 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.cdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.cdb new file mode 100644 index 0000000..7aee5e5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.hdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.hdb new file mode 100644 index 0000000..0e87462 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.idb b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.idb new file mode 100644 index 0000000..9f9176f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.idb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.logdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.logdb new file mode 100644 index 0000000..f6c1f2d --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.logdb @@ -0,0 +1,60 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;18;18;0;0;18;18;0;0;0;0;0;0;14;0;0;0;4;14;0;4;0;0;14;0;18;18;18;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,18;0;0;18;18;0;0;18;18;18;18;18;18;4;18;18;18;14;4;18;14;18;18;4;18;0;0;0;18;18, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.rdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.rdb new file mode 100644 index 0000000..89ff261 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp_merge.kpt b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp_merge.kpt new file mode 100644 index 0000000..a62466c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.db_info b/EE203/Noah Woodlee/Lab2/part2/db/part2.db_info new file mode 100644 index 0000000..4201d3a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sat Apr 24 19:15:51 2021 diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.fit.qmsg b/EE203/Noah Woodlee/Lab2/part2/db/part2.fit.qmsg new file mode 100644 index 0000000..9b043f2 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.fit.qmsg @@ -0,0 +1,54 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1619309970781 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619309970781 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part2 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619309970792 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619309970856 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619309970856 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1619309971244 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619309971259 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619309971431 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 0 { 0 ""} 0 85 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619309971445 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 0 { 0 ""} 0 87 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619309971445 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 0 { 0 ""} 0 89 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619309971445 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 0 { 0 ""} 0 91 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619309971445 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 0 { 0 ""} 0 93 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619309971445 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 0 { 0 ""} 0 95 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619309971445 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 0 { 0 ""} 0 97 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619309971445 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619309971445 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1619309971445 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619309971447 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619309971447 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619309971447 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619309971447 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1619309971451 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part2.sdc " "Synopsys Design Constraints File file not found: 'part2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1619309972116 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1619309972117 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1619309972118 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1619309972118 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1619309972121 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1619309972121 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1619309972122 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1619309972129 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619309972130 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619309972130 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619309972131 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619309972132 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1619309972133 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1619309972133 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1619309972133 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1619309972133 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1619309972134 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619309972134 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619309972175 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1619309972175 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619309972176 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1619309972190 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619309975039 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619309975159 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619309975212 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619309975662 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619309975662 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619309982331 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X56_Y44 X66_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54" { } { { "loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54"} { { 12 { 0 ""} 56 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1619309985861 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619309985861 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1619309986044 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1619309986044 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1619309986044 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619309986048 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.04 " "Total time spent on timing analysis during the Fitter is 0.04 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1619309986368 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619309986378 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1619309986378 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619309986823 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619309986823 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1619309986823 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619309987250 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619309987885 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1619309988077 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/output_files/part2.fit.smsg " "Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/output_files/part2.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619309988141 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 25 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1085 " "Peak virtual memory: 1085 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619309988603 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 19:19:48 2021 " "Processing ended: Sat Apr 24 19:19:48 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619309988603 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619309988603 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619309988603 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619309988603 ""} diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.hier_info b/EE203/Noah Woodlee/Lab2/part2/db/part2.hier_info new file mode 100644 index 0000000..3eca858 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.hier_info @@ -0,0 +1,85 @@ +|part2 +SW[0] => V[0].IN2 +SW[1] => V[1].IN1 +SW[2] => V[2].IN1 +SW[3] => V[3].IN1 +HEX0[0] <= bcd:B0.port1 +HEX0[1] <= bcd:B0.port1 +HEX0[2] <= bcd:B0.port1 +HEX0[3] <= bcd:B0.port1 +HEX0[4] <= bcd:B0.port1 +HEX0[5] <= bcd:B0.port1 +HEX0[6] <= bcd:B0.port1 +HEX1[0] <= z.DB_MAX_OUTPUT_PORT_TYPE +HEX1[1] <= +HEX1[2] <= +HEX1[3] <= z.DB_MAX_OUTPUT_PORT_TYPE +HEX1[4] <= z.DB_MAX_OUTPUT_PORT_TYPE +HEX1[5] <= z.DB_MAX_OUTPUT_PORT_TYPE +HEX1[6] <= + + +|part2|mux_2to1:M0 +IN1[0] => OUT.DATAA +IN1[1] => OUT.DATAA +IN1[2] => OUT.DATAA +IN1[3] => OUT.DATAA +IN2[0] => OUT.DATAB +IN2[1] => OUT.DATAB +IN2[2] => OUT.DATAB +IN2[3] => OUT.DATAB +S => OUT.OUTPUTSELECT +S => OUT.OUTPUTSELECT +S => OUT.OUTPUTSELECT +S => OUT.OUTPUTSELECT +OUT[0] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= OUT.DB_MAX_OUTPUT_PORT_TYPE + + +|part2|bcd:B0 +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAA +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.DATAA +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +OUT[0] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[4] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[5] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[6] <= OUT.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.hif b/EE203/Noah Woodlee/Lab2/part2/db/part2.hif new file mode 100644 index 0000000..9d280b1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.hif differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.html b/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.html new file mode 100644 index 0000000..5b0d3d6 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.html @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
B04000700000000
M09000400000000
diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.rdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.rdb new file mode 100644 index 0000000..7724fb2 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.txt b/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.txt new file mode 100644 index 0000000..743d23b --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.lpc.txt @@ -0,0 +1,8 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; B0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; M0 ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map.ammdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.ammdb new file mode 100644 index 0000000..790b913 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map.bpm b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.bpm new file mode 100644 index 0000000..de5fe5a Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map.cdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.cdb new file mode 100644 index 0000000..4ec8d80 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map.hdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.hdb new file mode 100644 index 0000000..361e863 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map.kpt b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.kpt new file mode 100644 index 0000000..59afe45 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map.logdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map.qmsg b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.qmsg new file mode 100644 index 0000000..5024096 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.qmsg @@ -0,0 +1,20 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619309955053 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619309955054 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 19:19:14 2021 " "Processing started: Sat Apr 24 19:19:14 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619309955054 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619309955054 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619309955054 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619309955374 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619309955374 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part2.v 3 3 " "Found 3 design units, including 3 entities, in source file part2.v" { { "Info" "ISGN_ENTITY_NAME" "1 bcd " "Found entity 1: bcd" { } { { "part2.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619309966923 ""} { "Info" "ISGN_ENTITY_NAME" "2 mux_2to1 " "Found entity 2: mux_2to1" { } { { "part2.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 13 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619309966923 ""} { "Info" "ISGN_ENTITY_NAME" "3 part2 " "Found entity 3: part2" { } { { "part2.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619309966923 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619309966923 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part2 " "Elaborating entity \"part2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619309966990 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 part2.v(31) " "Verilog HDL assignment warning at part2.v(31): truncated value with size 32 to match size of target (1)" { } { { "part2.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1619309966992 "|part2"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_2to1 mux_2to1:M0 " "Elaborating entity \"mux_2to1\" for hierarchy \"mux_2to1:M0\"" { } { { "part2.v" "M0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 35 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619309967023 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd bcd:B0 " "Elaborating entity \"bcd\" for hierarchy \"bcd:B0\"" { } { { "part2.v" "B0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619309967027 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[1\] GND " "Pin \"HEX1\[1\]\" is stuck at GND" { } { { "part2.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619309967683 "|part2|HEX1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[2\] GND " "Pin \"HEX1\[2\]\" is stuck at GND" { } { { "part2.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619309967683 "|part2|HEX1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[6\] VCC " "Pin \"HEX1\[6\]\" is stuck at VCC" { } { { "part2.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619309967683 "|part2|HEX1[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1619309967683 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619309967789 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309968315 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1619309968460 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619309968460 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1619309968578 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1619309968578 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1619309968578 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1619309968578 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 131 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 131 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "396 " "Peak virtual memory: 396 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619309968592 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 19:19:28 2021 " "Processing ended: Sat Apr 24 19:19:28 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619309968592 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619309968592 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619309968592 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619309968592 ""} diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map.rdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.rdb new file mode 100644 index 0000000..3856f84 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.map.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.cdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.cdb new file mode 100644 index 0000000..fc953ca Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.hdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.hdb new file mode 100644 index 0000000..2c6a5ed Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.logdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.pre_map.hdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.pre_map.hdb new file mode 100644 index 0000000..c234ce0 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.pre_map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.quiproj.8245.rdr.flock b/EE203/Noah Woodlee/Lab2/part2/db/part2.quiproj.8245.rdr.flock new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.root_partition.map.reg_db.cdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..f036abe Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.root_partition.map.reg_db.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.routing.rdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.routing.rdb new file mode 100644 index 0000000..52f84c1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.routing.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv.hdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv.hdb new file mode 100644 index 0000000..2f98df5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv_sg.cdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv_sg.cdb new file mode 100644 index 0000000..45b5877 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv_sg.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv_sg_swap.cdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv_sg_swap.cdb new file mode 100644 index 0000000..9c3c22b Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.rtlv_sg_swap.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.sld_design_entry.sci b/EE203/Noah Woodlee/Lab2/part2/db/part2.sld_design_entry.sci new file mode 100644 index 0000000..7d39add Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.sld_design_entry.sci differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.sld_design_entry_dsc.sci b/EE203/Noah Woodlee/Lab2/part2/db/part2.sld_design_entry_dsc.sci new file mode 100644 index 0000000..7d39add Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.smart_action.txt b/EE203/Noah Woodlee/Lab2/part2/db/part2.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.sta.qmsg b/EE203/Noah Woodlee/Lab2/part2/db/part2.sta.qmsg new file mode 100644 index 0000000..bac272f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.sta.qmsg @@ -0,0 +1,56 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619309996954 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619309996954 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 19:19:56 2021 " "Processing started: Sat Apr 24 19:19:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619309996954 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1619309996954 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta part2 -c part2 " "Command: quartus_sta part2 -c part2" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1619309996955 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1619309997021 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997090 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619309997090 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part1 24 " "Ignored 24 assignments for entity \"part1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997091 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for 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"part1_bcd 24 " "Ignored 24 assignments for entity \"part1_bcd\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1_bcd -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL 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{ } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment 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"Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id 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"WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id 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-1 1619309997092 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997092 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619309997092 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part4 24 " "Ignored 24 assignments for entity \"part4\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part4 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part4 -section_id Top was ignored" { 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1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 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"Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997094 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619309997094 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part5 24 " "Ignored 24 assignments for entity \"part5\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619309997095 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619309997095 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619309997222 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619309997222 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619309997293 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619309997293 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part2.sdc " "Synopsys Design Constraints File file not found: 'part2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619309997729 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619309997730 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619309997731 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619309997731 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619309997731 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619309997732 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619309997733 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1619309997739 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619309997740 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619309997742 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1619309997743 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619309997745 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619309997746 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619309997751 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619309997752 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619309997753 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619309997759 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619309997800 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Timing Analyzer" 0 -1 1619309997800 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619310001370 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619310001415 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619310001416 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619310001416 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619310001416 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001417 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001419 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001420 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001421 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001421 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001422 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619310001424 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619310001591 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619310001591 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619310001591 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619310001592 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001593 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001594 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001595 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001596 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619310001597 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619310002881 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619310002881 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 131 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 131 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "509 " "Peak virtual memory: 509 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619310002914 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 19:20:02 2021 " "Processing ended: Sat Apr 24 19:20:02 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619310002914 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619310002914 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619310002914 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619310002914 ""} diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.sta.rdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.sta.rdb new file mode 100644 index 0000000..9863d10 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.sta.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.sta_cmp.6_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..bcc5130 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.tis_db_list.ddb b/EE203/Noah Woodlee/Lab2/part2/db/part2.tis_db_list.ddb new file mode 100644 index 0000000..73e5ec9 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..23d6d27 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..128644f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..2d56c3d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.tmw_info b/EE203/Noah Woodlee/Lab2/part2/db/part2.tmw_info new file mode 100644 index 0000000..340cca6 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:51 +start_analysis_synthesis:s:00:00:16-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:20-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:08-start_full_compilation diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.vpr.ammdb b/EE203/Noah Woodlee/Lab2/part2/db/part2.vpr.ammdb new file mode 100644 index 0000000..540a066 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..0259d60 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.tt_0c_slow.hsd b/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..090de61 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.tt_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.tt_85c_slow.hsd b/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..09ac6ef Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/db/part2.zippleback_io_sim_cache.tt_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part2/db/part2_partition_pins.json b/EE203/Noah Woodlee/Lab2/part2/db/part2_partition_pins.json new file mode 100644 index 0000000..9ceac2a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/part2_partition_pins.json @@ -0,0 +1,69 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "HEX0[0]", + "strict" : false + }, + { + "name" : "HEX0[1]", + "strict" : false + }, + { + "name" : "HEX0[2]", + "strict" : false + }, + { + "name" : "HEX0[3]", + "strict" : false + }, + { + "name" : "HEX0[4]", + "strict" : false + }, + { + "name" : "HEX0[5]", + "strict" : false + }, + { + "name" : "HEX0[6]", + "strict" : false + }, + { + "name" : "HEX1[0]", + "strict" : false + }, + { + "name" : "HEX1[3]", + "strict" : false + }, + { + "name" : "HEX1[4]", + "strict" : false + }, + { + "name" : "HEX1[5]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[2]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part2/db/prev_cmp_part2.qmsg b/EE203/Noah Woodlee/Lab2/part2/db/prev_cmp_part2.qmsg new file mode 100644 index 0000000..7a0bd35 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/db/prev_cmp_part2.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1618622830609 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1618622830609 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 16 20:27:10 2021 " "Processing started: Fri Apr 16 20:27:10 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1618622830609 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1618622830609 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1618622830609 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1618622830929 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1618622830929 ""} diff --git a/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..d89a873 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| George Totolos :| 08/22/2016:| Initial Revision +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a2885da --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +DE10_LITE_Golden_Top.v +platform_setup.tcl +filelist.txt diff --git a/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..d9cea11 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,435 @@ +proc ::setup_project {} { +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name SDC_FILE DE10_LITE_Golden_Top.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS + +#============================================================ +# Accelerometer +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO + +#============================================================ +# Arduino +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..1c1dfa3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/home/gtotolos/Desktop/max10_de10_lite/Golden_Top/", + "acds_version" : "Version 16.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part2/devkits/readme.txt b/EE203/Noah Woodlee/Lab2/part2/devkits/readme.txt new file mode 100644 index 0000000..f6ba267 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/README b/EE203/Noah Woodlee/Lab2/part2/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.db_info b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.db_info new file mode 100644 index 0000000..4201d3a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sat Apr 24 19:15:51 2021 diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.ammdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.ammdb new file mode 100644 index 0000000..fa50f87 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.cdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.cdb new file mode 100644 index 0000000..d608ec0 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.dfp b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.hdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.hdb new file mode 100644 index 0000000..120a31e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.logdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.rcfdb new file mode 100644 index 0000000..e31c252 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.cdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.cdb new file mode 100644 index 0000000..1ed1d4c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.dpi b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.dpi new file mode 100644 index 0000000..57df5f8 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..fffbad0 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..8529c86 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hdb new file mode 100644 index 0000000..c642e65 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.kpt b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.kpt new file mode 100644 index 0000000..1b8b924 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.rrp.hdb b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.rrp.hdb new file mode 100644 index 0000000..87cff24 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/incremental_db/compiled_partitions/part2.rrp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.asm.rpt b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.asm.rpt new file mode 100644 index 0000000..f5605fd --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for part2 +Sat Apr 24 19:19:55 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: part2.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Apr 24 19:19:55 2021 ; +; Revision Name ; part2 ; +; Top-level Entity Name ; part2 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------------------------+ +; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/output_files/part2.sof ; ++-----------------------------------------------------------------------------------------------+ + + ++-------------------------------------+ +; Assembler Device Options: part2.sof ; ++----------------+--------------------+ +; Option ; Setting ; ++----------------+--------------------+ +; JTAG usercode ; 0x00271D02 ; +; Checksum ; 0x00271D02 ; ++----------------+--------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 19:19:50 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off part2 -c part2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 358 megabytes + Info: Processing ended: Sat Apr 24 19:19:55 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.done b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.done new file mode 100644 index 0000000..7103d50 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.done @@ -0,0 +1 @@ +Sat Apr 24 19:20:03 2021 diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.rpt b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.rpt new file mode 100644 index 0000000..36f6b1f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.rpt @@ -0,0 +1,1314 @@ +Fitter report for part2 +Sat Apr 24 19:19:48 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sat Apr 24 19:19:48 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part2 ; +; Top-level Entity Name ; part2 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 9 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 9 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 18 / 360 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.3% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; LEDR[0] ; PIN_A8 ; QSF Assignment ; +; Location ; ; ; LEDR[1] ; PIN_A9 ; QSF Assignment ; +; Location ; ; ; LEDR[2] ; PIN_A10 ; QSF Assignment ; +; Location ; ; ; LEDR[3] ; PIN_B10 ; QSF Assignment ; +; Location ; ; ; LEDR[4] ; PIN_D13 ; QSF Assignment ; +; Location ; ; ; LEDR[5] ; PIN_C13 ; QSF Assignment ; +; Location ; ; ; LEDR[6] ; PIN_E14 ; QSF Assignment ; +; Location ; ; ; LEDR[7] ; PIN_D14 ; QSF Assignment ; +; Location ; ; ; LEDR[8] ; PIN_A11 ; QSF Assignment ; +; Location ; ; ; LEDR[9] ; PIN_B11 ; QSF Assignment ; +; Location ; ; ; SW[4] ; PIN_A12 ; QSF Assignment ; +; Location ; ; ; SW[5] ; PIN_B12 ; QSF Assignment ; +; Location ; ; ; SW[6] ; PIN_A13 ; QSF Assignment ; +; Location ; ; ; SW[7] ; PIN_A14 ; QSF Assignment ; +; Location ; ; ; SW[8] ; PIN_B14 ; QSF Assignment ; +; Location ; ; ; SW[9] ; PIN_F15 ; QSF Assignment ; ++----------+----------------+--------------+------------+---------------+----------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; +; -- Achieved ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 48 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/output_files/part2.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 9 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 9 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 7 ; +; -- 3 input functions ; 1 ; +; -- <=2 input functions ; 1 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 9 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 18 / 360 ( 5 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.2% / 0.3% / 0.1% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 71 ; +; Average fan-out ; 1.11 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 9 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 9 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 7 ; 0 ; +; -- 3 input functions ; 1 ; 0 ; +; -- <=2 input functions ; 1 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 9 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 18 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 77 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 4 ; 0 ; +; -- Output Ports ; 14 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; C10 ; 7 ; 51 ; 54 ; 28 ; 7 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[2] ; D12 ; 7 ; 51 ; 54 ; 0 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[3] ; C12 ; 7 ; 54 ; 54 ; 28 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; HEX0[0] ; C14 ; 7 ; 58 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[1] ; E15 ; 7 ; 74 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[2] ; C15 ; 7 ; 60 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[3] ; C16 ; 7 ; 62 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[4] ; E16 ; 7 ; 74 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[5] ; D17 ; 7 ; 74 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[6] ; C17 ; 7 ; 74 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[0] ; C18 ; 7 ; 69 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[1] ; D18 ; 6 ; 78 ; 49 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[2] ; E18 ; 6 ; 78 ; 49 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[3] ; B16 ; 7 ; 60 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[4] ; A17 ; 7 ; 64 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[5] ; A18 ; 7 ; 66 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[6] ; B17 ; 7 ; 69 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 2 / 60 ( 3 % ) ; 2.5V ; -- ; +; 7 ; 16 / 52 ( 31 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; HEX1[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A18 ; 405 ; 7 ; HEX1[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; HEX1[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B17 ; 402 ; 7 ; HEX1[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; SW[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C15 ; 418 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C16 ; 416 ; 7 ; HEX0[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C17 ; 391 ; 7 ; HEX0[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C18 ; 400 ; 7 ; HEX1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; HEX0[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D18 ; 385 ; 6 ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 388 ; 7 ; HEX0[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; HEX0[0] ; Incomplete set of assignments ; +; HEX0[1] ; Incomplete set of assignments ; +; HEX0[2] ; Incomplete set of assignments ; +; HEX0[3] ; Incomplete set of assignments ; +; HEX0[4] ; Incomplete set of assignments ; +; HEX0[5] ; Incomplete set of assignments ; +; HEX0[6] ; Incomplete set of assignments ; +; HEX1[0] ; Incomplete set of assignments ; +; HEX1[1] ; Incomplete set of assignments ; +; HEX1[2] ; Incomplete set of assignments ; +; HEX1[3] ; Incomplete set of assignments ; +; HEX1[4] ; Incomplete set of assignments ; +; HEX1[5] ; Incomplete set of assignments ; +; HEX1[6] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |part2 ; 9 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 18 ; 0 ; 9 (2) ; 0 (0) ; 0 (0) ; 0 ; |part2 ; part2 ; work ; +; |bcd:B0| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; |part2|bcd:B0 ; bcd ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++------------------------+-------------------+---------+ +; SW[1] ; ; ; +; - bcd:B0|OUT[0]~0 ; 0 ; 6 ; +; - bcd:B0|OUT~1 ; 0 ; 6 ; +; - bcd:B0|OUT[2]~2 ; 0 ; 6 ; +; - bcd:B0|OUT[3]~3 ; 0 ; 6 ; +; - bcd:B0|OUT[4]~4 ; 0 ; 6 ; +; - bcd:B0|OUT[5]~5 ; 0 ; 6 ; +; - bcd:B0|OUT[6]~6 ; 0 ; 6 ; +; - LessThan0~0 ; 0 ; 6 ; +; SW[3] ; ; ; +; - bcd:B0|OUT[0]~0 ; 0 ; 6 ; +; - bcd:B0|OUT~1 ; 0 ; 6 ; +; - bcd:B0|OUT[2]~2 ; 0 ; 6 ; +; - bcd:B0|OUT[3]~3 ; 0 ; 6 ; +; - bcd:B0|OUT[4]~4 ; 0 ; 6 ; +; - bcd:B0|OUT[5]~5 ; 0 ; 6 ; +; - bcd:B0|OUT[6]~6 ; 0 ; 6 ; +; - LessThan0~0 ; 0 ; 6 ; +; SW[0] ; ; ; +; - bcd:B0|OUT[0]~0 ; 0 ; 6 ; +; - bcd:B0|OUT~1 ; 0 ; 6 ; +; - bcd:B0|OUT[2]~2 ; 0 ; 6 ; +; - bcd:B0|OUT[3]~3 ; 0 ; 6 ; +; - bcd:B0|OUT[4]~4 ; 0 ; 6 ; +; - bcd:B0|OUT[5]~5 ; 0 ; 6 ; +; - bcd:B0|OUT[6]~6 ; 0 ; 6 ; +; SW[2] ; ; ; +; - bcd:B0|OUT[0]~0 ; 0 ; 6 ; +; - bcd:B0|OUT~1 ; 0 ; 6 ; +; - bcd:B0|OUT[2]~2 ; 0 ; 6 ; +; - bcd:B0|OUT[3]~3 ; 0 ; 6 ; +; - bcd:B0|OUT[4]~4 ; 0 ; 6 ; +; - bcd:B0|OUT[5]~5 ; 0 ; 6 ; +; - bcd:B0|OUT[6]~6 ; 0 ; 6 ; +; - LessThan0~0 ; 0 ; 6 ; ++------------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 19 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 1 / 5,382 ( < 1 % ) ; +; C4 interconnects ; 19 / 106,704 ( < 1 % ) ; +; Direct links ; 0 / 148,641 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 49,760 ( 0 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 0 / 5,406 ( 0 % ) ; +; R4 interconnects ; 29 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 4.50) ; Number of LABs (Total = 2) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 4.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 4.50) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 2.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 18 ; 18 ; 0 ; 0 ; 18 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 4 ; 14 ; 0 ; 4 ; 0 ; 0 ; 14 ; 0 ; 18 ; 18 ; 18 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 18 ; 0 ; 0 ; 18 ; 18 ; 0 ; 0 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 4 ; 18 ; 18 ; 18 ; 14 ; 4 ; 18 ; 14 ; 18 ; 18 ; 4 ; 18 ; 0 ; 0 ; 0 ; 18 ; 18 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device 10M50DAF484C6GES for design "part2" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds. +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/output_files/part2.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 25 warnings + Info: Peak virtual memory: 1085 megabytes + Info: Processing ended: Sat Apr 24 19:19:48 2021 + Info: Elapsed time: 00:00:19 + Info: Total CPU time (on all processors): 00:00:22 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/output_files/part2.fit.smsg. + + diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.smsg b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.summary b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.summary new file mode 100644 index 0000000..ea48545 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Sat Apr 24 19:19:48 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part2 +Top-level Entity Name : part2 +Family : MAX 10 +Device : 10M50DAF484C6GES +Timing Models : Preliminary +Total logic elements : 9 / 49,760 ( < 1 % ) + Total combinational functions : 9 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 18 / 360 ( 5 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.flow.rpt b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.flow.rpt new file mode 100644 index 0000000..9993459 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.flow.rpt @@ -0,0 +1,140 @@ +Flow report for part2 +Sat Apr 24 19:20:02 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sat Apr 24 19:19:55 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part2 ; +; Top-level Entity Name ; part2 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 9 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 9 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 18 / 360 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/24/2021 19:19:15 ; +; Main task ; Compilation ; +; Revision Name ; part2 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 164639278517.161930995509115 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 390 MB ; 00:00:31 ; +; Fitter ; 00:00:19 ; 1.0 ; 1085 MB ; 00:00:22 ; +; Assembler ; 00:00:05 ; 1.0 ; 358 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:06 ; 1.0 ; 509 MB ; 00:00:06 ; +; Total ; 00:00:44 ; -- ; -- ; 00:01:04 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+-------------------+------------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+-------------------+------------------+------------+----------------+ +; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; ++----------------------+-------------------+------------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2 +quartus_fit --read_settings_files=off --write_settings_files=off part2 -c part2 +quartus_asm --read_settings_files=off --write_settings_files=off part2 -c part2 +quartus_sta part2 -c part2 + + + diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.jdi b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.jdi new file mode 100644 index 0000000..692af55 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.map.rpt b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.map.rpt new file mode 100644 index 0000000..02f444b --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.map.rpt @@ -0,0 +1,421 @@ +Analysis & Synthesis report for part2 +Sat Apr 24 19:19:28 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Apr 24 19:19:28 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part2 ; +; Top-level Entity Name ; part2 ; +; Family ; MAX 10 ; +; Total logic elements ; 8 ; +; Total combinational functions ; 8 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 18 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Top-level entity name ; part2 ; part2 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; part2.v ; yes ; User Verilog HDL File ; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v ; ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimated Total logic elements ; 8 ; +; ; ; +; Total combinational functions ; 8 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 7 ; +; -- 3 input functions ; 1 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 8 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 18 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; SW[1]~input ; +; Maximum fan-out ; 8 ; +; Total fan-out ; 60 ; +; Average fan-out ; 1.36 ; ++---------------------------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |part2 ; 8 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 ; |part2 ; part2 ; work ; +; |bcd:B0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part2|bcd:B0 ; bcd ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 18 ; +; cycloneiii_lcell_comb ; 11 ; +; normal ; 11 ; +; 0 data inputs ; 2 ; +; 1 data inputs ; 1 ; +; 3 data inputs ; 1 ; +; 4 data inputs ; 7 ; +; ; ; +; Max LUT depth ; 2.00 ; +; Average LUT depth ; 1.27 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 19:19:14 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 3 design units, including 3 entities, in source file part2.v + Info (12023): Found entity 1: bcd File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 1 + Info (12023): Found entity 2: mux_2to1 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 13 + Info (12023): Found entity 3: part2 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 22 +Info (12127): Elaborating entity "part2" for the top level hierarchy +Warning (10230): Verilog HDL assignment warning at part2.v(31): truncated value with size 32 to match size of target (1) File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 31 +Info (12128): Elaborating entity "mux_2to1" for hierarchy "mux_2to1:M0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 35 +Info (12128): Elaborating entity "bcd" for hierarchy "bcd:B0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 36 +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "HEX1[1]" is stuck at GND File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 24 + Warning (13410): Pin "HEX1[2]" is stuck at GND File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 24 + Warning (13410): Pin "HEX1[6]" is stuck at VCC File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part2/part2.v Line: 24 +Info (286030): Timing-Driven Synthesis is running +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 26 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 4 input pins + Info (21059): Implemented 14 output pins + Info (21061): Implemented 8 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 131 warnings + Info: Peak virtual memory: 396 megabytes + Info: Processing ended: Sat Apr 24 19:19:28 2021 + Info: Elapsed time: 00:00:14 + Info: Total CPU time (on all processors): 00:00:31 + + diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.map.summary b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.map.summary new file mode 100644 index 0000000..2c30067 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Sat Apr 24 19:19:28 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part2 +Top-level Entity Name : part2 +Family : MAX 10 +Total logic elements : 8 + Total combinational functions : 8 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 18 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.pin b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.pin new file mode 100644 index 0000000..d52d08c --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2020 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +CHIP "part2" ASSIGNED TO AN: 10M50DAF484C6GES + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +HEX1[4] : A17 : output : 2.5 V : : 7 : Y +HEX1[5] : A18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +GND : B13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +HEX1[3] : B16 : output : 2.5 V : : 7 : Y +HEX1[6] : B17 : output : 2.5 V : : 7 : Y +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[0] : C10 : input : 2.5 V : : 7 : Y +SW[1] : C11 : input : 2.5 V : : 7 : Y +SW[3] : C12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +HEX0[0] : C14 : output : 2.5 V : : 7 : Y +HEX0[2] : C15 : output : 2.5 V : : 7 : Y +HEX0[3] : C16 : output : 2.5 V : : 7 : Y +HEX0[6] : C17 : output : 2.5 V : : 7 : Y +HEX1[0] : C18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +SW[2] : D12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +HEX0[5] : D17 : output : 2.5 V : : 7 : Y +HEX1[1] : D18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +HEX0[1] : E15 : output : 2.5 V : : 7 : Y +HEX0[4] : E16 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +HEX1[2] : E18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.pof b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.pof new file mode 100644 index 0000000..717446f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.pof differ diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sld b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sof b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sof new file mode 100644 index 0000000..9fc6a7e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sof differ diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sta.rpt b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sta.rpt new file mode 100644 index 0000000..dd9573e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sta.rpt @@ -0,0 +1,629 @@ +Timing Analyzer report for part2 +Sat Apr 24 19:20:02 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; part2 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.4% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 4 ; 4 ; +; Unconstrained Input Port Paths ; 40 ; 40 ; +; Unconstrained Output Ports ; 11 ; 11 ; +; Unconstrained Output Port Paths ; 40 ; 40 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 19:19:56 2021 +Info: Command: quartus_sta part2 -c part2 +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 131 warnings + Info: Peak virtual memory: 509 megabytes + Info: Processing ended: Sat Apr 24 19:20:02 2021 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 + + diff --git a/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sta.summary b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/output_files/part2.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/Lab2/part2/part2.qpf b/EE203/Noah Woodlee/Lab2/part2/part2.qpf new file mode 100644 index 0000000..f143c98 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/part2.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:26:21 April 16, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "20:26:21 April 16, 2021" + +# Revisions + +PROJECT_REVISION = "part2" diff --git a/EE203/Noah Woodlee/Lab2/part2/part2.qsf b/EE203/Noah Woodlee/Lab2/part2/part2.qsf new file mode 100644 index 0000000..59f80d7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/part2.qsf @@ -0,0 +1,108 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:26:21 April 16, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part2_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:26:21 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part2.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part2/part2.qsf.bak b/EE203/Noah Woodlee/Lab2/part2/part2.qsf.bak new file mode 100644 index 0000000..f626b9f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/part2.qsf.bak @@ -0,0 +1,54 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:26:21 April 16, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part2_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:26:21 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part2.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part2/part2.qws b/EE203/Noah Woodlee/Lab2/part2/part2.qws new file mode 100644 index 0000000..40ba43c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part2/part2.qws differ diff --git a/EE203/Noah Woodlee/Lab2/part2/part2.v b/EE203/Noah Woodlee/Lab2/part2/part2.v new file mode 100644 index 0000000..874ee40 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/part2.v @@ -0,0 +1,37 @@ +module bcd(IN,OUT); + input [3:0] IN; + output [6:0] OUT; + + assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000): + (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010): + (IN[0]? 7'b0010_010:7'b0011_001)): + (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100): + (IN[0]? 7'b1111_001:7'b1000_000))); + +endmodule + +module mux_2to1 (IN1, IN2, S, OUT); + input[3:0]IN1, IN2; + input S; + output [3:0]OUT; + + assign OUT=S? IN2:IN1; + +endmodule + +module part2(SW, HEX0, HEX1); + input [3:0] SW; + output [6:0] HEX0, HEX1; + + wire z; + wire [3:0] A, V; + wire [3:0] W; + + assign V=SW[3:0]; + assign z = V[3:0] > 9? 1:0; + assign HEX1 =z? 7'b1111_001:7'b1000_000; + + assign A=V[3:0]-4'b1010; + mux_2to1 M0 (V, A, z, W); + bcd B0 (W, HEX0); +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part2/part2_assignment_defaults.qdf b/EE203/Noah Woodlee/Lab2/part2/part2_assignment_defaults.qdf new file mode 100644 index 0000000..4a1e1fe --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part2/part2_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 19:15:51 April 24, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value ENABLE +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off 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MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/EE203/Noah Woodlee/Lab2/part3/Waveform.vwf b/EE203/Noah Woodlee/Lab2/part3/Waveform.vwf new file mode 100644 index 0000000..1d7037c --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/Waveform.vwf @@ -0,0 +1,534 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform.vwf" --testbench_file="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform.vwf" --testbench_file="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 5; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 9; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 280.0; + LEVEL 0 FOR 720.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 280.0; + LEVEL 0 FOR 720.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 280.0; + LEVEL 0 FOR 720.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 280.0; + LEVEL 0 FOR 720.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; + CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 6; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Lab2/part3/Waveform1.vwf b/EE203/Noah Woodlee/Lab2/part3/Waveform1.vwf new file mode 100644 index 0000000..b21c133 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/Waveform1.vwf @@ -0,0 +1,534 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform1.vwf.vt +vsim -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform1.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 5; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 9; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; + CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 6; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Lab2/part3/Waveform2.vwf b/EE203/Noah Woodlee/Lab2/part3/Waveform2.vwf new file mode 100644 index 0000000..16c8e65 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/Waveform2.vwf @@ -0,0 +1,534 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="/home/andrew/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform2.vwf" --testbench_file="/home/andrew/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform2.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="/home/andrew/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform2.vwf" --testbench_file="/home/andrew/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform2.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/andrew/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/andrew/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform2.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform2.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 5; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 9; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 290.0; + LEVEL 0 FOR 710.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 290.0; + LEVEL 0 FOR 710.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 290.0; + LEVEL 0 FOR 710.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 290.0; + LEVEL 0 FOR 710.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; + CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 6; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Lab2/part3/Waveform3.vwf b/EE203/Noah Woodlee/Lab2/part3/Waveform3.vwf new file mode 100644 index 0000000..29b1b67 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/Waveform3.vwf @@ -0,0 +1,534 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform3.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform3.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform3.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform3.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform3.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform3.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 5; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 9; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 440.0; + LEVEL 0 FOR 560.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 440.0; + LEVEL 0 FOR 560.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 440.0; + LEVEL 0 FOR 560.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 440.0; + LEVEL 0 FOR 560.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; + CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 6; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Lab2/part3/Waveform4.vwf b/EE203/Noah Woodlee/Lab2/part3/Waveform4.vwf new file mode 100644 index 0000000..8dbe671 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/Waveform4.vwf @@ -0,0 +1,534 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform4.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform4.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform4.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform4.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform4.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform4.vwf.vt +vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 5; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 9; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 640.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 640.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 640.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 360.0; + LEVEL 0 FOR 640.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; + CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 6; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.(0).cnf.cdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.(0).cnf.cdb new file mode 100644 index 0000000..3a671ca Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.(0).cnf.hdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.(0).cnf.hdb new file mode 100644 index 0000000..4934c25 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.(1).cnf.cdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.(1).cnf.cdb new file mode 100644 index 0000000..2b8753f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.(1).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.(1).cnf.hdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.(1).cnf.hdb new file mode 100644 index 0000000..7bfb314 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.(1).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.asm.qmsg b/EE203/Noah Woodlee/Lab2/part3/db/part3.asm.qmsg new file mode 100644 index 0000000..c880367 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619328329240 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619328329241 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 00:25:29 2021 " "Processing started: Sun Apr 25 00:25:29 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619328329241 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619328329241 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part3 -c part3 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part3 -c part3" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619328329241 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619328329636 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619328332493 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619328332594 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "358 " "Peak virtual memory: 358 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619328333803 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 00:25:33 2021 " "Processing ended: Sun Apr 25 00:25:33 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619328333803 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619328333803 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619328333803 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619328333803 ""} diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.asm.rdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.asm.rdb new file mode 100644 index 0000000..fcbd912 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.asm.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.asm_labs.ddb b/EE203/Noah Woodlee/Lab2/part3/db/part3.asm_labs.ddb new file mode 100644 index 0000000..7636302 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.cbx.xml b/EE203/Noah Woodlee/Lab2/part3/db/part3.cbx.xml new file mode 100644 index 0000000..8bb0038 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.bpm b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.bpm new file mode 100644 index 0000000..2c5f79f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.cdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.cdb new file mode 100644 index 0000000..a313327 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.hdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.hdb new file mode 100644 index 0000000..58bb5a1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.idb b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.idb new file mode 100644 index 0000000..8075749 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.idb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.logdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.logdb new file mode 100644 index 0000000..d71b976 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.logdb @@ -0,0 +1,56 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;14;14;0;0;14;14;0;0;0;0;0;0;5;0;0;0;9;5;0;9;0;0;5;0;14;14;14;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,14;0;0;14;14;0;0;14;14;14;14;14;14;9;14;14;14;5;9;14;5;14;14;9;14;0;0;0;14;14, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.rdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.rdb new file mode 100644 index 0000000..14000cc Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp_merge.kpt b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp_merge.kpt new file mode 100644 index 0000000..bfde9a7 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.db_info b/EE203/Noah Woodlee/Lab2/part3/db/part3.db_info new file mode 100644 index 0000000..8f3f50b --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sun Apr 25 11:51:28 2021 diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.eda.qmsg b/EE203/Noah Woodlee/Lab2/part3/db/part3.eda.qmsg new file mode 100644 index 0000000..09d88a0 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.eda.qmsg @@ -0,0 +1,11 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619329921119 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2020 Intel Corporation. All rights reserved. " "Copyright (C) 2020 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic " "and other software and tools, and any partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 00:52:00 2021 " "Processing started: Sun Apr 25 00:52:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619329921119 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1619329921119 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/\" part3 -c part3 " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/\" part3 -c part3" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1619329921120 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619329921464 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "EDA Netlist Writer" 0 -1 1619329921464 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1619329921708 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "part3.vo C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim// simulation " "Generated file part3.vo in folder \"C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1619329921781 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 126 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 126 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4660 " "Peak virtual memory: 4660 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619329921825 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 00:52:01 2021 " "Processing ended: Sun Apr 25 00:52:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619329921825 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619329921825 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619329921825 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1619329921825 ""} diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.fit.qmsg b/EE203/Noah Woodlee/Lab2/part3/db/part3.fit.qmsg new file mode 100644 index 0000000..d596068 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.fit.qmsg @@ -0,0 +1,52 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1619328315362 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619328315362 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part3 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part3\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619328315373 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619328315451 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619328315451 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1619328315828 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619328315837 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619328315925 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 54 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328315932 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 56 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328315932 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 58 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328315932 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 60 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328315932 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 62 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328315932 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 64 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328315932 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 66 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328315932 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 68 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328315932 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1619328315932 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619328315933 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619328315933 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619328315933 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619328315933 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1619328315935 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part3.sdc " "Synopsys Design Constraints File file not found: 'part3.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1619328316494 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1619328316495 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1619328316496 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1619328316496 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1619328316498 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1619328316498 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1619328316499 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1619328316503 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619328316504 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619328316504 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619328316506 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619328316506 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1619328316506 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1619328316507 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1619328316507 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1619328316507 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1619328316507 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619328316507 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619328316537 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1619328316543 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619328319411 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619328319533 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619328319582 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619328320077 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619328320077 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619328320784 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1619328324317 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619328324317 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1619328324547 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1619328324547 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1619328324547 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619328324549 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.04 " "Total time spent on timing analysis during the Fitter is 0.04 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1619328324863 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619328324874 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1619328324875 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619328325294 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619328325294 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1619328325294 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619328325714 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619328326298 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/output_files/part3.fit.smsg " "Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/output_files/part3.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619328326541 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1079 " "Peak virtual memory: 1079 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619328326988 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 00:25:26 2021 " "Processing ended: Sun Apr 25 00:25:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619328326988 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619328326988 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619328326988 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619328326988 ""} diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.hier_info b/EE203/Noah Woodlee/Lab2/part3/db/part3.hier_info new file mode 100644 index 0000000..42b2cc0 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.hier_info @@ -0,0 +1,57 @@ +|part3 +SW[0] => SW[0].IN1 +SW[1] => SW[1].IN1 +SW[2] => SW[2].IN1 +SW[3] => SW[3].IN1 +SW[4] => SW[4].IN1 +SW[5] => SW[5].IN1 +SW[6] => SW[6].IN1 +SW[7] => SW[7].IN1 +SW[8] => SW[8].IN1 +LEDR[0] << adder:A0.port0 +LEDR[1] << adder:A1.port0 +LEDR[2] << adder:A2.port0 +LEDR[3] << adder:A3.port0 +LEDR[4] << adder:A3.port1 + + +|part3|adder:A0 +SUM <= x1.DB_MAX_OUTPUT_PORT_TYPE +COUT <= COUT.DB_MAX_OUTPUT_PORT_TYPE +A => x0.IN0 +B => x0.IN1 +B => COUT.DATAA +CIN => x1.IN1 +CIN => COUT.DATAB + + +|part3|adder:A1 +SUM <= x1.DB_MAX_OUTPUT_PORT_TYPE +COUT <= COUT.DB_MAX_OUTPUT_PORT_TYPE +A => x0.IN0 +B => x0.IN1 +B => COUT.DATAA +CIN => x1.IN1 +CIN => COUT.DATAB + + +|part3|adder:A2 +SUM <= x1.DB_MAX_OUTPUT_PORT_TYPE +COUT <= COUT.DB_MAX_OUTPUT_PORT_TYPE +A => x0.IN0 +B => x0.IN1 +B => COUT.DATAA +CIN => x1.IN1 +CIN => COUT.DATAB + + +|part3|adder:A3 +SUM <= x1.DB_MAX_OUTPUT_PORT_TYPE +COUT <= COUT.DB_MAX_OUTPUT_PORT_TYPE +A => x0.IN0 +B => x0.IN1 +B => COUT.DATAA +CIN => x1.IN1 +CIN => COUT.DATAB + + diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.hif b/EE203/Noah Woodlee/Lab2/part3/db/part3.hif new file mode 100644 index 0000000..6cfe71b Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.hif differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.html b/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.html new file mode 100644 index 0000000..9cef06b --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.html @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
A33000200000000
A23000200000000
A13000200000000
A03000200000000
diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.rdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.rdb new file mode 100644 index 0000000..7751fab Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.txt b/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.txt new file mode 100644 index 0000000..22bde28 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.lpc.txt @@ -0,0 +1,10 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; A3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; A2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; A1 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; A0 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map.ammdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.ammdb new file mode 100644 index 0000000..790b913 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map.bpm b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.bpm new file mode 100644 index 0000000..c77a87d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map.cdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.cdb new file mode 100644 index 0000000..6fd7731 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map.hdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.hdb new file mode 100644 index 0000000..fb68930 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map.kpt b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.kpt new file mode 100644 index 0000000..3da288e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map.logdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map.qmsg b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.qmsg new file mode 100644 index 0000000..6e411fe --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.qmsg @@ -0,0 +1,17 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619328299154 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619328299155 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 00:24:58 2021 " "Processing started: Sun Apr 25 00:24:58 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619328299155 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619328299155 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619328299155 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619328299516 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619328299517 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part3.v 2 2 " "Found 2 design units, including 2 entities, in source file part3.v" { { "Info" "ISGN_ENTITY_NAME" "1 adder " "Found entity 1: adder" { } { { "part3.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619328311705 ""} { "Info" "ISGN_ENTITY_NAME" "2 part3 " "Found entity 2: part3" { } { { "part3.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619328311705 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619328311705 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part3 " "Elaborating entity \"part3\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619328311775 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder adder:A0 " "Elaborating entity \"adder\" for hierarchy \"adder:A0\"" { } { { "part3.v" "A0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v" 23 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619328311778 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619328312555 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328313154 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328313154 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328313154 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328313154 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328313154 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328313154 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1619328313303 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619328313303 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "23 " "Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1619328313359 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1619328313359 ""} { "Info" "ICUT_CUT_TM_LCELLS" "9 " "Implemented 9 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1619328313359 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1619328313359 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 126 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 126 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "395 " "Peak virtual memory: 395 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619328313372 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 00:25:13 2021 " "Processing ended: Sun Apr 25 00:25:13 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619328313372 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619328313372 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619328313372 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619328313372 ""} diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map.rdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.rdb new file mode 100644 index 0000000..bc5b465 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.map.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.cdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.cdb new file mode 100644 index 0000000..f7e82fa Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.hdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.hdb new file mode 100644 index 0000000..4f933fa Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.logdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.pplq.rdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.pplq.rdb new file mode 100644 index 0000000..219c385 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.pplq.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.pre_map.hdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.pre_map.hdb new file mode 100644 index 0000000..d64321c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.pre_map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.quiproj.23018.rdr.flock b/EE203/Noah Woodlee/Lab2/part3/db/part3.quiproj.23018.rdr.flock new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.quiproj.30902.rdr.flock b/EE203/Noah Woodlee/Lab2/part3/db/part3.quiproj.30902.rdr.flock new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.quiproj.31257.rdr.flock b/EE203/Noah Woodlee/Lab2/part3/db/part3.quiproj.31257.rdr.flock new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.quiproj.7615.rdr.flock b/EE203/Noah Woodlee/Lab2/part3/db/part3.quiproj.7615.rdr.flock new file mode 100644 index 0000000..e69de29 diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.root_partition.map.reg_db.cdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..e524171 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.root_partition.map.reg_db.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.routing.rdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.routing.rdb new file mode 100644 index 0000000..3623774 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.routing.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv.hdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv.hdb new file mode 100644 index 0000000..e80e28a Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv_sg.cdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv_sg.cdb new file mode 100644 index 0000000..30da65d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv_sg.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv_sg_swap.cdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv_sg_swap.cdb new file mode 100644 index 0000000..91c9747 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.rtlv_sg_swap.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.sld_design_entry.sci b/EE203/Noah Woodlee/Lab2/part3/db/part3.sld_design_entry.sci new file mode 100644 index 0000000..7d39add Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.sld_design_entry.sci differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.sld_design_entry_dsc.sci b/EE203/Noah Woodlee/Lab2/part3/db/part3.sld_design_entry_dsc.sci new file mode 100644 index 0000000..7d39add Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.smart_action.txt b/EE203/Noah Woodlee/Lab2/part3/db/part3.smart_action.txt new file mode 100644 index 0000000..f1e1649 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.sta.qmsg b/EE203/Noah Woodlee/Lab2/part3/db/part3.sta.qmsg new file mode 100644 index 0000000..a2ddb78 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.sta.qmsg @@ -0,0 +1,56 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619328335542 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619328335543 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 00:25:35 2021 " "Processing started: Sun Apr 25 00:25:35 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619328335543 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1619328335543 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta part3 -c part3 " "Command: quartus_sta part3 -c part3" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1619328335543 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1619328335648 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335716 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619328335716 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part1 24 " "Ignored 24 assignments for entity \"part1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was 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"set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335718 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity 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"Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd 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1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335719 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name 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PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335720 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619328335720 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part5 24 " "Ignored 24 assignments for entity \"part5\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328335721 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619328335721 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619328335846 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619328335846 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328335930 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328335930 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part3.sdc " "Synopsys Design Constraints File file not found: 'part3.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619328336384 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328336384 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619328336385 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619328336385 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619328336386 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619328336386 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619328336387 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1619328336393 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619328336394 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336395 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1619328336397 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336398 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336399 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336400 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336401 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336402 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619328336405 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619328336448 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Timing Analyzer" 0 -1 1619328336448 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619328336900 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328336946 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619328336946 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619328336946 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619328336947 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336947 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336949 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336951 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336952 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336953 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328336954 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619328336957 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328337127 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619328337127 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619328337128 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619328337128 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328337129 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328337130 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328337131 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328337132 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328337133 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619328338348 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619328338349 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 131 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 131 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "508 " "Peak virtual memory: 508 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619328338379 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 00:25:38 2021 " "Processing ended: Sun Apr 25 00:25:38 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619328338379 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619328338379 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619328338379 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619328338379 ""} diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.sta.rdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.sta.rdb new file mode 100644 index 0000000..8ad40a3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.sta.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.sta_cmp.6_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..ce804cd Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.tis_db_list.ddb b/EE203/Noah Woodlee/Lab2/part3/db/part3.tis_db_list.ddb new file mode 100644 index 0000000..73e5ec9 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..b7baa4c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..e927179 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..51c8dd5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.tmw_info b/EE203/Noah Woodlee/Lab2/part3/db/part3.tmw_info new file mode 100644 index 0000000..8d51757 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3.tmw_info @@ -0,0 +1,3 @@ +start_full_compilation:s +start_assembler:s-start_full_compilation +start_timing_analyzer:s-start_full_compilation diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.vpr.ammdb b/EE203/Noah Woodlee/Lab2/part3/db/part3.vpr.ammdb new file mode 100644 index 0000000..8f55ac1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..c96a6fd Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.tt_0c_slow.hsd b/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..090de61 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.tt_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.tt_85c_slow.hsd b/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..2d8ff11 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/db/part3.zippleback_io_sim_cache.tt_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part3/db/part3_partition_pins.json b/EE203/Noah Woodlee/Lab2/part3/db/part3_partition_pins.json new file mode 100644 index 0000000..a4308fc --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/part3_partition_pins.json @@ -0,0 +1,65 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "LEDR[0]", + "strict" : false + }, + { + "name" : "LEDR[1]", + "strict" : false + }, + { + "name" : "LEDR[2]", + "strict" : false + }, + { + "name" : "LEDR[3]", + "strict" : false + }, + { + "name" : "LEDR[4]", + "strict" : false + }, + { + "name" : "SW[8]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[4]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[5]", + "strict" : false + }, + { + "name" : "SW[2]", + "strict" : false + }, + { + "name" : "SW[6]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + }, + { + "name" : "SW[7]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part3/db/prev_cmp_part3.qmsg b/EE203/Noah Woodlee/Lab2/part3/db/prev_cmp_part3.qmsg new file mode 100644 index 0000000..d29f8f7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/db/prev_cmp_part3.qmsg @@ -0,0 +1,140 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619328093927 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619328093928 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 00:21:33 2021 " "Processing started: Sun Apr 25 00:21:33 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619328093928 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619328093928 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619328093929 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619328094386 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619328094387 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part3.v 2 2 " "Found 2 design units, including 2 entities, in source file part3.v" { { "Info" "ISGN_ENTITY_NAME" "1 adder " "Found entity 1: adder" { } { { "part3.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619328107011 ""} { "Info" "ISGN_ENTITY_NAME" "2 part3 " "Found entity 2: part3" { } { { "part3.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619328107011 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619328107011 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part3 " "Elaborating entity \"part3\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619328107086 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder adder:A0 " "Elaborating entity \"adder\" for hierarchy \"adder:A0\"" { } { { "part3.v" "A0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v" 23 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619328107115 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619328107965 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328108529 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1619328108529 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part1 24 " "Ignored 24 assignments for entity \"part1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1619328108700 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619328108700 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "23 " "Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1619328108835 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1619328108835 ""} { "Info" "ICUT_CUT_TM_LCELLS" "9 " "Implemented 9 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1619328108835 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1619328108835 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 126 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 126 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "395 " "Peak virtual memory: 395 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619328108851 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 00:21:48 2021 " "Processing ended: Sun Apr 25 00:21:48 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619328108851 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619328108851 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619328108851 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619328108851 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1619328111087 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619328111087 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 00:21:50 2021 " "Processing started: Sun Apr 25 00:21:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619328111087 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1619328111087 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off part3 -c part3 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off part3 -c part3" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1619328111088 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1619328111257 ""} +{ "Info" "0" "" "Project = part3" { } { } 0 0 "Project = part3" 0 0 "Fitter" 0 0 1619328111260 ""} +{ "Info" "0" "" "Revision = part3" { } { } 0 0 "Revision = part3" 0 0 "Fitter" 0 0 1619328111260 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1619328111409 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619328111409 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part3 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part3\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619328111416 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619328111495 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619328111495 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1619328111906 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619328111921 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619328112095 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 54 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328112109 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 56 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328112109 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 58 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328112109 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 60 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328112109 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 62 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328112109 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 64 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328112109 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 66 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328112109 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 0 { 0 ""} 0 68 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619328112109 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1619328112109 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619328112110 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619328112110 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619328112110 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619328112111 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1619328112114 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part3.sdc " "Synopsys Design Constraints File file not found: 'part3.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1619328112755 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1619328112756 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1619328112757 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1619328112758 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1619328112762 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1619328112763 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1619328112764 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1619328112773 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619328112774 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619328112774 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619328112776 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619328112777 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1619328112777 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1619328112777 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1619328112777 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1619328112778 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1619328112778 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619328112778 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619328112814 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1619328112828 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619328115626 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619328115757 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619328115816 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619328116311 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619328116311 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619328117001 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1619328120589 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619328120589 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1619328120812 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1619328120812 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619328125907 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619328128739 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619328128842 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "355 " "Peak virtual memory: 355 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619328130098 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 00:22:10 2021 " "Processing ended: Sun Apr 25 00:22:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619328130098 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619328130098 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619328130098 ""} } { } 0 0 "%6!s! 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was ignored" 0 0 "Design Software" 0 -1 1619328132003 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132003 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132003 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619328132003 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part1_bcd 24 " "Ignored 24 assignments for entity \"part1_bcd\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1_bcd -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619328132004 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132004 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132004 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619328132004 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132004 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132004 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619328132004 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part4 24 " "Ignored 24 assignments for entity \"part4\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part4 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132005 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619328132005 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part5 24 " "Ignored 24 assignments for entity \"part5\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619328132006 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619328132006 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619328132130 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619328132131 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328132217 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328132217 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part3.sdc " "Synopsys Design Constraints File file not found: 'part3.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619328132671 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328132672 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619328132672 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619328132673 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619328132673 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619328132673 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619328132675 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1619328132683 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619328132684 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328132687 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1619328132688 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328132689 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328132690 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328132691 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328132692 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328132693 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619328132697 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619328132739 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Timing Analyzer" 0 -1 1619328132740 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619328133190 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328133235 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619328133236 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619328133236 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619328133236 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133237 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133239 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133240 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133241 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133242 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133243 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619328133245 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619328133406 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619328133406 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619328133406 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619328133406 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133409 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133410 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133410 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133411 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619328133412 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619328134604 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619328134605 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 131 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 131 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "508 " "Peak virtual memory: 508 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619328134635 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 00:22:14 2021 " "Processing ended: Sun Apr 25 00:22:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619328134635 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619328134635 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619328134635 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619328134635 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 265 s " "Quartus Prime Full Compilation was successful. 0 errors, 265 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619328134849 ""} diff --git a/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..d89a873 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| George Totolos :| 08/22/2016:| Initial Revision +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a2885da --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +DE10_LITE_Golden_Top.v +platform_setup.tcl +filelist.txt diff --git a/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..d9cea11 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,435 @@ +proc ::setup_project {} { +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0" +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name SDC_FILE DE10_LITE_Golden_Top.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS + +#============================================================ +# Accelerometer +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO + +#============================================================ +# Arduino +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..1c1dfa3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/home/gtotolos/Desktop/max10_de10_lite/Golden_Top/", + "acds_version" : "Version 16.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part3/devkits/readme.txt b/EE203/Noah Woodlee/Lab2/part3/devkits/readme.txt new file mode 100644 index 0000000..f6ba267 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/README b/EE203/Noah Woodlee/Lab2/part3/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.db_info b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.db_info new file mode 100644 index 0000000..e24ce12 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sat Apr 24 20:06:27 2021 diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.ammdb b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.ammdb new file mode 100644 index 0000000..90637ea Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.cdb b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.cdb new file mode 100644 index 0000000..9926de6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.dfp b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.hdb b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.hdb new file mode 100644 index 0000000..cd91f29 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.logdb b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.rcfdb new file mode 100644 index 0000000..ed5d15c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.cdb b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.cdb new file mode 100644 index 0000000..da62fc0 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.dpi b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.dpi new file mode 100644 index 0000000..c482fa0 Binary files /dev/null and b/EE203/Noah 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b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..dbac8ef Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.hdb b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.hdb new file mode 100644 index 0000000..337ea2f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.kpt b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.kpt new file mode 100644 index 0000000..113f4ca Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.rrp.hdb b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.rrp.hdb new file mode 100644 index 0000000..6e3e731 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/incremental_db/compiled_partitions/part3.rrp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.asm.rpt b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.asm.rpt new file mode 100644 index 0000000..d1b0ebf --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for part3 +Sun Apr 25 00:25:33 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: part3.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sun Apr 25 00:25:33 2021 ; +; Revision Name ; part3 ; +; Top-level Entity Name ; part3 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------------------------+ +; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/output_files/part3.sof ; ++-----------------------------------------------------------------------------------------------+ + + ++-------------------------------------+ +; Assembler Device Options: part3.sof ; ++----------------+--------------------+ +; Option ; Setting ; ++----------------+--------------------+ +; JTAG usercode ; 0x00271568 ; +; Checksum ; 0x00271568 ; ++----------------+--------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 00:25:29 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off part3 -c part3 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 358 megabytes + Info: Processing ended: Sun Apr 25 00:25:33 2021 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.done b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.done new file mode 100644 index 0000000..5fee194 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.done @@ -0,0 +1 @@ +Sun Apr 25 00:25:38 2021 diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.eda.rpt b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.eda.rpt new file mode 100644 index 0000000..f3906a6 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.eda.rpt @@ -0,0 +1,233 @@ +EDA Netlist Writer report for part3 +Sun Apr 25 00:52:01 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Sun Apr 25 00:52:01 2021 ; +; Revision Name ; part3 ; +; Top-level Entity Name ; part3 ; +; Family ; MAX 10 ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------------------------+ +; C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim//part3.vo ; ++---------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Copyright (C) 2020 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and any partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel FPGA IP License Agreement, or other applicable license + Info: agreement, including, without limitation, that your use is for + Info: the sole purpose of programming logic devices manufactured by + Info: Intel and sold by Intel or its authorized distributors. Please + Info: refer to the applicable agreement for further details, at + Info: https://fpgasoftware.intel.com/eula. + Info: Processing started: Sun Apr 25 00:52:00 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file part3.vo in folder "C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 126 warnings + Info: Peak virtual memory: 4660 megabytes + Info: Processing ended: Sun Apr 25 00:52:01 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.rpt b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.rpt new file mode 100644 index 0000000..eedb366 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.rpt @@ -0,0 +1,1255 @@ +Fitter report for part3 +Sun Apr 25 00:25:26 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sun Apr 25 00:25:26 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part3 ; +; Top-level Entity Name ; part3 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 10 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 10 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 14 / 360 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.4% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 57 ) ; 0.00 % ( 0 / 57 ) ; 0.00 % ( 0 / 57 ) ; +; -- Achieved ; 0.00 % ( 0 / 57 ) ; 0.00 % ( 0 / 57 ) ; 0.00 % ( 0 / 57 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 41 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/output_files/part3.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 10 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 10 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 2 ; +; -- 3 input functions ; 6 ; +; -- <=2 input functions ; 2 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 10 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 14 / 360 ( 4 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.3% / 0.2% / 0.3% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 58 ; +; Average fan-out ; 1.02 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 10 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 10 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 2 ; 0 ; +; -- 3 input functions ; 6 ; 0 ; +; -- <=2 input functions ; 2 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 10 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 14 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 64 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 9 ; 0 ; +; -- Output Ports ; 5 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; C10 ; 7 ; 51 ; 54 ; 28 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[2] ; D12 ; 7 ; 51 ; 54 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[3] ; C12 ; 7 ; 54 ; 54 ; 28 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[4] ; A12 ; 7 ; 54 ; 54 ; 21 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[5] ; B12 ; 7 ; 49 ; 54 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[6] ; A13 ; 7 ; 54 ; 54 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[7] ; A14 ; 7 ; 58 ; 54 ; 28 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[8] ; B14 ; 7 ; 56 ; 54 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; LEDR[0] ; A8 ; 7 ; 46 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[1] ; A9 ; 7 ; 46 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[2] ; A10 ; 7 ; 51 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[3] ; B10 ; 7 ; 46 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[4] ; D13 ; 7 ; 56 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 0 / 60 ( 0 % ) ; 2.5V ; -- ; +; 7 ; 14 / 52 ( 27 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 449 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 439 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; SW[4] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 433 ; 7 ; SW[6] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 425 ; 7 ; SW[7] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; SW[5] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; SW[8] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; SW[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 391 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D13 ; 431 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 388 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; LEDR[0] ; Incomplete set of assignments ; +; LEDR[1] ; Incomplete set of assignments ; +; LEDR[2] ; Incomplete set of assignments ; +; LEDR[3] ; Incomplete set of assignments ; +; LEDR[4] ; Incomplete set of assignments ; +; SW[8] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |part3 ; 10 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 14 ; 0 ; 10 (1) ; 0 (0) ; 0 (0) ; 0 ; |part3 ; part3 ; work ; +; |adder:A0| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part3|adder:A0 ; adder ; work ; +; |adder:A1| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; |part3|adder:A1 ; adder ; work ; +; |adder:A2| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; |part3|adder:A2 ; adder ; work ; +; |adder:A3| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part3|adder:A3 ; adder ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[7] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++------------------------+-------------------+---------+ +; SW[8] ; ; ; +; - adder:A0|x1 ; 1 ; 6 ; +; - adder:A0|COUT~0 ; 1 ; 6 ; +; SW[0] ; ; ; +; - adder:A0|x1 ; 0 ; 6 ; +; - adder:A0|COUT~0 ; 0 ; 6 ; +; SW[4] ; ; ; +; - adder:A0|x1 ; 0 ; 6 ; +; - adder:A0|COUT~0 ; 0 ; 6 ; +; SW[1] ; ; ; +; - adder:A1|x1 ; 0 ; 6 ; +; - adder:A2|x1 ; 0 ; 6 ; +; - adder:A2|COUT~2 ; 0 ; 6 ; +; SW[5] ; ; ; +; - adder:A1|x1 ; 0 ; 6 ; +; - adder:A2|x1 ; 0 ; 6 ; +; - adder:A2|COUT~2 ; 0 ; 6 ; +; SW[2] ; ; ; +; - adder:A2|x0 ; 0 ; 6 ; +; - adder:A2|COUT~3 ; 0 ; 6 ; +; SW[6] ; ; ; +; - adder:A2|x0 ; 0 ; 6 ; +; - adder:A2|COUT~3 ; 0 ; 6 ; +; SW[3] ; ; ; +; - adder:A3|x1 ; 1 ; 6 ; +; - adder:A3|COUT~0 ; 1 ; 6 ; +; SW[7] ; ; ; +; - adder:A3|x1 ; 0 ; 6 ; +; - adder:A3|COUT~0 ; 0 ; 6 ; ++------------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 19 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 0 / 5,382 ( 0 % ) ; +; C4 interconnects ; 19 / 106,704 ( < 1 % ) ; +; Direct links ; 1 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 4 / 49,760 ( < 1 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 0 / 5,406 ( 0 % ) ; +; R4 interconnects ; 13 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 5.00) ; Number of LABs (Total = 2) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 5.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 3.00) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 4.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 14 ; 14 ; 0 ; 0 ; 14 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 9 ; 5 ; 0 ; 9 ; 0 ; 0 ; 5 ; 0 ; 14 ; 14 ; 14 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 14 ; 0 ; 0 ; 14 ; 14 ; 0 ; 0 ; 14 ; 14 ; 14 ; 14 ; 14 ; 14 ; 9 ; 14 ; 14 ; 14 ; 5 ; 9 ; 14 ; 5 ; 14 ; 14 ; 9 ; 14 ; 0 ; 0 ; 0 ; 14 ; 14 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device 10M50DAF484C6GES for design "part3" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part3.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds. +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Info (144001): Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/output_files/part3.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings + Info: Peak virtual memory: 1079 megabytes + Info: Processing ended: Sun Apr 25 00:25:26 2021 + Info: Elapsed time: 00:00:12 + Info: Total CPU time (on all processors): 00:00:16 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/output_files/part3.fit.smsg. + + diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.smsg b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.summary b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.summary new file mode 100644 index 0000000..63b9675 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Sun Apr 25 00:25:26 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part3 +Top-level Entity Name : part3 +Family : MAX 10 +Device : 10M50DAF484C6GES +Timing Models : Preliminary +Total logic elements : 10 / 49,760 ( < 1 % ) + Total combinational functions : 10 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 14 / 360 ( 4 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.flow.rpt b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.flow.rpt new file mode 100644 index 0000000..db38f22 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.flow.rpt @@ -0,0 +1,158 @@ +Flow report for part3 +Sun Apr 25 00:52:01 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sun Apr 25 00:52:01 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part3 ; +; Top-level Entity Name ; part3 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 10 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 10 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 14 / 360 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/25/2021 00:24:59 ; +; Main task ; Compilation ; +; Revision Name ; part3 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 164639278517.161932829928305 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:15 ; 1.0 ; 390 MB ; 00:00:31 ; +; Fitter ; 00:00:12 ; 1.0 ; 1079 MB ; 00:00:16 ; +; Assembler ; 00:00:04 ; 1.0 ; 358 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:03 ; 1.0 ; 508 MB ; 00:00:03 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 593 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 597 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4656 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4660 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4652 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4660 MB ; 00:00:01 ; +; Total ; 00:00:40 ; -- ; -- ; 00:01:01 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+-------------------+------------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+-------------------+------------------+------------+----------------+ +; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; EDA Netlist Writer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; EDA Netlist Writer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+-------------------+------------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3 +quartus_fit --read_settings_files=off --write_settings_files=off part3 -c part3 +quartus_asm --read_settings_files=off --write_settings_files=off part3 -c part3 +quartus_sta part3 -c part3 +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform.vwf" --testbench_file="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt" +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt" +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 + + + diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.jdi b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.jdi new file mode 100644 index 0000000..a54ada2 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.map.rpt b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.map.rpt new file mode 100644 index 0000000..0905d57 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.map.rpt @@ -0,0 +1,416 @@ +Analysis & Synthesis report for part3 +Sun Apr 25 00:25:13 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sun Apr 25 00:25:13 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part3 ; +; Top-level Entity Name ; part3 ; +; Family ; MAX 10 ; +; Total logic elements ; 9 ; +; Total combinational functions ; 9 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 14 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Top-level entity name ; part3 ; part3 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; part3.v ; yes ; User Verilog HDL File ; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v ; ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ + + ++---------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-----------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------+ +; Estimated Total logic elements ; 9 ; +; ; ; +; Total combinational functions ; 9 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 2 ; +; -- 3 input functions ; 6 ; +; -- <=2 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 9 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 14 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; adder:A0|COUT~0 ; +; Maximum fan-out ; 3 ; +; Total fan-out ; 47 ; +; Average fan-out ; 1.27 ; ++---------------------------------------------+-----------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |part3 ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; |part3 ; part3 ; work ; +; |adder:A0| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part3|adder:A0 ; adder ; work ; +; |adder:A1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part3|adder:A1 ; adder ; work ; +; |adder:A2| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part3|adder:A2 ; adder ; work ; +; |adder:A3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part3|adder:A3 ; adder ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 14 ; +; cycloneiii_lcell_comb ; 9 ; +; normal ; 9 ; +; 2 data inputs ; 1 ; +; 3 data inputs ; 6 ; +; 4 data inputs ; 2 ; +; ; ; +; Max LUT depth ; 4.00 ; +; Average LUT depth ; 3.17 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 00:24:58 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 2 design units, including 2 entities, in source file part3.v + Info (12023): Found entity 1: adder File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v Line: 1 + Info (12023): Found entity 2: part3 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v Line: 15 +Info (12127): Elaborating entity "part3" for the top level hierarchy +Info (12128): Elaborating entity "adder" for hierarchy "adder:A0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v Line: 23 +Info (286030): Timing-Driven Synthesis is running +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 23 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 9 input pins + Info (21059): Implemented 5 output pins + Info (21061): Implemented 9 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 126 warnings + Info: Peak virtual memory: 395 megabytes + Info: Processing ended: Sun Apr 25 00:25:13 2021 + Info: Elapsed time: 00:00:15 + Info: Total CPU time (on all processors): 00:00:31 + + diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.map.summary b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.map.summary new file mode 100644 index 0000000..22fb4e4 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Sun Apr 25 00:25:13 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part3 +Top-level Entity Name : part3 +Family : MAX 10 +Total logic elements : 9 + Total combinational functions : 9 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 14 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.pin b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.pin new file mode 100644 index 0000000..45271e7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2020 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +CHIP "part3" ASSIGNED TO AN: 10M50DAF484C6GES + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +LEDR[0] : A8 : output : 2.5 V : : 7 : Y +LEDR[1] : A9 : output : 2.5 V : : 7 : Y +LEDR[2] : A10 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +SW[4] : A12 : input : 2.5 V : : 7 : Y +SW[6] : A13 : input : 2.5 V : : 7 : Y +SW[7] : A14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +LEDR[3] : B10 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +SW[5] : B12 : input : 2.5 V : : 7 : Y +GND : B13 : gnd : : : : +SW[8] : B14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[0] : C10 : input : 2.5 V : : 7 : Y +SW[1] : C11 : input : 2.5 V : : 7 : Y +SW[3] : C12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +SW[2] : D12 : input : 2.5 V : : 7 : Y +LEDR[4] : D13 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.pof b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.pof new file mode 100644 index 0000000..b363427 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.pof differ diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sld b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sof b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sof new file mode 100644 index 0000000..a1afe70 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sof differ diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sta.rpt b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sta.rpt new file mode 100644 index 0000000..bb9b060 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sta.rpt @@ -0,0 +1,596 @@ +Timing Analyzer report for part3 +Sun Apr 25 00:25:38 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; part3 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.03 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.8% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 9 ; 9 ; +; Unconstrained Input Port Paths ; 33 ; 33 ; +; Unconstrained Output Ports ; 5 ; 5 ; +; Unconstrained Output Port Paths ; 33 ; 33 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 00:25:35 2021 +Info: Command: quartus_sta part3 -c part3 +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part3.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 131 warnings + Info: Peak virtual memory: 508 megabytes + Info: Processing ended: Sun Apr 25 00:25:38 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sta.summary b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/output_files/part3.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/Lab2/part3/part3.qpf b/EE203/Noah Woodlee/Lab2/part3/part3.qpf new file mode 100644 index 0000000..f1afc11 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/part3.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:34:51 April 16, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "20:34:51 April 16, 2021" + +# Revisions + +PROJECT_REVISION = "part3" diff --git a/EE203/Noah Woodlee/Lab2/part3/part3.qsf b/EE203/Noah Woodlee/Lab2/part3/part3.qsf new file mode 100644 index 0000000..7d95555 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/part3.qsf @@ -0,0 +1,93 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:34:51 April 16, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part3_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part3 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:34:51 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part3.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform2.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform3.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform4.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part3/part3.qsf.bak b/EE203/Noah Woodlee/Lab2/part3/part3.qsf.bak new file mode 100644 index 0000000..942b783 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/part3.qsf.bak @@ -0,0 +1,49 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 20:34:51 April 16, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part3_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part3 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:34:51 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part3/part3.qws b/EE203/Noah Woodlee/Lab2/part3/part3.qws new file mode 100644 index 0000000..10a78d6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/part3.qws differ diff --git a/EE203/Noah Woodlee/Lab2/part3/part3.v b/EE203/Noah Woodlee/Lab2/part3/part3.v new file mode 100644 index 0000000..a38254a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/part3.v @@ -0,0 +1,30 @@ +module adder(SUM, COUT, A, B, CIN); + input A, B, CIN; + output SUM, COUT; + + wire x; + + + xor x0(x, A, B); + xor x1(SUM, x, CIN); + + assign COUT=x? CIN: B; + +endmodule + +module part3(SW, LEDR); + input [8:0] SW; + output [4:0] LEDR; + + + wire C0,C1,C2,C3; + wire [3:0] S; + + adder A0(S[0], C0, SW[0], SW[4], SW[8]); + adder A1(S[1], C1, SW[1], SW[5], C0); + adder A2(S[2], C2, SW[2], SW[6], C1); + adder A3(S[3], C3, SW[3], SW[7], C2); + + assign LEDR = {C3, S}; + +endmodule diff --git a/EE203/Noah Woodlee/Lab2/part3/part3.v.bak b/EE203/Noah Woodlee/Lab2/part3/part3.v.bak new file mode 100644 index 0000000..88ffabc --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/part3.v.bak @@ -0,0 +1,15 @@ +module adder(SUM, COUT, A, B, CIN); + input A, B, CIN; + output SUM, COUT; + + wire x; + + + xor x0(x, A, B); + xor x1(SUM, x, CIN); + + assign COUT=x? CIN: B; + +endmodule + +module \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part3/part3_assignment_defaults.qdf b/EE203/Noah Woodlee/Lab2/part3/part3_assignment_defaults.qdf new file mode 100644 index 0000000..698018e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/part3_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 20:06:27 April 24, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" 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+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value ENABLE +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off 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SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform.vwf.vt b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform.vwf.vt new file mode 100644 index 0000000..bd3b1a0 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform.vwf.vt @@ -0,0 +1,97 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "04/25/2021 00:26:26" + +// Verilog Test Bench (with test vectors) for design : part3 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module part3_vlg_vec_tst(); +// constants +// general purpose registers +reg [8:0] SW; +// wires +wire [4:0] LEDR; + +// assign statements (if any) +part3 i1 ( +// port map - connection between master ports and signals/registers + .LEDR(LEDR), + .SW(SW) +); +initial +begin +#1000000 $finish; +end +// SW[ 8 ] +initial +begin + SW[8] = 1'b1; + SW[8] = #280000 1'b0; +end +// SW[ 7 ] +initial +begin + SW[7] = 1'b1; + SW[7] = #280000 1'b0; +end +// SW[ 6 ] +initial +begin + SW[6] = 1'b1; + SW[6] = #280000 1'b0; +end +// SW[ 5 ] +initial +begin + SW[5] = 1'b0; +end +// SW[ 4 ] +initial +begin + SW[4] = 1'b0; +end +// SW[ 3 ] +initial +begin + SW[3] = 1'b0; +end +// SW[ 2 ] +initial +begin + SW[2] = 1'b1; + SW[2] = #280000 1'b0; +end +// SW[ 1 ] +initial +begin + SW[1] = 1'b0; +end +// SW[ 0 ] +initial +begin + SW[0] = 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt new file mode 100644 index 0000000..4a24e9b --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt @@ -0,0 +1,97 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "04/25/2021 00:51:59" + +// Verilog Test Bench (with test vectors) for design : part3 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module part3_vlg_vec_tst(); +// constants +// general purpose registers +reg [8:0] SW; +// wires +wire [4:0] LEDR; + +// assign statements (if any) +part3 i1 ( +// port map - connection between master ports and signals/registers + .LEDR(LEDR), + .SW(SW) +); +initial +begin +#1000000 $finish; +end +// SW[ 8 ] +initial +begin + SW[8] = 1'b1; + SW[8] = #400000 1'b0; +end +// SW[ 7 ] +initial +begin + SW[7] = 1'b1; + SW[7] = #400000 1'b0; +end +// SW[ 6 ] +initial +begin + SW[6] = 1'b1; + SW[6] = #400000 1'b0; +end +// SW[ 5 ] +initial +begin + SW[5] = 1'b0; +end +// SW[ 4 ] +initial +begin + SW[4] = 1'b0; +end +// SW[ 3 ] +initial +begin + SW[3] = 1'b0; +end +// SW[ 2 ] +initial +begin + SW[2] = 1'b1; + SW[2] = #400000 1'b0; +end +// SW[ 1 ] +initial +begin + SW[1] = 1'b0; +end +// SW[ 0 ] +initial +begin + SW[0] = 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform2.vwf.vt b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform2.vwf.vt new file mode 100644 index 0000000..1a8f88d --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform2.vwf.vt @@ -0,0 +1,97 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "04/25/2021 00:09:09" + +// Verilog Test Bench (with test vectors) for design : part3 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module part3_vlg_vec_tst(); +// constants +// general purpose registers +reg [8:0] SW; +// wires +wire [4:0] LEDR; + +// assign statements (if any) +part3 i1 ( +// port map - connection between master ports and signals/registers + .LEDR(LEDR), + .SW(SW) +); +initial +begin +#1000000 $finish; +end +// SW[ 8 ] +initial +begin + SW[8] = 1'b1; + SW[8] = #290000 1'b0; +end +// SW[ 7 ] +initial +begin + SW[7] = 1'b1; + SW[7] = #290000 1'b0; +end +// SW[ 6 ] +initial +begin + SW[6] = 1'b1; + SW[6] = #290000 1'b0; +end +// SW[ 5 ] +initial +begin + SW[5] = 1'b0; +end +// SW[ 4 ] +initial +begin + SW[4] = 1'b0; +end +// SW[ 3 ] +initial +begin + SW[3] = 1'b0; +end +// SW[ 2 ] +initial +begin + SW[2] = 1'b1; + SW[2] = #290000 1'b0; +end +// SW[ 1 ] +initial +begin + SW[1] = 1'b0; +end +// SW[ 0 ] +initial +begin + SW[0] = 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform3.vwf.vt b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform3.vwf.vt new file mode 100644 index 0000000..46cfc71 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform3.vwf.vt @@ -0,0 +1,97 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "04/25/2021 00:16:46" + +// Verilog Test Bench (with test vectors) for design : part3 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module part3_vlg_vec_tst(); +// constants +// general purpose registers +reg [8:0] SW; +// wires +wire [4:0] LEDR; + +// assign statements (if any) +part3 i1 ( +// port map - connection between master ports and signals/registers + .LEDR(LEDR), + .SW(SW) +); +initial +begin +#1000000 $finish; +end +// SW[ 8 ] +initial +begin + SW[8] = 1'b1; + SW[8] = #440000 1'b0; +end +// SW[ 7 ] +initial +begin + SW[7] = 1'b1; + SW[7] = #440000 1'b0; +end +// SW[ 6 ] +initial +begin + SW[6] = 1'b1; + SW[6] = #440000 1'b0; +end +// SW[ 5 ] +initial +begin + SW[5] = 1'b0; +end +// SW[ 4 ] +initial +begin + SW[4] = 1'b0; +end +// SW[ 3 ] +initial +begin + SW[3] = 1'b0; +end +// SW[ 2 ] +initial +begin + SW[2] = 1'b1; + SW[2] = #440000 1'b0; +end +// SW[ 1 ] +initial +begin + SW[1] = 1'b0; +end +// SW[ 0 ] +initial +begin + SW[0] = 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform4.vwf.vt b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform4.vwf.vt new file mode 100644 index 0000000..9992b96 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform4.vwf.vt @@ -0,0 +1,97 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "04/25/2021 00:19:15" + +// Verilog Test Bench (with test vectors) for design : part3 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module part3_vlg_vec_tst(); +// constants +// general purpose registers +reg [8:0] SW; +// wires +wire [4:0] LEDR; + +// assign statements (if any) +part3 i1 ( +// port map - connection between master ports and signals/registers + .LEDR(LEDR), + .SW(SW) +); +initial +begin +#1000000 $finish; +end +// SW[ 8 ] +initial +begin + SW[8] = 1'b1; + SW[8] = #360000 1'b0; +end +// SW[ 7 ] +initial +begin + SW[7] = 1'b1; + SW[7] = #360000 1'b0; +end +// SW[ 6 ] +initial +begin + SW[6] = 1'b1; + SW[6] = #360000 1'b0; +end +// SW[ 5 ] +initial +begin + SW[5] = 1'b0; +end +// SW[ 4 ] +initial +begin + SW[4] = 1'b0; +end +// SW[ 3 ] +initial +begin + SW[3] = 1'b0; +end +// SW[ 2 ] +initial +begin + SW[2] = 1'b1; + SW[2] = #360000 1'b0; +end +// SW[ 1 ] +initial +begin + SW[1] = 1'b0; +end +// SW[ 0 ] +initial +begin + SW[0] = 1'b0; +end +endmodule + diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.do b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.do new file mode 100644 index 0000000..be3ede1 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vlog -work work part3.vo +vlog -work work Waveform1.vwf.vt +vsim -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +vcd file -direction part3.msim.vcd +vcd add -internal part3_vlg_vec_tst/* +vcd add -internal part3_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.msim.vcd b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.msim.vcd new file mode 100644 index 0000000..7e80132 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.msim.vcd @@ -0,0 +1,124 @@ +$comment + File created using the following command: + vcd file part3.msim.vcd -direction +$end +$date + Sun Apr 25 00:52:04 2021 +$end +$version + ModelSim Version 2020.1 +$end +$timescale + 1ps +$end + +$scope module part3_vlg_vec_tst $end +$var reg 9 ! SW [8:0] $end +$var wire 1 " LEDR [4] $end +$var wire 1 # LEDR [3] $end +$var wire 1 $ LEDR [2] $end +$var wire 1 % LEDR [1] $end +$var wire 1 & LEDR [0] $end + +$scope module i1 $end +$var wire 1 ' gnd $end +$var wire 1 ( vcc $end +$var wire 1 ) unknown $end +$var tri1 1 * devclrn $end +$var tri1 1 + devpor $end +$var tri1 1 , devoe $end +$var wire 1 - ~QUARTUS_CREATED_GND~I_combout $end +$var wire 1 . ~QUARTUS_CREATED_UNVM~~busy $end +$var wire 1 / ~QUARTUS_CREATED_ADC1~~eoc $end +$var wire 1 0 ~QUARTUS_CREATED_ADC2~~eoc $end +$var wire 1 1 LEDR[0]~output_o $end +$var wire 1 2 LEDR[1]~output_o $end +$var wire 1 3 LEDR[2]~output_o $end +$var wire 1 4 LEDR[3]~output_o $end +$var wire 1 5 LEDR[4]~output_o $end +$var wire 1 6 SW[4]~input_o $end +$var wire 1 7 SW[0]~input_o $end +$var wire 1 8 SW[8]~input_o $end +$var wire 1 9 A0|x1~combout $end +$var wire 1 : SW[5]~input_o $end +$var wire 1 ; SW[1]~input_o $end +$var wire 1 < A0|COUT~0_combout $end +$var wire 1 = A1|x1~combout $end +$var wire 1 > SW[2]~input_o $end +$var wire 1 ? SW[6]~input_o $end +$var wire 1 @ A2|x0~combout $end +$var wire 1 A A2|x1~combout $end +$var wire 1 B A2|COUT~2_combout $end +$var wire 1 C A2|COUT~3_combout $end +$var wire 1 D SW[3]~input_o $end +$var wire 1 E SW[7]~input_o $end +$var wire 1 F A3|x1~combout $end +$var wire 1 G A3|COUT~0_combout $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b111000100 ! +1& +0% +0$ +0# +1" +0' +1( +x) +1* +1+ +1, +0- +z. +z/ +z0 +11 +02 +03 +04 +15 +06 +07 +18 +19 +0: +0; +0< +0= +1> +1? +0@ +0A +0B +1C +0D +1E +0F +1G +$end +#400000 +b11000100 ! +b1000100 ! +b100 ! +b0 ! +08 +0E +0? +0> +0C +09 +0G +1F +14 +05 +01 +0& +0" +1# +0F +04 +0# +#1000000 diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.sft b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.sft new file mode 100644 index 0000000..f324fea --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.vo b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.vo new file mode 100644 index 0000000..80eafe7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.vo @@ -0,0 +1,582 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +// DATE "04/25/2021 00:52:01" + +// +// Device: Altera 10M50DAF484C6GES Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module part3 ( + SW, + LEDR); +input [8:0] SW; +output [4:0] LEDR; + +// Design Ports Information +// LEDR[0] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[2] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[3] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// LEDR[4] => Location: PIN_D13, I/O Standard: 2.5 V, Current Strength: Default +// SW[8] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// SW[0] => Location: PIN_C10, I/O Standard: 2.5 V, Current Strength: Default +// SW[4] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// SW[1] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// SW[5] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// SW[2] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default +// SW[6] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// SW[3] => Location: PIN_C12, I/O Standard: 2.5 V, Current Strength: Default +// SW[7] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \~QUARTUS_CREATED_UNVM~~busy ; +wire \~QUARTUS_CREATED_ADC1~~eoc ; +wire \~QUARTUS_CREATED_ADC2~~eoc ; +wire \LEDR[0]~output_o ; +wire \LEDR[1]~output_o ; +wire \LEDR[2]~output_o ; +wire \LEDR[3]~output_o ; +wire \LEDR[4]~output_o ; +wire \SW[4]~input_o ; +wire \SW[0]~input_o ; +wire \SW[8]~input_o ; +wire \A0|x1~combout ; +wire \SW[5]~input_o ; +wire \SW[1]~input_o ; +wire \A0|COUT~0_combout ; +wire \A1|x1~combout ; +wire \SW[2]~input_o ; +wire \SW[6]~input_o ; +wire \A2|x0~combout ; +wire \A2|x1~combout ; +wire \A2|COUT~2_combout ; +wire \A2|COUT~3_combout ; +wire \SW[3]~input_o ; +wire \SW[7]~input_o ; +wire \A3|x1~combout ; +wire \A3|COUT~0_combout ; + + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: LCCOMB_X44_Y41_N16 +fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): +// \~QUARTUS_CREATED_GND~I_combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .cout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000; +defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X46_Y54_N2 +fiftyfivenm_io_obuf \LEDR[0]~output ( + .i(\A0|x1~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[0]~output .bus_hold = "false"; +defparam \LEDR[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X46_Y54_N23 +fiftyfivenm_io_obuf \LEDR[1]~output ( + .i(\A1|x1~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[1]~output .bus_hold = "false"; +defparam \LEDR[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X51_Y54_N16 +fiftyfivenm_io_obuf \LEDR[2]~output ( + .i(\A2|x1~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[2]~output .bus_hold = "false"; +defparam \LEDR[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X46_Y54_N9 +fiftyfivenm_io_obuf \LEDR[3]~output ( + .i(\A3|x1~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[3]~output .bus_hold = "false"; +defparam \LEDR[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X56_Y54_N30 +fiftyfivenm_io_obuf \LEDR[4]~output ( + .i(\A3|COUT~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\LEDR[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \LEDR[4]~output .bus_hold = "false"; +defparam \LEDR[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X54_Y54_N22 +fiftyfivenm_io_ibuf \SW[4]~input ( + .i(SW[4]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[4]~input_o )); +// synopsys translate_off +defparam \SW[4]~input .bus_hold = "false"; +defparam \SW[4]~input .listen_to_nsleep_signal = "false"; +defparam \SW[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N29 +fiftyfivenm_io_ibuf \SW[0]~input ( + .i(SW[0]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[0]~input_o )); +// synopsys translate_off +defparam \SW[0]~input .bus_hold = "false"; +defparam \SW[0]~input .listen_to_nsleep_signal = "false"; +defparam \SW[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X56_Y54_N1 +fiftyfivenm_io_ibuf \SW[8]~input ( + .i(SW[8]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[8]~input_o )); +// synopsys translate_off +defparam \SW[8]~input .bus_hold = "false"; +defparam \SW[8]~input .listen_to_nsleep_signal = "false"; +defparam \SW[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N24 +fiftyfivenm_lcell_comb \A0|x1 ( +// Equation(s): +// \A0|x1~combout = \SW[4]~input_o $ (\SW[0]~input_o $ (\SW[8]~input_o )) + + .dataa(\SW[4]~input_o ), + .datab(\SW[0]~input_o ), + .datac(gnd), + .datad(\SW[8]~input_o ), + .cin(gnd), + .combout(\A0|x1~combout ), + .cout()); +// synopsys translate_off +defparam \A0|x1 .lut_mask = 16'h9966; +defparam \A0|x1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X49_Y54_N1 +fiftyfivenm_io_ibuf \SW[5]~input ( + .i(SW[5]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[5]~input_o )); +// synopsys translate_off +defparam \SW[5]~input .bus_hold = "false"; +defparam \SW[5]~input .listen_to_nsleep_signal = "false"; +defparam \SW[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N22 +fiftyfivenm_io_ibuf \SW[1]~input ( + .i(SW[1]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[1]~input_o )); +// synopsys translate_off +defparam \SW[1]~input .bus_hold = "false"; +defparam \SW[1]~input .listen_to_nsleep_signal = "false"; +defparam \SW[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N26 +fiftyfivenm_lcell_comb \A0|COUT~0 ( +// Equation(s): +// \A0|COUT~0_combout = (\SW[4]~input_o & ((\SW[0]~input_o ) # (\SW[8]~input_o ))) # (!\SW[4]~input_o & (\SW[0]~input_o & \SW[8]~input_o )) + + .dataa(\SW[4]~input_o ), + .datab(\SW[0]~input_o ), + .datac(gnd), + .datad(\SW[8]~input_o ), + .cin(gnd), + .combout(\A0|COUT~0_combout ), + .cout()); +// synopsys translate_off +defparam \A0|COUT~0 .lut_mask = 16'hEE88; +defparam \A0|COUT~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N12 +fiftyfivenm_lcell_comb \A1|x1 ( +// Equation(s): +// \A1|x1~combout = \SW[5]~input_o $ (\SW[1]~input_o $ (\A0|COUT~0_combout )) + + .dataa(\SW[5]~input_o ), + .datab(\SW[1]~input_o ), + .datac(\A0|COUT~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\A1|x1~combout ), + .cout()); +// synopsys translate_off +defparam \A1|x1 .lut_mask = 16'h9696; +defparam \A1|x1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X51_Y54_N1 +fiftyfivenm_io_ibuf \SW[2]~input ( + .i(SW[2]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[2]~input_o )); +// synopsys translate_off +defparam \SW[2]~input .bus_hold = "false"; +defparam \SW[2]~input .listen_to_nsleep_signal = "false"; +defparam \SW[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X54_Y54_N15 +fiftyfivenm_io_ibuf \SW[6]~input ( + .i(SW[6]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[6]~input_o )); +// synopsys translate_off +defparam \SW[6]~input .bus_hold = "false"; +defparam \SW[6]~input .listen_to_nsleep_signal = "false"; +defparam \SW[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N22 +fiftyfivenm_lcell_comb \A2|x0 ( +// Equation(s): +// \A2|x0~combout = \SW[2]~input_o $ (\SW[6]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\SW[2]~input_o ), + .datad(\SW[6]~input_o ), + .cin(gnd), + .combout(\A2|x0~combout ), + .cout()); +// synopsys translate_off +defparam \A2|x0 .lut_mask = 16'h0FF0; +defparam \A2|x0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N16 +fiftyfivenm_lcell_comb \A2|x1 ( +// Equation(s): +// \A2|x1~combout = \A2|x0~combout $ (((\SW[1]~input_o & ((\A0|COUT~0_combout ) # (\SW[5]~input_o ))) # (!\SW[1]~input_o & (\A0|COUT~0_combout & \SW[5]~input_o )))) + + .dataa(\A2|x0~combout ), + .datab(\SW[1]~input_o ), + .datac(\A0|COUT~0_combout ), + .datad(\SW[5]~input_o ), + .cin(gnd), + .combout(\A2|x1~combout ), + .cout()); +// synopsys translate_off +defparam \A2|x1 .lut_mask = 16'h566A; +defparam \A2|x1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N10 +fiftyfivenm_lcell_comb \A2|COUT~2 ( +// Equation(s): +// \A2|COUT~2_combout = (\A2|x0~combout & ((\SW[1]~input_o & ((\A0|COUT~0_combout ) # (\SW[5]~input_o ))) # (!\SW[1]~input_o & (\A0|COUT~0_combout & \SW[5]~input_o )))) + + .dataa(\A2|x0~combout ), + .datab(\SW[1]~input_o ), + .datac(\A0|COUT~0_combout ), + .datad(\SW[5]~input_o ), + .cin(gnd), + .combout(\A2|COUT~2_combout ), + .cout()); +// synopsys translate_off +defparam \A2|COUT~2 .lut_mask = 16'hA880; +defparam \A2|COUT~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N0 +fiftyfivenm_lcell_comb \A2|COUT~3 ( +// Equation(s): +// \A2|COUT~3_combout = (\A2|COUT~2_combout ) # ((\SW[2]~input_o & \SW[6]~input_o )) + + .dataa(\A2|COUT~2_combout ), + .datab(gnd), + .datac(\SW[2]~input_o ), + .datad(\SW[6]~input_o ), + .cin(gnd), + .combout(\A2|COUT~3_combout ), + .cout()); +// synopsys translate_off +defparam \A2|COUT~3 .lut_mask = 16'hFAAA; +defparam \A2|COUT~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X54_Y54_N29 +fiftyfivenm_io_ibuf \SW[3]~input ( + .i(SW[3]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[3]~input_o )); +// synopsys translate_off +defparam \SW[3]~input .bus_hold = "false"; +defparam \SW[3]~input .listen_to_nsleep_signal = "false"; +defparam \SW[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X58_Y54_N29 +fiftyfivenm_io_ibuf \SW[7]~input ( + .i(SW[7]), + .ibar(gnd), + .nsleep(vcc), + .o(\SW[7]~input_o )); +// synopsys translate_off +defparam \SW[7]~input .bus_hold = "false"; +defparam \SW[7]~input .listen_to_nsleep_signal = "false"; +defparam \SW[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N20 +fiftyfivenm_lcell_comb \A3|x1 ( +// Equation(s): +// \A3|x1~combout = \A2|COUT~3_combout $ (\SW[3]~input_o $ (\SW[7]~input_o )) + + .dataa(gnd), + .datab(\A2|COUT~3_combout ), + .datac(\SW[3]~input_o ), + .datad(\SW[7]~input_o ), + .cin(gnd), + .combout(\A3|x1~combout ), + .cout()); +// synopsys translate_off +defparam \A3|x1 .lut_mask = 16'hC33C; +defparam \A3|x1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X51_Y53_N6 +fiftyfivenm_lcell_comb \A3|COUT~0 ( +// Equation(s): +// \A3|COUT~0_combout = (\A2|COUT~3_combout & ((\SW[3]~input_o ) # (\SW[7]~input_o ))) # (!\A2|COUT~3_combout & (\SW[3]~input_o & \SW[7]~input_o )) + + .dataa(gnd), + .datab(\A2|COUT~3_combout ), + .datac(\SW[3]~input_o ), + .datad(\SW[7]~input_o ), + .cin(gnd), + .combout(\A3|COUT~0_combout ), + .cout()); +// synopsys translate_off +defparam \A3|COUT~0 .lut_mask = 16'hFCC0; +defparam \A3|COUT~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: UNVM_X0_Y40_N40 +fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ ( + .arclk(vcc), + .arshft(vcc), + .drclk(vcc), + .drshft(vcc), + .drdin(vcc), + .nprogram(vcc), + .nerase(vcc), + .nosc_ena(\~QUARTUS_CREATED_GND~I_combout ), + .par_en(vcc), + .xe_ye(\~QUARTUS_CREATED_GND~I_combout ), + .se(\~QUARTUS_CREATED_GND~I_combout ), + .ardin(23'b11111111111111111111111), + .busy(\~QUARTUS_CREATED_UNVM~~busy ), + .osc(), + .bgpbusy(), + .sp_pass(), + .se_pass(), + .drdout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_end_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .addr_range3_offset = -1; +defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false"; +defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1; +defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm"; +defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true"; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y52_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC1~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1; +defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0; +// synopsys translate_on + +// Location: ADCBLOCK_X43_Y51_N0 +fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ ( + .soc(\~QUARTUS_CREATED_GND~I_combout ), + .usr_pwd(vcc), + .tsen(\~QUARTUS_CREATED_GND~I_combout ), + .clkin_from_pll_c0(gnd), + .chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }), + .eoc(\~QUARTUS_CREATED_ADC2~~eoc ), + .dout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0; +defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none"; +defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2; +defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0; +defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1; +defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0; +defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true"; +defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66; +defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1; +defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0; +// synopsys translate_on + +assign LEDR[0] = \LEDR[0]~output_o ; + +assign LEDR[1] = \LEDR[1]~output_o ; + +assign LEDR[2] = \LEDR[2]~output_o ; + +assign LEDR[3] = \LEDR[3]~output_o ; + +assign LEDR[4] = \LEDR[4]~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default +// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_TMS~~padout ; +wire \~ALTERA_TCK~~padout ; +wire \~ALTERA_TDI~~padout ; +wire \~ALTERA_CONFIG_SEL~~padout ; +wire \~ALTERA_nCONFIG~~padout ; +wire \~ALTERA_nSTATUS~~padout ; +wire \~ALTERA_CONF_DONE~~padout ; +wire \~ALTERA_TMS~~ibuf_o ; +wire \~ALTERA_TCK~~ibuf_o ; +wire \~ALTERA_TDI~~ibuf_o ; +wire \~ALTERA_CONFIG_SEL~~ibuf_o ; +wire \~ALTERA_nCONFIG~~ibuf_o ; +wire \~ALTERA_nSTATUS~~ibuf_o ; +wire \~ALTERA_CONF_DONE~~ibuf_o ; + + +endmodule diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_20210416205858.sim.vwf b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_20210416205858.sim.vwf new file mode 100644 index 0000000..c751815 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_20210416205858.sim.vwf @@ -0,0 +1,545 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Intel and sold by Intel or its +authorized distributors. Please refer to the applicable +agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 5; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 9; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 520.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 480.0; + LEVEL 1 FOR 520.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; + CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 6; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_20210425005204.sim.vwf b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_20210425005204.sim.vwf new file mode 100644 index 0000000..cd5c905 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_20210425005204.sim.vwf @@ -0,0 +1,549 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 5; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 9; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 600.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; + CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 6; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 6; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_modelsim.xrf b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_modelsim.xrf new file mode 100644 index 0000000..0f2e53e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3_modelsim.xrf @@ -0,0 +1,44 @@ +vendor_name = ModelSim +source_file = 1, C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v +source_file = 1, C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform.vwf +source_file = 1, C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf +source_file = 1, Waveform2.vwf +source_file = 1, Waveform3.vwf +source_file = 1, Waveform4.vwf +source_file = 1, C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/db/part3.cbx.xml +design_name = part3 +instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, part3, 1 +instance = comp, \LEDR[0]~output , LEDR[0]~output, part3, 1 +instance = comp, \LEDR[1]~output , LEDR[1]~output, part3, 1 +instance = comp, \LEDR[2]~output , LEDR[2]~output, part3, 1 +instance = comp, \LEDR[3]~output , LEDR[3]~output, part3, 1 +instance = comp, \LEDR[4]~output , LEDR[4]~output, part3, 1 +instance = comp, \SW[4]~input , SW[4]~input, part3, 1 +instance = comp, \SW[0]~input , SW[0]~input, part3, 1 +instance = comp, \SW[8]~input , SW[8]~input, part3, 1 +instance = comp, \A0|x1 , A0|x1, part3, 1 +instance = comp, \SW[5]~input , SW[5]~input, part3, 1 +instance = comp, \SW[1]~input , SW[1]~input, part3, 1 +instance = comp, \A0|COUT~0 , A0|COUT~0, part3, 1 +instance = comp, \A1|x1 , A1|x1, part3, 1 +instance = comp, \SW[2]~input , SW[2]~input, part3, 1 +instance = comp, \SW[6]~input , SW[6]~input, part3, 1 +instance = comp, \A2|x0 , A2|x0, part3, 1 +instance = comp, \A2|x1 , A2|x1, part3, 1 +instance = comp, \A2|COUT~2 , A2|COUT~2, part3, 1 +instance = comp, \A2|COUT~3 , A2|COUT~3, part3, 1 +instance = comp, \SW[3]~input , SW[3]~input, part3, 1 +instance = comp, \SW[7]~input , SW[7]~input, part3, 1 +instance = comp, \A3|x1 , A3|x1, part3, 1 +instance = comp, \A3|COUT~0 , A3|COUT~0, part3, 1 +instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, part3, 1 +instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, part3, 1 +instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, part3, 1 +design_name = hard_block +instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1 diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/transcript b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/transcript new file mode 100644 index 0000000..d6d543d --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/transcript @@ -0,0 +1,42 @@ +# do part3.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 00:52:03 on Apr 25,2021 +# vlog -work work part3.vo +# -- Compiling module part3 +# -- Compiling module hard_block +# +# Top level modules: +# part3 +# End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 00:52:03 on Apr 25,2021 +# vlog -work work Waveform1.vwf.vt +# -- Compiling module part3_vlg_vec_tst +# +# Top level modules: +# part3_vlg_vec_tst +# End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +# Start time: 00:52:03 on Apr 25,2021 +# Loading work.part3_vlg_vec_tst +# Loading work.part3 +# Loading work.hard_block +# Loading fiftyfivenm_ver.fiftyfivenm_lcell_comb +# Loading fiftyfivenm_ver.fiftyfivenm_io_obuf +# Loading fiftyfivenm_ver.fiftyfivenm_io_ibuf +# Loading fiftyfivenm_ver.fiftyfivenm_unvm +# Loading fiftyfivenm_ver.fiftyfivenm_adcblock +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC1~ '. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: part3.vo Line: 481 +# ** Warning: (vsim-3722) part3.vo(481): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC2~ '. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: part3.vo Line: 504 +# ** Warning: (vsim-3722) part3.vo(504): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform1.vwf.vt(45) +# Time: 1 us Iteration: 0 Instance: /part3_vlg_vec_tst +# End time: 00:52:04 on Apr 25,2021, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 4 diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/vwf_sim_transcript b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..f831c16 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,403 @@ +Determining the location of the ModelSim executable... + +Using: c:/intelfpga_lite/20.1/modelsim_ase/win32aloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt" + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Copyright (C) 2020 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and any partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel FPGA IP License Agreement, or other applicable license + Info: agreement, including, without limitation, that your use is for + Info: the sole purpose of programming logic devices manufactured by + Info: Intel and sold by Intel or its authorized distributors. Please + Info: refer to the applicable agreement for further details, at + Info: https://fpgasoftware.intel.com/eula. + Info: Processing started: Sun Apr 25 00:51:58 2021 +Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt" +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning + (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. + +utput pin "LEDR" in vector source file when writing test bench files + +Completed successfully. + +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 + +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Copyright (C) 2020 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and any partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel FPGA IP License Agreement, or other applicable license + Info: agreement, including, without limitation, that your use is for + Info: the sole purpose of programming logic devices manufactured by + Info: Intel and sold by Intel or its authorized distributors. Please + Info: refer to the applicable agreement for further details, at + Info: https://fpgasoftware.intel.com/eula. + Info: Processing started: Sun Apr 25 00:52:00 2021 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE +_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file part3.vo in folder "C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee +/Lab2/part3/simulation/qsim//" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 126 warnings + Info: Peak virtual memory: 4660 megabytes + Info: Processing ended: Sun Apr 25 00:52:01 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + +Completed successfully. + +**** Generating the ModelSim .do script **** + +C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/part3.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +c:/intelfpga_lite/20.1/modelsim_ase/win32aloem//vsim -c -do part3.do + +Reading pref.tcl + +# 2020.1 + + +# do part3.do + +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 00:52:03 on Apr 25,2021 +# vlog -work work part3.vo + +# -- Compiling module part3 +# -- Compiling module hard_block +# +# Top level modules: +# part3 +# End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 00:52:03 on Apr 25,2021 +# vlog -work work Waveform1.vwf.vt +# -- Compiling module part3_vlg_vec_tst +# +# Top level modules: +# part3_vlg_vec_tst +# End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 + +# vsim -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst +# Start time: 00:52:03 on Apr 25,2021 +# Loading work.part3_vlg_vec_tst +# Loading work.part3 +# Loading work.hard_block +# Loading fiftyfivenm_ver.fiftyfivenm_lcell_comb +# Loading fiftyfivenm_ver.fiftyfivenm_io_obuf +# Loading fiftyfivenm_ver.fiftyfivenm_io_ibuf +# Loading fiftyfivenm_ver.fiftyfivenm_unvm +# Loading fiftyfivenm_ver.fiftyfivenm_adcblock +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC1~ '. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: part3.vo Line: 481 +# ** Warning: (vsim-3722) part3.vo(481): [TFMPC] - Missing connection for port 'clk_dft'. +# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC2~ '. Expected 8, found 7. +# Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: part3.vo Line: 504 +# ** Warning: (vsim-3722) part3.vo(504): [TFMPC] - Missing connection for port 'clk_dft'. +# after#26 +# ** Note: $finish : Waveform1.vwf.vt(45) +# Time: 1 us Iteration: 0 Instance: /part3_vlg_vec_tst +# End time: 00:52:04 on Apr 25,2021, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 4 + +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf... + +Reading C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/part3.msim.vcd... + +Processing channel transitions... + +Writing the resulting VWF to C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/part3_20210425005204.sim.vwf + +Finished VCD to VWF conversion. + +Completed successfully. + +All completed. \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_info b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_info new file mode 100644 index 0000000..82963ee --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_info @@ -0,0 +1,80 @@ +m255 +K4 +z2 +!s11f vlog 2020.1 2020.02, Feb 28 2020 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dC:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim +vhard_block +Z1 !s110 1619329923 +!i10b 1 +!s100 hk;iOES1OEEkmIH`g28P^2 +Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1 +I:0VO>2Okd0fffWJm?T;9Q0 +Z3 VDg1SIo80bB@j0V0VzS_@n1 +R0 +Z4 w1619329921 +Z5 8part3.vo +Z6 Fpart3.vo +!i122 2 +L0 538 45 +Z7 OV;L;2020.1;71 +r1 +!s85 0 +31 +Z8 !s108 1619329923.000000 +Z9 !s107 part3.vo| +Z10 !s90 -work|work|part3.vo| +!i113 1 +Z11 o-work work +Z12 tCvgOpt 0 +vpart3 +R1 +!i10b 1 +!s100 @Dk8V0jGN0cVf@O6]8BlI1 +R2 +IN0IA31^WL4mZlO5c]]QzO1 +R3 +R0 +R4 +R5 +R6 +!i122 2 +L0 32 505 +R7 +r1 +!s85 0 +31 +R8 +R9 +R10 +!i113 1 +R11 +R12 +vpart3_vlg_vec_tst +R1 +!i10b 1 +!s100 fT[cU72ZYER_eYz1VlYE[2 +R2 +IK`ig?Wo_giD0?]E<@Be_53 +R3 +R0 +w1619329920 +8Waveform1.vwf.vt +FWaveform1.vwf.vt +!i122 3 +L0 30 67 +R7 +r1 +!s85 0 +31 +R8 +!s107 Waveform1.vwf.vt| +!s90 -work|work|Waveform1.vwf.vt| +!i113 1 +R11 +R12 diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib.qdb b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib.qdb new file mode 100644 index 0000000..b8a52fb Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib.qdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qdb b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qdb new file mode 100644 index 0000000..d5775e0 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qdb differ diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qpg b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qpg new file mode 100644 index 0000000..bb1b8a8 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qpg differ diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qtl b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qtl new file mode 100644 index 0000000..256eadd Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qtl differ diff --git a/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_vmake b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/EE203/Noah Woodlee/Lab2/part4.v b/EE203/Noah Woodlee/Lab2/part4.v new file mode 100644 index 0000000..2364296 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4.v @@ -0,0 +1,81 @@ +module bcd(IN,OUT); + input [3:0] IN; + output [6:0] OUT; + + assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000): + (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010): + (IN[0]? 7'b0010_010:7'b0011_001)): + (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100): + (IN[0]? 7'b1111_001:7'b1000_000))); + +endmodule + +module mux_2to1 (IN1, IN2, S, OUT); + input[3:0]IN1, IN2; + input S; + output [3:0]OUT; + + assign OUT=S? IN2:IN1; + +endmodule + +module BCD_ex(SW, D0, D1); + input [3:0] SW; + output [6:0] D0, D1; + + wire z; + wire [4:0] A, V; + wire [4:0] W; + + assign V=SW[3:0]; + assign z = V[4:0] > 9? 1:0; + assign D1 =z? 7'b1111_001:7'b1000_000; + + assign A=V[3:0]-4'b1010; + mux_2to1 M0 (V, A, z, W); + bcd B0 (W, D0); +endmodule + +module adder(SUM, COUT, A, B, CIN); + input A, B, CIN; + output SUM, COUT; + + wire x; + + xor x0(x, A, B); + xor x1(SUM, x, CIN); + + assign COUT = x? CIN: B; + +endmodule + +module RippleCarryAdder(SUM, COUT, IN1, IN2, CIN); + input [4:0] IN1, IN2; + input CIN; + output COUT; + output [3:0] SUM; + + wire C0, C1, C2, C3; + + adder A0(SUM[0], C0, IN1[0], IN2[0], CIN); + adder A1(SUM[1], C1, IN1[1], IN2[1], C0); + adder A2(SUM[2], C2, IN1[2], IN2[2], C1); + adder A3(SUM[3], C3, IN1[3], IN2[3], C2); + + assign COUT = C3; + +endmodule + +// if the inputs excede decimal value 9, result is unknown +module part4(SW, HEX0, HEX1); + input [8:0] SW; + output [6:0] HEX0, HEX1; + + wire COUT; + wire [3:0] U; + + // Add the decimal number's 0-9 + RippleCarryAdder R0(U, COUT, SW[3:0], SW[7:4], SW[8]); + // send the output along with carry to 7-segment display + BCD_ex({COUT, U}, HEX0, HEX1); +endmodule diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(0).cnf.cdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(0).cnf.cdb new file mode 100644 index 0000000..ea4bdc5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(0).cnf.hdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(0).cnf.hdb new file mode 100644 index 0000000..24bf6d9 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(1).cnf.cdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(1).cnf.cdb new file mode 100644 index 0000000..a8538d0 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(1).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(1).cnf.hdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(1).cnf.hdb new file mode 100644 index 0000000..7fa8490 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(1).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(2).cnf.cdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(2).cnf.cdb new file mode 100644 index 0000000..7ba2e49 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(2).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(2).cnf.hdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(2).cnf.hdb new file mode 100644 index 0000000..131940d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(2).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(3).cnf.cdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(3).cnf.cdb new file mode 100644 index 0000000..786b3bc Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(3).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(3).cnf.hdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(3).cnf.hdb new file mode 100644 index 0000000..a7413fe Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(3).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(4).cnf.cdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(4).cnf.cdb new file mode 100644 index 0000000..032afae Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(4).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(4).cnf.hdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(4).cnf.hdb new file mode 100644 index 0000000..52de931 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(4).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(5).cnf.cdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(5).cnf.cdb new file mode 100644 index 0000000..d092373 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(5).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.(5).cnf.hdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.(5).cnf.hdb new file mode 100644 index 0000000..407cd8f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.(5).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.asm.qmsg b/EE203/Noah Woodlee/Lab2/part4/db/part4.asm.qmsg new file mode 100644 index 0000000..fd5b23e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619378546180 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619378546181 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 14:22:25 2021 " "Processing started: Sun Apr 25 14:22:25 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619378546181 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619378546181 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619378546182 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619378546573 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619378549402 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619378549503 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "356 " "Peak virtual memory: 356 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619378550733 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 14:22:30 2021 " "Processing ended: Sun Apr 25 14:22:30 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619378550733 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619378550733 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619378550733 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619378550733 ""} diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.asm.rdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.asm.rdb new file mode 100644 index 0000000..e6a9b31 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.asm.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.asm_labs.ddb b/EE203/Noah Woodlee/Lab2/part4/db/part4.asm_labs.ddb new file mode 100644 index 0000000..041f333 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.cbx.xml b/EE203/Noah Woodlee/Lab2/part4/db/part4.cbx.xml new file mode 100644 index 0000000..b1c43dd --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.bpm b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.bpm new file mode 100644 index 0000000..5e735c6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.cdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.cdb new file mode 100644 index 0000000..0ffcce2 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.hdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.hdb new file mode 100644 index 0000000..dffe1e1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.idb b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.idb new file mode 100644 index 0000000..e2b2740 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.idb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.logdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.logdb new file mode 100644 index 0000000..5d92093 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.logdb @@ -0,0 +1,65 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;23;23;0;0;23;23;0;0;0;0;0;0;14;0;0;0;9;14;0;9;0;0;14;0;23;23;23;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,23;0;0;23;23;0;0;23;23;23;23;23;23;9;23;23;23;14;9;23;14;23;23;9;23;0;0;0;23;23, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.rdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.rdb new file mode 100644 index 0000000..2adb0cf Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp_merge.kpt b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp_merge.kpt new file mode 100644 index 0000000..2e5db87 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.db_info b/EE203/Noah Woodlee/Lab2/part4/db/part4.db_info new file mode 100644 index 0000000..73c2788 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sun Apr 25 14:16:58 2021 diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.fit.qmsg b/EE203/Noah Woodlee/Lab2/part4/db/part4.fit.qmsg new file mode 100644 index 0000000..46ab81a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.fit.qmsg @@ -0,0 +1,54 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1619378531547 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619378531548 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part4 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part4\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619378531559 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1619378531652 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1619378531652 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1619378532066 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619378532080 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619378532245 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 131 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619378532259 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619378532259 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 135 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619378532259 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 137 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619378532259 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 139 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619378532259 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 141 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619378532259 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 143 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619378532259 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 145 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619378532259 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1619378532259 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619378532261 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619378532261 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619378532261 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619378532261 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1619378532265 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1619378532995 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1619378532995 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1619378532996 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1619378532997 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1619378533000 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1619378533000 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1619378533001 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1619378533010 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619378533010 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619378533011 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619378533013 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619378533014 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1619378533014 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1619378533014 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1619378533015 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1619378533015 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1619378533015 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619378533015 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619378533061 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1619378533061 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619378533062 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1619378533076 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619378536018 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619378536153 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619378536208 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619378536716 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619378536717 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619378537494 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X56_Y44 X66_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54" { } { { "loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54"} { { 12 { 0 ""} 56 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1619378541070 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619378541070 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1619378541324 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1619378541324 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1619378541324 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619378541327 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.04 " "Total time spent on timing analysis during the Fitter is 0.04 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1619378541642 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619378541652 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1619378541653 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619378542106 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619378542106 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1619378542106 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619378542547 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619378543187 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1619378543382 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/output_files/part4.fit.smsg " "Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/output_files/part4.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619378543444 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 34 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 34 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1083 " "Peak virtual memory: 1083 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619378543906 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 14:22:23 2021 " "Processing ended: Sun Apr 25 14:22:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619378543906 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619378543906 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619378543906 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619378543906 ""} diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.hier_info b/EE203/Noah Woodlee/Lab2/part4/db/part4.hier_info new file mode 100644 index 0000000..2201f55 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.hier_info @@ -0,0 +1,170 @@ +|part4 +SW[0] => SW[0].IN1 +SW[1] => SW[1].IN1 +SW[2] => SW[2].IN1 +SW[3] => SW[3].IN1 +SW[4] => SW[4].IN1 +SW[5] => SW[5].IN1 +SW[6] => SW[6].IN1 +SW[7] => SW[7].IN1 +SW[8] => SW[8].IN1 +HEX0[0] << BCD_ex:comb_3.port1 +HEX0[1] << BCD_ex:comb_3.port1 +HEX0[2] << BCD_ex:comb_3.port1 +HEX0[3] << BCD_ex:comb_3.port1 +HEX0[4] << BCD_ex:comb_3.port1 +HEX0[5] << BCD_ex:comb_3.port1 +HEX0[6] << BCD_ex:comb_3.port1 +HEX1[0] << BCD_ex:comb_3.port2 +HEX1[1] << BCD_ex:comb_3.port2 +HEX1[2] << BCD_ex:comb_3.port2 +HEX1[3] << BCD_ex:comb_3.port2 +HEX1[4] << BCD_ex:comb_3.port2 +HEX1[5] << BCD_ex:comb_3.port2 +HEX1[6] << BCD_ex:comb_3.port2 + + +|part4|RippleCarryAdder:R0 +SUM[0] <= adder:A0.port0 +SUM[1] <= adder:A1.port0 +SUM[2] <= adder:A2.port0 +SUM[3] <= adder:A3.port0 +COUT <= adder:A3.port1 +IN1[0] => IN1[0].IN1 +IN1[1] => IN1[1].IN1 +IN1[2] => IN1[2].IN1 +IN1[3] => IN1[3].IN1 +IN1[4] => ~NO_FANOUT~ +IN2[0] => IN2[0].IN1 +IN2[1] => IN2[1].IN1 +IN2[2] => IN2[2].IN1 +IN2[3] => IN2[3].IN1 +IN2[4] => ~NO_FANOUT~ +CIN => CIN.IN1 + + +|part4|RippleCarryAdder:R0|adder:A0 +SUM <= x1.DB_MAX_OUTPUT_PORT_TYPE +COUT <= COUT.DB_MAX_OUTPUT_PORT_TYPE +A => x0.IN0 +B => x0.IN1 +B => COUT.DATAA +CIN => x1.IN1 +CIN => COUT.DATAB + + +|part4|RippleCarryAdder:R0|adder:A1 +SUM <= x1.DB_MAX_OUTPUT_PORT_TYPE +COUT <= COUT.DB_MAX_OUTPUT_PORT_TYPE +A => x0.IN0 +B => x0.IN1 +B => COUT.DATAA +CIN => x1.IN1 +CIN => COUT.DATAB + + +|part4|RippleCarryAdder:R0|adder:A2 +SUM <= x1.DB_MAX_OUTPUT_PORT_TYPE +COUT <= COUT.DB_MAX_OUTPUT_PORT_TYPE +A => x0.IN0 +B => x0.IN1 +B => COUT.DATAA +CIN => x1.IN1 +CIN => COUT.DATAB + + +|part4|RippleCarryAdder:R0|adder:A3 +SUM <= x1.DB_MAX_OUTPUT_PORT_TYPE +COUT <= COUT.DB_MAX_OUTPUT_PORT_TYPE +A => x0.IN0 +B => x0.IN1 +B => COUT.DATAA +CIN => x1.IN1 +CIN => COUT.DATAB + + +|part4|BCD_ex:comb_3 +SW[0] => V[0].IN2 +SW[1] => V[1].IN1 +SW[2] => V[2].IN1 +SW[3] => V[3].IN1 +D0[0] <= bcd:B0.port1 +D0[1] <= bcd:B0.port1 +D0[2] <= bcd:B0.port1 +D0[3] <= bcd:B0.port1 +D0[4] <= bcd:B0.port1 +D0[5] <= bcd:B0.port1 +D0[6] <= bcd:B0.port1 +D1[0] <= z.DB_MAX_OUTPUT_PORT_TYPE +D1[1] <= +D1[2] <= +D1[3] <= z.DB_MAX_OUTPUT_PORT_TYPE +D1[4] <= z.DB_MAX_OUTPUT_PORT_TYPE +D1[5] <= z.DB_MAX_OUTPUT_PORT_TYPE +D1[6] <= + + +|part4|BCD_ex:comb_3|mux_2to1:M0 +IN1[0] => OUT.DATAA +IN1[1] => OUT.DATAA +IN1[2] => OUT.DATAA +IN1[3] => OUT.DATAA +IN2[0] => OUT.DATAB +IN2[1] => OUT.DATAB +IN2[2] => OUT.DATAB +IN2[3] => OUT.DATAB +S => OUT.OUTPUTSELECT +S => OUT.OUTPUTSELECT +S => OUT.OUTPUTSELECT +S => OUT.OUTPUTSELECT +OUT[0] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= OUT.DB_MAX_OUTPUT_PORT_TYPE + + +|part4|BCD_ex:comb_3|bcd:B0 +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAA +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.DATAA +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +OUT[0] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[4] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[5] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[6] <= OUT.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.hif b/EE203/Noah Woodlee/Lab2/part4/db/part4.hif new file mode 100644 index 0000000..8561666 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.hif differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.html b/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.html new file mode 100644 index 0000000..33aeca3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.html @@ -0,0 +1,146 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
comb_3|B04000700000000
comb_3|M09000400000000
comb_343031433300000
R0|A33000200000000
R0|A23000200000000
R0|A13000200000000
R0|A03000200000000
R011202522200000
diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.rdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.rdb new file mode 100644 index 0000000..f12493e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.txt b/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.txt new file mode 100644 index 0000000..6167a31 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.lpc.txt @@ -0,0 +1,14 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; comb_3|B0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; comb_3|M0 ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; comb_3 ; 4 ; 3 ; 0 ; 3 ; 14 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; R0|A3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; R0|A2 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; R0|A1 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; R0|A0 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; R0 ; 11 ; 2 ; 0 ; 2 ; 5 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.map.ammdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.ammdb new file mode 100644 index 0000000..790b913 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.map.bpm b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.bpm new file mode 100644 index 0000000..d9d9cae Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.map.cdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.cdb new file mode 100644 index 0000000..9d7ed02 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.map.hdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.hdb new file mode 100644 index 0000000..6e6a4e5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.map.kpt b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.kpt new file mode 100644 index 0000000..f518496 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.map.logdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.map.qmsg b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.qmsg new file mode 100644 index 0000000..7cec0ef --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.map.qmsg @@ -0,0 +1,23 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619378514251 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619378514252 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 14:21:54 2021 " "Processing started: Sun Apr 25 14:21:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619378514252 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619378514252 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619378514253 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619378514714 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619378514714 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part4.v 6 6 " "Found 6 design units, including 6 entities, in source file part4.v" { { "Info" "ISGN_ENTITY_NAME" "1 bcd " "Found entity 1: bcd" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619378526984 ""} { "Info" "ISGN_ENTITY_NAME" "2 mux_2to1 " "Found entity 2: mux_2to1" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 13 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619378526984 ""} { "Info" "ISGN_ENTITY_NAME" "3 BCD_ex " "Found entity 3: BCD_ex" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619378526984 ""} { "Info" "ISGN_ENTITY_NAME" "4 adder " "Found entity 4: adder" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619378526984 ""} { "Info" "ISGN_ENTITY_NAME" "5 RippleCarryAdder " "Found entity 5: RippleCarryAdder" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 52 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619378526984 ""} { "Info" "ISGN_ENTITY_NAME" "6 part4 " "Found entity 6: part4" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 70 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619378526984 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619378526984 ""} +{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "part4.v(80) " "Verilog HDL Instantiation warning at part4.v(80): instance has no name" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 80 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1619378526985 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part4 " "Elaborating entity \"part4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619378527140 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RippleCarryAdder RippleCarryAdder:R0 " "Elaborating entity \"RippleCarryAdder\" for hierarchy \"RippleCarryAdder:R0\"" { } { { "part4.v" "R0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619378527159 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder RippleCarryAdder:R0\|adder:A0 " "Elaborating entity \"adder\" for hierarchy \"RippleCarryAdder:R0\|adder:A0\"" { } { { "part4.v" "A0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619378527161 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BCD_ex BCD_ex:comb_3 " "Elaborating entity \"BCD_ex\" for hierarchy \"BCD_ex:comb_3\"" { } { { "part4.v" "comb_3" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619378527166 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 part4.v(31) " "Verilog HDL assignment warning at part4.v(31): truncated value with size 32 to match size of target (1)" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1619378527167 "|part4|BCD_ex:comb_3"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_2to1 BCD_ex:comb_3\|mux_2to1:M0 " "Elaborating entity \"mux_2to1\" for hierarchy \"BCD_ex:comb_3\|mux_2to1:M0\"" { } { { "part4.v" "M0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 35 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619378527168 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd BCD_ex:comb_3\|bcd:B0 " "Elaborating entity \"bcd\" for hierarchy \"BCD_ex:comb_3\|bcd:B0\"" { } { { "part4.v" "B0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619378527169 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "BCD_ex:comb_3\|W\[4\] " "Net \"BCD_ex:comb_3\|W\[4\]\" is missing source, defaulting to GND" { } { { "part4.v" "W\[4\]" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 28 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1619378527190 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1619378527190 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "4 " "4 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1619378528107 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[1\] GND " "Pin \"HEX1\[1\]\" is stuck at GND" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619378528206 "|part4|HEX1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[2\] GND " "Pin \"HEX1\[2\]\" is stuck at GND" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619378528206 "|part4|HEX1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[6\] VCC " "Pin \"HEX1\[6\]\" is stuck at VCC" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619378528206 "|part4|HEX1[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1619378528206 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619378528325 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528959 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1619378528959 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part5 24 " "Ignored 24 assignments for entity \"part5\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378528961 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1619378528961 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! 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DDIO, %3!d! PLL, %4!d! transceiver and %5!d! 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Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 60 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "395 " "Peak virtual memory: 395 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619378529262 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 14:22:09 2021 " "Processing ended: Sun Apr 25 14:22:09 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619378529262 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619378529262 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619378529262 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619378529262 ""} diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.map.rdb b/EE203/Noah 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"*******************************************************************" 0 0 "Design Software" 0 -1 1619378552695 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619378552695 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 14:22:32 2021 " "Processing started: Sun Apr 25 14:22:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619378552695 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1619378552695 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta part4 -c part4 " "Command: quartus_sta part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1619378552696 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: 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-name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552836 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619378552836 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "part5 24 " "Ignored 24 assignments for entity \"part5\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619378552838 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619378552838 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619378552965 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619378552965 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1619378553054 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1619378553055 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619378553515 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619378553516 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619378553516 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619378553517 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619378553517 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619378553517 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619378553519 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1619378553525 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619378553526 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378553529 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1619378553530 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378553533 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378553541 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378553542 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378553543 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378553543 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619378553547 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619378553588 ""} +{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Timing Analyzer" 0 -1 1619378553588 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619378554116 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619378554162 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619378554163 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619378554163 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619378554163 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554167 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554177 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554178 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554180 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554181 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554182 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619378554185 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619378554359 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619378554359 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619378554359 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619378554360 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554361 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554362 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554363 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554364 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619378554364 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619378555654 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619378555655 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 56 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 56 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "509 " "Peak virtual memory: 509 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619378555685 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 14:22:35 2021 " "Processing ended: Sun Apr 25 14:22:35 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619378555685 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619378555685 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619378555685 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619378555685 ""} diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.sta.rdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.sta.rdb new file mode 100644 index 0000000..a21849f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.sta.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.sta_cmp.6_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..a9019c9 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.tis_db_list.ddb b/EE203/Noah Woodlee/Lab2/part4/db/part4.tis_db_list.ddb new file mode 100644 index 0000000..73e5ec9 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..c0ca91b Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..835faa5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..26509af Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.tmw_info b/EE203/Noah Woodlee/Lab2/part4/db/part4.tmw_info new file mode 100644 index 0000000..9e8732a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:44 +start_analysis_synthesis:s:00:00:18-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:15-start_full_compilation +start_assembler:s:00:00:06-start_full_compilation +start_timing_analyzer:s:00:00:05-start_full_compilation diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.vpr.ammdb b/EE203/Noah Woodlee/Lab2/part4/db/part4.vpr.ammdb new file mode 100644 index 0000000..e397645 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..c96a6fd Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.ii_85c_slow.hsd b/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..ba3fa5d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.ii_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.tt_0c_slow.hsd b/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..090de61 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.tt_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.tt_85c_slow.hsd b/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..2d8ff11 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/db/part4.zippleback_io_sim_cache.tt_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part4/db/part4_partition_pins.json b/EE203/Noah Woodlee/Lab2/part4/db/part4_partition_pins.json new file mode 100644 index 0000000..76cce97 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/part4_partition_pins.json @@ -0,0 +1,89 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "HEX0[0]", + "strict" : false + }, + { + "name" : "HEX0[1]", + "strict" : false + }, + { + "name" : "HEX0[2]", + "strict" : false + }, + { + "name" : "HEX0[3]", + "strict" : false + }, + { + "name" : "HEX0[4]", + "strict" : false + }, + { + "name" : "HEX0[5]", + "strict" : false + }, + { + "name" : "HEX0[6]", + "strict" : false + }, + { + "name" : "HEX1[0]", + "strict" : false + }, + { + "name" : "HEX1[3]", + "strict" : false + }, + { + "name" : "HEX1[4]", + "strict" : false + }, + { + "name" : "HEX1[5]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[5]", + "strict" : false + }, + { + "name" : "SW[8]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[4]", + "strict" : false + }, + { + "name" : "SW[2]", + "strict" : false + }, + { + "name" : "SW[6]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + }, + { + "name" : "SW[7]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part4/db/prev_cmp_part4.qmsg b/EE203/Noah Woodlee/Lab2/part4/db/prev_cmp_part4.qmsg new file mode 100644 index 0000000..f3d0bc2 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/db/prev_cmp_part4.qmsg @@ -0,0 +1,68 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1618984937463 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1618984937463 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 01:02:17 2021 " "Processing started: Wed Apr 21 01:02:17 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1618984937463 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1618984937463 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1618984937464 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1618984937920 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1618984937920 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part4.v 6 6 " "Found 6 design units, including 6 entities, in source file part4.v" { { "Info" "ISGN_ENTITY_NAME" "1 bcd " "Found entity 1: bcd" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618984951340 ""} { "Info" "ISGN_ENTITY_NAME" "2 mux_2to1 " "Found entity 2: mux_2to1" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 13 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618984951340 ""} { "Info" "ISGN_ENTITY_NAME" "3 BCD_ex " "Found entity 3: BCD_ex" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618984951340 ""} { "Info" "ISGN_ENTITY_NAME" "4 adder " "Found entity 4: adder" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618984951340 ""} { "Info" "ISGN_ENTITY_NAME" "5 RippleCarryAdder " "Found entity 5: RippleCarryAdder" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 52 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618984951340 ""} { "Info" "ISGN_ENTITY_NAME" "6 part4 " "Found entity 6: part4" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 70 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1618984951340 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1618984951340 ""} +{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "part4.v(80) " "Verilog HDL Instantiation warning at part4.v(80): instance has no name" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 80 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1618984951341 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part4 " "Elaborating entity \"part4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1618984951435 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RippleCarryAdder RippleCarryAdder:R0 " "Elaborating entity \"RippleCarryAdder\" for hierarchy \"RippleCarryAdder:R0\"" { } { { "part4.v" "R0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1618984951468 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder RippleCarryAdder:R0\|adder:A0 " "Elaborating entity \"adder\" for hierarchy \"RippleCarryAdder:R0\|adder:A0\"" { } { { "part4.v" "A0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1618984951474 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BCD_ex BCD_ex:comb_3 " "Elaborating entity \"BCD_ex\" for hierarchy \"BCD_ex:comb_3\"" { } { { "part4.v" "comb_3" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1618984951478 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 part4.v(31) " "Verilog HDL assignment warning at part4.v(31): truncated value with size 32 to match size of target (1)" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1618984951479 "|part4|BCD_ex:comb_3"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_2to1 BCD_ex:comb_3\|mux_2to1:M0 " "Elaborating entity \"mux_2to1\" for hierarchy \"BCD_ex:comb_3\|mux_2to1:M0\"" { } { { "part4.v" "M0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 35 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1618984951486 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd BCD_ex:comb_3\|bcd:B0 " "Elaborating entity \"bcd\" for hierarchy \"BCD_ex:comb_3\|bcd:B0\"" { } { { "part4.v" "B0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1618984951489 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "BCD_ex:comb_3\|W\[4\] " "Net \"BCD_ex:comb_3\|W\[4\]\" is missing source, defaulting to GND" { } { { "part4.v" "W\[4\]" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 28 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1618984951505 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1618984951505 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "4 " "4 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1618984952414 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[1\] GND " "Pin \"HEX1\[1\]\" is stuck at GND" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1618984952526 "|part4|HEX1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[2\] GND " "Pin \"HEX1\[2\]\" is stuck at GND" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1618984952526 "|part4|HEX1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[6\] VCC " "Pin \"HEX1\[6\]\" is stuck at VCC" { } { { "part4.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1618984952526 "|part4|HEX1[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1618984952526 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1618984952642 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618984953271 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618984953271 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618984953271 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618984953271 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618984953271 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1618984953271 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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LCELL" 0 0 "Design Software" 0 -1 1618984953435 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1618984953435 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "42 " "Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1618984953577 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1618984953577 ""} { "Info" "ICUT_CUT_TM_LCELLS" "19 " "Implemented 19 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1618984953577 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1618984953577 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 60 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 60 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "393 " "Peak virtual memory: 393 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1618984953592 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 01:02:33 2021 " "Processing ended: Wed Apr 21 01:02:33 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1618984953592 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1618984953592 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1618984953592 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1618984953592 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1618984985926 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1618984985926 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 01:03:05 2021 " "Processing started: Wed Apr 21 01:03:05 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1618984985926 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618984985926 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off part4 -c part4 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618984985927 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618984986105 ""} +{ "Info" "0" "" "Project = part4" { } { } 0 0 "Project = part4" 0 0 "Fitter" 0 0 1618984986107 ""} +{ "Info" "0" "" "Revision = part4" { } { } 0 0 "Revision = part4" 0 0 "Fitter" 0 0 1618984986108 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1618984986260 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618984986260 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part4 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"part4\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618984986271 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618984986350 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618984986350 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1618984986758 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618984986772 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7P " "Device 10M08DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484A7G " "Device 10M16DAF484A7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7P " "Device 10M16DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484A7G " "Device 10M25DAF484A7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1618984986945 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618984986945 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 131 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618984986961 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618984986961 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 135 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618984986961 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 137 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618984986961 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 139 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618984986961 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 141 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618984986961 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 143 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618984986961 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/" { { 0 { 0 ""} 0 145 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1618984986961 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1618984986961 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1618984986963 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1618984986963 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1618984986963 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1618984986963 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1618984986967 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618984987670 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618984987671 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1618984987672 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1618984987673 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1618984987678 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1618984987678 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1618984987680 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1618984987688 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618984987688 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618984987689 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1618984987690 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1618984987691 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1618984987691 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1618984987691 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1618984987691 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1618984987692 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1618984987692 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618984987692 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1618984987741 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618984987741 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618984987742 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1618984987758 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618984990835 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618984990976 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618984991030 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618984991516 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618984991516 ""} diff --git a/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..402472e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a837f14 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +platform_setup.tcl +filelist.txt +DE10_LITE_Golden_Top.v diff --git a/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..3b32d96 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,429 @@ +proc ::setup_project {} { +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 09:47:48 June 12, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VERILOG_FILE DE10_LITE_Golden_Top.v +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..536fab3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/data/adu/17.0/Lite/Max10/Max_10_DE10_LITE/DE10_LITE_Golden_Top_project/", + "acds_version" : "Version 17.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part4/devkits/readme.txt b/EE203/Noah Woodlee/Lab2/part4/devkits/readme.txt new file mode 100644 index 0000000..15cc67e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/README b/EE203/Noah Woodlee/Lab2/part4/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.db_info b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.db_info new file mode 100644 index 0000000..857b901 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Wed Apr 21 01:16:27 2021 diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.ammdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.ammdb new file mode 100644 index 0000000..6248b34 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.cdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.cdb new file mode 100644 index 0000000..6d9f7c2 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.dfp b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.hdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.hdb new file mode 100644 index 0000000..78e5ab1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.logdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.rcfdb new file mode 100644 index 0000000..94f95f8 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.cdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.cdb new file mode 100644 index 0000000..52bc31e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.dpi b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.dpi new file mode 100644 index 0000000..3d6817f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..8debd50 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..bf230ae Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hdb new file mode 100644 index 0000000..7b5eeb2 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.kpt b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.kpt new file mode 100644 index 0000000..3014be3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.rrp.hdb b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.rrp.hdb new file mode 100644 index 0000000..68d38c1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/incremental_db/compiled_partitions/part4.rrp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.asm.rpt b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.asm.rpt new file mode 100644 index 0000000..0aa674e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for part4 +Sun Apr 25 14:22:30 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: part4.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sun Apr 25 14:22:30 2021 ; +; Revision Name ; part4 ; +; Top-level Entity Name ; part4 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------------------------+ +; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/output_files/part4.sof ; ++-----------------------------------------------------------------------------------------------+ + + ++-------------------------------------+ +; Assembler Device Options: part4.sof ; ++----------------+--------------------+ +; Option ; Setting ; ++----------------+--------------------+ +; JTAG usercode ; 0x00273611 ; +; Checksum ; 0x00273611 ; ++----------------+--------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 14:22:25 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 356 megabytes + Info: Processing ended: Sun Apr 25 14:22:30 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.done b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.done new file mode 100644 index 0000000..7f8c72f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.done @@ -0,0 +1 @@ +Sun Apr 25 14:22:35 2021 diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.rpt b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.rpt new file mode 100644 index 0000000..54ec560 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.rpt @@ -0,0 +1,1361 @@ +Fitter report for part4 +Sun Apr 25 14:22:23 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sun Apr 25 14:22:23 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part4 ; +; Top-level Entity Name ; part4 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 20 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 20 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 23 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.4% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; HEX2[0] ; PIN_B20 ; QSF Assignment ; +; Location ; ; ; HEX2[1] ; PIN_A20 ; QSF Assignment ; +; Location ; ; ; HEX2[2] ; PIN_B19 ; QSF Assignment ; +; Location ; ; ; HEX2[3] ; PIN_A21 ; QSF Assignment ; +; Location ; ; ; HEX2[4] ; PIN_B21 ; QSF Assignment ; +; Location ; ; ; HEX2[5] ; PIN_C22 ; QSF Assignment ; +; Location ; ; ; HEX2[6] ; PIN_B22 ; QSF Assignment ; +; Location ; ; ; HEX3[0] ; PIN_F21 ; QSF Assignment ; +; Location ; ; ; HEX3[1] ; PIN_E22 ; QSF Assignment ; +; Location ; ; ; HEX3[2] ; PIN_E21 ; QSF Assignment ; +; Location ; ; ; HEX3[3] ; PIN_C19 ; QSF Assignment ; +; Location ; ; ; HEX3[4] ; PIN_C20 ; QSF Assignment ; +; Location ; ; ; HEX3[5] ; PIN_D19 ; QSF Assignment ; +; Location ; ; ; HEX3[6] ; PIN_E17 ; QSF Assignment ; +; Location ; ; ; LEDR[0] ; PIN_A8 ; QSF Assignment ; +; Location ; ; ; LEDR[1] ; PIN_A9 ; QSF Assignment ; +; Location ; ; ; LEDR[2] ; PIN_A10 ; QSF Assignment ; +; Location ; ; ; LEDR[3] ; PIN_B10 ; QSF Assignment ; +; Location ; ; ; LEDR[4] ; PIN_D13 ; QSF Assignment ; +; Location ; ; ; LEDR[5] ; PIN_C13 ; QSF Assignment ; +; Location ; ; ; LEDR[6] ; PIN_E14 ; QSF Assignment ; +; Location ; ; ; LEDR[7] ; PIN_D14 ; QSF Assignment ; +; Location ; ; ; LEDR[8] ; PIN_A11 ; QSF Assignment ; +; Location ; ; ; LEDR[9] ; PIN_B11 ; QSF Assignment ; +; Location ; ; ; SW[9] ; PIN_F15 ; QSF Assignment ; ++----------+----------------+--------------+------------+---------------+----------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 85 ) ; 0.00 % ( 0 / 85 ) ; 0.00 % ( 0 / 85 ) ; +; -- Achieved ; 0.00 % ( 0 / 85 ) ; 0.00 % ( 0 / 85 ) ; 0.00 % ( 0 / 85 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 69 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/output_files/part4.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 20 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 20 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 8 ; +; -- 3 input functions ; 7 ; +; -- <=2 input functions ; 5 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 20 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 3 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 23 / 360 ( 6 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.3% / 0.5% / 0.2% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 106 ; +; Average fan-out ; 1.25 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 20 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 20 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 8 ; 0 ; +; -- 3 input functions ; 7 ; 0 ; +; -- <=2 input functions ; 5 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 20 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 3 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 23 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 112 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 9 ; 0 ; +; -- Output Ports ; 14 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; C10 ; 7 ; 51 ; 54 ; 28 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[2] ; D12 ; 7 ; 51 ; 54 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[3] ; C12 ; 7 ; 54 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[4] ; A12 ; 7 ; 54 ; 54 ; 21 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[5] ; B12 ; 7 ; 49 ; 54 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[6] ; A13 ; 7 ; 54 ; 54 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[7] ; A14 ; 7 ; 58 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[8] ; B14 ; 7 ; 56 ; 54 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; HEX0[0] ; C14 ; 7 ; 58 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[1] ; E15 ; 7 ; 74 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[2] ; C15 ; 7 ; 60 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[3] ; C16 ; 7 ; 62 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[4] ; E16 ; 7 ; 74 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[5] ; D17 ; 7 ; 74 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[6] ; C17 ; 7 ; 74 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[0] ; C18 ; 7 ; 69 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[1] ; D18 ; 6 ; 78 ; 49 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[2] ; E18 ; 6 ; 78 ; 49 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[3] ; B16 ; 7 ; 60 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[4] ; A17 ; 7 ; 64 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[5] ; A18 ; 7 ; 66 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[6] ; B17 ; 7 ; 69 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 2 / 60 ( 3 % ) ; 2.5V ; -- ; +; 7 ; 21 / 52 ( 40 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; SW[4] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 433 ; 7 ; SW[6] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 425 ; 7 ; SW[7] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; HEX1[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A18 ; 405 ; 7 ; HEX1[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; SW[5] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; SW[8] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; HEX1[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B17 ; 402 ; 7 ; HEX1[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; SW[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C15 ; 418 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C16 ; 416 ; 7 ; HEX0[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C17 ; 391 ; 7 ; HEX0[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C18 ; 400 ; 7 ; HEX1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; HEX0[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D18 ; 385 ; 6 ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 388 ; 7 ; HEX0[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; HEX0[0] ; Incomplete set of assignments ; +; HEX0[1] ; Incomplete set of assignments ; +; HEX0[2] ; Incomplete set of assignments ; +; HEX0[3] ; Incomplete set of assignments ; +; HEX0[4] ; Incomplete set of assignments ; +; HEX0[5] ; Incomplete set of assignments ; +; HEX0[6] ; Incomplete set of assignments ; +; HEX1[0] ; Incomplete set of assignments ; +; HEX1[1] ; Incomplete set of assignments ; +; HEX1[2] ; Incomplete set of assignments ; +; HEX1[3] ; Incomplete set of assignments ; +; HEX1[4] ; Incomplete set of assignments ; +; HEX1[5] ; Incomplete set of assignments ; +; HEX1[6] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[8] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-------------------------------------+------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-------------------------------------+------------------+--------------+ +; |part4 ; 20 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 23 ; 0 ; 20 (1) ; 0 (0) ; 0 (0) ; 0 ; |part4 ; part4 ; work ; +; |BCD_ex:comb_3| ; 12 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (1) ; 0 (0) ; 0 (0) ; 0 ; |part4|BCD_ex:comb_3 ; BCD_ex ; work ; +; |bcd:B0| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; |part4|BCD_ex:comb_3|bcd:B0 ; bcd ; work ; +; |mux_2to1:M0| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; |part4|BCD_ex:comb_3|mux_2to1:M0 ; mux_2to1 ; work ; +; |RippleCarryAdder:R0| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; |part4|RippleCarryAdder:R0 ; RippleCarryAdder ; work ; +; |adder:A0| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part4|RippleCarryAdder:R0|adder:A0 ; adder ; work ; +; |adder:A1| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part4|RippleCarryAdder:R0|adder:A1 ; adder ; work ; +; |adder:A2| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; |part4|RippleCarryAdder:R0|adder:A2 ; adder ; work ; +; |adder:A3| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; |part4|RippleCarryAdder:R0|adder:A3 ; adder ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-------------------------------------+------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++--------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------------+-------------------+---------+ +; SW[1] ; ; ; +; - RippleCarryAdder:R0|adder:A1|x1 ; 0 ; 6 ; +; - RippleCarryAdder:R0|adder:A1|COUT~0 ; 0 ; 6 ; +; - BCD_ex:comb_3|mux_2to1:M0|OUT[3]~1 ; 0 ; 6 ; +; SW[5] ; ; ; +; - RippleCarryAdder:R0|adder:A1|x1 ; 0 ; 6 ; +; - RippleCarryAdder:R0|adder:A1|COUT~0 ; 0 ; 6 ; +; - BCD_ex:comb_3|mux_2to1:M0|OUT[3]~1 ; 0 ; 6 ; +; SW[8] ; ; ; +; - RippleCarryAdder:R0|adder:A0|COUT~0 ; 1 ; 6 ; +; - RippleCarryAdder:R0|adder:A0|x1~0 ; 1 ; 6 ; +; SW[0] ; ; ; +; - RippleCarryAdder:R0|adder:A0|COUT~0 ; 0 ; 6 ; +; - RippleCarryAdder:R0|adder:A0|x1~0 ; 0 ; 6 ; +; SW[4] ; ; ; +; - RippleCarryAdder:R0|adder:A0|COUT~0 ; 0 ; 6 ; +; - RippleCarryAdder:R0|adder:A0|x1~0 ; 0 ; 6 ; +; SW[2] ; ; ; +; - RippleCarryAdder:R0|adder:A2|x0 ; 0 ; 6 ; +; - RippleCarryAdder:R0|adder:A3|x1 ; 0 ; 6 ; +; SW[6] ; ; ; +; - RippleCarryAdder:R0|adder:A2|x0 ; 0 ; 6 ; +; - RippleCarryAdder:R0|adder:A3|x1 ; 0 ; 6 ; +; SW[3] ; ; ; +; - RippleCarryAdder:R0|adder:A3|x1~2 ; 0 ; 6 ; +; SW[7] ; ; ; +; - RippleCarryAdder:R0|adder:A3|x1~2 ; 1 ; 6 ; ++--------------------------------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 28 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 0 / 5,382 ( 0 % ) ; +; C4 interconnects ; 23 / 106,704 ( < 1 % ) ; +; Direct links ; 4 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 9 / 49,760 ( < 1 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 2 / 5,406 ( < 1 % ) ; +; R4 interconnects ; 31 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 6.67) ; Number of LABs (Total = 3) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 6.67) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 4.00) ; Number of LABs (Total = 3) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 4.00) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 23 ; 23 ; 0 ; 0 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 9 ; 14 ; 0 ; 9 ; 0 ; 0 ; 14 ; 0 ; 23 ; 23 ; 23 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 23 ; 0 ; 0 ; 23 ; 23 ; 0 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 23 ; 23 ; 14 ; 9 ; 23 ; 14 ; 23 ; 23 ; 9 ; 23 ; 0 ; 0 ; 0 ; 23 ; 23 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device 10M50DAF484C6GES for design "part4" +Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'. +Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds. +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/output_files/part4.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 34 warnings + Info: Peak virtual memory: 1083 megabytes + Info: Processing ended: Sun Apr 25 14:22:23 2021 + Info: Elapsed time: 00:00:13 + Info: Total CPU time (on all processors): 00:00:17 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/output_files/part4.fit.smsg. + + diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.smsg b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.summary b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.summary new file mode 100644 index 0000000..f2f57e3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Sun Apr 25 14:22:23 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part4 +Top-level Entity Name : part4 +Family : MAX 10 +Device : 10M50DAF484C6GES +Timing Models : Preliminary +Total logic elements : 20 / 49,760 ( < 1 % ) + Total combinational functions : 20 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 23 / 360 ( 6 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.flow.rpt b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.flow.rpt new file mode 100644 index 0000000..2576a85 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.flow.rpt @@ -0,0 +1,129 @@ +Flow report for part4 +Sun Apr 25 14:22:35 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sun Apr 25 14:22:30 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part4 ; +; Top-level Entity Name ; part4 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 20 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 20 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 23 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/25/2021 14:21:54 ; +; Main task ; Compilation ; +; Revision Name ; part4 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 164639278517.161937851407219 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part5 ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 388 MB ; 00:00:31 ; +; Fitter ; 00:00:13 ; 1.0 ; 1083 MB ; 00:00:16 ; +; Assembler ; 00:00:05 ; 1.0 ; 356 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:03 ; 1.0 ; 509 MB ; 00:00:03 ; +; Total ; 00:00:35 ; -- ; -- ; 00:00:55 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+-------------------+------------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+-------------------+------------------+------------+----------------+ +; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; ++----------------------+-------------------+------------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 +quartus_fit --read_settings_files=off --write_settings_files=off part4 -c part4 +quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4 +quartus_sta part4 -c part4 + + + diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.jdi b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.jdi new file mode 100644 index 0000000..178f1db --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.map.rpt b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.map.rpt new file mode 100644 index 0000000..bd152ae --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.map.rpt @@ -0,0 +1,418 @@ +Analysis & Synthesis report for part4 +Sun Apr 25 14:22:09 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Multiplexer Restructuring Statistics (Restructuring Performed) + 10. Port Connectivity Checks: "BCD_ex:comb_3|bcd:B0" + 11. Port Connectivity Checks: "BCD_ex:comb_3|mux_2to1:M0" + 12. Port Connectivity Checks: "BCD_ex:comb_3" + 13. Port Connectivity Checks: "RippleCarryAdder:R0" + 14. Post-Synthesis Netlist Statistics for Top Partition + 15. Elapsed Time Per Partition + 16. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sun Apr 25 14:22:09 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part4 ; +; Top-level Entity Name ; part4 ; +; Family ; MAX 10 ; +; Total logic elements ; 19 ; +; Total combinational functions ; 19 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 23 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C6GES ; ; +; Top-level entity name ; part4 ; part4 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; part4.v ; yes ; User Verilog HDL File ; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v ; ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+------------------------------------+ +; Estimated Total logic elements ; 19 ; +; ; ; +; Total combinational functions ; 19 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 8 ; +; -- 3 input functions ; 7 ; +; -- <=2 input functions ; 4 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 19 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 23 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; BCD_ex:comb_3|mux_2to1:M0|OUT[2]~0 ; +; Maximum fan-out ; 7 ; +; Total fan-out ; 95 ; +; Average fan-out ; 1.46 ; ++---------------------------------------------+------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-------------------------------------+------------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-------------------------------------+------------------+--------------+ +; |part4 ; 19 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 ; 0 ; 0 ; |part4 ; part4 ; work ; +; |BCD_ex:comb_3| ; 12 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part4|BCD_ex:comb_3 ; BCD_ex ; work ; +; |bcd:B0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part4|BCD_ex:comb_3|bcd:B0 ; bcd ; work ; +; |mux_2to1:M0| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part4|BCD_ex:comb_3|mux_2to1:M0 ; mux_2to1 ; work ; +; |RippleCarryAdder:R0| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part4|RippleCarryAdder:R0 ; RippleCarryAdder ; work ; +; |adder:A0| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part4|RippleCarryAdder:R0|adder:A0 ; adder ; work ; +; |adder:A1| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part4|RippleCarryAdder:R0|adder:A1 ; adder ; work ; +; |adder:A2| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part4|RippleCarryAdder:R0|adder:A2 ; adder ; work ; +; |adder:A3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part4|RippleCarryAdder:R0|adder:A3 ; adder ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-------------------------------------+------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+ +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |part4|BCD_ex:comb_3|bcd:B0|OUT[3] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "BCD_ex:comb_3|bcd:B0" ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; IN ; Input ; Warning ; Input port expression (5 bits) is wider than the input port (4 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "BCD_ex:comb_3|mux_2to1:M0" ; ++------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; IN1 ; Input ; Warning ; Input port expression (5 bits) is wider than the input port (4 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; IN2 ; Input ; Warning ; Input port expression (5 bits) is wider than the input port (4 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; OUT ; Output ; Warning ; Output or bidir port (4 bits) is smaller than the port expression (5 bits) it drives. The 1 most-significant bit(s) in the port expression will be connected to GND. ; ++------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "BCD_ex:comb_3" ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SW ; Input ; Warning ; Input port expression (5 bits) is wider than the input port (4 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; ++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "RippleCarryAdder:R0" ; ++------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; COUT ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; IN1 ; Input ; Warning ; Input port expression (4 bits) is smaller than the input port (5 bits) it drives. Extra input bit(s) "IN1[4..4]" will be connected to GND. ; +; IN2 ; Input ; Warning ; Input port expression (4 bits) is smaller than the input port (5 bits) it drives. Extra input bit(s) "IN2[4..4]" will be connected to GND. ; ++------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 23 ; +; cycloneiii_lcell_comb ; 22 ; +; normal ; 22 ; +; 0 data inputs ; 2 ; +; 1 data inputs ; 1 ; +; 2 data inputs ; 4 ; +; 3 data inputs ; 7 ; +; 4 data inputs ; 8 ; +; ; ; +; Max LUT depth ; 6.00 ; +; Average LUT depth ; 4.94 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 14:21:54 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 6 design units, including 6 entities, in source file part4.v + Info (12023): Found entity 1: bcd File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 1 + Info (12023): Found entity 2: mux_2to1 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 13 + Info (12023): Found entity 3: BCD_ex File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 22 + Info (12023): Found entity 4: adder File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 39 + Info (12023): Found entity 5: RippleCarryAdder File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 52 + Info (12023): Found entity 6: part4 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 70 +Critical Warning (10846): Verilog HDL Instantiation warning at part4.v(80): instance has no name File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 80 +Info (12127): Elaborating entity "part4" for the top level hierarchy +Info (12128): Elaborating entity "RippleCarryAdder" for hierarchy "RippleCarryAdder:R0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 78 +Info (12128): Elaborating entity "adder" for hierarchy "RippleCarryAdder:R0|adder:A0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 60 +Info (12128): Elaborating entity "BCD_ex" for hierarchy "BCD_ex:comb_3" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 80 +Warning (10230): Verilog HDL assignment warning at part4.v(31): truncated value with size 32 to match size of target (1) File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 31 +Info (12128): Elaborating entity "mux_2to1" for hierarchy "BCD_ex:comb_3|mux_2to1:M0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 35 +Info (12128): Elaborating entity "bcd" for hierarchy "BCD_ex:comb_3|bcd:B0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 36 +Warning (12011): Net is missing source, defaulting to GND + Warning (12110): Net "BCD_ex:comb_3|W[4]" is missing source, defaulting to GND File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 28 +Warning (12241): 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "HEX1[1]" is stuck at GND File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 72 + Warning (13410): Pin "HEX1[2]" is stuck at GND File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 72 + Warning (13410): Pin "HEX1[6]" is stuck at VCC File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part4/part4.v Line: 72 +Info (286030): Timing-Driven Synthesis is running +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 42 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 9 input pins + Info (21059): Implemented 14 output pins + Info (21061): Implemented 19 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 60 warnings + Info: Peak virtual memory: 395 megabytes + Info: Processing ended: Sun Apr 25 14:22:09 2021 + Info: Elapsed time: 00:00:15 + Info: Total CPU time (on all processors): 00:00:32 + + diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.map.summary b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.map.summary new file mode 100644 index 0000000..833508a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Sun Apr 25 14:22:09 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part4 +Top-level Entity Name : part4 +Family : MAX 10 +Total logic elements : 19 + Total combinational functions : 19 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 23 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.pin b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.pin new file mode 100644 index 0000000..2c96e56 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2020 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +CHIP "part4" ASSIGNED TO AN: 10M50DAF484C6GES + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +SW[4] : A12 : input : 2.5 V : : 7 : Y +SW[6] : A13 : input : 2.5 V : : 7 : Y +SW[7] : A14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +HEX1[4] : A17 : output : 2.5 V : : 7 : Y +HEX1[5] : A18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +SW[5] : B12 : input : 2.5 V : : 7 : Y +GND : B13 : gnd : : : : +SW[8] : B14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +HEX1[3] : B16 : output : 2.5 V : : 7 : Y +HEX1[6] : B17 : output : 2.5 V : : 7 : Y +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[0] : C10 : input : 2.5 V : : 7 : Y +SW[1] : C11 : input : 2.5 V : : 7 : Y +SW[3] : C12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +HEX0[0] : C14 : output : 2.5 V : : 7 : Y +HEX0[2] : C15 : output : 2.5 V : : 7 : Y +HEX0[3] : C16 : output : 2.5 V : : 7 : Y +HEX0[6] : C17 : output : 2.5 V : : 7 : Y +HEX1[0] : C18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +SW[2] : D12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +HEX0[5] : D17 : output : 2.5 V : : 7 : Y +HEX1[1] : D18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +HEX0[1] : E15 : output : 2.5 V : : 7 : Y +HEX0[4] : E16 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +HEX1[2] : E18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.pof b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.pof new file mode 100644 index 0000000..f49628f Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.pof differ diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sld b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sof b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sof new file mode 100644 index 0000000..f3e2153 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sof differ diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sta.rpt b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sta.rpt new file mode 100644 index 0000000..e23b4c9 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sta.rpt @@ -0,0 +1,569 @@ +Timing Analyzer report for part4 +Sun Apr 25 14:22:35 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; part4 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.03 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 1.2% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 9 ; 9 ; +; Unconstrained Input Port Paths ; 99 ; 99 ; +; Unconstrained Output Ports ; 11 ; 11 ; +; Unconstrained Output Port Paths ; 99 ; 99 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 14:22:32 2021 +Info: Command: quartus_sta part4 -c part4 +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'. +Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 56 warnings + Info: Peak virtual memory: 509 megabytes + Info: Processing ended: Sun Apr 25 14:22:35 2021 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sta.summary b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/output_files/part4.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/Lab2/part4/part4.qpf b/EE203/Noah Woodlee/Lab2/part4/part4.qpf new file mode 100644 index 0000000..fa7f1d9 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/part4.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 01:15:20 April 21, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "01:15:20 April 21, 2021" + +# Revisions + +PROJECT_REVISION = "part4" diff --git a/EE203/Noah Woodlee/Lab2/part4/part4.qsf b/EE203/Noah Woodlee/Lab2/part4/part4.qsf new file mode 100644 index 0000000..4bd94dd --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/part4.qsf @@ -0,0 +1,108 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 01:15:20 April 21, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part4_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part4 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:15:20 APRIL 21, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name VERILOG_FILE part4.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part4/part4.qsf.bak b/EE203/Noah Woodlee/Lab2/part4/part4.qsf.bak new file mode 100644 index 0000000..cf40f32 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/part4.qsf.bak @@ -0,0 +1,47 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 01:15:20 April 21, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part4_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part4 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:15:20 APRIL 21, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part4/part4.qws b/EE203/Noah Woodlee/Lab2/part4/part4.qws new file mode 100644 index 0000000..ffd6e07 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part4/part4.qws differ diff --git a/EE203/Noah Woodlee/Lab2/part4/part4.v b/EE203/Noah Woodlee/Lab2/part4/part4.v new file mode 100644 index 0000000..fa2e6a2 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/part4.v @@ -0,0 +1,81 @@ +module bcd(IN,OUT); + input [3:0] IN; + output [6:0] OUT; + + assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000): + (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010): + (IN[0]? 7'b0010_010:7'b0011_001)): + (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100): + (IN[0]? 7'b1111_001:7'b1000_000))); + +endmodule + +module mux_2to1 (IN1, IN2, S, OUT); + input[3:0]IN1, IN2; + input S; + output [3:0]OUT; + + assign OUT=S? IN2:IN1; + +endmodule + +module BCD_ex(SW, D0, D1); + input [3:0] SW; + output [6:0] D0, D1; + + wire z; + wire [4:0] A, V; + wire [4:0] W; + + assign V=SW[3:0]; + assign z = V[4:0] > 9? 1:0; + assign D1 =z? 7'b1111_001:7'b1000_000; + + assign A=V[3:0]-4'b1010; + mux_2to1 M0 (V, A, z, W); + bcd B0 (W, D0); +endmodule + +module adder(SUM, COUT, A, B, CIN); + input A, B, CIN; + output SUM, COUT; + + wire x; + + xor x0(x, A, B); + xor x1(SUM, x, CIN); + + assign COUT = x? CIN: B; + +endmodule + +module RippleCarryAdder(SUM, COUT, IN1, IN2, CIN); + input [4:0] IN1, IN2; + input CIN; + output COUT; + output [3:0] SUM; + + wire C0, C1, C2, C3; + + adder A0(SUM[0], C0, IN1[0], IN2[0], CIN); + adder A1(SUM[1], C1, IN1[1], IN2[1], C0); + adder A2(SUM[2], C2, IN1[2], IN2[2], C1); + adder A3(SUM[3], C3, IN1[3], IN2[3], C2); + + assign COUT = C3; + +endmodule + +// if the inputs excede decimal value 9, result is unknown +module part4(SW, HEX0, HEX1); + input [8:0] SW; + output [6:0] HEX0, HEX1; + + wire COUT; + wire [3:0] U; + + // Add the decimal number's 0-9 + RippleCarryAdder R0(U, COUT, SW[3:0], SW[7:4], SW[8]); + // send the output along with carry to 7-segment display + BCD_ex({COUT, U}, HEX0, HEX1); +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part4/part4.v.bak b/EE203/Noah Woodlee/Lab2/part4/part4.v.bak new file mode 100644 index 0000000..634ee85 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part4/part4.v.bak @@ -0,0 +1,37 @@ +module bcd(IN,OUT); + input [3:0] IN; + output [6:0] OUT; + + assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000): + (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010): + (IN[0]? 7'b0010_010:7'b0011_001)): + (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100): + (IN[0]? 7'b1111_001:7'b1000_000))); + +endmodule + +module mux_2to1 (IN1, IN2, S, OUT); + input[3:0]IN1, IN2; + input S; + output [3:0]OUT; + + assign OUT=S? IN2:IN1; + +endmodule + +module part2(SW, HEX0, HEX1); + input [3:0] SW; + output [6:0] HEX0, HEX1; + + wire z; + wire [3:0] A, V; + wire [3:0] W; + + assign V=SW[3:0]; + assign z = V[3:0] > 9? 1:0; + assign HEX1 =z? 7'b1111_001:7'b1000_000; + + assign A=V[3:0]-4'b1010; + mux_2to1 M0 (V, A, z, W); + bcd B0 (W, HEX0); +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part5.v b/EE203/Noah Woodlee/Lab2/part5.v new file mode 100644 index 0000000..b27e0e6 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5.v @@ -0,0 +1,37 @@ +module bcd(IN,OUT); + input [3:0] IN; + output [6:0] OUT; + + assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000): + (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010): + (IN[0]? 7'b0010_010:7'b0011_001)): + (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100): + (IN[0]? 7'b1111_001:7'b1000_000))); + +endmodule + +module part5(SW, HEX0, HEX1); + input [8:0] SW; + output [6:0] HEX0, HEX1; + + reg [4:0] U; + + always@(*) + + begin + U = SW[3:0] + SW[7:4] + SW[8]; + if (U > 9) begin + U[3:0] = U[3:0]-10; + U[4] = 1; + end + + else begin + U[4] = 0; + end + + end + + bcd b0(U[3:0], HEX0); + bcd b1(U[4], HEX1); + +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.(0).cnf.cdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.(0).cnf.cdb new file mode 100644 index 0000000..8c7e324 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.(0).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.(0).cnf.hdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.(0).cnf.hdb new file mode 100644 index 0000000..dbecc1c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.(0).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.(1).cnf.cdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.(1).cnf.cdb new file mode 100644 index 0000000..0745dfd Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.(1).cnf.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.(1).cnf.hdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.(1).cnf.hdb new file mode 100644 index 0000000..a37eac4 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.(1).cnf.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.asm.qmsg b/EE203/Noah Woodlee/Lab2/part5/db/part5.asm.qmsg new file mode 100644 index 0000000..7038d10 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619383456627 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619383456628 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 15:44:16 2021 " "Processing started: Sun Apr 25 15:44:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619383456628 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619383456628 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part5 -c part5 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part5 -c part5" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619383456629 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619383457148 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619383460110 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619383460211 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "360 " "Peak virtual memory: 360 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619383461571 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 15:44:21 2021 " "Processing ended: Sun Apr 25 15:44:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619383461571 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619383461571 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619383461571 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619383461571 ""} diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.asm.rdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.asm.rdb new file mode 100644 index 0000000..38dab9d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.asm.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.asm_labs.ddb b/EE203/Noah Woodlee/Lab2/part5/db/part5.asm_labs.ddb new file mode 100644 index 0000000..c6cc4df Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.asm_labs.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.cbx.xml b/EE203/Noah Woodlee/Lab2/part5/db/part5.cbx.xml new file mode 100644 index 0000000..70328de --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.bpm b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.bpm new file mode 100644 index 0000000..c0e906c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.cdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.cdb new file mode 100644 index 0000000..f8eabc3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.hdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.hdb new file mode 100644 index 0000000..b24839a Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.idb b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.idb new file mode 100644 index 0000000..47abffc Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.idb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.logdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.logdb new file mode 100644 index 0000000..bccc510 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.logdb @@ -0,0 +1,65 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;23;23;0;0;23;23;0;0;0;0;0;0;14;0;0;0;9;14;0;9;0;0;14;0;23;23;23;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,23;0;0;23;23;0;0;23;23;23;23;23;23;9;23;23;23;14;9;23;14;23;23;9;23;0;0;0;23;23, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.rdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.rdb new file mode 100644 index 0000000..df6b971 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp_merge.kpt b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp_merge.kpt new file mode 100644 index 0000000..76d26a1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.cmp_merge.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.db_info b/EE203/Noah Woodlee/Lab2/part5/db/part5.db_info new file mode 100644 index 0000000..56edd16 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sun Apr 25 15:43:08 2021 diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.fit.qmsg b/EE203/Noah Woodlee/Lab2/part5/db/part5.fit.qmsg new file mode 100644 index 0000000..2f5c767 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.fit.qmsg @@ -0,0 +1,52 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1619383438863 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619383438864 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "part5 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"part5\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619383438876 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619383438980 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619383438980 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1619383439421 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619383439446 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7P " "Device 10M08DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484A7G " "Device 10M16DAF484A7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7P " "Device 10M16DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484A7G " "Device 10M25DAF484A7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619383439669 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 129 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 131 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 135 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 137 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 139 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 141 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 143 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1619383439690 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619383439692 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619383439692 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619383439692 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619383439692 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1619383439698 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part5.sdc " "Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1619383440494 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1619383440497 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1619383440512 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1619383440516 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1619383440530 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1619383440530 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1619383440534 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1619383440547 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619383440547 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619383440548 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619383440549 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619383440550 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1619383440551 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1619383440551 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1619383440551 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1619383440551 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1619383440552 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619383440552 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1619383440599 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383440601 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1619383440625 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619383443979 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383444137 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619383444207 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619383444767 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383444767 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619383445585 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X56_Y44 X66_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54" { } { { "loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54"} { { 12 { 0 ""} 56 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1619383449375 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619383449375 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1619383449642 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1619383449642 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1619383449642 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383449645 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1619383449973 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619383449993 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619383450512 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619383450512 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619383451060 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383451765 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1619383451973 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg " "Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619383452183 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 32 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1082 " "Peak virtual memory: 1082 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619383452839 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 15:44:12 2021 " "Processing ended: Sun Apr 25 15:44:12 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619383452839 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619383452839 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619383452839 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619383452839 ""} diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.hier_info b/EE203/Noah Woodlee/Lab2/part5/db/part5.hier_info new file mode 100644 index 0000000..17ea7c8 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.hier_info @@ -0,0 +1,116 @@ +|part5 +SW[0] => Add0.IN8 +SW[1] => Add0.IN7 +SW[2] => Add0.IN6 +SW[3] => Add0.IN5 +SW[4] => Add0.IN4 +SW[5] => Add0.IN3 +SW[6] => Add0.IN2 +SW[7] => Add0.IN1 +SW[8] => Add1.IN10 +HEX0[0] << bcd:b0.port1 +HEX0[1] << bcd:b0.port1 +HEX0[2] << bcd:b0.port1 +HEX0[3] << bcd:b0.port1 +HEX0[4] << bcd:b0.port1 +HEX0[5] << bcd:b0.port1 +HEX0[6] << bcd:b0.port1 +HEX1[0] << bcd:b1.port1 +HEX1[1] << bcd:b1.port1 +HEX1[2] << bcd:b1.port1 +HEX1[3] << bcd:b1.port1 +HEX1[4] << bcd:b1.port1 +HEX1[5] << bcd:b1.port1 +HEX1[6] << bcd:b1.port1 + + +|part5|bcd:b0 +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAA +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.DATAA +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +OUT[0] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[4] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[5] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[6] <= OUT.DB_MAX_OUTPUT_PORT_TYPE + + +|part5|bcd:b1 +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAA +IN[0] => OUT.DATAB +IN[0] => OUT.DATAB +IN[0] => OUT.DATAA +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.OUTPUTSELECT +IN[1] => OUT.DATAA +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[2] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +IN[3] => OUT.OUTPUTSELECT +OUT[0] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[1] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[2] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[3] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[4] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[5] <= OUT.DB_MAX_OUTPUT_PORT_TYPE +OUT[6] <= OUT.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.hif b/EE203/Noah Woodlee/Lab2/part5/db/part5.hif new file mode 100644 index 0000000..214cac6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.hif differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.html b/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.html new file mode 100644 index 0000000..046fbe0 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.html @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
b14303733300000
b04000700000000
diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.rdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.rdb new file mode 100644 index 0000000..6919aa3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.txt b/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.txt new file mode 100644 index 0000000..09234aa --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.lpc.txt @@ -0,0 +1,8 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; b1 ; 4 ; 3 ; 0 ; 3 ; 7 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; b0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map.ammdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.ammdb new file mode 100644 index 0000000..790b913 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map.bpm b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.bpm new file mode 100644 index 0000000..2a693fb Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.bpm differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map.cdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.cdb new file mode 100644 index 0000000..c796bfa Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map.hdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.hdb new file mode 100644 index 0000000..bcfecd3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map.kpt b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.kpt new file mode 100644 index 0000000..4e0283a Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map.logdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map.qmsg b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.qmsg new file mode 100644 index 0000000..e7b50cc --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.qmsg @@ -0,0 +1,17 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619383418085 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619383418087 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 15:43:37 2021 " "Processing started: Sun Apr 25 15:43:37 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619383418087 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619383418087 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619383418088 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619383418598 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619383418598 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part5.v 2 2 " "Found 2 design units, including 2 entities, in source file part5.v" { { "Info" "ISGN_ENTITY_NAME" "1 bcd " "Found entity 1: bcd" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619383433499 ""} { "Info" "ISGN_ENTITY_NAME" "2 part5 " "Found entity 2: part5" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v" 13 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619383433499 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619383433499 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "part5 " "Elaborating entity \"part5\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619383433601 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 part5.v(24) " "Verilog HDL assignment warning at part5.v(24): truncated value with size 32 to match size of target (4)" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1619383433619 "|part5"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd bcd:b0 " "Elaborating entity \"bcd\" for hierarchy \"bcd:b0\"" { } { { "part5.v" "b0" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v" 34 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619383433626 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1619383434433 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[1\] GND " "Pin \"HEX1\[1\]\" is stuck at GND" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619383434474 "|part5|HEX1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[2\] GND " "Pin \"HEX1\[2\]\" is stuck at GND" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619383434474 "|part5|HEX1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[6\] VCC " "Pin \"HEX1\[6\]\" is stuck at VCC" { } { { "part5.v" "" { Text "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619383434474 "|part5|HEX1[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1619383434474 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619383434601 ""} +{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435294 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! 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was ignored" 0 0 "Design Software" 0 -1 1619383435295 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435295 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383435295 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1619383435295 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! 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Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 57 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619383435624 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 15:43:55 2021 " "Processing ended: Sun Apr 25 15:43:55 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619383435624 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619383435624 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619383435624 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619383435624 ""} diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map.rdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.rdb new file mode 100644 index 0000000..7a5aec0 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.map.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.cdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.cdb new file mode 100644 index 0000000..63850db Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.hdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.hdb new file mode 100644 index 0000000..1b024f1 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.logdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.pre_map.hdb b/EE203/Noah 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new file mode 100644 index 0000000..7d39add Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.sld_design_entry_dsc.sci differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.smart_action.txt b/EE203/Noah Woodlee/Lab2/part5/db/part5.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.sta.qmsg b/EE203/Noah Woodlee/Lab2/part5/db/part5.sta.qmsg new file mode 100644 index 0000000..4fd87b8 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.sta.qmsg @@ -0,0 +1,52 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619383464157 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { 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Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1619383464450 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1619383464450 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619383464581 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619383464582 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619383464675 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619383464675 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part5.sdc " "Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619383465153 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619383465154 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619383465157 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619383465157 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619383465159 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619383465159 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619383465161 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1619383465171 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619383465174 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465176 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1619383465177 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465179 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465180 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465181 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465182 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465183 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619383465187 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619383465228 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619383465883 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619383465973 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619383465973 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619383465974 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619383465974 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465975 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465976 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465977 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465978 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465979 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383465980 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619383465982 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619383466225 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1619383466226 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1619383466226 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1619383466226 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383466227 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383466228 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383466229 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383466230 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619383466231 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619383467526 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619383467528 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 55 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 55 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "510 " "Peak virtual memory: 510 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619383467561 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 15:44:27 2021 " "Processing ended: Sun Apr 25 15:44:27 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619383467561 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619383467561 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619383467561 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619383467561 ""} diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.sta.rdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.sta.rdb new file mode 100644 index 0000000..2293790 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.sta.rdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.sta_cmp.6_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..7cb4f9e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.sta_cmp.7_slow_1200mv_85c.tdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.sta_cmp.7_slow_1200mv_85c.tdb new file mode 100644 index 0000000..99893dc Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.sta_cmp.7_slow_1200mv_85c.tdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.tis_db_list.ddb b/EE203/Noah Woodlee/Lab2/part5/db/part5.tis_db_list.ddb new file mode 100644 index 0000000..abcfeea Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.tis_db_list.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fast_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..8620b7c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fast_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fastest_slow_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..c3b7d11 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fastest_slow_1200mv_85c.ddb b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..72571a5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.slow_1200mv_0c.ddb b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..588340d Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.slow_1200mv_0c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.slow_1200mv_85c.ddb b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..3b0f73e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.tiscmp.slow_1200mv_85c.ddb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.tmw_info b/EE203/Noah Woodlee/Lab2/part5/db/part5.tmw_info new file mode 100644 index 0000000..ae8e34e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:53 +start_analysis_synthesis:s:00:00:21-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:18-start_full_compilation +start_assembler:s:00:00:08-start_full_compilation +start_timing_analyzer:s:00:00:06-start_full_compilation diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.vpr.ammdb b/EE203/Noah Woodlee/Lab2/part5/db/part5.vpr.ammdb new file mode 100644 index 0000000..06be7e3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.vpr.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ff_0c_fast.hsd b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..c96a6fd Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ii_0c_slow.hsd b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..cd343a8 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ii_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ii_85c_slow.hsd b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..2a0d0d5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.ii_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.tt_0c_slow.hsd b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..090de61 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.tt_0c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.tt_85c_slow.hsd b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..09ac6ef Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/db/part5.zippleback_io_sim_cache.tt_85c_slow.hsd differ diff --git a/EE203/Noah Woodlee/Lab2/part5/db/part5_partition_pins.json b/EE203/Noah Woodlee/Lab2/part5/db/part5_partition_pins.json new file mode 100644 index 0000000..7d2f41a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/db/part5_partition_pins.json @@ -0,0 +1,89 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "HEX0[0]", + "strict" : false + }, + { + "name" : "HEX0[1]", + "strict" : false + }, + { + "name" : "HEX0[2]", + "strict" : false + }, + { + "name" : "HEX0[3]", + "strict" : false + }, + { + "name" : "HEX0[4]", + "strict" : false + }, + { + "name" : "HEX0[5]", + "strict" : false + }, + { + "name" : "HEX0[6]", + "strict" : false + }, + { + "name" : "HEX1[0]", + "strict" : false + }, + { + "name" : "HEX1[3]", + "strict" : false + }, + { + "name" : "HEX1[4]", + "strict" : false + }, + { + "name" : "HEX1[5]", + "strict" : false + }, + { + "name" : "SW[4]", + "strict" : false + }, + { + "name" : "SW[0]", + "strict" : false + }, + { + "name" : "SW[8]", + "strict" : false + }, + { + "name" : "SW[6]", + "strict" : false + }, + { + "name" : "SW[2]", + "strict" : false + }, + { + "name" : "SW[5]", + "strict" : false + }, + { + "name" : "SW[1]", + "strict" : false + }, + { + "name" : "SW[7]", + "strict" : false + }, + { + "name" : "SW[3]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v b/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v new file mode 100644 index 0000000..402472e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v @@ -0,0 +1,139 @@ +// ============================================================================ +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file +// ============================================================================ + + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define ENABLE_ADC_CLOCK +`define ENABLE_CLOCK1 +`define ENABLE_CLOCK2 +`define ENABLE_SDRAM +`define ENABLE_HEX0 +`define ENABLE_HEX1 +`define ENABLE_HEX2 +`define ENABLE_HEX3 +`define ENABLE_HEX4 +`define ENABLE_HEX5 +`define ENABLE_KEY +`define ENABLE_LED +`define ENABLE_SW +`define ENABLE_VGA +`define ENABLE_ACCELEROMETER +`define ENABLE_ARDUINO +`define ENABLE_GPIO + +module DE10_LITE_Golden_Top( + + //////////// ADC CLOCK: 3.3-V LVTTL ////////// +`ifdef ENABLE_ADC_CLOCK + input ADC_CLK_10, +`endif + //////////// CLOCK 1: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK1 + input MAX10_CLK1_50, +`endif + //////////// CLOCK 2: 3.3-V LVTTL ////////// +`ifdef ENABLE_CLOCK2 + input MAX10_CLK2_50, +`endif + + //////////// SDRAM: 3.3-V LVTTL ////////// +`ifdef ENABLE_SDRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, +`endif + + //////////// SEG7: 3.3-V LVTTL ////////// +`ifdef ENABLE_HEX0 + output [7:0] HEX0, +`endif +`ifdef ENABLE_HEX1 + output [7:0] HEX1, +`endif +`ifdef ENABLE_HEX2 + output [7:0] HEX2, +`endif +`ifdef ENABLE_HEX3 + output [7:0] HEX3, +`endif +`ifdef ENABLE_HEX4 + output [7:0] HEX4, +`endif +`ifdef ENABLE_HEX5 + output [7:0] HEX5, +`endif + + //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// +`ifdef ENABLE_KEY + input [1:0] KEY, +`endif + + //////////// LED: 3.3-V LVTTL ////////// +`ifdef ENABLE_LED + output [9:0] LEDR, +`endif + + //////////// SW: 3.3-V LVTTL ////////// +`ifdef ENABLE_SW + input [9:0] SW, +`endif + + //////////// VGA: 3.3-V LVTTL ////////// +`ifdef ENABLE_VGA + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, +`endif + + //////////// Accelerometer: 3.3-V LVTTL ////////// +`ifdef ENABLE_ACCELEROMETER + output GSENSOR_CS_N, + input [2:1] GSENSOR_INT, + output GSENSOR_SCLK, + inout GSENSOR_SDI, + inout GSENSOR_SDO, +`endif + + //////////// Arduino: 3.3-V LVTTL ////////// +`ifdef ENABLE_ARDUINO + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, +`endif + + //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// +`ifdef ENABLE_GPIO + inout [35:0] GPIO +`endif +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule diff --git a/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/filelist.txt b/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/filelist.txt new file mode 100644 index 0000000..a837f14 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/filelist.txt @@ -0,0 +1,3 @@ +platform_setup.tcl +filelist.txt +DE10_LITE_Golden_Top.v diff --git a/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/platform_setup.tcl b/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/platform_setup.tcl new file mode 100644 index 0000000..3b32d96 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/platform_setup.tcl @@ -0,0 +1,429 @@ +proc ::setup_project {} { +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 09:47:48 June 12, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VERILOG_FILE DE10_LITE_Golden_Top.v +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +} diff --git a/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/qar_info.json b/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/qar_info.json new file mode 100644 index 0000000..536fab3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/devkits/DE10_LITE_Golden_Top/qar_info.json @@ -0,0 +1,6 @@ +{ + "common_dir" : "/data/adu/17.0/Lite/Max10/Max_10_DE10_LITE/DE10_LITE_Golden_Top_project/", + "acds_version" : "Version 17.0.0", + "platform" : "linux", + "os" : "Red Hat" +} \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part5/devkits/readme.txt b/EE203/Noah Woodlee/Lab2/part5/devkits/readme.txt new file mode 100644 index 0000000..15cc67e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/devkits/readme.txt @@ -0,0 +1,8 @@ +This devkits directory contains development kit baseline example designs. + +HOW TO SETUP PIN ASSIGNMENTS +1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows. +2) Type command 'source platform_setup.tcl' in the Tcl console. +3) Type command 'setup_project' in the Tcl console. + - Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file. + diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/README b/EE203/Noah Woodlee/Lab2/part5/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.db_info b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.db_info new file mode 100644 index 0000000..4cccac7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Wed Apr 21 16:27:42 2021 diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.ammdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.ammdb new file mode 100644 index 0000000..71883e7 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.ammdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.cdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.cdb new file mode 100644 index 0000000..43dcf4c Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.dfp b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.dfp differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.hdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.hdb new file mode 100644 index 0000000..d8857cd Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.logdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.rcfdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.rcfdb new file mode 100644 index 0000000..dcebf49 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.cmp.rcfdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.cdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.cdb new file mode 100644 index 0000000..5d6c85e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.dpi b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.dpi new file mode 100644 index 0000000..fd8514b Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.dpi differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.cdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..592ccb3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.cdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hb_info b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hb_info differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..ce4d62e Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.sig b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.sig new file mode 100644 index 0000000..2b953e3 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +fa8634a97a99232bb4bb1c2e0a376209 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hdb new file mode 100644 index 0000000..146f2e3 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.kpt b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.kpt new file mode 100644 index 0000000..c974172 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.root_partition.map.kpt differ diff --git a/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.rrp.hdb b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.rrp.hdb new file mode 100644 index 0000000..3ba63d7 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/incremental_db/compiled_partitions/part5.rrp.hdb differ diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.asm.rpt b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.asm.rpt new file mode 100644 index 0000000..214be2e --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for part5 +Sun Apr 25 15:44:21 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: part5.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sun Apr 25 15:44:21 2021 ; +; Revision Name ; part5 ; +; Top-level Entity Name ; part5 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------------------------+ +; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/output_files/part5.sof ; ++-----------------------------------------------------------------------------------------------+ + + ++-------------------------------------+ +; Assembler Device Options: part5.sof ; ++----------------+--------------------+ +; Option ; Setting ; ++----------------+--------------------+ +; JTAG usercode ; 0x0027305F ; +; Checksum ; 0x0027305F ; ++----------------+--------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 15:44:16 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off part5 -c part5 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 360 megabytes + Info: Processing ended: Sun Apr 25 15:44:21 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.done b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.done new file mode 100644 index 0000000..ce4c3ac --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.done @@ -0,0 +1 @@ +Sun Apr 25 15:44:27 2021 diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.rpt b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.rpt new file mode 100644 index 0000000..3b9da08 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.rpt @@ -0,0 +1,1349 @@ +Fitter report for part5 +Sun Apr 25 15:44:12 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sun Apr 25 15:44:12 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part5 ; +; Top-level Entity Name ; part5 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 20 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 20 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 23 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M50DAF484C7G ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.4% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; HEX2[0] ; PIN_B20 ; QSF Assignment ; +; Location ; ; ; HEX2[1] ; PIN_A20 ; QSF Assignment ; +; Location ; ; ; HEX2[2] ; PIN_B19 ; QSF Assignment ; +; Location ; ; ; HEX2[3] ; PIN_A21 ; QSF Assignment ; +; Location ; ; ; HEX2[4] ; PIN_B21 ; QSF Assignment ; +; Location ; ; ; HEX2[5] ; PIN_C22 ; QSF Assignment ; +; Location ; ; ; HEX2[6] ; PIN_B22 ; QSF Assignment ; +; Location ; ; ; HEX3[0] ; PIN_F21 ; QSF Assignment ; +; Location ; ; ; HEX3[1] ; PIN_E22 ; QSF Assignment ; +; Location ; ; ; HEX3[2] ; PIN_E21 ; QSF Assignment ; +; Location ; ; ; HEX3[3] ; PIN_C19 ; QSF Assignment ; +; Location ; ; ; HEX3[4] ; PIN_C20 ; QSF Assignment ; +; Location ; ; ; HEX3[5] ; PIN_D19 ; QSF Assignment ; +; Location ; ; ; HEX3[6] ; PIN_E17 ; QSF Assignment ; +; Location ; ; ; LEDR[0] ; PIN_A8 ; QSF Assignment ; +; Location ; ; ; LEDR[1] ; PIN_A9 ; QSF Assignment ; +; Location ; ; ; LEDR[2] ; PIN_A10 ; QSF Assignment ; +; Location ; ; ; LEDR[3] ; PIN_B10 ; QSF Assignment ; +; Location ; ; ; LEDR[4] ; PIN_D13 ; QSF Assignment ; +; Location ; ; ; LEDR[5] ; PIN_C13 ; QSF Assignment ; +; Location ; ; ; LEDR[6] ; PIN_E14 ; QSF Assignment ; +; Location ; ; ; LEDR[7] ; PIN_D14 ; QSF Assignment ; +; Location ; ; ; LEDR[8] ; PIN_A11 ; QSF Assignment ; +; Location ; ; ; LEDR[9] ; PIN_B11 ; QSF Assignment ; +; Location ; ; ; SW[9] ; PIN_F15 ; QSF Assignment ; ++----------+----------------+--------------+------------+---------------+----------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 85 ) ; 0.00 % ( 0 / 85 ) ; 0.00 % ( 0 / 85 ) ; +; -- Achieved ; 0.00 % ( 0 / 85 ) ; 0.00 % ( 0 / 85 ) ; 0.00 % ( 0 / 85 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 69 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 16 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/output_files/part5.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 20 / 49,760 ( < 1 % ) ; +; -- Combinational with no register ; 20 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 10 ; +; -- 3 input functions ; 6 ; +; -- <=2 input functions ; 4 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 15 ; +; -- arithmetic mode ; 5 ; +; ; ; +; Total registers* ; 0 / 51,509 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; -- I/O registers ; 0 / 1,749 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 4 / 3,110 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 23 / 360 ( 6 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 182 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; +; Total block memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.3% / 0.4% / 0.2% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 17 ; +; Total fan-out ; 107 ; +; Average fan-out ; 1.26 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 20 / 49760 ( < 1 % ) ; 0 / 49760 ( 0 % ) ; +; -- Combinational with no register ; 20 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 10 ; 0 ; +; -- 3 input functions ; 6 ; 0 ; +; -- <=2 input functions ; 4 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 15 ; 0 ; +; -- arithmetic mode ; 5 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 49760 ( 0 % ) ; 0 / 49760 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 4 / 3110 ( < 1 % ) ; 0 / 3110 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 23 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; 0 / 288 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 2 / 2 ( 100 % ) ; 0 / 2 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 113 ; 8 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 9 ; 0 ; +; -- Output Ports ; 14 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; SW[0] ; C10 ; 7 ; 51 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[1] ; C11 ; 7 ; 51 ; 54 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[2] ; D12 ; 7 ; 51 ; 54 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[3] ; C12 ; 7 ; 54 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[4] ; A12 ; 7 ; 54 ; 54 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[5] ; B12 ; 7 ; 49 ; 54 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[6] ; A13 ; 7 ; 54 ; 54 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[7] ; A14 ; 7 ; 58 ; 54 ; 28 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; +; SW[8] ; B14 ; 7 ; 56 ; 54 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; 0 ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; HEX0[0] ; C14 ; 7 ; 58 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[1] ; E15 ; 7 ; 74 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[2] ; C15 ; 7 ; 60 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[3] ; C16 ; 7 ; 62 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[4] ; E16 ; 7 ; 74 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[5] ; D17 ; 7 ; 74 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[6] ; C17 ; 7 ; 74 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[0] ; C18 ; 7 ; 69 ; 54 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[1] ; D18 ; 6 ; 78 ; 49 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[2] ; E18 ; 6 ; 78 ; 49 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[3] ; B16 ; 7 ; 60 ; 54 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[4] ; A17 ; 7 ; 64 ; 54 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[5] ; A18 ; 7 ; 66 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[6] ; B17 ; 7 ; 69 ; 54 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; H2 ; DIFFIO_RX_L17n, DIFFOUT_L17n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; G2 ; DIFFIO_RX_L17p, DIFFOUT_L17p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; L4 ; DIFFIO_RX_L18n, DIFFOUT_L18n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; M5 ; DIFFIO_RX_L18p, DIFFOUT_L18p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; H10 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; H9 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; G9 ; DIFFIO_RX_T50p, DIFFOUT_T50p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_RX_T50n, DIFFOUT_T50n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 24 ( 17 % ) ; 2.5V ; -- ; +; 2 ; 0 / 36 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 40 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 2 / 60 ( 3 % ) ; 2.5V ; -- ; +; 7 ; 21 / 52 ( 40 % ) ; 2.5V ; -- ; +; 8 ; 4 / 36 ( 11 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 483 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 473 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 471 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 447 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 435 ; 7 ; SW[4] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 433 ; 7 ; SW[6] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 425 ; 7 ; SW[7] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 421 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 407 ; 7 ; HEX1[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A18 ; 405 ; 7 ; HEX1[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A19 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA2 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA3 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AA14 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA19 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB3 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B7 ; 469 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 451 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 441 ; 7 ; SW[5] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7 ; SW[8] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; 417 ; 7 ; HEX1[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B17 ; 402 ; 7 ; HEX1[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 399 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B21 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 33 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; C2 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 467 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 465 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 442 ; 7 ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C11 ; 440 ; 7 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; 436 ; 7 ; SW[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C13 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 424 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C15 ; 418 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C16 ; 416 ; 7 ; HEX0[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C17 ; 391 ; 7 ; HEX0[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C18 ; 400 ; 7 ; HEX1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C19 ; 397 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 343 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 35 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 31 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; 29 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D8 ; 472 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D12 ; 438 ; 7 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D13 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 428 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 389 ; 7 ; HEX0[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D18 ; 385 ; 6 ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D19 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D21 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; D22 ; 341 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 41 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; 3 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 1 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 466 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 464 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 390 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 388 ; 7 ; HEX0[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E17 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E18 ; 387 ; 6 ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E19 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E20 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E21 ; 335 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 333 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 47 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 43 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 7 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F5 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 494 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; F9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F15 ; 398 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 396 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F19 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 342 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 340 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 331 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 45 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 34 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; G3 ; 11 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 5 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; 492 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; G10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G16 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G17 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G19 ; 330 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G20 ; 328 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G22 ; 329 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 44 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; 32 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H3 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 9 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; -- ; VCCA_ADC ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H9 ; 482 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; H10 ; 480 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H11 ; 470 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 420 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H19 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 46 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 15 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; ANAIN2 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J10 ; 468 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 446 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 327 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 325 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 49 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 37 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 13 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K15 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K18 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K20 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K21 ; 326 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 51 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 39 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L8 ; 40 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; 42 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; 344 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L15 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L19 ; 349 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L20 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L22 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; 50 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 48 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 38 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M6 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; 334 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 332 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M18 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; 337 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N10 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N17 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N18 ; 336 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 338 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 339 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P19 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P20 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R7 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R9 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R15 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R16 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R18 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T3 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T5 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T18 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 296 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 295 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U11 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U15 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U18 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U19 ; 282 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 290 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V5 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; 289 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 291 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W5 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W6 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 286 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W22 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y2 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y3 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 202 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y21 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 281 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; HEX0[0] ; Incomplete set of assignments ; +; HEX0[1] ; Incomplete set of assignments ; +; HEX0[2] ; Incomplete set of assignments ; +; HEX0[3] ; Incomplete set of assignments ; +; HEX0[4] ; Incomplete set of assignments ; +; HEX0[5] ; Incomplete set of assignments ; +; HEX0[6] ; Incomplete set of assignments ; +; HEX1[0] ; Incomplete set of assignments ; +; HEX1[1] ; Incomplete set of assignments ; +; HEX1[2] ; Incomplete set of assignments ; +; HEX1[3] ; Incomplete set of assignments ; +; HEX1[4] ; Incomplete set of assignments ; +; HEX1[5] ; Incomplete set of assignments ; +; HEX1[6] ; Incomplete set of assignments ; +; SW[4] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; +; SW[8] ; Incomplete set of assignments ; +; SW[6] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[5] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; SW[7] ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +; |part5 ; 20 (11) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 23 ; 0 ; 20 (11) ; 0 (0) ; 0 (0) ; 0 ; |part5 ; part5 ; work ; +; |bcd:b0| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; |part5|bcd:b0 ; bcd ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[8] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; +; SW[6] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; (6) 868 ps ; -- ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; SW[4] ; ; ; +; - Add0~2 ; 0 ; 6 ; +; SW[0] ; ; ; +; - Add0~2 ; 1 ; 6 ; +; SW[8] ; ; ; +; - Add0~1 ; 1 ; 6 ; +; SW[6] ; ; ; +; - Add0~6 ; 0 ; 6 ; +; SW[2] ; ; ; +; - Add0~6 ; 0 ; 6 ; +; SW[5] ; ; ; +; - Add0~4 ; 0 ; 6 ; +; SW[1] ; ; ; +; - Add0~4 ; 0 ; 6 ; +; SW[7] ; ; ; +; - Add0~8 ; 0 ; 6 ; +; SW[3] ; ; ; +; - Add0~8 ; 1 ; 6 ; ++---------------------+-------------------+---------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 33 / 148,641 ( < 1 % ) ; +; C16 interconnects ; 0 / 5,382 ( 0 % ) ; +; C4 interconnects ; 24 / 106,704 ( < 1 % ) ; +; Direct links ; 4 / 148,641 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 2 / 49,760 ( < 1 % ) ; +; NSLEEPs ; 0 / 500 ( 0 % ) ; +; R24 interconnects ; 3 / 5,406 ( < 1 % ) ; +; R4 interconnects ; 24 / 147,764 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 5.00) ; Number of LABs (Total = 4) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 4.75) ; Number of LABs (Total = 4) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 4.25) ; Number of LABs (Total = 4) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 4.50) ; Number of LABs (Total = 4) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 23 ; 23 ; 0 ; 0 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 9 ; 14 ; 0 ; 9 ; 0 ; 0 ; 14 ; 0 ; 23 ; 23 ; 23 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 23 ; 0 ; 0 ; 23 ; 23 ; 0 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 23 ; 23 ; 14 ; 9 ; 23 ; 14 ; 23 ; 23 ; 9 ; 23 ; 0 ; 0 ; 0 ; 23 ; 23 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device 10M50DAF484C7G for design "part5" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 10M08DAF484I7G is compatible + Info (176445): Device 10M08DAF484I7P is compatible + Info (176445): Device 10M16DAF484A7G is compatible + Info (176445): Device 10M16DAF484C7G is compatible + Info (176445): Device 10M16DAF484I7G is compatible + Info (176445): Device 10M16DAF484I7P is compatible + Info (176445): Device 10M25DAF484A7G is compatible + Info (176445): Device 10M25DAF484C7G is compatible + Info (176445): Device 10M25DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7G is compatible + Info (176445): Device 10M50DAF484I7P is compatible + Info (176445): Device 10M40DAF484C7G is compatible + Info (176445): Device 10M40DAF484I7G is compatible +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location H2 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location G2 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location L4 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location M5 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.08 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 32 warnings + Info: Peak virtual memory: 1082 megabytes + Info: Processing ended: Sun Apr 25 15:44:12 2021 + Info: Elapsed time: 00:00:15 + Info: Total CPU time (on all processors): 00:00:18 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg. + + diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.summary b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.summary new file mode 100644 index 0000000..403d2c2 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Sun Apr 25 15:44:12 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part5 +Top-level Entity Name : part5 +Family : MAX 10 +Device : 10M50DAF484C7G +Timing Models : Final +Total logic elements : 20 / 49,760 ( < 1 % ) + Total combinational functions : 20 / 49,760 ( < 1 % ) + Dedicated logic registers : 0 / 49,760 ( 0 % ) +Total registers : 0 +Total pins : 23 / 360 ( 6 % ) +Total virtual pins : 0 +Total memory bits : 0 / 1,677,312 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 2 ( 0 % ) diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.flow.rpt b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.flow.rpt new file mode 100644 index 0000000..2445e6b --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.flow.rpt @@ -0,0 +1,131 @@ +Flow report for part5 +Sun Apr 25 15:44:27 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sun Apr 25 15:44:21 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part5 ; +; Top-level Entity Name ; part5 ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Total logic elements ; 20 / 49,760 ( < 1 % ) ; +; Total combinational functions ; 20 / 49,760 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 23 / 360 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 1,677,312 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/25/2021 15:43:38 ; +; Main task ; Compilation ; +; Revision Name ; part5 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 164639278517.161938341830598 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part4 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:18 ; 1.0 ; 391 MB ; 00:00:33 ; +; Fitter ; 00:00:15 ; 1.0 ; 1082 MB ; 00:00:17 ; +; Assembler ; 00:00:05 ; 1.0 ; 360 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:04 ; 1.0 ; 510 MB ; 00:00:04 ; +; Total ; 00:00:42 ; -- ; -- ; 00:00:59 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+-------------------+------------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+-------------------+------------------+------------+----------------+ +; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; +; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ; ++----------------------+-------------------+------------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 +quartus_fit --read_settings_files=off --write_settings_files=off part5 -c part5 +quartus_asm --read_settings_files=off --write_settings_files=off part5 -c part5 +quartus_sta part5 -c part5 + + + diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.jdi b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.jdi new file mode 100644 index 0000000..21af662 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.map.rpt b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.map.rpt new file mode 100644 index 0000000..ef6eec9 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.map.rpt @@ -0,0 +1,359 @@ +Analysis & Synthesis report for part5 +Sun Apr 25 15:43:55 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Port Connectivity Checks: "bcd:b1" + 10. Post-Synthesis Netlist Statistics for Top Partition + 11. Elapsed Time Per Partition + 12. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sun Apr 25 15:43:55 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; part5 ; +; Top-level Entity Name ; part5 ; +; Family ; MAX 10 ; +; Total logic elements ; 19 ; +; Total combinational functions ; 19 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 23 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M50DAF484C7G ; ; +; Top-level entity name ; part5 ; part5 ; +; Family name ; MAX 10 ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ +; part5.v ; yes ; User Verilog HDL File ; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v ; ; ++----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+ + + ++------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+--------+ +; Resource ; Usage ; ++---------------------------------------------+--------+ +; Estimated Total logic elements ; 19 ; +; ; ; +; Total combinational functions ; 19 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 10 ; +; -- 3 input functions ; 6 ; +; -- <=2 input functions ; 3 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 14 ; +; -- arithmetic mode ; 5 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 23 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; Add0~2 ; +; Maximum fan-out ; 8 ; +; Total fan-out ; 96 ; +; Average fan-out ; 1.48 ; ++---------------------------------------------+--------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +; |part5 ; 19 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 ; 0 ; 0 ; |part5 ; part5 ; work ; +; |bcd:b0| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part5|bcd:b0 ; bcd ; work ; ++----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "bcd:b1" ; ++------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; IN ; Input ; Warning ; Input port expression (1 bits) is smaller than the input port (4 bits) it drives. Extra input bit(s) "IN[3..1]" will be connected to GND. ; ++------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 23 ; +; cycloneiii_lcell_comb ; 22 ; +; arith ; 5 ; +; 2 data inputs ; 1 ; +; 3 data inputs ; 4 ; +; normal ; 17 ; +; 0 data inputs ; 3 ; +; 1 data inputs ; 1 ; +; 2 data inputs ; 1 ; +; 3 data inputs ; 2 ; +; 4 data inputs ; 10 ; +; ; ; +; Max LUT depth ; 4.50 ; +; Average LUT depth ; 3.79 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 15:43:37 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 2 design units, including 2 entities, in source file part5.v + Info (12023): Found entity 1: bcd File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v Line: 1 + Info (12023): Found entity 2: part5 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v Line: 13 +Info (12127): Elaborating entity "part5" for the top level hierarchy +Warning (10230): Verilog HDL assignment warning at part5.v(24): truncated value with size 32 to match size of target (4) File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v Line: 24 +Info (12128): Elaborating entity "bcd" for hierarchy "bcd:b0" File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v Line: 34 +Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "HEX1[1]" is stuck at GND File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v Line: 15 + Warning (13410): Pin "HEX1[2]" is stuck at GND File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v Line: 15 + Warning (13410): Pin "HEX1[6]" is stuck at VCC File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/part5.v Line: 15 +Info (286030): Timing-Driven Synthesis is running +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 42 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 9 input pins + Info (21059): Implemented 14 output pins + Info (21061): Implemented 19 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 57 warnings + Info: Peak virtual memory: 397 megabytes + Info: Processing ended: Sun Apr 25 15:43:55 2021 + Info: Elapsed time: 00:00:18 + Info: Total CPU time (on all processors): 00:00:33 + + diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.map.summary b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.map.summary new file mode 100644 index 0000000..4b67c7a --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Sun Apr 25 15:43:55 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : part5 +Top-level Entity Name : part5 +Family : MAX 10 +Total logic elements : 19 + Total combinational functions : 19 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 23 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 +UFM blocks : 0 +ADC blocks : 0 diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.pin b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.pin new file mode 100644 index 0000000..e3d6b05 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.pin @@ -0,0 +1,556 @@ + -- Copyright (C) 2020 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +CHIP "part5" ASSIGNED TO AN: 10M50DAF484C7G + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +SW[4] : A12 : input : 2.5 V : : 7 : Y +SW[6] : A13 : input : 2.5 V : : 7 : Y +SW[7] : A14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +HEX1[4] : A17 : output : 2.5 V : : 7 : Y +HEX1[5] : A18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +GND : AA4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +GND : AA18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +GND : AB22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +GND : B6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +SW[5] : B12 : input : 2.5 V : : 7 : Y +GND : B13 : gnd : : : : +SW[8] : B14 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +HEX1[3] : B16 : output : 2.5 V : : 7 : Y +HEX1[6] : B17 : output : 2.5 V : : 7 : Y +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +SW[0] : C10 : input : 2.5 V : : 7 : Y +SW[1] : C11 : input : 2.5 V : : 7 : Y +SW[3] : C12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +HEX0[0] : C14 : output : 2.5 V : : 7 : Y +HEX0[2] : C15 : output : 2.5 V : : 7 : Y +HEX0[3] : C16 : output : 2.5 V : : 7 : Y +HEX0[6] : C17 : output : 2.5 V : : 7 : Y +HEX1[0] : C18 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B : +GND : D4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +GND : D11 : gnd : : : : +SW[2] : D12 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +GND : D16 : gnd : : : : +HEX0[5] : D17 : output : 2.5 V : : 7 : Y +HEX1[1] : D18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 : +GND : D20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B : +GND : E2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A : +NC : E5 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +GND : E7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +HEX0[1] : E15 : output : 2.5 V : : 7 : Y +HEX0[4] : E16 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 : +HEX1[2] : E18 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +NC : F6 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : F9 : power : : 2.5V : 8 : +GND : F10 : gnd : : : : +VCCIO8 : F11 : power : : 2.5V : 8 : +VCCIO7 : F12 : power : : 2.5V : 7 : +GND : F13 : gnd : : : : +VCCIO7 : F14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B : +~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A : +ANAIN1 : G5 : : : : : +GND : G6 : gnd : : : : +VCCD_PLL3 : G7 : power : : 1.2V : : +GND : G8 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N +VCCIO8 : G10 : power : : 2.5V : 8 : +VCCIO8 : G11 : power : : 2.5V : 8 : +VCCIO7 : G12 : power : : 2.5V : 7 : +VCCIO7 : G13 : power : : 2.5V : 7 : +VCCIO7 : G14 : power : : 2.5V : 7 : +GND : G15 : gnd : : : : +VCCD_PLL2 : G16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +GND : G18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 : +GND : G21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A : +REFGND : H5 : : : : : +ADC_VREF : H6 : : : : : +VCCA_ADC : H7 : power : : 2.5V : : +VCCA3 : H8 : power : : 2.5V : : +~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +VCCA2 : H15 : power : : 2.5V : : +VCCIO6 : H16 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A : +ANAIN2 : J5 : : : : : +GND : J6 : gnd : : : : +VCCINT : J7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +GND : J16 : gnd : : : : +VCCIO6 : J17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +GND : K3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A : +VCCIO1A : K7 : power : : 2.5V : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B : +GND : K10 : gnd : : : : +VCC : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +VCCIO6 : K16 : power : : 2.5V : 6 : +VCCIO6 : K17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B : +DNU : L3 : : : : : +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N +GND : L5 : gnd : : : : +VCCIO1A : L6 : power : : 2.5V : 1A : +VCCIO1B : L7 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B : +VCC : L10 : power : : 1.2V : : +VCC : L11 : power : : 1.2V : : +VCC : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +VCCIO6 : L16 : power : : 2.5V : 6 : +GND : L17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 : +GND : L21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B : +~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N +VCCIO1B : M6 : power : : 2.5V : 1B : +GND : M7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.2V : : +VCC : M12 : power : : 1.2V : : +VCC : M13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 : +GND : M16 : gnd : : : : +VCCIO6 : M17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 : +GND : M19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +VCCIO2 : N6 : power : : 2.5V : 2 : +VCCIO2 : N7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 : +VCC : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 : +VCCIO5 : N16 : power : : 2.5V : 5 : +VCCIO6 : N17 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +GND : P2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +GND : P6 : gnd : : : : +VCCIO2 : P7 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +VCCIO5 : P16 : power : : 2.5V : 5 : +GND : P17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +VCCIO2 : R6 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +VCCA1 : R8 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 : +VCCIO5 : R16 : power : : 2.5V : 5 : +VCCIO5 : R17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +GND : R19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +GND : R21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +GND : T4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 : +VCCD_PLL1 : T7 : power : : 1.2V : : +GND : T8 : gnd : : : : +VCCIO3 : T9 : power : : 2.5V : 3 : +VCCIO3 : T10 : power : : 2.5V : 3 : +VCCIO3 : T11 : power : : 2.5V : 3 : +VCCIO4 : T12 : power : : 2.5V : 4 : +VCCIO4 : T13 : power : : 2.5V : 4 : +GND : T14 : gnd : : : : +VCCA4 : T15 : power : : 2.5V : : +GND : T16 : gnd : : : : +VCCIO5 : T17 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +VCCIO3 : U8 : power : : 2.5V : 3 : +VCCIO3 : U9 : power : : 2.5V : 3 : +GND : U10 : gnd : : : : +VCCIO4 : U11 : power : : 2.5V : 4 : +VCCIO4 : U12 : power : : 2.5V : 4 : +GND : U13 : gnd : : : : +VCCIO4 : U14 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCD_PLL4 : U16 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +GND : V2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +GND : V6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 : +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +GND : W21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 : +GND : Y15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.pof b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.pof new file mode 100644 index 0000000..eafda2a Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.pof differ diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sld b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sld @@ -0,0 +1 @@ + diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sof b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sof new file mode 100644 index 0000000..dbb3ae5 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sof differ diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sta.rpt b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sta.rpt new file mode 100644 index 0000000..174fc75 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sta.rpt @@ -0,0 +1,568 @@ +Timing Analyzer report for part5 +Sun Apr 25 15:44:27 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Clock Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths Summary + 35. Unconstrained Input Ports + 36. Unconstrained Output Ports + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; part5 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M50DAF484C7G ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.03 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.9% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0407 V ; 0.211 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0407 V ; 0.211 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0174 V ; 0.144 V ; 0.094 V ; 6.45e-10 s ; 7.22e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0174 V ; 0.144 V ; 0.094 V ; 6.45e-10 s ; 7.22e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 9 ; 9 ; +; Unconstrained Input Port Paths ; 99 ; 99 ; +; Unconstrained Output Ports ; 11 ; 11 ; +; Unconstrained Output Port Paths ; 99 ; 99 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sun Apr 25 15:44:23 2021 +Info: Command: quartus_sta part5 -c part5 +Info: qsta_default_script.tcl version: #1 +Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored +Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design + Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored + Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 55 warnings + Info: Peak virtual memory: 510 megabytes + Info: Processing ended: Sun Apr 25 15:44:27 2021 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:04 + + diff --git a/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sta.summary b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/output_files/part5.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/EE203/Noah Woodlee/Lab2/part5/part5.qpf b/EE203/Noah Woodlee/Lab2/part5/part5.qpf new file mode 100644 index 0000000..71dc6df --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/part5.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 16:26:05 April 21, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "16:26:05 April 21, 2021" + +# Revisions + +PROJECT_REVISION = "part5" diff --git a/EE203/Noah Woodlee/Lab2/part5/part5.qsf b/EE203/Noah Woodlee/Lab2/part5/part5.qsf new file mode 100644 index 0000000..42aaaaf --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/part5.qsf @@ -0,0 +1,110 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 16:26:05 April 21, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part5_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY part5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:26:05 APRIL 21, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name VERILOG_FILE part5.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part5/part5.qsf.bak b/EE203/Noah Woodlee/Lab2/part5/part5.qsf.bak new file mode 100644 index 0000000..603912d --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/part5.qsf.bak @@ -0,0 +1,49 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 16:26:05 April 21, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# part5_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY part5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:26:05 APRIL 21, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part5/part5.qws b/EE203/Noah Woodlee/Lab2/part5/part5.qws new file mode 100644 index 0000000..ee0e469 Binary files /dev/null and b/EE203/Noah Woodlee/Lab2/part5/part5.qws differ diff --git a/EE203/Noah Woodlee/Lab2/part5/part5.v b/EE203/Noah Woodlee/Lab2/part5/part5.v new file mode 100644 index 0000000..b27e0e6 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/part5.v @@ -0,0 +1,37 @@ +module bcd(IN,OUT); + input [3:0] IN; + output [6:0] OUT; + + assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000): + (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010): + (IN[0]? 7'b0010_010:7'b0011_001)): + (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100): + (IN[0]? 7'b1111_001:7'b1000_000))); + +endmodule + +module part5(SW, HEX0, HEX1); + input [8:0] SW; + output [6:0] HEX0, HEX1; + + reg [4:0] U; + + always@(*) + + begin + U = SW[3:0] + SW[7:4] + SW[8]; + if (U > 9) begin + U[3:0] = U[3:0]-10; + U[4] = 1; + end + + else begin + U[4] = 0; + end + + end + + bcd b0(U[3:0], HEX0); + bcd b1(U[4], HEX1); + +endmodule \ No newline at end of file diff --git a/EE203/Noah Woodlee/Lab2/part5/part5.v.bak b/EE203/Noah Woodlee/Lab2/part5/part5.v.bak new file mode 100644 index 0000000..6a19f97 --- /dev/null +++ b/EE203/Noah Woodlee/Lab2/part5/part5.v.bak @@ -0,0 +1,12 @@ +module bcd(IN,OUT); + input [3:0] IN; + output [6:0] OUT; + + assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000): + (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010): + (IN[0]? 7'b0010_010:7'b0011_001)): + (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100): + (IN[0]? 7'b1111_001:7'b1000_000))); + +endmodule + diff --git a/EE203/Noah Woodlee/Pin Assignments/Lab1Pt1.qsf b/EE203/Noah Woodlee/Pin Assignments/Lab1Pt1.qsf new file mode 100644 index 0000000..c6b079b --- /dev/null +++ b/EE203/Noah Woodlee/Pin Assignments/Lab1Pt1.qsf @@ -0,0 +1,36 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY Lab1Pt1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:34:44 FEBRUARY 25, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name VERILOG_FILE Lab1Pt1.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf diff --git a/EE203/Noah Woodlee/Pin Assignments/part1.qsf b/EE203/Noah Woodlee/Pin Assignments/part1.qsf new file mode 100644 index 0000000..d8b7603 --- /dev/null +++ b/EE203/Noah Woodlee/Pin Assignments/part1.qsf @@ -0,0 +1,65 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:13:22 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top +set_global_assignment -name VERILOG_FILE part1.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top diff --git a/EE203/Noah Woodlee/Pin Assignments/part1_bcd.qsf b/EE203/Noah Woodlee/Pin Assignments/part1_bcd.qsf new file mode 100644 index 0000000..818b55d --- /dev/null +++ b/EE203/Noah Woodlee/Pin Assignments/part1_bcd.qsf @@ -0,0 +1,61 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part1_bcd +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:29:06 APRIL 16, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part1_bcd.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top diff --git a/EE203/Noah Woodlee/Pin Assignments/part4.qsf b/EE203/Noah Woodlee/Pin Assignments/part4.qsf new file mode 100644 index 0000000..1c6d220 --- /dev/null +++ b/EE203/Noah Woodlee/Pin Assignments/part4.qsf @@ -0,0 +1,46 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part4 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:21:59 APRIL 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part4.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top diff --git a/EE203/Noah Woodlee/Pin Assignments/part5.qsf b/EE203/Noah Woodlee/Pin Assignments/part5.qsf new file mode 100644 index 0000000..43eac59 --- /dev/null +++ b/EE203/Noah Woodlee/Pin Assignments/part5.qsf @@ -0,0 +1,71 @@ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY part5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:34:56 APRIL 08, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "MAX 10 DE10 - Lite" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE part5.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top