module Lab1Part2 (SW,LEDR);
  input [9:0]SW;
  output [9:0]LEDR;
  wire sel;
  wire [3:0]X,Y,M;
  assign X=SW[3:0];
  assign Y=SW[7:4];
  assign sel=SW[9];
  assign M[0]=(~sel &X[0])|(sel &Y[0]);
  assign M[1]=(~sel &X[1])|(sel &Y[1]);
  assign M[2]=(~sel &X[2])|(sel &Y[2]);
  assign M[3]=(~sel &X[3])|(sel &Y[3]);
  assign LEDR[9]=sel;
  assign LEDR[3:0]=M;
  assign LEDR[8:4]=5`b0;
  endmodule