{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615514302220 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615514302230 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 19:58:22 2021 " "Processing started: Thu Mar 11 19:58:22 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615514302230 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615514302230 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Lab1Part2 -c Lab1Part2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1Part2 -c Lab1Part2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615514302230 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1615514302580 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1615514302580 ""}
{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "b0 Lab1Part2.v(15) " "Verilog HDL Compiler Directive warning at Lab1Part2.v(15): text macro \"b0\" is undefined" {  } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 15 0 0 } }  } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1615514310839 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lab1part2.v 1 1 " "Found 1 design units, including 1 entities, in source file lab1part2.v" { { "Info" "ISGN_ENTITY_NAME" "1 Lab1Part2 " "Found entity 1: Lab1Part2" {  } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615514310839 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615514310839 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Lab1Part2 " "Elaborating entity \"Lab1Part2\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1615514310879 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] VCC " "Pin \"LEDR\[4\]\" is stuck at VCC" {  } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" {  } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] VCC " "Pin \"LEDR\[6\]\" is stuck at VCC" {  } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" {  } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" {  } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 3 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1615514311209 "|Lab1Part2|LEDR[8]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1615514311209 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1615514311269 ""}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1615514311539 ""}  } {  } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1615514311539 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1615514311669 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615514311669 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "Lab1Part2.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Lab1Part2.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1615514311719 "|Lab1Part2|SW[8]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1615514311719 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "24 " "Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1615514311719 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1615514311719 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1615514311719 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1615514311719 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4781 " "Peak virtual memory: 4781 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615514311769 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 19:58:31 2021 " "Processing ended: Thu Mar 11 19:58:31 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615514311769 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615514311769 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615514311769 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1615514311769 ""}