EDA Netlist Writer report for Lab1Part2 Thu Mar 11 19:52:32 2021 Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. EDA Netlist Writer Summary 3. Simulation Settings 4. Simulation Generated Files 5. EDA Netlist Writer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2016 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ ; EDA Netlist Writer Status ; Successful - Thu Mar 11 19:52:32 2021 ; ; Revision Name ; Lab1Part2 ; ; Top-level Entity Name ; Lab1Part2 ; ; Family ; MAX 10 ; ; Simulation Files Creation ; Successful ; +---------------------------+---------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------+ ; Simulation Settings ; +---------------------------------------------------------------------------------------------------+---------------------------+ ; Option ; Setting ; +---------------------------------------------------------------------------------------------------+---------------------------+ ; Tool Name ; ModelSim-Altera (Verilog) ; ; Generate functional simulation netlist ; On ; ; Truncate long hierarchy paths ; Off ; ; Map illegal HDL characters ; Off ; ; Flatten buses into individual nodes ; Off ; ; Maintain hierarchy ; Off ; ; Bring out device-wide set/reset signals as ports ; Off ; ; Enable glitch filtering ; Off ; ; Do not write top level VHDL entity ; Off ; ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; ; Architecture name in VHDL output netlist ; structure ; ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; ; Generate third-party EDA tool command script for gate-level simulation ; Off ; +---------------------------------------------------------------------------------------------------+---------------------------+ +------------------------------------------------------------------------------------+ ; Simulation Generated Files ; +------------------------------------------------------------------------------------+ ; Generated Files ; +------------------------------------------------------------------------------------+ ; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim//Lab1Part2.vo ; +------------------------------------------------------------------------------------+ +-----------------------------+ ; EDA Netlist Writer Messages ; +-----------------------------+ Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition Info: Copyright (C) 2016 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Intel and sold by Intel or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Thu Mar 11 19:52:32 2021 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2 Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file Lab1Part2.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 26 warnings Info: Peak virtual memory: 4641 megabytes Info: Processing ended: Thu Mar 11 19:52:32 2021 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:01