# do decoder.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:12:11 on Jan 21,2021
# vlog -work work decoder.vo 
# -- Compiling module decoder
# -- Compiling module hard_block
# 
# Top level modules:
# 	decoder
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:12:12 on Jan 21,2021
# vlog -work work Waveform.vwf.vt 
# -- Compiling module decoder_vlg_vec_tst
# 
# Top level modules:
# 	decoder_vlg_vec_tst
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst 
# Start time: 20:12:12 on Jan 21,2021
# Loading work.decoder_vlg_vec_tst
# Loading work.decoder
# Loading work.hard_block
# ** Warning: (vsim-3017) decoder.vo(284): [TFMPC] - Too few port connections. Expected 8, found 7.
#    Time: 0 ps  Iteration: 0  Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~  File: nofile
# ** Warning: (vsim-3722) decoder.vo(284): [TFMPC] - Missing connection for port 'clk_dft'.
# ** Warning: (vsim-3017) decoder.vo(307): [TFMPC] - Too few port connections. Expected 8, found 7.
#    Time: 0 ps  Iteration: 0  Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~  File: nofile
# ** Warning: (vsim-3722) decoder.vo(307): [TFMPC] - Missing connection for port 'clk_dft'.
# after#26
# ** Note: $finish    : Waveform.vwf.vt(53)
#    Time: 200 ns  Iteration: 0  Instance: /decoder_vlg_vec_tst
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 4