# do Lab1Part2.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 19:52:33 on Mar 11,2021
# vlog -work work Lab1Part2.vo 
# -- Compiling module Lab1Part2
# -- Compiling module hard_block
# 
# Top level modules:
# 	Lab1Part2
# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 19:52:33 on Mar 11,2021
# vlog -work work Waveform.vwf.vt 
# -- Compiling module Lab1Part2_vlg_vec_tst
# 
# Top level modules:
# 	Lab1Part2_vlg_vec_tst
# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst 
# Start time: 19:52:33 on Mar 11,2021
# Loading work.Lab1Part2_vlg_vec_tst
# Loading work.Lab1Part2
# Loading work.hard_block
# ** Warning: (vsim-3017) Lab1Part2.vo(478): [TFMPC] - Too few port connections. Expected 8, found 7.
#    Time: 0 ps  Iteration: 0  Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~  File: nofile
# ** Warning: (vsim-3722) Lab1Part2.vo(478): [TFMPC] - Missing connection for port 'clk_dft'.
# ** Warning: (vsim-3017) Lab1Part2.vo(501): [TFMPC] - Too few port connections. Expected 8, found 7.
#    Time: 0 ps  Iteration: 0  Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~  File: nofile
# ** Warning: (vsim-3722) Lab1Part2.vo(501): [TFMPC] - Missing connection for port 'clk_dft'.
# after#26
# ** Note: $finish    : Waveform.vwf.vt(45)
#    Time: 1 us  Iteration: 0  Instance: /Lab1Part2_vlg_vec_tst
# End time: 19:52:34 on Mar 11,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 4