|Part3
SW[0] => U_V.IN0
SW[1] => U_V.IN0
SW[2] => U_V.IN0
SW[3] => U_V.IN0
SW[4] => W_X.IN0
SW[5] => W_X.IN0
SW[6] => W_X.IN0
SW[7] => W_X.IN0
SW[8] => U_V.IN1
SW[8] => U_V.IN1
SW[8] => W_X.IN1
SW[8] => W_X.IN1
SW[8] => M.IN1
SW[8] => W_X.IN1
SW[8] => U_V.IN1
SW[8] => W_X.IN1
SW[8] => U_V.IN1
SW[8] => M.IN1
SW[9] => M.IN1
SW[9] => M.IN1
LEDR[0] << M.DB_MAX_OUTPUT_PORT_TYPE
LEDR[1] << M.DB_MAX_OUTPUT_PORT_TYPE
LEDR[2] << <GND>
LEDR[3] << <GND>
LEDR[4] << <GND>
LEDR[5] << <VCC>
LEDR[6] << <GND>
LEDR[7] << <GND>
LEDR[8] << <GND>
LEDR[9] << <GND>