module bcd(IN,OUT);
       input [3:0] IN;
       output [6:0] OUT;
       
       assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000):
                          (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010):
                          (IN[0]? 7'b0010_010:7'b0011_001)):
                          (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100):
                          (IN[0]? 7'b1111_001:7'b1000_000)));

endmodule

module mux_2to1 (IN1, IN2, S, OUT);
    input[3:0]IN1, IN2;
    input S;
    output [3:0]OUT;

    assign OUT=S? IN2:IN1;

endmodule

module part2(SW, HEX0, HEX1);
    input [3:0] SW;
    output [6:0] HEX0, HEX1;

    wire z;
    wire [3:0] A, V;
    wire [3:0] W;

    assign V=SW[3:0];
    assign z = V[3:0] > 9? 1:0;
    assign HEX1 =z? 7'b1111_001:7'b1000_000;

    assign A=V[3:0]-4'b1010;
    mux_2to1 M0 (V, A, z, W);
    bcd B0 (W, HEX0);
endmodule