// Copyright (C) 2016  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Intel and sold by Intel or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "01/21/2021 19:19:21"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          class1-21-21
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module class1-21-21_vlg_vec_tst();
// constants                                           
// general purpose registers
reg in1;
reg in2;
// wires                                               
wire out;

// assign statements (if any)                          
class1-21-21 i1 (
// port map - connection between master ports and signals/registers   
	.in1(in1),
	.in2(in2),
	.out(out)
);
initial 
begin 
#1000000 $finish;
end 

// in1
initial
begin
	in1 = 1'b0;
	in1 = #80000 1'b1;
	in1 = #220000 1'b0;
	in1 = #440000 1'b1;
	in1 = #40000 1'b0;
end 

// in2
initial
begin
	in2 = 1'b0;
	in2 = #260000 1'b1;
	in2 = #40000 1'b0;
	in2 = #40000 1'b1;
	in2 = #50000 1'b0;
	in2 = #100000 1'b1;
	in2 = #130000 1'b0;
end 
endmodule