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// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// the Intel MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Intel and sold by Intel or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "02/25/2021 20:02:10"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          Lab1Pt1
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module Lab1Pt1_vlg_vec_tst();
// constants                                           
// general purpose registers
reg [9:0] SW;
// wires                                               
wire [9:0] LEDR;

// assign statements (if any)                          
Lab1Pt1 i1 (
// port map - connection between master ports and signals/registers   
	.LEDR(LEDR),
	.SW(SW)
);
initial 
begin 
#1000000 $finish;
end 
// SW[ 9 ]
initial
begin
	SW[9] = 1'b0;
	SW[9] = #10000 1'b1;
	SW[9] = #10000 1'b0;
	SW[9] = #10000 1'b1;
	SW[9] = #10000 1'b0;
	SW[9] = #160000 1'b1;
	SW[9] = #60000 1'b0;
end 
// SW[ 8 ]
initial
begin
	SW[8] = 1'b0;
	SW[8] = #30000 1'b1;
	SW[8] = #10000 1'b0;
	SW[8] = #220000 1'b1;
	SW[8] = #40000 1'b0;
end 
// SW[ 7 ]
initial
begin
	SW[7] = 1'b0;
	SW[7] = #30000 1'b1;
	SW[7] = #10000 1'b0;
	SW[7] = #260000 1'b1;
	SW[7] = #40000 1'b0;
end 
// SW[ 6 ]
initial
begin
	SW[6] = 1'b0;
	SW[6] = #30000 1'b1;
	SW[6] = #10000 1'b0;
	SW[6] = #310000 1'b1;
	SW[6] = #20000 1'b0;
end 
// SW[ 5 ]
initial
begin
	SW[5] = 1'b0;
	SW[5] = #30000 1'b1;
	SW[5] = #10000 1'b0;
	SW[5] = #20000 1'b1;
	SW[5] = #70000 1'b0;
	SW[5] = #240000 1'b1;
	SW[5] = #20000 1'b0;
end 
// SW[ 4 ]
initial
begin
	SW[4] = 1'b0;
	SW[4] = #30000 1'b1;
	SW[4] = #10000 1'b0;
	SW[4] = #350000 1'b1;
	SW[4] = #20000 1'b0;
end 
// SW[ 3 ]
initial
begin
	SW[3] = 1'b0;
	SW[3] = #30000 1'b1;
	SW[3] = #10000 1'b0;
	SW[3] = #370000 1'b1;
	SW[3] = #20000 1'b0;
end 
// SW[ 2 ]
initial
begin
	SW[2] = 1'b0;
	SW[2] = #30000 1'b1;
	SW[2] = #10000 1'b0;
	SW[2] = #390000 1'b1;
	SW[2] = #20000 1'b0;
end 
// SW[ 1 ]
initial
begin
	SW[1] = 1'b0;
	SW[1] = #30000 1'b1;
	SW[1] = #10000 1'b0;
	SW[1] = #410000 1'b1;
	SW[1] = #20000 1'b0;
end 
// SW[ 0 ]
initial
begin
	SW[0] = 1'b0;
	SW[0] = #30000 1'b1;
	SW[0] = #10000 1'b0;
	SW[0] = #430000 1'b1;
	SW[0] = #20000 1'b0;
end 
endmodule