/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Part2 -c Lab1Part2 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Part2 -c Lab1Part2 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vlog -work work Lab1Part2.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst
vcd file -direction Lab1Part2.msim.vcd
vcd add -internal Lab1Part2_vlg_vec_tst/*
vcd add -internal Lab1Part2_vlg_vec_tst/i1/*
proc simTimestamp {} {
    echo "Simulation time: $::now ps"
    if { [string equal running [runStatus]] } {
        after 2500 simTimestamp
    }
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vlog -work work Lab1Part2.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst
vcd file -direction Lab1Part2.msim.vcd
vcd add -internal Lab1Part2_vlg_vec_tst/*
vcd add -internal Lab1Part2_vlg_vec_tst/i1/*
proc simTimestamp {} {
    echo "Simulation time: $::now ps"
    if { [string equal running [runStatus]] } {
        after 2500 simTimestamp
    }
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 2016  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Intel and sold by Intel or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	DATA_OFFSET = 0.0;
	DATA_DURATION = 1000.0;
	SIMULATION_TIME = 0.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("LEDR")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 10;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("LEDR[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("LEDR[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LEDR";
}

SIGNAL("SW")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 10;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("SW[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

SIGNAL("SW[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "SW";
}

TRANSITION_LIST("LEDR[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("LEDR[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("SW[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 560.0;
		LEVEL 0 FOR 430.0;
	}
}

TRANSITION_LIST("SW[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 90.0;
		LEVEL 0 FOR 880.0;
	}
}

TRANSITION_LIST("SW[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 130.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 750.0;
	}
}

TRANSITION_LIST("SW[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 260.0;
		LEVEL 1 FOR 70.0;
		LEVEL 0 FOR 670.0;
	}
}

TRANSITION_LIST("SW[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 330.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 550.0;
	}
}

TRANSITION_LIST("SW[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 460.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 490.0;
	}
}

TRANSITION_LIST("SW[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 510.0;
		LEVEL 1 FOR 70.0;
		LEVEL 0 FOR 420.0;
	}
}

TRANSITION_LIST("SW[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 580.0;
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 360.0;
	}
}

TRANSITION_LIST("SW[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 640.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 310.0;
	}
}

TRANSITION_LIST("SW[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 700.0;
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 240.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "LEDR";
	EXPAND_STATUS = EXPANDED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
	CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "LEDR[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SW";
	EXPAND_STATUS = EXPANDED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 0;
	CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21;
}

DISPLAY_LINE
{
	CHANNEL = "SW[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "SW[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 11;
}

TIME_BAR
{
	TIME = 0;
	MASTER = TRUE;
}
;