TimeQuest Timing Analyzer report for part4 Thu Apr 08 19:14:51 2021 Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation 4. Clocks 5. Slow 1200mV 85C Model Fmax Summary 6. Slow 1200mV 85C Model Setup Summary 7. Slow 1200mV 85C Model Hold Summary 8. Slow 1200mV 85C Model Recovery Summary 9. Slow 1200mV 85C Model Removal Summary 10. Slow 1200mV 85C Model Minimum Pulse Width Summary 11. Slow 1200mV 85C Model Metastability Summary 12. Slow 1200mV 0C Model Fmax Summary 13. Slow 1200mV 0C Model Setup Summary 14. Slow 1200mV 0C Model Hold Summary 15. Slow 1200mV 0C Model Recovery Summary 16. Slow 1200mV 0C Model Removal Summary 17. Slow 1200mV 0C Model Minimum Pulse Width Summary 18. Slow 1200mV 0C Model Metastability Summary 19. Fast 1200mV 0C Model Setup Summary 20. Fast 1200mV 0C Model Hold Summary 21. Fast 1200mV 0C Model Recovery Summary 22. Fast 1200mV 0C Model Removal Summary 23. Fast 1200mV 0C Model Minimum Pulse Width Summary 24. Fast 1200mV 0C Model Metastability Summary 25. Multicorner Timing Analysis Summary 26. Board Trace Model Assignments 27. Input Transition Times 28. Signal Integrity Metrics (Slow 1200mv 0c Model) 29. Signal Integrity Metrics (Slow 1200mv 85c Model) 30. Signal Integrity Metrics (Fast 1200mv 0c Model) 31. Clock Transfers 32. Report TCCS 33. Report RSKM 34. Unconstrained Paths Summary 35. Unconstrained Input Ports 36. Unconstrained Output Ports 37. Unconstrained Input Ports 38. Unconstrained Output Ports 39. TimeQuest Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2016 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +-----------------------+-----------------------------------------------------+ ; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; ; Timing Analyzer ; TimeQuest ; ; Revision Name ; part4 ; ; Device Family ; MAX 10 ; ; Device Name ; 10M50DAF484C6GES ; ; Timing Models ; Preliminary ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +-----------------------+-----------------------------------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 8 ; ; ; ; ; Average used ; 1.02 ; ; Maximum used ; 8 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processors 2-8 ; 0.3% ; +----------------------------+-------------+ ---------- ; Clocks ; ---------- No clocks to report. -------------------------------------- ; Slow 1200mV 85C Model Fmax Summary ; -------------------------------------- No paths to report. --------------------------------------- ; Slow 1200mV 85C Model Setup Summary ; --------------------------------------- No paths to report. -------------------------------------- ; Slow 1200mV 85C Model Hold Summary ; -------------------------------------- No paths to report. ------------------------------------------ ; Slow 1200mV 85C Model Recovery Summary ; ------------------------------------------ No paths to report. ----------------------------------------- ; Slow 1200mV 85C Model Removal Summary ; ----------------------------------------- No paths to report. ----------------------------------------------------- ; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ----------------------------------------------------- No paths to report. ----------------------------------------------- ; Slow 1200mV 85C Model Metastability Summary ; ----------------------------------------------- No synchronizer chains to report. ------------------------------------- ; Slow 1200mV 0C Model Fmax Summary ; ------------------------------------- No paths to report. -------------------------------------- ; Slow 1200mV 0C Model Setup Summary ; -------------------------------------- No paths to report. ------------------------------------- ; Slow 1200mV 0C Model Hold Summary ; ------------------------------------- No paths to report. ----------------------------------------- ; Slow 1200mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Slow 1200mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. ---------------------------------------------------- ; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ---------------------------------------------------- No paths to report. ---------------------------------------------- ; Slow 1200mV 0C Model Metastability Summary ; ---------------------------------------------- No synchronizer chains to report. -------------------------------------- ; Fast 1200mV 0C Model Setup Summary ; -------------------------------------- No paths to report. ------------------------------------- ; Fast 1200mV 0C Model Hold Summary ; ------------------------------------- No paths to report. ----------------------------------------- ; Fast 1200mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Fast 1200mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. ---------------------------------------------------- ; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ---------------------------------------------------- No paths to report. ---------------------------------------------- ; Fast 1200mV 0C Model Metastability Summary ; ---------------------------------------------- No synchronizer chains to report. +----------------------------------------------------------------------------+ ; Multicorner Timing Analysis Summary ; +------------------+-------+------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +------------------+-------+------+----------+---------+---------------------+ ; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; ; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +------------------+-------+------+----------+---------+---------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Board Trace Model Assignments ; +--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; +--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +---------------------------------------------------------------------------------+ ; Input Transition Times ; +---------------------+-----------------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +---------------------+-----------------------+-----------------+-----------------+ ; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; ; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; ; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; ; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +---------------------+-----------------------+-----------------+-----------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 0c Model) ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; ; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 85c Model) ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; ; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0108 V ; 0.13 V ; 0.066 V ; 6.32e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0108 V ; 0.13 V ; 0.066 V ; 6.32e-10 s ; 6.45e-10 s ; No ; Yes ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1200mv 0c Model) ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; ; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ------------------- ; Clock Transfers ; ------------------- Nothing to report. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No non-DPA dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ ; Unconstrained Paths Summary ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 2 ; 2 ; ; Unconstrained Input Port Paths ; 13 ; 13 ; ; Unconstrained Output Ports ; 9 ; 9 ; ; Unconstrained Output Port Paths ; 13 ; 13 ; +---------------------------------+-------+------+ +---------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +------------+--------------------------------------------------------------------------------------+ ; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------+--------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +-------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +-------------+---------------------------------------------------------------------------------------+ ; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +------------+--------------------------------------------------------------------------------------+ ; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------+--------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +-------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +-------------+---------------------------------------------------------------------------------------+ ; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ +------------------------------------+ ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition Info: Processing started: Thu Apr 08 19:14:48 2021 Info: Command: quartus_sta part4 -c part4 Info: qsta_default_script.tcl version: #1 Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Critical Warning (332012): Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Warning (332068): No clocks defined in design. Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info (332159): No clocks to report Info: Analyzing Slow 1200mV 85C Model Info (332140): No fmax paths to report Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Info (332140): No Setup paths to report Info (332140): No Hold paths to report Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332140): No Minimum Pulse Width paths to report Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary Info (334004): Delay annotation completed successfully Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Warning (332068): No clocks defined in design. Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. Info (332140): No fmax paths to report Info (332140): No Setup paths to report Info (332140): No Hold paths to report Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332140): No Minimum Pulse Width paths to report Info: Analyzing Fast 1200mV 0C Model Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Warning (332068): No clocks defined in design. Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. Info (332140): No Setup paths to report Info (332140): No Hold paths to report Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 31 warnings Info: Peak virtual memory: 4869 megabytes Info: Processing ended: Thu Apr 08 19:14:51 2021 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:02