/* ---------------------------------------------------------------------------------------
 *
 *
 *
 *
 */

#include <msp430.h> 
#define   SW1_PRESSED ((BIT0&P1IFG)==0)  // SW1 Status
#define   SW2_PRESSED ((BIT1&P1IFG)==0)  // SW2 Status
int main(void)
{
	WDTCTL = WDTPW | WDTHOLD;	// stop watchdog timer
	P2DIR |= BIT2;                  // Set LED1 as output
	P2OUT = 0x00;                   // clear LED1 status
	_EINT();                        // enable interrupts
	P1IE |= BIT0;                   // P1.0 interrupt enabled
	P1IE |= BIT1;                   // P1.1 interrupt enabled
	P1IES |= BIT0;                  // P1.0 hi/low edge
	P1IFG &= ~BIT0;                 // P1.0 IFG cleared
	P1IES |= BIT1;                  // P1.1 hi/low edge
	P1IFG &= ~BIT1;                 // P1.1 IFG cleared
	FLL_CTL0 |= DCOPLUS + XCAP18PF; // DCO+ set, freq = xtal x D x N+1
    SCFI0 |= FN_4 + FLLD_2;         // DCO range control, multiplier D
    SCFQCTL = 63;                  // (61+1) x 32768 x 2 = 4.19 MHz
	while(1){
	    _delay_cycles(1048576);          // Delay
	    P2OUT ^= BIT2;                  // LED1 is turned ON
	}
}
// Port 1 interrupt service routine
#pragma vector = PORT1_VECTOR
__interrupt void Port1_ISR (void) {
    if(!SW1_PRESSED) {
          //SW1pressed = 1;
          FLL_CTL0 |= DCOPLUS + XCAP18PF; // DCO+ set, freq = xtal x D x N+1
          SCFI0 |= FN_4 + FLLD_2;         // DCO range control, multiplier D
          SCFQCTL = 127;                 // (127+1) x 32768 x 2 = 8.39 MHz
          P1IES |= BIT0;                  // P1.0 hi/low edge
          P1IFG &= ~BIT0;                 // P1.0 IFG cleared
          P1IES |= BIT1;                  // P1.1 hi/low edge
          P1IFG &= ~BIT1;                 // P1.1 IFG cleared
      }
    else if(!SW2_PRESSED) {
          //SW1pressed = 0;
          FLL_CTL0 |= DCOPLUS + XCAP18PF; // DCO+ set, freq = xtal x D x N+1
          SCFI0 |= FN_4 + FLLD_2;         // DCO range control, multiplier D
          SCFQCTL = 31;                  // (31+1) x 32768 x 2 = 2.10 MHz
          P1IES |= BIT0;                  // P1.0 hi/low edge
          P1IFG &= ~BIT0;                 // P1.0 IFG cleared
          P1IES |= BIT1;                  // P1.1 hi/low edge
          P1IFG &= ~BIT1;                 // P1.1 IFG cleared
      }
}