module bcd(IN,OUT);
       input [3:0] IN;
       output [6:0] OUT;
       
       assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000):
                          (IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010):
                          (IN[0]? 7'b0010_010:7'b0011_001)):
                          (IN[1]? (IN[0]? 7'b0110_000:7'b0100_100):
                          (IN[0]? 7'b1111_001:7'b1000_000)));

endmodule

module part5(SW, HEX0, HEX1);
		input [8:0] SW;
		output [6:0] HEX0, HEX1;
		
		reg [4:0] U;
		
		always@(*)
		
		begin
				U = SW[3:0] + SW[7:4] + SW[8];
				if (U > 9) begin
							U[3:0] = U[3:0]-10;
							U[4] = 1;
				end
				
				else		  begin
							  U[4] = 0;
				end
				
		end
		
		bcd b0(U[3:0], HEX0);
		bcd b1(U[4], HEX1);
		
endmodule