module sevenSegment (IN, OUT);
       input [1:0]IN;
		 output reg [6:0]OUT;
		 
		 always @ (*)
		 begin
		        case (IN[1:0])
				        2'b00: OUT=7'b010_0001;
						  2'b01: OUT=7'b000_0110;
						  2'b10: OUT=7'b111_1001;
						  2'b11: OUT=7'b100_0000;
				  endcase
		end
endmodule

module Mux_4to1 (IN1, IN2, IN3, IN4, SEL, M);
       input [1:0]  IN1, IN2, IN3, IN4;
		 input [1:0]  SEL;
		 output reg[1:0] M; 
		 
		 always@(*)
		 begin
		       case(SEL[1:0])
				        2'b00: M=IN1;
						  2'b01: M=IN2;
						  2'b10: M=IN3;
						  2'b11: M=IN4;
				 endcase
		 end
		 
endmodule

module part5 (SW, LEDR, HEX0, HEX1, HEX2, HEX3);
     input [9:0]SW;
	  output [6:0]HEX0, HEX1, HEX2, HEX3;
	  output [9:0]LEDR;
	  
	  wire[1:0] M1, M2, M3, M0;
	  
	  // Chooses 'd' when SW[9:8] is 00
	  Mux_4to1 (SW[7:6], SW[5:4], SW[3:2], SW[1:0], SW[9:8], M3);
	  // Chooses 'E' when SW[9:8] is 00
	  Mux_4to1 (SW[5:4], SW[3:2], SW[1:0], SW[7:6], SW[9:8], M2);
	  // Chooses '1' when SW[9:8] is 00
	  Mux_4to1 (SW[3:2], SW[1:0], SW[7:6], SW[5:4], SW[9:8], M1);
	  // Chooses '0' when SW[9:8] is 00
	  Mux_4to1 (SW[1:0], SW[7:6], SW[5:4], SW[3:2], SW[9:8], M0);
	  
	  sevenSegment S0(M0, HEX0);
	  sevenSegment S1(M1, HEX1);
	  sevenSegment S2(M2, HEX2);
	  sevenSegment S3(M3, HEX3);
	  
	  assign LEDR=SW;
	  
endmodule