$comment
	File created using the following command:
		vcd file part3.msim.vcd -direction
$end
$date
	Sun Apr 25 00:52:04 2021
$end
$version
	ModelSim Version 2020.1
$end
$timescale
	1ps
$end

$scope module part3_vlg_vec_tst $end
$var reg 9 ! SW [8:0] $end
$var wire 1 " LEDR [4] $end
$var wire 1 # LEDR [3] $end
$var wire 1 $ LEDR [2] $end
$var wire 1 % LEDR [1] $end
$var wire 1 & LEDR [0] $end

$scope module i1 $end
$var wire 1 ' gnd $end
$var wire 1 ( vcc $end
$var wire 1 ) unknown $end
$var tri1 1 * devclrn $end
$var tri1 1 + devpor $end
$var tri1 1 , devoe $end
$var wire 1 - ~QUARTUS_CREATED_GND~I_combout $end
$var wire 1 . ~QUARTUS_CREATED_UNVM~~busy $end
$var wire 1 / ~QUARTUS_CREATED_ADC1~~eoc $end
$var wire 1 0 ~QUARTUS_CREATED_ADC2~~eoc $end
$var wire 1 1 LEDR[0]~output_o $end
$var wire 1 2 LEDR[1]~output_o $end
$var wire 1 3 LEDR[2]~output_o $end
$var wire 1 4 LEDR[3]~output_o $end
$var wire 1 5 LEDR[4]~output_o $end
$var wire 1 6 SW[4]~input_o $end
$var wire 1 7 SW[0]~input_o $end
$var wire 1 8 SW[8]~input_o $end
$var wire 1 9 A0|x1~combout $end
$var wire 1 : SW[5]~input_o $end
$var wire 1 ; SW[1]~input_o $end
$var wire 1 < A0|COUT~0_combout $end
$var wire 1 = A1|x1~combout $end
$var wire 1 > SW[2]~input_o $end
$var wire 1 ? SW[6]~input_o $end
$var wire 1 @ A2|x0~combout $end
$var wire 1 A A2|x1~combout $end
$var wire 1 B A2|COUT~2_combout $end
$var wire 1 C A2|COUT~3_combout $end
$var wire 1 D SW[3]~input_o $end
$var wire 1 E SW[7]~input_o $end
$var wire 1 F A3|x1~combout $end
$var wire 1 G A3|COUT~0_combout $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b111000100 !
1&
0%
0$
0#
1"
0'
1(
x)
1*
1+
1,
0-
z.
z/
z0
11
02
03
04
15
06
07
18
19
0:
0;
0<
0=
1>
1?
0@
0A
0B
1C
0D
1E
0F
1G
$end
#400000
b11000100 !
b1000100 !
b100 !
b0 !
08
0E
0?
0>
0C
09
0G
1F
14
05
01
0&
0"
1#
0F
04
0#
#1000000