# do part3.do # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 # Start time: 00:52:03 on Apr 25,2021 # vlog -work work part3.vo # -- Compiling module part3 # -- Compiling module hard_block # # Top level modules: # part3 # End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 # Start time: 00:52:03 on Apr 25,2021 # vlog -work work Waveform1.vwf.vt # -- Compiling module part3_vlg_vec_tst # # Top level modules: # part3_vlg_vec_tst # End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vsim -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst # Start time: 00:52:03 on Apr 25,2021 # Loading work.part3_vlg_vec_tst # Loading work.part3 # Loading work.hard_block # Loading fiftyfivenm_ver.fiftyfivenm_lcell_comb # Loading fiftyfivenm_ver.fiftyfivenm_io_obuf # Loading fiftyfivenm_ver.fiftyfivenm_io_ibuf # Loading fiftyfivenm_ver.fiftyfivenm_unvm # Loading fiftyfivenm_ver.fiftyfivenm_adcblock # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC1~ '. Expected 8, found 7. # Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: part3.vo Line: 481 # ** Warning: (vsim-3722) part3.vo(481): [TFMPC] - Missing connection for port 'clk_dft'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC2~ '. Expected 8, found 7. # Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: part3.vo Line: 504 # ** Warning: (vsim-3722) part3.vo(504): [TFMPC] - Missing connection for port 'clk_dft'. # after#26 # ** Note: $finish : Waveform1.vwf.vt(45) # Time: 1 us Iteration: 0 Instance: /part3_vlg_vec_tst # End time: 00:52:04 on Apr 25,2021, Elapsed time: 0:00:01 # Errors: 0, Warnings: 4