143 lines
3.5 KiB
Plaintext
143 lines
3.5 KiB
Plaintext
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// Copyright (C) 2016 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel MegaCore Function License Agreement, or other
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// applicable license agreement, including, without limitation,
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// that your use is for the sole purpose of programming logic
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// devices manufactured by Intel and sold by Intel or its
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// authorized distributors. Please refer to the applicable
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// agreement for further details.
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// *****************************************************************************
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// This file contains a Verilog test bench with test vectors .The test vectors
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// are exported from a vector file in the Quartus Waveform Editor and apply to
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// the top level entity of the current Quartus project .The user can use this
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// testbench to simulate his design using a third-party simulation tool .
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// *****************************************************************************
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// Generated on "02/25/2021 20:02:10"
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// Verilog Test Bench (with test vectors) for design : Lab1Pt1
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//
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// Simulation tool : 3rd Party
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//
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`timescale 1 ps/ 1 ps
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module Lab1Pt1_vlg_vec_tst();
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// constants
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// general purpose registers
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reg [9:0] SW;
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// wires
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wire [9:0] LEDR;
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// assign statements (if any)
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Lab1Pt1 i1 (
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// port map - connection between master ports and signals/registers
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.LEDR(LEDR),
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.SW(SW)
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);
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initial
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begin
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#1000000 $finish;
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end
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// SW[ 9 ]
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initial
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begin
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SW[9] = 1'b0;
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SW[9] = #10000 1'b1;
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SW[9] = #10000 1'b0;
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SW[9] = #10000 1'b1;
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SW[9] = #10000 1'b0;
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SW[9] = #160000 1'b1;
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SW[9] = #60000 1'b0;
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end
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// SW[ 8 ]
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initial
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begin
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SW[8] = 1'b0;
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SW[8] = #30000 1'b1;
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SW[8] = #10000 1'b0;
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SW[8] = #220000 1'b1;
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SW[8] = #40000 1'b0;
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end
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// SW[ 7 ]
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initial
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begin
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SW[7] = 1'b0;
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SW[7] = #30000 1'b1;
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SW[7] = #10000 1'b0;
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SW[7] = #260000 1'b1;
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SW[7] = #40000 1'b0;
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end
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// SW[ 6 ]
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initial
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begin
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SW[6] = 1'b0;
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SW[6] = #30000 1'b1;
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SW[6] = #10000 1'b0;
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SW[6] = #310000 1'b1;
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SW[6] = #20000 1'b0;
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end
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// SW[ 5 ]
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initial
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begin
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SW[5] = 1'b0;
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SW[5] = #30000 1'b1;
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SW[5] = #10000 1'b0;
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SW[5] = #20000 1'b1;
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SW[5] = #70000 1'b0;
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SW[5] = #240000 1'b1;
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SW[5] = #20000 1'b0;
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end
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// SW[ 4 ]
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initial
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begin
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SW[4] = 1'b0;
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SW[4] = #30000 1'b1;
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SW[4] = #10000 1'b0;
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SW[4] = #350000 1'b1;
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SW[4] = #20000 1'b0;
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end
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// SW[ 3 ]
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initial
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begin
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SW[3] = 1'b0;
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SW[3] = #30000 1'b1;
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SW[3] = #10000 1'b0;
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SW[3] = #370000 1'b1;
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SW[3] = #20000 1'b0;
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end
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// SW[ 2 ]
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initial
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begin
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SW[2] = 1'b0;
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SW[2] = #30000 1'b1;
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SW[2] = #10000 1'b0;
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SW[2] = #390000 1'b1;
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SW[2] = #20000 1'b0;
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end
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// SW[ 1 ]
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initial
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begin
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SW[1] = 1'b0;
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SW[1] = #30000 1'b1;
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SW[1] = #10000 1'b0;
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SW[1] = #410000 1'b1;
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SW[1] = #20000 1'b0;
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end
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// SW[ 0 ]
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initial
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begin
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SW[0] = 1'b0;
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SW[0] = #30000 1'b1;
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SW[0] = #10000 1'b0;
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SW[0] = #430000 1'b1;
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SW[0] = #20000 1'b0;
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end
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endmodule
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