159 lines
12 KiB
Plaintext
159 lines
12 KiB
Plaintext
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Flow report for part3
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Sun Apr 25 00:52:01 2021
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Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Flow Summary
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3. Flow Settings
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4. Flow Non-Default Global Settings
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5. Flow Elapsed Time
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6. Flow OS Summary
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7. Flow Log
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8. Flow Messages
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9. Flow Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Flow Summary ;
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+------------------------------------+---------------------------------------------+
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; Flow Status ; Successful - Sun Apr 25 00:52:01 2021 ;
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; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
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; Revision Name ; part3 ;
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; Top-level Entity Name ; part3 ;
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; Family ; MAX 10 ;
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; Device ; 10M50DAF484C6GES ;
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; Timing Models ; Preliminary ;
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; Total logic elements ; 10 / 49,760 ( < 1 % ) ;
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; Total combinational functions ; 10 / 49,760 ( < 1 % ) ;
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; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ;
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; Total registers ; 0 ;
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; Total pins ; 14 / 360 ( 4 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 / 1,677,312 ( 0 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
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; Total PLLs ; 0 / 4 ( 0 % ) ;
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; UFM blocks ; 0 / 1 ( 0 % ) ;
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; ADC blocks ; 0 / 2 ( 0 % ) ;
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+------------------------------------+---------------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 04/25/2021 00:24:59 ;
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; Main task ; Compilation ;
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; Revision Name ; part3 ;
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+-------------------+---------------------+
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+-------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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+-------------------------------------+----------------------------------------+---------------+-------------+------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+-------------------------------------+----------------------------------------+---------------+-------------+------------+
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; COMPILER_SIGNATURE_ID ; 164639278517.161932829928305 ; -- ; -- ; -- ;
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; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1 ; Top ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1 ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1 ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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+-------------------------------------+----------------------------------------+---------------+-------------+------------+
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+--------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:00:15 ; 1.0 ; 390 MB ; 00:00:31 ;
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; Fitter ; 00:00:12 ; 1.0 ; 1079 MB ; 00:00:16 ;
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; Assembler ; 00:00:04 ; 1.0 ; 358 MB ; 00:00:05 ;
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; Timing Analyzer ; 00:00:03 ; 1.0 ; 508 MB ; 00:00:03 ;
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; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 593 MB ; 00:00:01 ;
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; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 597 MB ; 00:00:01 ;
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; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4656 MB ; 00:00:01 ;
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; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4660 MB ; 00:00:01 ;
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; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4652 MB ; 00:00:01 ;
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; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4660 MB ; 00:00:01 ;
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; Total ; 00:00:40 ; -- ; -- ; 00:01:01 ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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+-------------------------------------------------------------------------------------------+
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; Flow OS Summary ;
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+----------------------+-------------------+------------------+------------+----------------+
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; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
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+----------------------+-------------------+------------------+------------+----------------+
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; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
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; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
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; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
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; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
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; EDA Netlist Writer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
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; EDA Netlist Writer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
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; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ;
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; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ;
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; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ;
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; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ;
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+----------------------+-------------------+------------------+------------+----------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3
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quartus_fit --read_settings_files=off --write_settings_files=off part3 -c part3
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quartus_asm --read_settings_files=off --write_settings_files=off part3 -c part3
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quartus_sta part3 -c part3
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quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform.vwf" --testbench_file="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform.vwf.vt"
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quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3
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quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt"
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quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3
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quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt"
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quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3
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