53 lines
34 KiB
Plaintext
53 lines
34 KiB
Plaintext
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1619383438863 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619383438864 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "part5 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"part5\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619383438876 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619383438980 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619383438980 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1619383439421 ""}
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{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619383439446 ""}
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{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7P " "Device 10M08DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484A7G " "Device 10M16DAF484A7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7P " "Device 10M16DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484A7G " "Device 10M25DAF484A7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619383439669 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619383439669 ""}
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{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 129 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 131 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 135 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 137 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 139 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 0 { 0 ""} 0 141 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619383439690 ""} { "In
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{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619383439692 ""}
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{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619383439692 ""}
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{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619383439692 ""}
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{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1619383439692 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1619383439698 ""}
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{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part5.sdc " "Synopsys Design Constraints File file not found: 'part5.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1619383440494 ""}
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{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1619383440497 ""}
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{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1619383440512 ""}
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{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1619383440516 ""}
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{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1619383440530 ""}
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{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1619383440530 ""}
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{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1619383440534 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1619383440547 ""}
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{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619383440547 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619383440548 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619383440549 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619383440550 ""}
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{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1619383440551 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1619383440551 ""}
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{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1619383440551 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1619383440551 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1619383440552 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619383440552 ""}
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{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/andrew/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619383440599 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/ho
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{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383440601 ""}
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{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1619383440625 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619383443979 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383444137 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619383444207 ""}
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{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619383444767 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383444767 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619383445585 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X56_Y44 X66_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54" { } { { "loc" "" { Generic "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X56_Y44 to location X66_Y54"} { { 12 { 0 ""} 56 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1619383449375 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619383449375 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1619383449642 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1619383449642 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1619383449642 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383449645 ""}
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{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1619383449973 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619383449993 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619383450512 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619383450512 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619383451060 ""}
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{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619383451765 ""}
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{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1619383451973 ""}
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg " "Generated suppressed messages file /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part5/output_files/part5.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619383452183 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 32 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1082 " "Peak virtual memory: 1082 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619383452839 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 15:44:12 2021 " "Processing ended: Sun Apr 25 15:44:12 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619383452839 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619383452839 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619383452839 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619383452839 ""}
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