741 lines
12 KiB
Plaintext
741 lines
12 KiB
Plaintext
|
/*<simulation_settings>
|
||
|
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work Part3.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Part3_vlg_vec_tst
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vcd file -direction Part3.msim.vcd
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vcd add -internal Part3_vlg_vec_tst/*
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vcd add -internal Part3_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work Part3.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Part3_vlg_vec_tst
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vcd file -direction Part3.msim.vcd
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vcd add -internal Part3_vlg_vec_tst/*
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vcd add -internal Part3_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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|
editor if you plan to continue editing the block that represents it in
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|
the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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|
Copyright (C) 2016 Intel Corporation. All rights reserved.
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|
Your use of Intel Corporation's design tools, logic functions
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|
and other software and tools, and its AMPP partner logic
|
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|
functions, and any output files from any of the foregoing
|
||
|
(including device programming or simulation files), and any
|
||
|
associated documentation or information are expressly subject
|
||
|
to the terms and conditions of the Intel Program License
|
||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
the Intel MegaCore Function License Agreement, or other
|
||
|
applicable license agreement, including, without limitation,
|
||
|
that your use is for the sole purpose of programming logic
|
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|
devices manufactured by Intel and sold by Intel or its
|
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|
authorized distributors. Please refer to the applicable
|
||
|
agreement for further details.
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|
*/
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HEADER
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|
{
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|
VERSION = 1;
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|
TIME_UNIT = ns;
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|
DATA_OFFSET = 0.0;
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|
DATA_DURATION = 1000.0;
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|
SIMULATION_TIME = 0.0;
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|
GRID_PHASE = 0.0;
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|
GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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|
}
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|
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|
SIGNAL("LEDR")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = BUS;
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|
WIDTH = 10;
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|
LSB_INDEX = 0;
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||
|
DIRECTION = OUTPUT;
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||
|
PARENT = "";
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||
|
}
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||
|
|
||
|
SIGNAL("LEDR[9]")
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||
|
{
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||
|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
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||
|
WIDTH = 1;
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||
|
LSB_INDEX = -1;
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||
|
DIRECTION = OUTPUT;
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||
|
PARENT = "LEDR";
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||
|
}
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||
|
|
||
|
SIGNAL("LEDR[8]")
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||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
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||
|
SIGNAL_TYPE = SINGLE_BIT;
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||
|
WIDTH = 1;
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||
|
LSB_INDEX = -1;
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||
|
DIRECTION = OUTPUT;
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||
|
PARENT = "LEDR";
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||
|
}
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||
|
|
||
|
SIGNAL("LEDR[7]")
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||
|
{
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||
|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
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||
|
WIDTH = 1;
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||
|
LSB_INDEX = -1;
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||
|
DIRECTION = OUTPUT;
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||
|
PARENT = "LEDR";
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||
|
}
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||
|
|
||
|
SIGNAL("LEDR[6]")
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||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
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||
|
SIGNAL_TYPE = SINGLE_BIT;
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||
|
WIDTH = 1;
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||
|
LSB_INDEX = -1;
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||
|
DIRECTION = OUTPUT;
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||
|
PARENT = "LEDR";
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||
|
}
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||
|
|
||
|
SIGNAL("LEDR[5]")
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||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
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||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
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||
|
LSB_INDEX = -1;
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||
|
DIRECTION = OUTPUT;
|
||
|
PARENT = "LEDR";
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||
|
}
|
||
|
|
||
|
SIGNAL("LEDR[4]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
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||
|
DIRECTION = OUTPUT;
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||
|
PARENT = "LEDR";
|
||
|
}
|
||
|
|
||
|
SIGNAL("LEDR[3]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = OUTPUT;
|
||
|
PARENT = "LEDR";
|
||
|
}
|
||
|
|
||
|
SIGNAL("LEDR[2]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = OUTPUT;
|
||
|
PARENT = "LEDR";
|
||
|
}
|
||
|
|
||
|
SIGNAL("LEDR[1]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = OUTPUT;
|
||
|
PARENT = "LEDR";
|
||
|
}
|
||
|
|
||
|
SIGNAL("LEDR[0]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = OUTPUT;
|
||
|
PARENT = "LEDR";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = BUS;
|
||
|
WIDTH = 10;
|
||
|
LSB_INDEX = 0;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[9]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[8]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[7]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[6]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[5]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[4]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[3]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[2]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[1]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
SIGNAL("SW[0]")
|
||
|
{
|
||
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
WIDTH = 1;
|
||
|
LSB_INDEX = -1;
|
||
|
DIRECTION = INPUT;
|
||
|
PARENT = "SW";
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[9]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[8]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[7]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[6]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[5]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[4]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[3]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[2]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[1]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("LEDR[0]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 1000.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[9]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL 0 FOR 470.0;
|
||
|
LEVEL 1 FOR 530.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[8]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL 0 FOR 230.0;
|
||
|
LEVEL 1 FOR 240.0;
|
||
|
LEVEL 0 FOR 270.0;
|
||
|
LEVEL 1 FOR 260.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[7]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 740.0;
|
||
|
LEVEL 1 FOR 70.0;
|
||
|
LEVEL 0 FOR 90.0;
|
||
|
LEVEL 1 FOR 100.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[6]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 740.0;
|
||
|
LEVEL 1 FOR 70.0;
|
||
|
LEVEL 0 FOR 90.0;
|
||
|
LEVEL 1 FOR 100.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[5]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 470.0;
|
||
|
LEVEL 1 FOR 80.0;
|
||
|
LEVEL 0 FOR 90.0;
|
||
|
LEVEL 1 FOR 100.0;
|
||
|
LEVEL X FOR 260.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[4]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 470.0;
|
||
|
LEVEL 1 FOR 80.0;
|
||
|
LEVEL 0 FOR 90.0;
|
||
|
LEVEL 1 FOR 100.0;
|
||
|
LEVEL X FOR 260.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[3]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 230.0;
|
||
|
LEVEL 0 FOR 80.0;
|
||
|
LEVEL 1 FOR 80.0;
|
||
|
LEVEL 0 FOR 80.0;
|
||
|
LEVEL X FOR 530.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[2]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL X FOR 230.0;
|
||
|
LEVEL 0 FOR 80.0;
|
||
|
LEVEL 1 FOR 80.0;
|
||
|
LEVEL 0 FOR 80.0;
|
||
|
LEVEL X FOR 530.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[1]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL 0 FOR 40.0;
|
||
|
LEVEL 1 FOR 60.0;
|
||
|
LEVEL 0 FOR 80.0;
|
||
|
LEVEL 1 FOR 50.0;
|
||
|
LEVEL X FOR 770.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
TRANSITION_LIST("SW[0]")
|
||
|
{
|
||
|
NODE
|
||
|
{
|
||
|
REPEAT = 1;
|
||
|
LEVEL 0 FOR 40.0;
|
||
|
LEVEL 1 FOR 60.0;
|
||
|
LEVEL 0 FOR 80.0;
|
||
|
LEVEL 1 FOR 50.0;
|
||
|
LEVEL X FOR 770.0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR";
|
||
|
EXPAND_STATUS = EXPANDED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 0;
|
||
|
TREE_LEVEL = 0;
|
||
|
CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[9]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 1;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[8]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 2;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[7]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 3;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[6]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 4;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[5]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 5;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[4]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 6;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[3]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 7;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[2]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 8;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[1]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 9;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "LEDR[0]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 10;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 0;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW";
|
||
|
EXPAND_STATUS = EXPANDED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 11;
|
||
|
TREE_LEVEL = 0;
|
||
|
CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[9]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 12;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[8]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 13;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[7]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 14;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[6]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 15;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[5]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 16;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[4]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 17;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[3]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 18;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[2]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 19;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[1]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 20;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
DISPLAY_LINE
|
||
|
{
|
||
|
CHANNEL = "SW[0]";
|
||
|
EXPAND_STATUS = COLLAPSED;
|
||
|
RADIX = Binary;
|
||
|
TREE_INDEX = 21;
|
||
|
TREE_LEVEL = 1;
|
||
|
PARENT = 11;
|
||
|
}
|
||
|
|
||
|
TIME_BAR
|
||
|
{
|
||
|
TIME = 0;
|
||
|
MASTER = TRUE;
|
||
|
}
|
||
|
;
|