135 lines
9.1 KiB
Plaintext
135 lines
9.1 KiB
Plaintext
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Flow report for Part3
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Thu Mar 11 20:47:38 2021
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Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Flow Summary
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3. Flow Settings
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4. Flow Non-Default Global Settings
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5. Flow Elapsed Time
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6. Flow OS Summary
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7. Flow Log
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8. Flow Messages
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9. Flow Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2016 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Intel and sold by Intel or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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+----------------------------------------------------------------------------------+
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; Flow Summary ;
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+------------------------------------+---------------------------------------------+
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; Flow Status ; Successful - Thu Mar 11 20:47:38 2021 ;
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; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
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; Revision Name ; Part3 ;
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; Top-level Entity Name ; Part3 ;
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; Family ; MAX 10 ;
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; Device ; 10M50DAF484C7G ;
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; Timing Models ; Final ;
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; Total logic elements ; 4 / 49,760 ( < 1 % ) ;
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; Total combinational functions ; 4 / 49,760 ( < 1 % ) ;
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; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ;
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; Total registers ; 0 ;
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; Total pins ; 20 / 360 ( 6 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 / 1,677,312 ( 0 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
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; Total PLLs ; 0 / 4 ( 0 % ) ;
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; UFM blocks ; 0 / 1 ( 0 % ) ;
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; ADC blocks ; 0 / 2 ( 0 % ) ;
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+------------------------------------+---------------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 03/11/2021 20:43:20 ;
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; Main task ; Compilation ;
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; Revision Name ; Part3 ;
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+-------------------+---------------------+
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+-------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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+-------------------------------------+----------------------------------------+---------------+-------------+------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+-------------------------------------+----------------------------------------+---------------+-------------+------------+
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; COMPILER_SIGNATURE_ID ; 189559947077153.161551700008156 ; -- ; -- ; -- ;
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; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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+-------------------------------------+----------------------------------------+---------------+-------------+------------+
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+-------------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time ;
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4781 MB ; 00:00:22 ;
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; Fitter ; 00:00:07 ; 1.0 ; 5904 MB ; 00:00:10 ;
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; Assembler ; 00:00:04 ; 1.0 ; 4684 MB ; 00:00:03 ;
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; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:01 ;
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; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4867 MB ; 00:00:02 ;
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; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:01 ;
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; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:01 ;
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; Total ; 00:00:23 ; -- ; -- ; 00:00:40 ;
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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+-----------------------------------------------------------------------------------------+
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; Flow OS Summary ;
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+---------------------------+------------------+------------+------------+----------------+
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; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
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+---------------------------+------------------+------------+------------+----------------+
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; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
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; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
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; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
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; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
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; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
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; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
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; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
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+---------------------------+------------------+------------+------------+----------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off Part3 -c Part3
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quartus_fit --read_settings_files=off --write_settings_files=off Part3 -c Part3
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quartus_asm --read_settings_files=off --write_settings_files=off Part3 -c Part3
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quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3
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quartus_sta Part3 -c Part3
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quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt"
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quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3
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