484 lines
59 KiB
Plaintext
484 lines
59 KiB
Plaintext
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TimeQuest Timing Analyzer report for Part3
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Thu Mar 11 20:43:50 2021
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Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. TimeQuest Timing Analyzer Summary
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3. Parallel Compilation
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4. Clocks
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5. Slow 1200mV 85C Model Fmax Summary
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6. Slow 1200mV 85C Model Setup Summary
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7. Slow 1200mV 85C Model Hold Summary
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8. Slow 1200mV 85C Model Recovery Summary
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9. Slow 1200mV 85C Model Removal Summary
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10. Slow 1200mV 85C Model Minimum Pulse Width Summary
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11. Slow 1200mV 85C Model Metastability Summary
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12. Slow 1200mV 0C Model Fmax Summary
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13. Slow 1200mV 0C Model Setup Summary
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14. Slow 1200mV 0C Model Hold Summary
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15. Slow 1200mV 0C Model Recovery Summary
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16. Slow 1200mV 0C Model Removal Summary
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17. Slow 1200mV 0C Model Minimum Pulse Width Summary
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18. Slow 1200mV 0C Model Metastability Summary
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19. Fast 1200mV 0C Model Setup Summary
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20. Fast 1200mV 0C Model Hold Summary
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21. Fast 1200mV 0C Model Recovery Summary
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22. Fast 1200mV 0C Model Removal Summary
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23. Fast 1200mV 0C Model Minimum Pulse Width Summary
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24. Fast 1200mV 0C Model Metastability Summary
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25. Multicorner Timing Analysis Summary
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26. Board Trace Model Assignments
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27. Input Transition Times
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28. Signal Integrity Metrics (Slow 1200mv 0c Model)
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29. Signal Integrity Metrics (Slow 1200mv 85c Model)
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30. Signal Integrity Metrics (Fast 1200mv 0c Model)
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31. Clock Transfers
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32. Report TCCS
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33. Report RSKM
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34. Unconstrained Paths Summary
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35. Unconstrained Input Ports
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36. Unconstrained Output Ports
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37. Unconstrained Input Ports
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38. Unconstrained Output Ports
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39. TimeQuest Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2016 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Intel and sold by Intel or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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+-----------------------------------------------------------------------------+
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; TimeQuest Timing Analyzer Summary ;
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+-----------------------+-----------------------------------------------------+
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; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
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; Timing Analyzer ; TimeQuest ;
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; Revision Name ; Part3 ;
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; Device Family ; MAX 10 ;
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; Device Name ; 10M50DAF484C7G ;
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; Timing Models ; Final ;
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; Delay Model ; Combined ;
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; Rise/Fall Delays ; Enabled ;
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+-----------------------+-----------------------------------------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 8 ;
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; ; ;
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; Average used ; 1.02 ;
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; Maximum used ; 8 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processors 2-8 ; 0.3% ;
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+----------------------------+-------------+
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----------
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; Clocks ;
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----------
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No clocks to report.
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--------------------------------------
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; Slow 1200mV 85C Model Fmax Summary ;
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--------------------------------------
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No paths to report.
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---------------------------------------
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; Slow 1200mV 85C Model Setup Summary ;
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---------------------------------------
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No paths to report.
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--------------------------------------
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; Slow 1200mV 85C Model Hold Summary ;
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--------------------------------------
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No paths to report.
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------------------------------------------
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; Slow 1200mV 85C Model Recovery Summary ;
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------------------------------------------
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No paths to report.
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-----------------------------------------
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; Slow 1200mV 85C Model Removal Summary ;
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-----------------------------------------
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No paths to report.
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-----------------------------------------------------
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; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
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-----------------------------------------------------
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No paths to report.
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-----------------------------------------------
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; Slow 1200mV 85C Model Metastability Summary ;
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-----------------------------------------------
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No synchronizer chains to report.
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-------------------------------------
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; Slow 1200mV 0C Model Fmax Summary ;
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-------------------------------------
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No paths to report.
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--------------------------------------
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; Slow 1200mV 0C Model Setup Summary ;
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--------------------------------------
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No paths to report.
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-------------------------------------
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; Slow 1200mV 0C Model Hold Summary ;
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-------------------------------------
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No paths to report.
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-----------------------------------------
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; Slow 1200mV 0C Model Recovery Summary ;
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-----------------------------------------
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No paths to report.
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----------------------------------------
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; Slow 1200mV 0C Model Removal Summary ;
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----------------------------------------
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No paths to report.
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----------------------------------------------------
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; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
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----------------------------------------------------
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No paths to report.
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----------------------------------------------
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; Slow 1200mV 0C Model Metastability Summary ;
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----------------------------------------------
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No synchronizer chains to report.
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--------------------------------------
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; Fast 1200mV 0C Model Setup Summary ;
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--------------------------------------
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No paths to report.
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-------------------------------------
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; Fast 1200mV 0C Model Hold Summary ;
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-------------------------------------
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No paths to report.
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-----------------------------------------
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; Fast 1200mV 0C Model Recovery Summary ;
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-----------------------------------------
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No paths to report.
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----------------------------------------
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; Fast 1200mV 0C Model Removal Summary ;
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----------------------------------------
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No paths to report.
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----------------------------------------------------
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; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
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----------------------------------------------------
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No paths to report.
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----------------------------------------------
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; Fast 1200mV 0C Model Metastability Summary ;
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----------------------------------------------
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No synchronizer chains to report.
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+----------------------------------------------------------------------------+
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; Multicorner Timing Analysis Summary ;
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+------------------+-------+------+----------+---------+---------------------+
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; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
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+------------------+-------+------+----------+---------+---------------------+
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; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
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; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
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+------------------+-------+------+----------+---------+---------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Board Trace Model Assignments ;
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+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
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+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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+---------------------------------------------------------------------------------+
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; Input Transition Times ;
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+---------------------+-----------------------+-----------------+-----------------+
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; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
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+---------------------+-----------------------+-----------------+-----------------+
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; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
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; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
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; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
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; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
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; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ;
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; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
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; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
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; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
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+---------------------+-----------------------+-----------------+-----------------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
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+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
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+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
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; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
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; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
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; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
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; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
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; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
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; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ;
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; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0783 V ; 0.157 V ; 0.167 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0783 V ; 0.157 V ; 0.167 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ;
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; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
|
||
|
|
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ;
|
||
|
|
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
|
||
|
|
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||
|
|
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ;
|
||
|
|
; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ;
|
||
|
|
; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ;
|
||
|
|
; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ;
|
||
|
|
; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ;
|
||
|
|
; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ;
|
||
|
|
; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ;
|
||
|
|
; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0459 V ; 0.201 V ; 0.093 V ; 4.9e-10 s ; 5.83e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0459 V ; 0.201 V ; 0.093 V ; 4.9e-10 s ; 5.83e-10 s ; Yes ; No ;
|
||
|
|
; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ;
|
||
|
|
; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ;
|
||
|
|
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ;
|
||
|
|
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
|
||
|
|
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||
|
|
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.77 V ; -0.0485 V ; 0.289 V ; 0.058 V ; 2.81e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.77 V ; -0.0485 V ; 0.289 V ; 0.058 V ; 2.81e-10 s ; 3.04e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ;
|
||
|
|
; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
|
||
|
|
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ;
|
||
|
|
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
-------------------
|
||
|
|
; Clock Transfers ;
|
||
|
|
-------------------
|
||
|
|
Nothing to report.
|
||
|
|
|
||
|
|
|
||
|
|
---------------
|
||
|
|
; Report TCCS ;
|
||
|
|
---------------
|
||
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
||
|
|
|
||
|
|
|
||
|
|
---------------
|
||
|
|
; Report RSKM ;
|
||
|
|
---------------
|
||
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------+
|
||
|
|
; Unconstrained Paths Summary ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
; Property ; Setup ; Hold ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
; Illegal Clocks ; 0 ; 0 ;
|
||
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
||
|
|
; Unconstrained Input Ports ; 8 ; 8 ;
|
||
|
|
; Unconstrained Input Port Paths ; 9 ; 9 ;
|
||
|
|
; Unconstrained Output Ports ; 2 ; 2 ;
|
||
|
|
; Unconstrained Output Port Paths ; 9 ; 9 ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Input Ports ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; Input Port ; Comment ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Output Ports ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; Output Port ; Comment ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Input Ports ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; Input Port ; Comment ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Output Ports ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; Output Port ; Comment ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------+
|
||
|
|
; TimeQuest Timing Analyzer Messages ;
|
||
|
|
+------------------------------------+
|
||
|
|
Info: *******************************************************************
|
||
|
|
Info: Running Quartus Prime TimeQuest Timing Analyzer
|
||
|
|
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
|
||
|
|
Info: Processing started: Thu Mar 11 20:43:47 2021
|
||
|
|
Info: Command: quartus_sta Part3 -c Part3
|
||
|
|
Info: qsta_default_script.tcl version: #1
|
||
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||
|
|
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
|
||
|
|
Info (21077): Low junction temperature is 0 degrees C
|
||
|
|
Info (21077): High junction temperature is 85 degrees C
|
||
|
|
Critical Warning (332012): Synopsys Design Constraints File file not found: 'Part3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||
|
|
Warning (332068): No clocks defined in design.
|
||
|
|
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||
|
|
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||
|
|
Info (332159): No clocks to report
|
||
|
|
Info: Analyzing Slow 1200mV 85C Model
|
||
|
|
Info (332140): No fmax paths to report
|
||
|
|
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
|
||
|
|
Info (332140): No Setup paths to report
|
||
|
|
Info (332140): No Hold paths to report
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332140): No Minimum Pulse Width paths to report
|
||
|
|
Info: Analyzing Slow 1200mV 0C Model
|
||
|
|
Info (334003): Started post-fitting delay annotation
|
||
|
|
Info (334004): Delay annotation completed successfully
|
||
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||
|
|
Warning (332068): No clocks defined in design.
|
||
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||
|
|
Info (332140): No fmax paths to report
|
||
|
|
Info (332140): No Setup paths to report
|
||
|
|
Info (332140): No Hold paths to report
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332140): No Minimum Pulse Width paths to report
|
||
|
|
Info: Analyzing Fast 1200mV 0C Model
|
||
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||
|
|
Warning (332068): No clocks defined in design.
|
||
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||
|
|
Info (332140): No Setup paths to report
|
||
|
|
Info (332140): No Hold paths to report
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332140): No Minimum Pulse Width paths to report
|
||
|
|
Info (332102): Design is not fully constrained for setup requirements
|
||
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Info (332102): Design is not fully constrained for hold requirements
|
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Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
|
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Info: Peak virtual memory: 4867 megabytes
|
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Info: Processing ended: Thu Mar 11 20:43:50 2021
|
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Info: Elapsed time: 00:00:03
|
||
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Info: Total CPU time (on all processors): 00:00:02
|
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