98 lines
2.5 KiB
Plaintext
98 lines
2.5 KiB
Plaintext
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// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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// *****************************************************************************
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// This file contains a Verilog test bench with test vectors .The test vectors
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// are exported from a vector file in the Quartus Waveform Editor and apply to
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// the top level entity of the current Quartus project .The user can use this
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// testbench to simulate his design using a third-party simulation tool .
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// *****************************************************************************
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// Generated on "04/25/2021 00:26:26"
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// Verilog Test Bench (with test vectors) for design : part3
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//
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// Simulation tool : 3rd Party
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//
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`timescale 1 ps/ 1 ps
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module part3_vlg_vec_tst();
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// constants
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// general purpose registers
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reg [8:0] SW;
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// wires
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wire [4:0] LEDR;
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// assign statements (if any)
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part3 i1 (
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// port map - connection between master ports and signals/registers
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.LEDR(LEDR),
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.SW(SW)
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);
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initial
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begin
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#1000000 $finish;
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end
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// SW[ 8 ]
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initial
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begin
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SW[8] = 1'b1;
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SW[8] = #280000 1'b0;
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end
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// SW[ 7 ]
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initial
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begin
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SW[7] = 1'b1;
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SW[7] = #280000 1'b0;
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end
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// SW[ 6 ]
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initial
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begin
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SW[6] = 1'b1;
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SW[6] = #280000 1'b0;
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end
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// SW[ 5 ]
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initial
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begin
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SW[5] = 1'b0;
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end
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// SW[ 4 ]
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initial
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begin
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SW[4] = 1'b0;
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end
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// SW[ 3 ]
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initial
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begin
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SW[3] = 1'b0;
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end
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// SW[ 2 ]
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initial
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begin
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SW[2] = 1'b1;
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SW[2] = #280000 1'b0;
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end
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// SW[ 1 ]
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initial
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begin
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SW[1] = 1'b0;
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end
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// SW[ 0 ]
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initial
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begin
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SW[0] = 1'b0;
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end
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endmodule
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