109 lines
7.0 KiB
Plaintext
109 lines
7.0 KiB
Plaintext
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EDA Netlist Writer report for Lab1Pt1
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Thu Feb 25 20:02:11 2021
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Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. EDA Netlist Writer Summary
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3. Simulation Settings
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4. Simulation Generated Files
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5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2016 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Intel and sold by Intel or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Thu Feb 25 20:02:11 2021 ;
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; Revision Name ; Lab1Pt1 ;
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; Top-level Entity Name ; Lab1Pt1 ;
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; Family ; MAX 10 ;
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; Simulation Files Creation ; Successful ;
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+---------------------------+---------------------------------------+
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+-------------------------------------------------------------------------------------------------------------------------------+
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; Simulation Settings ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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; Option ; Setting ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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; Tool Name ; ModelSim-Altera (Verilog) ;
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; Generate functional simulation netlist ; On ;
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; Truncate long hierarchy paths ; Off ;
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; Map illegal HDL characters ; Off ;
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; Flatten buses into individual nodes ; Off ;
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; Maintain hierarchy ; Off ;
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; Bring out device-wide set/reset signals as ports ; Off ;
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; Enable glitch filtering ; Off ;
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; Do not write top level VHDL entity ; Off ;
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; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
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; Architecture name in VHDL output netlist ; structure ;
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; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
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; Generate third-party EDA tool command script for gate-level simulation ; Off ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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+----------------------------------------------------------------------------------+
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; Simulation Generated Files ;
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+----------------------------------------------------------------------------------+
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; Generated Files ;
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+----------------------------------------------------------------------------------+
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; C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim//Lab1Pt1.vo ;
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+----------------------------------------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
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Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
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Info: Your use of Intel Corporation's design tools, logic functions
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|
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Info: and other software and tools, and its AMPP partner logic
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||
|
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Info: functions, and any output files from any of the foregoing
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|
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Info: (including device programming or simulation files), and any
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||
|
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Info: associated documentation or information are expressly subject
|
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|
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Info: to the terms and conditions of the Intel Program License
|
||
|
|
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
|
Info: the Intel MegaCore Function License Agreement, or other
|
||
|
|
Info: applicable license agreement, including, without limitation,
|
||
|
|
Info: that your use is for the sole purpose of programming logic
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||
|
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Info: devices manufactured by Intel and sold by Intel or its
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|
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Info: authorized distributors. Please refer to the applicable
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Info: agreement for further details.
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Info: Processing started: Thu Feb 25 20:02:10 2021
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Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (204019): Generated file Lab1Pt1.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim//" for EDA simulation tool
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Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 4641 megabytes
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Info: Processing ended: Thu Feb 25 20:02:11 2021
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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