142 lines
7.4 KiB
Plaintext
142 lines
7.4 KiB
Plaintext
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Determining the location of the ModelSim executable...
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Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/
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To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
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Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
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**** Generating the ModelSim Testbench ****
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quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt"
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
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Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
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Info: Your use of Intel Corporation's design tools, logic functions
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Info: and other software and tools, and its AMPP partner logic
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Info: functions, and any output files from any of the foregoing
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Info: (including device programming or simulation files), and any
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Info: associated documentation or information are expressly subject
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Info: to the terms and conditions of the Intel Program License
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Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
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Info: the Intel MegaCore Function License Agreement, or other
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Info: applicable license agreement, including, without limitation,
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Info: that your use is for the sole purpose of programming logic
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Info: devices manufactured by Intel and sold by Intel or its
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Info: authorized distributors. Please refer to the applicable
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Info: agreement for further details.
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Info: Processing started: Thu Feb 25 20:02:09 2021
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Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt"
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Completed successfully.
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Completed successfully.
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**** Generating the functional simulation netlist ****
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quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
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Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
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Info: Your use of Intel Corporation's design tools, logic functions
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Info: and other software and tools, and its AMPP partner logic
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Info: functions, and any output files from any of the foregoing
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Info: (including device programming or simulation files), and any
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Info: associated documentation or information are expressly subject
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Info: to the terms and conditions of the Intel Program License
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Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
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Info: the Intel MegaCore Function License Agreement, or other
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Info: applicable license agreement, including, without limitation,
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Info: that your use is for the sole purpose of programming logic
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Info: devices manufactured by Intel and sold by Intel or its
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Info: authorized distributors. Please refer to the applicable
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Info: agreement for further details.
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Info: Processing started: Thu Feb 25 20:02:10 2021
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Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (204019): Generated file Lab1Pt1.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim//" for EDA simulation tool
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Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 4641 megabytes
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Info: Processing ended: Thu Feb 25 20:02:11 2021
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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Completed successfully.
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**** Generating the ModelSim .do script ****
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C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.do generated.
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Completed successfully.
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**** Running the ModelSim simulation ****
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c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do Lab1Pt1.do
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Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl
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# 10.5b
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# do Lab1Pt1.do
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:02:13 on Feb 25,2021
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# vlog -work work Lab1Pt1.vo
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# -- Compiling module Lab1Pt1
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# -- Compiling module hard_block
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#
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# Top level modules:
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# Lab1Pt1
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# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:02:13 on Feb 25,2021
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# vlog -work work Waveform.vwf.vt
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# -- Compiling module Lab1Pt1_vlg_vec_tst
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#
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# Top level modules:
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# Lab1Pt1_vlg_vec_tst
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# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst
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# Start time: 20:02:14 on Feb 25,2021
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# Loading work.Lab1Pt1_vlg_vec_tst
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# Loading work.Lab1Pt1
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# Loading work.hard_block
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# ** Warning: (vsim-3017) Lab1Pt1.vo(406): [TFMPC] - Too few port connections. Expected 8, found 7.
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# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile
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# ** Warning: (vsim-3722) Lab1Pt1.vo(406): [TFMPC] - Missing connection for port 'clk_dft'.
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# ** Warning: (vsim-3017) Lab1Pt1.vo(429): [TFMPC] - Too few port connections. Expected 8, found 7.
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# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile
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# ** Warning: (vsim-3722) Lab1Pt1.vo(429): [TFMPC] - Missing connection for port 'clk_dft'.
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# after#24
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# ** Note: $finish : Waveform.vwf.vt(45)
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# Time: 1 us Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst
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# End time: 20:02:14 on Feb 25,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 4
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Completed successfully.
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**** Converting ModelSim VCD to vector waveform ****
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Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf...
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Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.msim.vcd...
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Processing channel transitions...
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Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_20210225200214.sim.vwf
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Finished VCD to VWF conversion.
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Completed successfully.
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All completed.
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