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UAHCode/EE203/Noah Woodlee/LAB1/Part 4/db/prev_cmp_part4.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1617926007721 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617926007721 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 18:53:27 2021 " "Processing started: Thu Apr 08 18:53:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617926007721 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617926007721 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 " "Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617926007721 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1617926008071 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1617926008071 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part4.v 1 1 " "Found 1 design units, including 1 entities, in source file part4.v" { { "Info" "ISGN_ENTITY_NAME" "1 part4 " "Found entity 1: part4" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617926016271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617926016271 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "part4 " "Elaborating entity \"part4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1617926016301 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[2\] GND " "Pin \"LEDR\[2\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[3\] GND " "Pin \"LEDR\[3\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] GND " "Pin \"LEDR\[4\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "part4.v" "" { Text "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/part4.v" 3 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1617926016631 "|part4|LEDR[9]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1617926016631 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1617926016681 ""}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926016951
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1617926017071 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617926017071 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1617926017111 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1617926017111 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Implemented 2 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1617926017111 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1617926017111 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4779 " "Peak virtual memory: 4779 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617926017141 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 18:53:37 2021 " "Processing ended: Thu Apr 08 18:53:37 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617926017141 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617926017141 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617926017141 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1617926017141 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1617926018321 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617926018331 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 18:53:37 2021 " "Processing started: Thu Apr 08 18:53:37 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617926018331 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1617926018331 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off part4 -c part4 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1617926018331 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1617926018431 ""}
{ "Info" "0" "" "Project = part4" { } { } 0 0 "Project = part4" 0 0 "Fitter" 0 0 1617926018431 ""}
{ "Info" "0" "" "Revision = part4" { } { } 0 0 "Revision = part4" 0 0 "Fitter" 0 0 1617926018431 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1617926018531 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1617926018531 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "part4 10M50DAF484C6GES " "Selected device 10M50DAF484C6GES for design \"part4\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1617926018531 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1617926018571 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1617926018571 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1617926018791 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1617926018801 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1617926018911 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 61 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 63 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 65 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 67 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 69 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 71 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 0 { 0 ""} 0 73 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1617926018911 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617926018911 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617926018911 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617926018911 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1617926018911 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1617926018911 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 19 " "No exact pin location assignment(s) for 7 pins of 19 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1617926019151 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1617926019381 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1617926019381 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1617926019381 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1617926019381 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1617926019381 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1617926019381 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1617926019381 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1617926019381 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 2.5V 0 7 0 " "Number of I/O pins in group: 7 (unused VREF, 2.5V VCCIO, 0 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1617926019381 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1617926019381 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1617926019381 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 20 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 36 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 48 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 48 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 40 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 60 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 12 40 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 12 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 32 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1617926019391 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1617926019391 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1617926019391 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/16.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1617926019411 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1617926019411 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926019411 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1617926019411 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1617926020531 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926020581 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1617926020611 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1617926021221 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926021221 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1617926021711 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1617926023051 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1617926023051 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1617926023151 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1617926023151 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1617926023151 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926023151 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1617926023371 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1617926023381 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1617926023381 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1617926023631 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1617926023631 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1617926023631 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1617926023891 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1617926024281 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1617926024511 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part 4/output_files/part4.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1617926024561 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 18 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5903 " "Peak virtual memory: 5903 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617926024991 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 18:53:44 2021 " "Processing ended: Thu Apr 08 18:53:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617926024991 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617926024991 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617926024991 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1617926024991 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1617926026011 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617926026011 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 18:53:45 2021 " "Processing started: Thu Apr 08 18:53:45 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617926026011 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1617926026011 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1617926026011 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1617926026311 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1617926028061 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1617926028201 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4682 " "Peak virtual memory: 4682 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617926029251 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 18:53:49 2021 " "Processing ended: Thu Apr 08 18:53:49 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617926029251 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617926029251 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617926029251 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1617926029251 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1617926029851 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1617926030411 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617926030411 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 08 18:53:50 2021 " "Processing started: Thu Apr 08 18:53:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617926030411 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030411 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta part4 -c part4 " "Command: quartus_sta part4 -c part4" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030411 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926030521 ""}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "Lab1Pt1 24 " "Ignored 24 assignments for entity \"Lab1Pt1\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1617926030541
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030681 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030681 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030721 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030721 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "part4.sdc " "Synopsys Design Constraints File file not found: 'part4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030981 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926030981 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030991 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926030991 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926030991 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1617926031001 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031001 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031001 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031001 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031011 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031011 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926031021 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031041 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M50DAF484C6GES " "Timing characteristics of device 10M50DAF484C6GES are preliminary" { } { } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031041 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031321 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031351 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031361 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031361 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031371 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031371 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1617926031371 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031501 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031511 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926031511 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926032391 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926032391 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 31 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4864 " "Peak virtual memory: 4864 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617926032451 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 08 18:53:52 2021 " "Processing ended: Thu Apr 08 18:53:52 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617926032451 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617926032451 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617926032451 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926032451 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 85 s " "Quartus Prime Full Compilation was successful. 0 errors, 85 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1617926033081 ""}
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