38 lines
1.8 KiB
Plaintext
38 lines
1.8 KiB
Plaintext
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# do Lab1Part2.do
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# ** Warning: (vlib-34) Library already exists at "work".
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 19:52:33 on Mar 11,2021
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# vlog -work work Lab1Part2.vo
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# -- Compiling module Lab1Part2
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# -- Compiling module hard_block
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#
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# Top level modules:
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# Lab1Part2
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# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 19:52:33 on Mar 11,2021
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# vlog -work work Waveform.vwf.vt
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# -- Compiling module Lab1Part2_vlg_vec_tst
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#
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# Top level modules:
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# Lab1Part2_vlg_vec_tst
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# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst
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# Start time: 19:52:33 on Mar 11,2021
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# Loading work.Lab1Part2_vlg_vec_tst
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# Loading work.Lab1Part2
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# Loading work.hard_block
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# ** Warning: (vsim-3017) Lab1Part2.vo(478): [TFMPC] - Too few port connections. Expected 8, found 7.
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# Time: 0 ps Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile
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# ** Warning: (vsim-3722) Lab1Part2.vo(478): [TFMPC] - Missing connection for port 'clk_dft'.
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# ** Warning: (vsim-3017) Lab1Part2.vo(501): [TFMPC] - Too few port connections. Expected 8, found 7.
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# Time: 0 ps Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile
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# ** Warning: (vsim-3722) Lab1Part2.vo(501): [TFMPC] - Missing connection for port 'clk_dft'.
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# after#26
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# ** Note: $finish : Waveform.vwf.vt(45)
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# Time: 1 us Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst
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# End time: 19:52:34 on Mar 11,2021, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 4
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