56 lines
1.4 KiB
Coq
56 lines
1.4 KiB
Coq
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module sevenSegment (IN, OUT);
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input [1:0]IN;
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output reg [6:0]OUT;
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always @ (*)
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begin
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case (IN[1:0])
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2'b00: OUT=7'b010_0001;
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2'b01: OUT=7'b000_0110;
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2'b10: OUT=7'b111_1001;
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2'b11: OUT=7'b100_0000;
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endcase
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end
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endmodule
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module Mux_4to1 (IN1, IN2, IN3, IN4, SEL, M);
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input [1:0] IN1, IN2, IN3, IN4;
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input [1:0] SEL;
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output reg[1:0] M;
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always@(*)
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begin
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case(SEL[1:0])
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2'b00: M=IN1;
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2'b01: M=IN2;
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2'b10: M=IN3;
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2'b11: M=IN4;
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endcase
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end
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endmodule
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module part5 (SW, LEDR, HEX0, HEX1, HEX2, HEX3);
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input [9:0]SW;
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output [6:0]HEX0, HEX1, HEX2, HEX3;
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output [9:0]LEDR;
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wire[1:0] M1, M2, M3, M0;
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// Chooses 'd' when SW[9:8] is 00
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Mux_4to1 (SW[7:6], SW[5:4], SW[3:2], SW[1:0], SW[9:8], M3);
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// Chooses 'E' when SW[9:8] is 00
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Mux_4to1 (SW[5:4], SW[3:2], SW[1:0], SW[7:6], SW[9:8], M2);
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// Chooses '1' when SW[9:8] is 00
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Mux_4to1 (SW[3:2], SW[1:0], SW[7:6], SW[5:4], SW[9:8], M1);
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// Chooses '0' when SW[9:8] is 00
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Mux_4to1 (SW[1:0], SW[7:6], SW[5:4], SW[3:2], SW[9:8], M0);
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sevenSegment S0(M0, HEX0);
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sevenSegment S1(M1, HEX1);
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sevenSegment S2(M2, HEX2);
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sevenSegment S3(M3, HEX3);
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assign LEDR=SW;
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endmodule
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