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UAHCode/EE203/Noah Woodlee/LAB1/Part3/output_files/Part3.flow.rpt

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2022-08-28 21:12:16 +00:00
Flow report for Part3
Thu Mar 11 20:47:38 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Mar 11 20:47:38 2021 ;
; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Revision Name ; Part3 ;
; Top-level Entity Name ; Part3 ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C7G ;
; Timing Models ; Final ;
; Total logic elements ; 4 / 49,760 ( < 1 % ) ;
; Total combinational functions ; 4 / 49,760 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 20 / 360 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 1,677,312 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/11/2021 20:43:20 ;
; Main task ; Compilation ;
; Revision Name ; Part3 ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 189559947077153.161551700008156 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4781 MB ; 00:00:22 ;
; Fitter ; 00:00:07 ; 1.0 ; 5904 MB ; 00:00:10 ;
; Assembler ; 00:00:04 ; 1.0 ; 4684 MB ; 00:00:03 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:01 ;
; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4867 MB ; 00:00:02 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:01 ;
; Total ; 00:00:23 ; -- ; -- ; 00:00:40 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+-----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
+---------------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off Part3 -c Part3
quartus_fit --read_settings_files=off --write_settings_files=off Part3 -c Part3
quartus_asm --read_settings_files=off --write_settings_files=off Part3 -c Part3
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3
quartus_sta Part3 -c Part3
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt"
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3