583 lines
18 KiB
Plaintext
583 lines
18 KiB
Plaintext
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// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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// DATE "04/25/2021 00:52:01"
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//
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// Device: Altera 10M50DAF484C6GES Package FBGA484
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//
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//
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// This Verilog file should be used for ModelSim-Altera (Verilog) only
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//
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`timescale 1 ps/ 1 ps
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module part3 (
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SW,
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LEDR);
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input [8:0] SW;
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output [4:0] LEDR;
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// Design Ports Information
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// LEDR[0] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default
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// LEDR[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default
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// LEDR[2] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default
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// LEDR[3] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default
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// LEDR[4] => Location: PIN_D13, I/O Standard: 2.5 V, Current Strength: Default
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// SW[8] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default
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// SW[0] => Location: PIN_C10, I/O Standard: 2.5 V, Current Strength: Default
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// SW[4] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default
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// SW[1] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default
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// SW[5] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default
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// SW[2] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default
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// SW[6] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default
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// SW[3] => Location: PIN_C12, I/O Standard: 2.5 V, Current Strength: Default
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// SW[7] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \~QUARTUS_CREATED_GND~I_combout ;
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wire \~QUARTUS_CREATED_UNVM~~busy ;
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wire \~QUARTUS_CREATED_ADC1~~eoc ;
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wire \~QUARTUS_CREATED_ADC2~~eoc ;
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wire \LEDR[0]~output_o ;
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wire \LEDR[1]~output_o ;
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wire \LEDR[2]~output_o ;
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wire \LEDR[3]~output_o ;
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wire \LEDR[4]~output_o ;
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wire \SW[4]~input_o ;
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wire \SW[0]~input_o ;
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wire \SW[8]~input_o ;
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wire \A0|x1~combout ;
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wire \SW[5]~input_o ;
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wire \SW[1]~input_o ;
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wire \A0|COUT~0_combout ;
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wire \A1|x1~combout ;
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wire \SW[2]~input_o ;
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wire \SW[6]~input_o ;
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wire \A2|x0~combout ;
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wire \A2|x1~combout ;
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wire \A2|COUT~2_combout ;
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wire \A2|COUT~3_combout ;
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wire \SW[3]~input_o ;
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wire \SW[7]~input_o ;
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wire \A3|x1~combout ;
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wire \A3|COUT~0_combout ;
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hard_block auto_generated_inst(
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.devpor(devpor),
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.devclrn(devclrn),
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.devoe(devoe));
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// Location: LCCOMB_X44_Y41_N16
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fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
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// Equation(s):
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// \~QUARTUS_CREATED_GND~I_combout = GND
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.dataa(gnd),
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.datab(gnd),
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.datac(gnd),
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.datad(gnd),
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.cin(gnd),
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.combout(\~QUARTUS_CREATED_GND~I_combout ),
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.cout());
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// synopsys translate_off
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defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
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defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOOBUF_X46_Y54_N2
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fiftyfivenm_io_obuf \LEDR[0]~output (
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.i(\A0|x1~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\LEDR[0]~output_o ),
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.obar());
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// synopsys translate_off
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defparam \LEDR[0]~output .bus_hold = "false";
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defparam \LEDR[0]~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOOBUF_X46_Y54_N23
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fiftyfivenm_io_obuf \LEDR[1]~output (
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.i(\A1|x1~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\LEDR[1]~output_o ),
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.obar());
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// synopsys translate_off
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defparam \LEDR[1]~output .bus_hold = "false";
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defparam \LEDR[1]~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOOBUF_X51_Y54_N16
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fiftyfivenm_io_obuf \LEDR[2]~output (
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.i(\A2|x1~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\LEDR[2]~output_o ),
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.obar());
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// synopsys translate_off
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defparam \LEDR[2]~output .bus_hold = "false";
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defparam \LEDR[2]~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOOBUF_X46_Y54_N9
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fiftyfivenm_io_obuf \LEDR[3]~output (
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.i(\A3|x1~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\LEDR[3]~output_o ),
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.obar());
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// synopsys translate_off
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defparam \LEDR[3]~output .bus_hold = "false";
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defparam \LEDR[3]~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOOBUF_X56_Y54_N30
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fiftyfivenm_io_obuf \LEDR[4]~output (
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.i(\A3|COUT~0_combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\LEDR[4]~output_o ),
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.obar());
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// synopsys translate_off
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defparam \LEDR[4]~output .bus_hold = "false";
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defparam \LEDR[4]~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOIBUF_X54_Y54_N22
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fiftyfivenm_io_ibuf \SW[4]~input (
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.i(SW[4]),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\SW[4]~input_o ));
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// synopsys translate_off
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defparam \SW[4]~input .bus_hold = "false";
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defparam \SW[4]~input .listen_to_nsleep_signal = "false";
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defparam \SW[4]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X51_Y54_N29
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fiftyfivenm_io_ibuf \SW[0]~input (
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.i(SW[0]),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\SW[0]~input_o ));
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// synopsys translate_off
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defparam \SW[0]~input .bus_hold = "false";
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defparam \SW[0]~input .listen_to_nsleep_signal = "false";
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defparam \SW[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X56_Y54_N1
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fiftyfivenm_io_ibuf \SW[8]~input (
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.i(SW[8]),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\SW[8]~input_o ));
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// synopsys translate_off
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defparam \SW[8]~input .bus_hold = "false";
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defparam \SW[8]~input .listen_to_nsleep_signal = "false";
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defparam \SW[8]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X51_Y53_N24
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fiftyfivenm_lcell_comb \A0|x1 (
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// Equation(s):
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// \A0|x1~combout = \SW[4]~input_o $ (\SW[0]~input_o $ (\SW[8]~input_o ))
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.dataa(\SW[4]~input_o ),
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.datab(\SW[0]~input_o ),
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.datac(gnd),
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.datad(\SW[8]~input_o ),
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.cin(gnd),
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.combout(\A0|x1~combout ),
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.cout());
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// synopsys translate_off
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defparam \A0|x1 .lut_mask = 16'h9966;
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defparam \A0|x1 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X49_Y54_N1
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fiftyfivenm_io_ibuf \SW[5]~input (
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.i(SW[5]),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\SW[5]~input_o ));
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// synopsys translate_off
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defparam \SW[5]~input .bus_hold = "false";
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defparam \SW[5]~input .listen_to_nsleep_signal = "false";
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defparam \SW[5]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X51_Y54_N22
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fiftyfivenm_io_ibuf \SW[1]~input (
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.i(SW[1]),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\SW[1]~input_o ));
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// synopsys translate_off
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defparam \SW[1]~input .bus_hold = "false";
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defparam \SW[1]~input .listen_to_nsleep_signal = "false";
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defparam \SW[1]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X51_Y53_N26
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fiftyfivenm_lcell_comb \A0|COUT~0 (
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// Equation(s):
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// \A0|COUT~0_combout = (\SW[4]~input_o & ((\SW[0]~input_o ) # (\SW[8]~input_o ))) # (!\SW[4]~input_o & (\SW[0]~input_o & \SW[8]~input_o ))
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.dataa(\SW[4]~input_o ),
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.datab(\SW[0]~input_o ),
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.datac(gnd),
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.datad(\SW[8]~input_o ),
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.cin(gnd),
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.combout(\A0|COUT~0_combout ),
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.cout());
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// synopsys translate_off
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defparam \A0|COUT~0 .lut_mask = 16'hEE88;
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defparam \A0|COUT~0 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X51_Y53_N12
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fiftyfivenm_lcell_comb \A1|x1 (
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// Equation(s):
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// \A1|x1~combout = \SW[5]~input_o $ (\SW[1]~input_o $ (\A0|COUT~0_combout ))
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.dataa(\SW[5]~input_o ),
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.datab(\SW[1]~input_o ),
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.datac(\A0|COUT~0_combout ),
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.datad(gnd),
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.cin(gnd),
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.combout(\A1|x1~combout ),
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.cout());
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// synopsys translate_off
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defparam \A1|x1 .lut_mask = 16'h9696;
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defparam \A1|x1 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X51_Y54_N1
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fiftyfivenm_io_ibuf \SW[2]~input (
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.i(SW[2]),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\SW[2]~input_o ));
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// synopsys translate_off
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defparam \SW[2]~input .bus_hold = "false";
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defparam \SW[2]~input .listen_to_nsleep_signal = "false";
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defparam \SW[2]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X54_Y54_N15
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fiftyfivenm_io_ibuf \SW[6]~input (
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.i(SW[6]),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\SW[6]~input_o ));
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// synopsys translate_off
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defparam \SW[6]~input .bus_hold = "false";
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defparam \SW[6]~input .listen_to_nsleep_signal = "false";
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defparam \SW[6]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X51_Y53_N22
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fiftyfivenm_lcell_comb \A2|x0 (
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// Equation(s):
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// \A2|x0~combout = \SW[2]~input_o $ (\SW[6]~input_o )
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.dataa(gnd),
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.datab(gnd),
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|
|
.datac(\SW[2]~input_o ),
|
||
|
|
.datad(\SW[6]~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\A2|x0~combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \A2|x0 .lut_mask = 16'h0FF0;
|
||
|
|
defparam \A2|x0 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X51_Y53_N16
|
||
|
|
fiftyfivenm_lcell_comb \A2|x1 (
|
||
|
|
// Equation(s):
|
||
|
|
// \A2|x1~combout = \A2|x0~combout $ (((\SW[1]~input_o & ((\A0|COUT~0_combout ) # (\SW[5]~input_o ))) # (!\SW[1]~input_o & (\A0|COUT~0_combout & \SW[5]~input_o ))))
|
||
|
|
|
||
|
|
.dataa(\A2|x0~combout ),
|
||
|
|
.datab(\SW[1]~input_o ),
|
||
|
|
.datac(\A0|COUT~0_combout ),
|
||
|
|
.datad(\SW[5]~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\A2|x1~combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \A2|x1 .lut_mask = 16'h566A;
|
||
|
|
defparam \A2|x1 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X51_Y53_N10
|
||
|
|
fiftyfivenm_lcell_comb \A2|COUT~2 (
|
||
|
|
// Equation(s):
|
||
|
|
// \A2|COUT~2_combout = (\A2|x0~combout & ((\SW[1]~input_o & ((\A0|COUT~0_combout ) # (\SW[5]~input_o ))) # (!\SW[1]~input_o & (\A0|COUT~0_combout & \SW[5]~input_o ))))
|
||
|
|
|
||
|
|
.dataa(\A2|x0~combout ),
|
||
|
|
.datab(\SW[1]~input_o ),
|
||
|
|
.datac(\A0|COUT~0_combout ),
|
||
|
|
.datad(\SW[5]~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\A2|COUT~2_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \A2|COUT~2 .lut_mask = 16'hA880;
|
||
|
|
defparam \A2|COUT~2 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X51_Y53_N0
|
||
|
|
fiftyfivenm_lcell_comb \A2|COUT~3 (
|
||
|
|
// Equation(s):
|
||
|
|
// \A2|COUT~3_combout = (\A2|COUT~2_combout ) # ((\SW[2]~input_o & \SW[6]~input_o ))
|
||
|
|
|
||
|
|
.dataa(\A2|COUT~2_combout ),
|
||
|
|
.datab(gnd),
|
||
|
|
.datac(\SW[2]~input_o ),
|
||
|
|
.datad(\SW[6]~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\A2|COUT~3_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \A2|COUT~3 .lut_mask = 16'hFAAA;
|
||
|
|
defparam \A2|COUT~3 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X54_Y54_N29
|
||
|
|
fiftyfivenm_io_ibuf \SW[3]~input (
|
||
|
|
.i(SW[3]),
|
||
|
|
.ibar(gnd),
|
||
|
|
.nsleep(vcc),
|
||
|
|
.o(\SW[3]~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \SW[3]~input .bus_hold = "false";
|
||
|
|
defparam \SW[3]~input .listen_to_nsleep_signal = "false";
|
||
|
|
defparam \SW[3]~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X58_Y54_N29
|
||
|
|
fiftyfivenm_io_ibuf \SW[7]~input (
|
||
|
|
.i(SW[7]),
|
||
|
|
.ibar(gnd),
|
||
|
|
.nsleep(vcc),
|
||
|
|
.o(\SW[7]~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \SW[7]~input .bus_hold = "false";
|
||
|
|
defparam \SW[7]~input .listen_to_nsleep_signal = "false";
|
||
|
|
defparam \SW[7]~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X51_Y53_N20
|
||
|
|
fiftyfivenm_lcell_comb \A3|x1 (
|
||
|
|
// Equation(s):
|
||
|
|
// \A3|x1~combout = \A2|COUT~3_combout $ (\SW[3]~input_o $ (\SW[7]~input_o ))
|
||
|
|
|
||
|
|
.dataa(gnd),
|
||
|
|
.datab(\A2|COUT~3_combout ),
|
||
|
|
.datac(\SW[3]~input_o ),
|
||
|
|
.datad(\SW[7]~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\A3|x1~combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \A3|x1 .lut_mask = 16'hC33C;
|
||
|
|
defparam \A3|x1 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X51_Y53_N6
|
||
|
|
fiftyfivenm_lcell_comb \A3|COUT~0 (
|
||
|
|
// Equation(s):
|
||
|
|
// \A3|COUT~0_combout = (\A2|COUT~3_combout & ((\SW[3]~input_o ) # (\SW[7]~input_o ))) # (!\A2|COUT~3_combout & (\SW[3]~input_o & \SW[7]~input_o ))
|
||
|
|
|
||
|
|
.dataa(gnd),
|
||
|
|
.datab(\A2|COUT~3_combout ),
|
||
|
|
.datac(\SW[3]~input_o ),
|
||
|
|
.datad(\SW[7]~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\A3|COUT~0_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \A3|COUT~0 .lut_mask = 16'hFCC0;
|
||
|
|
defparam \A3|COUT~0 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: UNVM_X0_Y40_N40
|
||
|
|
fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
|
||
|
|
.arclk(vcc),
|
||
|
|
.arshft(vcc),
|
||
|
|
.drclk(vcc),
|
||
|
|
.drshft(vcc),
|
||
|
|
.drdin(vcc),
|
||
|
|
.nprogram(vcc),
|
||
|
|
.nerase(vcc),
|
||
|
|
.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
|
||
|
|
.par_en(vcc),
|
||
|
|
.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
|
||
|
|
.se(\~QUARTUS_CREATED_GND~I_combout ),
|
||
|
|
.ardin(23'b11111111111111111111111),
|
||
|
|
.busy(\~QUARTUS_CREATED_UNVM~~busy ),
|
||
|
|
.osc(),
|
||
|
|
.bgpbusy(),
|
||
|
|
.sp_pass(),
|
||
|
|
.se_pass(),
|
||
|
|
.drdout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_end_addr = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .addr_range3_offset = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
|
||
|
|
defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: ADCBLOCK_X43_Y52_N0
|
||
|
|
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
|
||
|
|
.soc(\~QUARTUS_CREATED_GND~I_combout ),
|
||
|
|
.usr_pwd(vcc),
|
||
|
|
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
|
||
|
|
.clkin_from_pll_c0(gnd),
|
||
|
|
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
|
||
|
|
.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
|
||
|
|
.dout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: ADCBLOCK_X43_Y51_N0
|
||
|
|
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
|
||
|
|
.soc(\~QUARTUS_CREATED_GND~I_combout ),
|
||
|
|
.usr_pwd(vcc),
|
||
|
|
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
|
||
|
|
.clkin_from_pll_c0(gnd),
|
||
|
|
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
|
||
|
|
.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
|
||
|
|
.dout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
|
||
|
|
defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
assign LEDR[0] = \LEDR[0]~output_o ;
|
||
|
|
|
||
|
|
assign LEDR[1] = \LEDR[1]~output_o ;
|
||
|
|
|
||
|
|
assign LEDR[2] = \LEDR[2]~output_o ;
|
||
|
|
|
||
|
|
assign LEDR[3] = \LEDR[3]~output_o ;
|
||
|
|
|
||
|
|
assign LEDR[4] = \LEDR[4]~output_o ;
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module hard_block (
|
||
|
|
|
||
|
|
devpor,
|
||
|
|
devclrn,
|
||
|
|
devoe);
|
||
|
|
|
||
|
|
// Design Ports Information
|
||
|
|
// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||
|
|
// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||
|
|
// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||
|
|
// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||
|
|
// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||
|
|
// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||
|
|
|
||
|
|
input devpor;
|
||
|
|
input devclrn;
|
||
|
|
input devoe;
|
||
|
|
|
||
|
|
wire gnd;
|
||
|
|
wire vcc;
|
||
|
|
wire unknown;
|
||
|
|
|
||
|
|
assign gnd = 1'b0;
|
||
|
|
assign vcc = 1'b1;
|
||
|
|
assign unknown = 1'bx;
|
||
|
|
|
||
|
|
wire \~ALTERA_TMS~~padout ;
|
||
|
|
wire \~ALTERA_TCK~~padout ;
|
||
|
|
wire \~ALTERA_TDI~~padout ;
|
||
|
|
wire \~ALTERA_CONFIG_SEL~~padout ;
|
||
|
|
wire \~ALTERA_nCONFIG~~padout ;
|
||
|
|
wire \~ALTERA_nSTATUS~~padout ;
|
||
|
|
wire \~ALTERA_CONF_DONE~~padout ;
|
||
|
|
wire \~ALTERA_TMS~~ibuf_o ;
|
||
|
|
wire \~ALTERA_TCK~~ibuf_o ;
|
||
|
|
wire \~ALTERA_TDI~~ibuf_o ;
|
||
|
|
wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
|
||
|
|
wire \~ALTERA_nCONFIG~~ibuf_o ;
|
||
|
|
wire \~ALTERA_nSTATUS~~ibuf_o ;
|
||
|
|
wire \~ALTERA_CONF_DONE~~ibuf_o ;
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|