UAHCode/EE203/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.msim.vcd

$comment
	File created using the following command:
		vcd file Part3.msim.vcd -direction
$end
$date
	Thu Mar 11 20:47:39 2021
$end
$version
	ModelSim Version 10.5b
$end
$timescale
	1ps
$end

$scope module Part3_vlg_vec_tst $end
$var reg 10 ! SW [9:0] $end
$var wire 1 " LEDR [9] $end
$var wire 1 # LEDR [8] $end
$var wire 1 $ LEDR [7] $end
$var wire 1 % LEDR [6] $end
$var wire 1 & LEDR [5] $end
$var wire 1 ' LEDR [4] $end
$var wire 1 ( LEDR [3] $end
$var wire 1 ) LEDR [2] $end
$var wire 1 * LEDR [1] $end
$var wire 1 + LEDR [0] $end

$scope module i1 $end
$var wire 1 , gnd $end
$var wire 1 - vcc $end
$var wire 1 . unknown $end
$var tri1 1 / devclrn $end
$var tri1 1 0 devpor $end
$var tri1 1 1 devoe $end
$var wire 1 2 SW[2]~input_o $end
$var wire 1 3 SW[4]~input_o $end
$var wire 1 4 ~QUARTUS_CREATED_GND~I_combout $end
$var wire 1 5 ~QUARTUS_CREATED_UNVM~~busy $end
$var wire 1 6 ~QUARTUS_CREATED_ADC1~~eoc $end
$var wire 1 7 ~QUARTUS_CREATED_ADC2~~eoc $end
$var wire 1 8 LEDR[0]~output_o $end
$var wire 1 9 LEDR[1]~output_o $end
$var wire 1 : LEDR[2]~output_o $end
$var wire 1 ; LEDR[3]~output_o $end
$var wire 1 < LEDR[4]~output_o $end
$var wire 1 = LEDR[5]~output_o $end
$var wire 1 > LEDR[6]~output_o $end
$var wire 1 ? LEDR[7]~output_o $end
$var wire 1 @ LEDR[8]~output_o $end
$var wire 1 A LEDR[9]~output_o $end
$var wire 1 B SW[0]~input_o $end
$var wire 1 C SW[8]~input_o $end
$var wire 1 D SW[6]~input_o $end
$var wire 1 E M~0_combout $end
$var wire 1 F SW[5]~input_o $end
$var wire 1 G SW[9]~input_o $end
$var wire 1 H SW[3]~input_o $end
$var wire 1 I SW[1]~input_o $end
$var wire 1 J M~1_combout $end
$var wire 1 K SW[7]~input_o $end
$var wire 1 L M~2_combout $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0xxxxxx00 !
0+
0*
0)
0(
0'
1&
0%
0$
0#
0"
0,
1-
x.
1/
10
11
x2
x3
04
z5
z6
z7
08
09
0:
0;
0<
1=
0>
0?
0@
0A
0B
0C
xD
0E
xF
0G
xH
0I
0J
xK
0L
$end
#40000
b0xxxxxx10 !
b0xxxxxx11 !
1I
1B
1J
1E
18
1+
1L
19
1*
#100000
b0xxxxxx01 !
b0xxxxxx00 !
0I
0B
0J
0E
08
0+
0L
09
0*
#180000
b0xxxxxx10 !
b0xxxxxx11 !
1I
1B
1J
1E
18
1+
1L
19
1*
#230000
b1xxxxxx11 !
b1xxxx0x11 !
b1xxxx0011 !
b1xxxx00x1 !
b1xxxx00xx !
1C
0H
02
xI
xB
0J
xE
x8
x+
0L
09
0*
#310000
b1xxxx10xx !
b1xxxx11xx !
1H
12
1J
1L
19
1*
#390000
b1xxxx01xx !
b1xxxx00xx !
0H
02
0J
0L
09
0*
#470000
b11xxxx00xx !
b11xx1x00xx !
b11xx1100xx !
b10xx1100xx !
b10xx11x0xx !
b10xx11xxxx !
1G
0C
1F
13
xH
x2
1L
19
1*
#550000
b10xx01xxxx !
b10xx00xxxx !
0F
03
0L
09
0*
#640000
b10xx10xxxx !
b10xx11xxxx !
1F
13
1L
19
1*
#740000
b101x11xxxx !
b101111xxxx !
b111111xxxx !
b1111x1xxxx !
b1111xxxxxx !
1C
1K
1D
xF
x3
1J
1E
xL
x9
18
1+
x*
1L
19
1*
#810000
b1101xxxxxx !
b1100xxxxxx !
0K
0D
0L
0E
08
09
0*
0+
#900000
b1110xxxxxx !
b1111xxxxxx !
1K
1D
1L
1E
18
19
1*
1+
#1000000