138 lines
9.6 KiB
Plaintext
138 lines
9.6 KiB
Plaintext
|
Flow report for decoder
|
||
|
|
Thu Jan 21 20:12:11 2021
|
||
|
|
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
|
||
|
|
|
||
|
|
|
||
|
|
---------------------
|
||
|
|
; Table of Contents ;
|
||
|
|
---------------------
|
||
|
|
1. Legal Notice
|
||
|
|
2. Flow Summary
|
||
|
|
3. Flow Settings
|
||
|
|
4. Flow Non-Default Global Settings
|
||
|
|
5. Flow Elapsed Time
|
||
|
|
6. Flow OS Summary
|
||
|
|
7. Flow Log
|
||
|
|
8. Flow Messages
|
||
|
|
9. Flow Suppressed Messages
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
----------------
|
||
|
|
; Legal Notice ;
|
||
|
|
----------------
|
||
|
|
Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||
|
|
Your use of Intel Corporation's design tools, logic functions
|
||
|
|
and other software and tools, and its AMPP partner logic
|
||
|
|
functions, and any output files from any of the foregoing
|
||
|
|
(including device programming or simulation files), and any
|
||
|
|
associated documentation or information are expressly subject
|
||
|
|
to the terms and conditions of the Intel Program License
|
||
|
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
|
the Intel MegaCore Function License Agreement, or other
|
||
|
|
applicable license agreement, including, without limitation,
|
||
|
|
that your use is for the sole purpose of programming logic
|
||
|
|
devices manufactured by Intel and sold by Intel or its
|
||
|
|
authorized distributors. Please refer to the applicable
|
||
|
|
agreement for further details.
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------+
|
||
|
|
; Flow Summary ;
|
||
|
|
+------------------------------------+---------------------------------------------+
|
||
|
|
; Flow Status ; Successful - Thu Jan 21 20:12:11 2021 ;
|
||
|
|
; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
|
||
|
|
; Revision Name ; decoder ;
|
||
|
|
; Top-level Entity Name ; decoder ;
|
||
|
|
; Family ; MAX 10 ;
|
||
|
|
; Device ; 10M50DAF484C7G ;
|
||
|
|
; Timing Models ; Final ;
|
||
|
|
; Total logic elements ; 5 / 49,760 ( < 1 % ) ;
|
||
|
|
; Total combinational functions ; 5 / 49,760 ( < 1 % ) ;
|
||
|
|
; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ;
|
||
|
|
; Total registers ; 0 ;
|
||
|
|
; Total pins ; 6 / 360 ( 2 % ) ;
|
||
|
|
; Total virtual pins ; 0 ;
|
||
|
|
; Total memory bits ; 0 / 1,677,312 ( 0 % ) ;
|
||
|
|
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
|
||
|
|
; Total PLLs ; 0 / 4 ( 0 % ) ;
|
||
|
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||
|
|
; ADC blocks ; 0 / 2 ( 0 % ) ;
|
||
|
|
+------------------------------------+---------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------+
|
||
|
|
; Flow Settings ;
|
||
|
|
+-------------------+---------------------+
|
||
|
|
; Option ; Setting ;
|
||
|
|
+-------------------+---------------------+
|
||
|
|
; Start date & time ; 01/21/2021 20:01:41 ;
|
||
|
|
; Main task ; Compilation ;
|
||
|
|
; Revision Name ; decoder ;
|
||
|
|
+-------------------+---------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Flow Non-Default Global Settings ;
|
||
|
|
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||
|
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||
|
|
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||
|
|
; COMPILER_SIGNATURE_ID ; 189559947077153.161128090107632 ; -- ; -- ; -- ;
|
||
|
|
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||
|
|
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||
|
|
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
||
|
|
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
||
|
|
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
||
|
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||
|
|
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Flow Elapsed Time ;
|
||
|
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||
|
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||
|
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||
|
|
; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 4788 MB ; 00:00:16 ;
|
||
|
|
; Fitter ; 00:00:06 ; 1.0 ; 5902 MB ; 00:00:08 ;
|
||
|
|
; Assembler ; 00:00:02 ; 1.0 ; 4685 MB ; 00:00:02 ;
|
||
|
|
; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4872 MB ; 00:00:02 ;
|
||
|
|
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:00 ;
|
||
|
|
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:00 ;
|
||
|
|
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:00 ;
|
||
|
|
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:00 ;
|
||
|
|
; Total ; 00:00:18 ; -- ; -- ; 00:00:28 ;
|
||
|
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------+
|
||
|
|
; Flow OS Summary ;
|
||
|
|
+---------------------------+------------------+------------+------------+----------------+
|
||
|
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||
|
|
+---------------------------+------------------+------------+------------+----------------+
|
||
|
|
; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
|
||
|
|
; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
|
||
|
|
; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
|
||
|
|
; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
|
||
|
|
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
|
||
|
|
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
|
||
|
|
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
|
||
|
|
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
|
||
|
|
+---------------------------+------------------+------------+------------+----------------+
|
||
|
|
|
||
|
|
|
||
|
|
------------
|
||
|
|
; Flow Log ;
|
||
|
|
------------
|
||
|
|
quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder
|
||
|
|
quartus_fit --read_settings_files=off --write_settings_files=off decoder -c decoder
|
||
|
|
quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder
|
||
|
|
quartus_sta decoder -c decoder
|
||
|
|
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"
|
||
|
|
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder
|
||
|
|
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"
|
||
|
|
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder
|
||
|
|
|
||
|
|
|
||
|
|
|