273 lines
8.7 KiB
Plaintext
273 lines
8.7 KiB
Plaintext
// Copyright (C) 2016 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel MegaCore Function License Agreement, or other
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// applicable license agreement, including, without limitation,
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// that your use is for the sole purpose of programming logic
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// devices manufactured by Intel and sold by Intel or its
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// authorized distributors. Please refer to the applicable
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// agreement for further details.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition"
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// DATE "01/21/2021 19:19:22"
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//
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// Device: Altera 10M50DAF484C6GES Package FBGA484
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//
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//
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// This Verilog file should be used for ModelSim-Altera (Verilog) only
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//
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`timescale 1 ps/ 1 ps
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module \class1-21-21 (
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out,
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in1,
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in2);
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output out;
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input in1;
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input in2;
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// Design Ports Information
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// out => Location: PIN_W8, I/O Standard: 2.5 V, Current Strength: Default
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// in1 => Location: PIN_AB4, I/O Standard: 2.5 V, Current Strength: Default
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// in2 => Location: PIN_AA3, I/O Standard: 2.5 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \~QUARTUS_CREATED_GND~I_combout ;
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wire \~QUARTUS_CREATED_UNVM~~busy ;
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wire \~QUARTUS_CREATED_ADC1~~eoc ;
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wire \~QUARTUS_CREATED_ADC2~~eoc ;
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wire \out~output_o ;
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wire \in1~input_o ;
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wire \in2~input_o ;
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wire \inst~combout ;
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hard_block auto_generated_inst(
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.devpor(devpor),
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.devclrn(devclrn),
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.devoe(devoe));
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// Location: LCCOMB_X44_Y52_N8
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fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
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// Equation(s):
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// \~QUARTUS_CREATED_GND~I_combout = GND
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.dataa(gnd),
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.datab(gnd),
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.datac(gnd),
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.datad(gnd),
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.cin(gnd),
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.combout(\~QUARTUS_CREATED_GND~I_combout ),
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.cout());
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// synopsys translate_off
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defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
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defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOOBUF_X24_Y0_N2
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fiftyfivenm_io_obuf \out~output (
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.i(\inst~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\out~output_o ),
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.obar());
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// synopsys translate_off
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defparam \out~output .bus_hold = "false";
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defparam \out~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOIBUF_X26_Y0_N22
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fiftyfivenm_io_ibuf \in1~input (
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.i(in1),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\in1~input_o ));
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// synopsys translate_off
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defparam \in1~input .bus_hold = "false";
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defparam \in1~input .listen_to_nsleep_signal = "false";
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defparam \in1~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X26_Y0_N29
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fiftyfivenm_io_ibuf \in2~input (
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.i(in2),
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.ibar(gnd),
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.nsleep(vcc),
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.o(\in2~input_o ));
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// synopsys translate_off
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defparam \in2~input .bus_hold = "false";
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defparam \in2~input .listen_to_nsleep_signal = "false";
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defparam \in2~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X26_Y1_N0
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fiftyfivenm_lcell_comb inst(
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// Equation(s):
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// \inst~combout = (\in1~input_o & \in2~input_o )
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.dataa(gnd),
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.datab(gnd),
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.datac(\in1~input_o ),
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.datad(\in2~input_o ),
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.cin(gnd),
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.combout(\inst~combout ),
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.cout());
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// synopsys translate_off
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defparam inst.lut_mask = 16'hF000;
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defparam inst.sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: UNVM_X0_Y40_N40
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fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
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.arclk(vcc),
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.arshft(vcc),
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.drclk(vcc),
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.drshft(vcc),
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.drdin(vcc),
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.nprogram(vcc),
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.nerase(vcc),
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.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
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.par_en(vcc),
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.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
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.se(\~QUARTUS_CREATED_GND~I_combout ),
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.ardin(23'b11111111111111111111111),
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.busy(\~QUARTUS_CREATED_UNVM~~busy ),
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.osc(),
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.bgpbusy(),
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.sp_pass(),
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.se_pass(),
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.drdout());
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// synopsys translate_off
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defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
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defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
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defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
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defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
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defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
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defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
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defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
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defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
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defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
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defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
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defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
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defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
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// synopsys translate_on
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// Location: ADCBLOCK_X43_Y52_N0
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fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
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.soc(\~QUARTUS_CREATED_GND~I_combout ),
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.usr_pwd(vcc),
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.tsen(\~QUARTUS_CREATED_GND~I_combout ),
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.clkin_from_pll_c0(gnd),
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.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
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.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
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.dout());
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// synopsys translate_off
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defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
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defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
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defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
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defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
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defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
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defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
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defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
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defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
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defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
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defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
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defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
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// synopsys translate_on
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// Location: ADCBLOCK_X43_Y51_N0
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fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
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.soc(\~QUARTUS_CREATED_GND~I_combout ),
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.usr_pwd(vcc),
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.tsen(\~QUARTUS_CREATED_GND~I_combout ),
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.clkin_from_pll_c0(gnd),
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.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
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.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
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.dout());
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// synopsys translate_off
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defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
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defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
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defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
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defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
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defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
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defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
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defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
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defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
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defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
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defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
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defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
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// synopsys translate_on
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assign out = \out~output_o ;
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endmodule
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module hard_block (
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devpor,
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devclrn,
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devoe);
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// Design Ports Information
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// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
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// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
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// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
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// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
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// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
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// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
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input devpor;
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input devclrn;
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input devoe;
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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wire \~ALTERA_TMS~~padout ;
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wire \~ALTERA_TCK~~padout ;
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wire \~ALTERA_TDI~~padout ;
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wire \~ALTERA_CONFIG_SEL~~padout ;
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wire \~ALTERA_nCONFIG~~padout ;
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wire \~ALTERA_nSTATUS~~padout ;
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wire \~ALTERA_CONF_DONE~~padout ;
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wire \~ALTERA_TMS~~ibuf_o ;
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wire \~ALTERA_TCK~~ibuf_o ;
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wire \~ALTERA_TDI~~ibuf_o ;
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wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
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wire \~ALTERA_nCONFIG~~ibuf_o ;
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wire \~ALTERA_nSTATUS~~ibuf_o ;
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wire \~ALTERA_CONF_DONE~~ibuf_o ;
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endmodule
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