31 lines
533 B
Verilog
31 lines
533 B
Verilog
module adder(SUM, COUT, A, B, CIN);
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input A, B, CIN;
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output SUM, COUT;
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wire x;
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xor x0(x, A, B);
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xor x1(SUM, x, CIN);
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assign COUT=x? CIN: B;
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endmodule
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module part3(SW, LEDR);
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input [8:0] SW;
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output [4:0] LEDR;
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wire C0,C1,C2,C3;
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wire [3:0] S;
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adder A0(S[0], C0, SW[0], SW[4], SW[8]);
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adder A1(S[1], C1, SW[1], SW[5], C0);
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adder A2(S[2], C2, SW[2], SW[6], C1);
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adder A3(S[3], C3, SW[3], SW[7], C2);
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assign LEDR = {C3, S};
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endmodule
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