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UAHCode/EE203/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform3.vwf.vt
2022-08-28 16:12:16 -05:00

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// Copyright (C) 2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "04/25/2021 00:16:46"
// Verilog Test Bench (with test vectors) for design : part3
//
// Simulation tool : 3rd Party
//
`timescale 1 ps/ 1 ps
module part3_vlg_vec_tst();
// constants
// general purpose registers
reg [8:0] SW;
// wires
wire [4:0] LEDR;
// assign statements (if any)
part3 i1 (
// port map - connection between master ports and signals/registers
.LEDR(LEDR),
.SW(SW)
);
initial
begin
#1000000 $finish;
end
// SW[ 8 ]
initial
begin
SW[8] = 1'b1;
SW[8] = #440000 1'b0;
end
// SW[ 7 ]
initial
begin
SW[7] = 1'b1;
SW[7] = #440000 1'b0;
end
// SW[ 6 ]
initial
begin
SW[6] = 1'b1;
SW[6] = #440000 1'b0;
end
// SW[ 5 ]
initial
begin
SW[5] = 1'b0;
end
// SW[ 4 ]
initial
begin
SW[4] = 1'b0;
end
// SW[ 3 ]
initial
begin
SW[3] = 1'b0;
end
// SW[ 2 ]
initial
begin
SW[2] = 1'b1;
SW[2] = #440000 1'b0;
end
// SW[ 1 ]
initial
begin
SW[1] = 1'b0;
end
// SW[ 0 ]
initial
begin
SW[0] = 1'b0;
end
endmodule