20 lines
423 B
Verilog
20 lines
423 B
Verilog
module part4 (SW, LEDR, HEX0);
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input[1:0] SW;
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output[9:0] LEDR;
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output[0:6] HEX0;
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wire[1:0] C;
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assign LEDR[1:0]=SW;
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assign LEDR[9:2]=8'b0;
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assign C=SW;
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assign HEX0[0]=~C[0];
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assign HEX0[1]=~C[1] & C[0];
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assign HEX0[2]=~C[1] & C[0];
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assign HEX0[3]=C[1] & ~C[0];
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assign HEX0[4]=C[1] & ~C[0];
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assign HEX0[5]=~C[0];
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assign HEX0[6]=C[1];
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endmodule |