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UAHCode/EE203/Noah Woodlee/LAB1/Decoder/simulation/qsim/Waveform.vwf.vt
2022-08-28 16:12:16 -05:00

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// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "01/21/2021 20:12:10"
// Verilog Test Bench (with test vectors) for design : decoder
//
// Simulation tool : 3rd Party
//
`timescale 1 ps/ 1 ps
module decoder_vlg_vec_tst();
// constants
// general purpose registers
reg A;
reg B;
// wires
wire Q0;
wire Q1;
wire Q2;
wire Q3;
// assign statements (if any)
decoder i1 (
// port map - connection between master ports and signals/registers
.A(A),
.B(B),
.Q0(Q0),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3)
);
initial
begin
#200000 $finish;
end
// A
initial
begin
A = 1'b0;
A = #10000 1'b1;
A = #20000 1'b0;
A = #30000 1'b1;
A = #30000 1'b0;
A = #60000 1'b1;
A = #10000 1'b0;
end
// B
initial
begin
B = 1'b0;
B = #60000 1'b1;
B = #30000 1'b0;
B = #20000 1'b1;
B = #10000 1'b0;
B = #30000 1'b1;
B = #10000 1'b0;
end
endmodule