193 lines
15 KiB
Plaintext
193 lines
15 KiB
Plaintext
Determining the location of the ModelSim executable...
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Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/
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To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
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Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
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**** Generating the ModelSim Testbench ****
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quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Part2 -c Lab1Part2 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt"
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
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Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
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Info: Your use of Intel Corporation's design tools, logic functions
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Info: and other software and tools, and its AMPP partner logic
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Info: functions, and any output files from any of the foregoing
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Info: (including device programming or simulation files), and any
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Info: associated documentation or information are expressly subject
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Info: to the terms and conditions of the Intel Program License
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Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
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Info: the Intel MegaCore Function License Agreement, or other
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Info: applicable license agreement, including, without limitation,
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Info: that your use is for the sole purpose of programming logic
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Info: devices manufactured by Intel and sold by Intel or its
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Info: authorized distributors. Please refer to the applicable
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Info: agreement for further details.
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Info: Processing started: Thu Mar 11 19:52:31 2021
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Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Part2 -c Lab1Part2 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Waveform.vwf.vt"
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Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design
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Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignm
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ent for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Completed successfully.
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Completed successfully.
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**** Generating the functional simulation netlist ****
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quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
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Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
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Info: Your use of Intel Corporation's design tools, logic functions
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Info: and other software and tools, and its AMPP partner logic
|
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Info: functions, and any output files from any of the foregoing
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Info: (including device programming or simulation files), and any
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Info: associated documentation or information are expressly subject
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Info: to the terms and conditions of the Intel Program License
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Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
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Info: the Intel MegaCore Function License Agreement, or other
|
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Info: applicable license agreement, including, without limitation,
|
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Info: that your use is for the sole purpose of programming logic
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Info: devices manufactured by Intel and sold by Intel or its
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Info: authorized distributors. Please refer to the applicable
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Info: agreement for further details.
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Info: Processing started: Thu Mar 11 19:52:32 2021
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Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/" Lab1Part2 -c Lab1Part2
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Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design
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Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANT
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S_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (204019): Generated file Lab1Part2.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim//" for EDA simulation tool
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Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 26 warnings
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Info: Peak virtual memory: 4641 megabytes
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Info: Processing ended: Thu Mar 11 19:52:32 2021
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Info: Elapsed time: 00:00:00
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Info: Total CPU time (on all processors): 00:00:01
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Completed successfully.
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**** Generating the ModelSim .do script ****
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C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.do generated.
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Completed successfully.
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**** Running the ModelSim simulation ****
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c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do Lab1Part2.do
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Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl
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# 10.5b
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# do Lab1Part2.do
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# ** Warning: (vlib-34) Library already exists at "work".
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 19:52:33 on Mar 11,2021
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# vlog -work work Lab1Part2.vo
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# -- Compiling module Lab1Part2
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# -- Compiling module hard_block
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#
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# Top level modules:
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# Lab1Part2
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# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 19:52:33 on Mar 11,2021
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# vlog -work work Waveform.vwf.vt
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# -- Compiling module Lab1Part2_vlg_vec_tst
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#
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# Top level modules:
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# Lab1Part2_vlg_vec_tst
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# End time: 19:52:33 on Mar 11,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Part2_vlg_vec_tst
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# Start time: 19:52:33 on Mar 11,2021
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# Loading work.Lab1Part2_vlg_vec_tst
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# Loading work.Lab1Part2
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# Loading work.hard_block
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# ** Warning: (vsim-3017) Lab1Part2.vo(478): [TFMPC] - Too few port connections. Expected 8, found 7.
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# Time: 0 ps Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile
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# ** Warning: (vsim-3722) Lab1Part2.vo(478): [TFMPC] - Missing connection for port 'clk_dft'.
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# ** Warning: (vsim-3017) Lab1Part2.vo(501): [TFMPC] - Too few port connections. Expected 8, found 7.
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# Time: 0 ps Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile
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# ** Warning: (vsim-3722) Lab1Part2.vo(501): [TFMPC] - Missing connection for port 'clk_dft'.
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# after#26
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# ** Note: $finish : Waveform.vwf.vt(45)
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# Time: 1 us Iteration: 0 Instance: /Lab1Part2_vlg_vec_tst
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# End time: 19:52:34 on Mar 11,2021, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 4
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Completed successfully.
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**** Converting ModelSim VCD to vector waveform ****
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Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/Waveform.vwf...
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Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.msim.vcd...
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Processing channel transitions...
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Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2_20210311195234.sim.vwf
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Finished VCD to VWF conversion.
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Completed successfully.
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All completed. |