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UAHCode/EE203/Noah Woodlee/LAB1/Lab1Part2/simulation/qsim/Lab1Part2.vo
2022-08-28 16:12:16 -05:00

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// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition"
// DATE "03/11/2021 19:52:32"
//
// Device: Altera 10M50DAF484C7G Package FBGA484
//
//
// This Verilog file should be used for ModelSim-Altera (Verilog) only
//
`timescale 1 ps/ 1 ps
module Lab1Part2 (
SW,
LEDR);
input [9:0] SW;
output [9:0] LEDR;
// Design Ports Information
// SW[8] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[0] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[2] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[3] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[4] => Location: PIN_D13, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[5] => Location: PIN_C13, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[6] => Location: PIN_E14, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[7] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[8] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default
// LEDR[9] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default
// SW[4] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default
// SW[0] => Location: PIN_C10, I/O Standard: 2.5 V, Current Strength: Default
// SW[9] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default
// SW[5] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default
// SW[1] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default
// SW[6] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default
// SW[2] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default
// SW[7] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default
// SW[3] => Location: PIN_C12, I/O Standard: 2.5 V, Current Strength: Default
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \SW[8]~input_o ;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \~QUARTUS_CREATED_UNVM~~busy ;
wire \~QUARTUS_CREATED_ADC1~~eoc ;
wire \~QUARTUS_CREATED_ADC2~~eoc ;
wire \LEDR[0]~output_o ;
wire \LEDR[1]~output_o ;
wire \LEDR[2]~output_o ;
wire \LEDR[3]~output_o ;
wire \LEDR[4]~output_o ;
wire \LEDR[5]~output_o ;
wire \LEDR[6]~output_o ;
wire \LEDR[7]~output_o ;
wire \LEDR[8]~output_o ;
wire \LEDR[9]~output_o ;
wire \SW[4]~input_o ;
wire \SW[0]~input_o ;
wire \SW[9]~input_o ;
wire \M~0_combout ;
wire \SW[5]~input_o ;
wire \SW[1]~input_o ;
wire \M~1_combout ;
wire \SW[6]~input_o ;
wire \SW[2]~input_o ;
wire \M~2_combout ;
wire \SW[3]~input_o ;
wire \SW[7]~input_o ;
wire \M~3_combout ;
hard_block auto_generated_inst(
.devpor(devpor),
.devclrn(devclrn),
.devoe(devoe));
// Location: LCCOMB_X44_Y41_N8
fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):
// \~QUARTUS_CREATED_GND~I_combout = GND
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.cin(gnd),
.combout(\~QUARTUS_CREATED_GND~I_combout ),
.cout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
// synopsys translate_on
// Location: IOOBUF_X46_Y54_N2
fiftyfivenm_io_obuf \LEDR[0]~output (
.i(\M~0_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[0]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[0]~output .bus_hold = "false";
defparam \LEDR[0]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X46_Y54_N23
fiftyfivenm_io_obuf \LEDR[1]~output (
.i(\M~1_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[1]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[1]~output .bus_hold = "false";
defparam \LEDR[1]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X51_Y54_N16
fiftyfivenm_io_obuf \LEDR[2]~output (
.i(\M~2_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[2]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[2]~output .bus_hold = "false";
defparam \LEDR[2]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X46_Y54_N9
fiftyfivenm_io_obuf \LEDR[3]~output (
.i(\M~3_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[3]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[3]~output .bus_hold = "false";
defparam \LEDR[3]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X56_Y54_N30
fiftyfivenm_io_obuf \LEDR[4]~output (
.i(vcc),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[4]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[4]~output .bus_hold = "false";
defparam \LEDR[4]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X58_Y54_N23
fiftyfivenm_io_obuf \LEDR[5]~output (
.i(gnd),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[5]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[5]~output .bus_hold = "false";
defparam \LEDR[5]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X66_Y54_N23
fiftyfivenm_io_obuf \LEDR[6]~output (
.i(vcc),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[6]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[6]~output .bus_hold = "false";
defparam \LEDR[6]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X56_Y54_N9
fiftyfivenm_io_obuf \LEDR[7]~output (
.i(gnd),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[7]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[7]~output .bus_hold = "false";
defparam \LEDR[7]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X51_Y54_N9
fiftyfivenm_io_obuf \LEDR[8]~output (
.i(gnd),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[8]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[8]~output .bus_hold = "false";
defparam \LEDR[8]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X49_Y54_N9
fiftyfivenm_io_obuf \LEDR[9]~output (
.i(\SW[9]~input_o ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\LEDR[9]~output_o ),
.obar());
// synopsys translate_off
defparam \LEDR[9]~output .bus_hold = "false";
defparam \LEDR[9]~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOIBUF_X54_Y54_N22
fiftyfivenm_io_ibuf \SW[4]~input (
.i(SW[4]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[4]~input_o ));
// synopsys translate_off
defparam \SW[4]~input .bus_hold = "false";
defparam \SW[4]~input .listen_to_nsleep_signal = "false";
defparam \SW[4]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X51_Y54_N29
fiftyfivenm_io_ibuf \SW[0]~input (
.i(SW[0]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[0]~input_o ));
// synopsys translate_off
defparam \SW[0]~input .bus_hold = "false";
defparam \SW[0]~input .listen_to_nsleep_signal = "false";
defparam \SW[0]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X69_Y54_N1
fiftyfivenm_io_ibuf \SW[9]~input (
.i(SW[9]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[9]~input_o ));
// synopsys translate_off
defparam \SW[9]~input .bus_hold = "false";
defparam \SW[9]~input .listen_to_nsleep_signal = "false";
defparam \SW[9]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LCCOMB_X51_Y53_N24
fiftyfivenm_lcell_comb \M~0 (
// Equation(s):
// \M~0_combout = (\SW[9]~input_o & (\SW[4]~input_o )) # (!\SW[9]~input_o & ((\SW[0]~input_o )))
.dataa(\SW[4]~input_o ),
.datab(\SW[0]~input_o ),
.datac(gnd),
.datad(\SW[9]~input_o ),
.cin(gnd),
.combout(\M~0_combout ),
.cout());
// synopsys translate_off
defparam \M~0 .lut_mask = 16'hAACC;
defparam \M~0 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: IOIBUF_X49_Y54_N1
fiftyfivenm_io_ibuf \SW[5]~input (
.i(SW[5]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[5]~input_o ));
// synopsys translate_off
defparam \SW[5]~input .bus_hold = "false";
defparam \SW[5]~input .listen_to_nsleep_signal = "false";
defparam \SW[5]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X51_Y54_N22
fiftyfivenm_io_ibuf \SW[1]~input (
.i(SW[1]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[1]~input_o ));
// synopsys translate_off
defparam \SW[1]~input .bus_hold = "false";
defparam \SW[1]~input .listen_to_nsleep_signal = "false";
defparam \SW[1]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LCCOMB_X50_Y53_N16
fiftyfivenm_lcell_comb \M~1 (
// Equation(s):
// \M~1_combout = (\SW[9]~input_o & (\SW[5]~input_o )) # (!\SW[9]~input_o & ((\SW[1]~input_o )))
.dataa(\SW[5]~input_o ),
.datab(gnd),
.datac(\SW[9]~input_o ),
.datad(\SW[1]~input_o ),
.cin(gnd),
.combout(\M~1_combout ),
.cout());
// synopsys translate_off
defparam \M~1 .lut_mask = 16'hAFA0;
defparam \M~1 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: IOIBUF_X54_Y54_N15
fiftyfivenm_io_ibuf \SW[6]~input (
.i(SW[6]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[6]~input_o ));
// synopsys translate_off
defparam \SW[6]~input .bus_hold = "false";
defparam \SW[6]~input .listen_to_nsleep_signal = "false";
defparam \SW[6]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X51_Y54_N1
fiftyfivenm_io_ibuf \SW[2]~input (
.i(SW[2]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[2]~input_o ));
// synopsys translate_off
defparam \SW[2]~input .bus_hold = "false";
defparam \SW[2]~input .listen_to_nsleep_signal = "false";
defparam \SW[2]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LCCOMB_X51_Y53_N26
fiftyfivenm_lcell_comb \M~2 (
// Equation(s):
// \M~2_combout = (\SW[9]~input_o & (\SW[6]~input_o )) # (!\SW[9]~input_o & ((\SW[2]~input_o )))
.dataa(gnd),
.datab(\SW[6]~input_o ),
.datac(\SW[2]~input_o ),
.datad(\SW[9]~input_o ),
.cin(gnd),
.combout(\M~2_combout ),
.cout());
// synopsys translate_off
defparam \M~2 .lut_mask = 16'hCCF0;
defparam \M~2 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: IOIBUF_X54_Y54_N29
fiftyfivenm_io_ibuf \SW[3]~input (
.i(SW[3]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[3]~input_o ));
// synopsys translate_off
defparam \SW[3]~input .bus_hold = "false";
defparam \SW[3]~input .listen_to_nsleep_signal = "false";
defparam \SW[3]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X58_Y54_N29
fiftyfivenm_io_ibuf \SW[7]~input (
.i(SW[7]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[7]~input_o ));
// synopsys translate_off
defparam \SW[7]~input .bus_hold = "false";
defparam \SW[7]~input .listen_to_nsleep_signal = "false";
defparam \SW[7]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LCCOMB_X54_Y53_N8
fiftyfivenm_lcell_comb \M~3 (
// Equation(s):
// \M~3_combout = (\SW[9]~input_o & ((\SW[7]~input_o ))) # (!\SW[9]~input_o & (\SW[3]~input_o ))
.dataa(gnd),
.datab(\SW[3]~input_o ),
.datac(\SW[9]~input_o ),
.datad(\SW[7]~input_o ),
.cin(gnd),
.combout(\M~3_combout ),
.cout());
// synopsys translate_off
defparam \M~3 .lut_mask = 16'hFC0C;
defparam \M~3 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: IOIBUF_X56_Y54_N1
fiftyfivenm_io_ibuf \SW[8]~input (
.i(SW[8]),
.ibar(gnd),
.nsleep(vcc),
.o(\SW[8]~input_o ));
// synopsys translate_off
defparam \SW[8]~input .bus_hold = "false";
defparam \SW[8]~input .listen_to_nsleep_signal = "false";
defparam \SW[8]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: UNVM_X0_Y40_N40
fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
.arclk(vcc),
.arshft(vcc),
.drclk(vcc),
.drshft(vcc),
.drdin(vcc),
.nprogram(vcc),
.nerase(vcc),
.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
.par_en(vcc),
.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
.se(\~QUARTUS_CREATED_GND~I_combout ),
.ardin(23'b11111111111111111111111),
.busy(\~QUARTUS_CREATED_UNVM~~busy ),
.osc(),
.bgpbusy(),
.sp_pass(),
.se_pass(),
.drdout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
// synopsys translate_on
// Location: ADCBLOCK_X43_Y52_N0
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
.soc(\~QUARTUS_CREATED_GND~I_combout ),
.usr_pwd(vcc),
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
.clkin_from_pll_c0(gnd),
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
.dout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
// synopsys translate_on
// Location: ADCBLOCK_X43_Y51_N0
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
.soc(\~QUARTUS_CREATED_GND~I_combout ),
.usr_pwd(vcc),
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
.clkin_from_pll_c0(gnd),
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
.dout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
// synopsys translate_on
assign LEDR[0] = \LEDR[0]~output_o ;
assign LEDR[1] = \LEDR[1]~output_o ;
assign LEDR[2] = \LEDR[2]~output_o ;
assign LEDR[3] = \LEDR[3]~output_o ;
assign LEDR[4] = \LEDR[4]~output_o ;
assign LEDR[5] = \LEDR[5]~output_o ;
assign LEDR[6] = \LEDR[6]~output_o ;
assign LEDR[7] = \LEDR[7]~output_o ;
assign LEDR[8] = \LEDR[8]~output_o ;
assign LEDR[9] = \LEDR[9]~output_o ;
endmodule
module hard_block (
devpor,
devclrn,
devoe);
// Design Ports Information
// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
input devpor;
input devclrn;
input devoe;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
wire \~ALTERA_TMS~~padout ;
wire \~ALTERA_TCK~~padout ;
wire \~ALTERA_TDI~~padout ;
wire \~ALTERA_CONFIG_SEL~~padout ;
wire \~ALTERA_nCONFIG~~padout ;
wire \~ALTERA_nSTATUS~~padout ;
wire \~ALTERA_CONF_DONE~~padout ;
wire \~ALTERA_TMS~~ibuf_o ;
wire \~ALTERA_TCK~~ibuf_o ;
wire \~ALTERA_TDI~~ibuf_o ;
wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
wire \~ALTERA_nCONFIG~~ibuf_o ;
wire \~ALTERA_nSTATUS~~ibuf_o ;
wire \~ALTERA_CONF_DONE~~ibuf_o ;
endmodule