19 lines
576 B
Verilog
19 lines
576 B
Verilog
module Part3 (SW,LEDR);
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input [9:0]SW;
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output [9:0]LEDR;
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wire [1:0] S, U, V, W, X, M;
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wire [1:0] U_V, W_X;
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assign S[1:0]=SW[9:8];
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assign U=SW[1:0];
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assign V=SW[3:2];
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assign W=SW[5:4];
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assign X=SW[7:6];
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assign U_V[0]=(~S[0] & U[0])|(S[0] & V[0]);
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assign U_V[1]=(~S[0] & U[1])|(S[0] & V[1]);
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assign W_X[0]=(~S[0] & W[0])|(S[0] & X[0]);
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assign W_X[1]=(~S[0] & W[1])|(S[0] & X[1]);
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assign M[0]=(~S[0] & U_V[0])|(S[0] & W_X[0]);
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assign M[1]=(~S[1] & U_V[1])|(S[1] & W_X[1]);
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assign LEDR[1:0]=M;
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assign LEDR[9:2]=8`b0;
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endmodule |