81 lines
2.4 KiB
Plaintext
81 lines
2.4 KiB
Plaintext
// Copyright (C) 2016 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel MegaCore Function License Agreement, or other
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// applicable license agreement, including, without limitation,
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// that your use is for the sole purpose of programming logic
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// devices manufactured by Intel and sold by Intel or its
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// authorized distributors. Please refer to the applicable
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// agreement for further details.
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// *****************************************************************************
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// This file contains a Verilog test bench with test vectors .The test vectors
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// are exported from a vector file in the Quartus Waveform Editor and apply to
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// the top level entity of the current Quartus project .The user can use this
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// testbench to simulate his design using a third-party simulation tool .
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// *****************************************************************************
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// Generated on "01/21/2021 20:12:10"
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// Verilog Test Bench (with test vectors) for design : decoder
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//
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// Simulation tool : 3rd Party
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//
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`timescale 1 ps/ 1 ps
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module decoder_vlg_vec_tst();
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// constants
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// general purpose registers
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reg A;
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reg B;
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// wires
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wire Q0;
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wire Q1;
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wire Q2;
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wire Q3;
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// assign statements (if any)
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decoder i1 (
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// port map - connection between master ports and signals/registers
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.A(A),
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.B(B),
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.Q0(Q0),
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.Q1(Q1),
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.Q2(Q2),
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.Q3(Q3)
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);
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initial
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begin
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#200000 $finish;
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end
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// A
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initial
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begin
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A = 1'b0;
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A = #10000 1'b1;
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A = #20000 1'b0;
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A = #30000 1'b1;
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A = #30000 1'b0;
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A = #60000 1'b1;
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A = #10000 1'b0;
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end
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// B
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initial
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begin
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B = 1'b0;
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B = #60000 1'b1;
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B = #30000 1'b0;
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B = #20000 1'b1;
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B = #10000 1'b0;
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B = #30000 1'b1;
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B = #10000 1'b0;
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end
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endmodule
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