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UAHCode/EE203/Noah Woodlee/Lab2/part3/output_files/part3.flow.rpt
2022-08-28 16:12:16 -05:00

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Flow report for part3
Sun Apr 25 00:52:01 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Sun Apr 25 00:52:01 2021 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; part3 ;
; Top-level Entity Name ; part3 ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C6GES ;
; Timing Models ; Preliminary ;
; Total logic elements ; 10 / 49,760 ( < 1 % ) ;
; Total combinational functions ; 10 / 49,760 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 14 / 360 ( 4 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 1,677,312 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/25/2021 00:24:59 ;
; Main task ; Compilation ;
; Revision Name ; part3 ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 164639278517.161932829928305 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1 ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1 ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1 ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:15 ; 1.0 ; 390 MB ; 00:00:31 ;
; Fitter ; 00:00:12 ; 1.0 ; 1079 MB ; 00:00:16 ;
; Assembler ; 00:00:04 ; 1.0 ; 358 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:03 ; 1.0 ; 508 MB ; 00:00:03 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 593 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 597 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4656 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4660 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4652 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4660 MB ; 00:00:01 ;
; Total ; 00:00:40 ; -- ; -- ; 00:01:01 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+-------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+-------------------+------------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+-------------------+------------------+------------+----------------+
; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; EDA Netlist Writer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; EDA Netlist Writer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; GENERAL-AN ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+-------------------+------------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3
quartus_fit --read_settings_files=off --write_settings_files=off part3 -c part3
quartus_asm --read_settings_files=off --write_settings_files=off part3 -c part3
quartus_sta part3 -c part3
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform.vwf" --testbench_file="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform.vwf.vt"
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt"
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt"
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3