110 lines
5.4 KiB
Plaintext
110 lines
5.4 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2020 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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# Date created = 16:26:05 April 21, 2021
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# part5_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name DEVICE 10M50DAF484C7G
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set_global_assignment -name TOP_LEVEL_ENTITY part5
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:26:05 APRIL 21, 2021"
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set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name VERILOG_FILE part5.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top
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set_location_assignment PIN_A8 -to LEDR[0]
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set_location_assignment PIN_A9 -to LEDR[1]
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set_location_assignment PIN_A10 -to LEDR[2]
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set_location_assignment PIN_B10 -to LEDR[3]
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set_location_assignment PIN_D13 -to LEDR[4]
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set_location_assignment PIN_C13 -to LEDR[5]
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set_location_assignment PIN_E14 -to LEDR[6]
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set_location_assignment PIN_D14 -to LEDR[7]
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set_location_assignment PIN_A11 -to LEDR[8]
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set_location_assignment PIN_B11 -to LEDR[9]
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set_location_assignment PIN_C10 -to SW[0]
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set_location_assignment PIN_C11 -to SW[1]
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set_location_assignment PIN_D12 -to SW[2]
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set_location_assignment PIN_C12 -to SW[3]
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set_location_assignment PIN_A12 -to SW[4]
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set_location_assignment PIN_B12 -to SW[5]
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set_location_assignment PIN_A13 -to SW[6]
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set_location_assignment PIN_A14 -to SW[7]
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set_location_assignment PIN_B14 -to SW[8]
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set_location_assignment PIN_F15 -to SW[9]
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top
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set_location_assignment PIN_C14 -to HEX0[0]
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set_location_assignment PIN_E15 -to HEX0[1]
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set_location_assignment PIN_C15 -to HEX0[2]
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set_location_assignment PIN_C16 -to HEX0[3]
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set_location_assignment PIN_E16 -to HEX0[4]
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set_location_assignment PIN_D17 -to HEX0[5]
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set_location_assignment PIN_C17 -to HEX0[6]
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set_location_assignment PIN_C18 -to HEX1[0]
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set_location_assignment PIN_D18 -to HEX1[1]
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set_location_assignment PIN_B20 -to HEX2[0]
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set_location_assignment PIN_A20 -to HEX2[1]
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set_location_assignment PIN_F21 -to HEX3[0]
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set_location_assignment PIN_E22 -to HEX3[1]
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set_location_assignment PIN_E18 -to HEX1[2]
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set_location_assignment PIN_B16 -to HEX1[3]
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set_location_assignment PIN_A17 -to HEX1[4]
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set_location_assignment PIN_A18 -to HEX1[5]
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set_location_assignment PIN_B17 -to HEX1[6]
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set_location_assignment PIN_B19 -to HEX2[2]
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set_location_assignment PIN_A21 -to HEX2[3]
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set_location_assignment PIN_B21 -to HEX2[4]
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set_location_assignment PIN_C22 -to HEX2[5]
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set_location_assignment PIN_B22 -to HEX2[6]
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set_location_assignment PIN_E21 -to HEX3[2]
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set_location_assignment PIN_C19 -to HEX3[3]
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set_location_assignment PIN_C20 -to HEX3[4]
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set_location_assignment PIN_D19 -to HEX3[5]
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set_location_assignment PIN_E17 -to HEX3[6]
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |