384 lines
11 KiB
Plaintext
384 lines
11 KiB
Plaintext
// Copyright (C) 2016 Intel Corporation. All rights reserved.
|
|
// Your use of Intel Corporation's design tools, logic functions
|
|
// and other software and tools, and its AMPP partner logic
|
|
// functions, and any output files from any of the foregoing
|
|
// (including device programming or simulation files), and any
|
|
// associated documentation or information are expressly subject
|
|
// to the terms and conditions of the Intel Program License
|
|
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
// the Intel MegaCore Function License Agreement, or other
|
|
// applicable license agreement, including, without limitation,
|
|
// that your use is for the sole purpose of programming logic
|
|
// devices manufactured by Intel and sold by Intel or its
|
|
// authorized distributors. Please refer to the applicable
|
|
// agreement for further details.
|
|
|
|
// VENDOR "Altera"
|
|
// PROGRAM "Quartus Prime"
|
|
// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition"
|
|
|
|
// DATE "01/21/2021 20:12:11"
|
|
|
|
//
|
|
// Device: Altera 10M50DAF484C7G Package FBGA484
|
|
//
|
|
|
|
//
|
|
// This Verilog file should be used for ModelSim-Altera (Verilog) only
|
|
//
|
|
|
|
`timescale 1 ps/ 1 ps
|
|
|
|
module decoder (
|
|
Q0,
|
|
B,
|
|
A,
|
|
Q1,
|
|
Q2,
|
|
Q3);
|
|
output Q0;
|
|
input B;
|
|
input A;
|
|
output Q1;
|
|
output Q2;
|
|
output Q3;
|
|
|
|
// Design Ports Information
|
|
// Q0 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
|
|
// Q1 => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default
|
|
// Q2 => Location: PIN_AA2, I/O Standard: 2.5 V, Current Strength: Default
|
|
// Q3 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default
|
|
// B => Location: PIN_W3, I/O Standard: 2.5 V, Current Strength: Default
|
|
// A => Location: PIN_W4, I/O Standard: 2.5 V, Current Strength: Default
|
|
|
|
|
|
wire gnd;
|
|
wire vcc;
|
|
wire unknown;
|
|
|
|
assign gnd = 1'b0;
|
|
assign vcc = 1'b1;
|
|
assign unknown = 1'bx;
|
|
|
|
tri1 devclrn;
|
|
tri1 devpor;
|
|
tri1 devoe;
|
|
wire \~QUARTUS_CREATED_GND~I_combout ;
|
|
wire \~QUARTUS_CREATED_UNVM~~busy ;
|
|
wire \~QUARTUS_CREATED_ADC1~~eoc ;
|
|
wire \~QUARTUS_CREATED_ADC2~~eoc ;
|
|
wire \Q0~output_o ;
|
|
wire \Q1~output_o ;
|
|
wire \Q2~output_o ;
|
|
wire \Q3~output_o ;
|
|
wire \B~input_o ;
|
|
wire \A~input_o ;
|
|
wire \inst~combout ;
|
|
wire \inst2~0_combout ;
|
|
wire \inst2~1_combout ;
|
|
wire \inst2~2_combout ;
|
|
|
|
|
|
hard_block auto_generated_inst(
|
|
.devpor(devpor),
|
|
.devclrn(devclrn),
|
|
.devoe(devoe));
|
|
|
|
// Location: LCCOMB_X44_Y42_N8
|
|
fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
|
|
// Equation(s):
|
|
// \~QUARTUS_CREATED_GND~I_combout = GND
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
|
|
defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X16_Y0_N16
|
|
fiftyfivenm_io_obuf \Q0~output (
|
|
.i(!\inst~combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(\Q0~output_o ),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \Q0~output .bus_hold = "false";
|
|
defparam \Q0~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X18_Y0_N30
|
|
fiftyfivenm_io_obuf \Q1~output (
|
|
.i(\inst2~0_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(\Q1~output_o ),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \Q1~output .bus_hold = "false";
|
|
defparam \Q1~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X18_Y0_N23
|
|
fiftyfivenm_io_obuf \Q2~output (
|
|
.i(\inst2~1_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(\Q2~output_o ),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \Q2~output .bus_hold = "false";
|
|
defparam \Q2~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X16_Y0_N2
|
|
fiftyfivenm_io_obuf \Q3~output (
|
|
.i(\inst2~2_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(\Q3~output_o ),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \Q3~output .bus_hold = "false";
|
|
defparam \Q3~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X18_Y0_N8
|
|
fiftyfivenm_io_ibuf \B~input (
|
|
.i(B),
|
|
.ibar(gnd),
|
|
.nsleep(vcc),
|
|
.o(\B~input_o ));
|
|
// synopsys translate_off
|
|
defparam \B~input .bus_hold = "false";
|
|
defparam \B~input .listen_to_nsleep_signal = "false";
|
|
defparam \B~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X18_Y0_N15
|
|
fiftyfivenm_io_ibuf \A~input (
|
|
.i(A),
|
|
.ibar(gnd),
|
|
.nsleep(vcc),
|
|
.o(\A~input_o ));
|
|
// synopsys translate_off
|
|
defparam \A~input .bus_hold = "false";
|
|
defparam \A~input .listen_to_nsleep_signal = "false";
|
|
defparam \A~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X18_Y1_N0
|
|
fiftyfivenm_lcell_comb inst(
|
|
// Equation(s):
|
|
// \inst~combout = (\B~input_o ) # (\A~input_o )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\B~input_o ),
|
|
.datad(\A~input_o ),
|
|
.cin(gnd),
|
|
.combout(\inst~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam inst.lut_mask = 16'hFFF0;
|
|
defparam inst.sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X18_Y1_N2
|
|
fiftyfivenm_lcell_comb \inst2~0 (
|
|
// Equation(s):
|
|
// \inst2~0_combout = (\B~input_o & !\A~input_o )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\B~input_o ),
|
|
.datad(\A~input_o ),
|
|
.cin(gnd),
|
|
.combout(\inst2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \inst2~0 .lut_mask = 16'h00F0;
|
|
defparam \inst2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X18_Y1_N4
|
|
fiftyfivenm_lcell_comb \inst2~1 (
|
|
// Equation(s):
|
|
// \inst2~1_combout = (!\B~input_o & \A~input_o )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\B~input_o ),
|
|
.datad(\A~input_o ),
|
|
.cin(gnd),
|
|
.combout(\inst2~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \inst2~1 .lut_mask = 16'h0F00;
|
|
defparam \inst2~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X18_Y1_N6
|
|
fiftyfivenm_lcell_comb \inst2~2 (
|
|
// Equation(s):
|
|
// \inst2~2_combout = (\B~input_o & \A~input_o )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\B~input_o ),
|
|
.datad(\A~input_o ),
|
|
.cin(gnd),
|
|
.combout(\inst2~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \inst2~2 .lut_mask = 16'hF000;
|
|
defparam \inst2~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: UNVM_X0_Y40_N40
|
|
fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
|
|
.arclk(vcc),
|
|
.arshft(vcc),
|
|
.drclk(vcc),
|
|
.drshft(vcc),
|
|
.drdin(vcc),
|
|
.nprogram(vcc),
|
|
.nerase(vcc),
|
|
.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.par_en(vcc),
|
|
.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.se(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.ardin(23'b11111111111111111111111),
|
|
.busy(\~QUARTUS_CREATED_UNVM~~busy ),
|
|
.osc(),
|
|
.bgpbusy(),
|
|
.sp_pass(),
|
|
.se_pass(),
|
|
.drdout());
|
|
// synopsys translate_off
|
|
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
|
|
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
|
|
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
|
|
defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
|
|
defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
|
|
defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
|
|
defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
|
|
defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
|
|
defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
|
|
defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
|
|
defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
|
|
defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
|
|
// synopsys translate_on
|
|
|
|
// Location: ADCBLOCK_X43_Y52_N0
|
|
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
|
|
.soc(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.usr_pwd(vcc),
|
|
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.clkin_from_pll_c0(gnd),
|
|
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
|
|
.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
|
|
.dout());
|
|
// synopsys translate_off
|
|
defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
|
|
defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
|
|
defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
|
|
defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
|
|
defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
|
|
defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
|
|
defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
|
|
defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
|
|
defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
|
|
defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
|
|
defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
|
|
// synopsys translate_on
|
|
|
|
// Location: ADCBLOCK_X43_Y51_N0
|
|
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
|
|
.soc(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.usr_pwd(vcc),
|
|
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
|
|
.clkin_from_pll_c0(gnd),
|
|
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
|
|
.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
|
|
.dout());
|
|
// synopsys translate_off
|
|
defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
|
|
defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
|
|
defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
|
|
defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
|
|
defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
|
|
defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
|
|
defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
|
|
defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
|
|
defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
|
|
defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
|
|
defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
|
|
// synopsys translate_on
|
|
|
|
assign Q0 = \Q0~output_o ;
|
|
|
|
assign Q1 = \Q1~output_o ;
|
|
|
|
assign Q2 = \Q2~output_o ;
|
|
|
|
assign Q3 = \Q3~output_o ;
|
|
|
|
endmodule
|
|
|
|
module hard_block (
|
|
|
|
devpor,
|
|
devclrn,
|
|
devoe);
|
|
|
|
// Design Ports Information
|
|
// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
|
// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
|
// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
|
// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
|
|
// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
|
|
// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
|
// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
|
// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
|
|
|
input devpor;
|
|
input devclrn;
|
|
input devoe;
|
|
|
|
wire gnd;
|
|
wire vcc;
|
|
wire unknown;
|
|
|
|
assign gnd = 1'b0;
|
|
assign vcc = 1'b1;
|
|
assign unknown = 1'bx;
|
|
|
|
wire \~ALTERA_TMS~~padout ;
|
|
wire \~ALTERA_TCK~~padout ;
|
|
wire \~ALTERA_TDI~~padout ;
|
|
wire \~ALTERA_CONFIG_SEL~~padout ;
|
|
wire \~ALTERA_nCONFIG~~padout ;
|
|
wire \~ALTERA_nSTATUS~~padout ;
|
|
wire \~ALTERA_CONF_DONE~~padout ;
|
|
wire \~ALTERA_TMS~~ibuf_o ;
|
|
wire \~ALTERA_TCK~~ibuf_o ;
|
|
wire \~ALTERA_TDI~~ibuf_o ;
|
|
wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
|
|
wire \~ALTERA_nCONFIG~~ibuf_o ;
|
|
wire \~ALTERA_nSTATUS~~ibuf_o ;
|
|
wire \~ALTERA_CONF_DONE~~ibuf_o ;
|
|
|
|
|
|
endmodule
|