37 lines
765 B
Verilog
37 lines
765 B
Verilog
module bcd(IN,OUT);
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input [3:0] IN;
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output [6:0] OUT;
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assign OUT=IN[3]? (IN[0]? 7'b0010_000:7'b0000_000):
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(IN[2]? (IN[1]? (IN[0]? 7'b1111_000:7'b0000_010):
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(IN[0]? 7'b0010_010:7'b0011_001)):
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(IN[1]? (IN[0]? 7'b0110_000:7'b0100_100):
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(IN[0]? 7'b1111_001:7'b1000_000)));
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endmodule
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module part5(SW, HEX0, HEX1);
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input [8:0] SW;
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output [6:0] HEX0, HEX1;
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reg [4:0] U;
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always@(*)
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begin
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U = SW[3:0] + SW[7:4] + SW[8];
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if (U > 9) begin
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U[3:0] = U[3:0]-10;
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U[4] = 1;
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end
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else begin
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U[4] = 0;
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end
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end
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bcd b0(U[3:0], HEX0);
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bcd b1(U[4], HEX1);
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endmodule
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