added more code
This commit is contained in:
Andrew W
27
CPE325/Lab10_Part3/Debug/Lab10_Part3.d
Normal file
27
CPE325/Lab10_Part3/Debug/Lab10_Part3.d
Normal file
@ -0,0 +1,27 @@
|
||||
# FIXED
|
||||
|
||||
Lab10_Part3.obj: ../Lab10_Part3.c
|
||||
Lab10_Part3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h
|
||||
Lab10_Part3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h
|
||||
Lab10_Part3.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h
|
||||
Lab10_Part3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h
|
||||
Lab10_Part3.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h
|
||||
Lab10_Part3.obj: C:/CPE325_Workspace/Lab10_Part3/sawtooth.h
|
||||
Lab10_Part3.obj: C:/CPE325_Workspace/Lab10_Part3/sine_lut_512.h
|
||||
|
||||
../Lab10_Part3.c:
|
||||
|
||||
C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h:
|
||||
|
||||
C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h:
|
||||
|
||||
C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h:
|
||||
|
||||
C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h:
|
||||
|
||||
C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h:
|
||||
|
||||
C:/CPE325_Workspace/Lab10_Part3/sawtooth.h:
|
||||
|
||||
C:/CPE325_Workspace/Lab10_Part3/sine_lut_512.h:
|
||||
|
||||
810
CPE325/Lab10_Part3/Debug/Lab10_Part3.map
Normal file
810
CPE325/Lab10_Part3/Debug/Lab10_Part3.map
Normal file
@ -0,0 +1,810 @@
|
||||
******************************************************************************
|
||||
MSP430 Linker PC v20.2.5
|
||||
******************************************************************************
|
||||
>> Linked Thu Dec 2 20:38:02 2021
|
||||
|
||||
OUTPUT FILE NAME: <Lab10_Part3.out>
|
||||
ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00003100
|
||||
|
||||
|
||||
MEMORY CONFIGURATION
|
||||
|
||||
name origin length used unused attr fill
|
||||
---------------------- -------- --------- -------- -------- ---- --------
|
||||
SFR 00000000 00000010 00000000 00000010 RWIX
|
||||
PERIPHERALS_8BIT 00000010 000000f0 00000000 000000f0 RWIX
|
||||
PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX
|
||||
INFOB 00001000 00000080 00000000 00000080 RWIX
|
||||
INFOA 00001080 00000080 00000000 00000080 RWIX
|
||||
RAM 00001100 00002000 00000854 000017ac RWIX
|
||||
FLASH 00003100 0000cebe 00000802 0000c6bc RWIX
|
||||
BSLSIGNATURE 0000ffbe 00000002 00000002 00000000 RWIX ffff
|
||||
INT00 0000ffc0 00000002 00000000 00000002 RWIX
|
||||
INT01 0000ffc2 00000002 00000000 00000002 RWIX
|
||||
INT02 0000ffc4 00000002 00000000 00000002 RWIX
|
||||
INT03 0000ffc6 00000002 00000000 00000002 RWIX
|
||||
INT04 0000ffc8 00000002 00000000 00000002 RWIX
|
||||
INT05 0000ffca 00000002 00000000 00000002 RWIX
|
||||
INT06 0000ffcc 00000002 00000000 00000002 RWIX
|
||||
INT07 0000ffce 00000002 00000000 00000002 RWIX
|
||||
INT08 0000ffd0 00000002 00000000 00000002 RWIX
|
||||
INT09 0000ffd2 00000002 00000000 00000002 RWIX
|
||||
INT10 0000ffd4 00000002 00000000 00000002 RWIX
|
||||
INT11 0000ffd6 00000002 00000000 00000002 RWIX
|
||||
INT12 0000ffd8 00000002 00000000 00000002 RWIX
|
||||
INT13 0000ffda 00000002 00000000 00000002 RWIX
|
||||
INT14 0000ffdc 00000002 00000002 00000000 RWIX
|
||||
INT15 0000ffde 00000002 00000002 00000000 RWIX
|
||||
INT16 0000ffe0 00000002 00000002 00000000 RWIX
|
||||
INT17 0000ffe2 00000002 00000002 00000000 RWIX
|
||||
INT18 0000ffe4 00000002 00000002 00000000 RWIX
|
||||
INT19 0000ffe6 00000002 00000002 00000000 RWIX
|
||||
INT20 0000ffe8 00000002 00000002 00000000 RWIX
|
||||
INT21 0000ffea 00000002 00000002 00000000 RWIX
|
||||
INT22 0000ffec 00000002 00000002 00000000 RWIX
|
||||
INT23 0000ffee 00000002 00000002 00000000 RWIX
|
||||
INT24 0000fff0 00000002 00000002 00000000 RWIX
|
||||
INT25 0000fff2 00000002 00000002 00000000 RWIX
|
||||
INT26 0000fff4 00000002 00000002 00000000 RWIX
|
||||
INT27 0000fff6 00000002 00000002 00000000 RWIX
|
||||
INT28 0000fff8 00000002 00000002 00000000 RWIX
|
||||
INT29 0000fffa 00000002 00000002 00000000 RWIX
|
||||
INT30 0000fffc 00000002 00000002 00000000 RWIX
|
||||
RESET 0000fffe 00000002 00000002 00000000 RWIX
|
||||
FLASH2 00010000 00010000 00000184 0000fe7c RWIX
|
||||
|
||||
|
||||
SECTION ALLOCATION MAP
|
||||
|
||||
output attributes/
|
||||
section page origin length input sections
|
||||
-------- ---- ---------- ---------- ----------------
|
||||
.data 0 00001100 00000804 UNINITIALIZED
|
||||
00001100 00000402 Lab10_Part3.obj (.data:sawtooth)
|
||||
00001502 00000402 Lab10_Part3.obj (.data:sine)
|
||||
|
||||
.stack 0 000030b0 00000050 UNINITIALIZED
|
||||
000030b0 00000004 rts430x_lc_rd_eabi.lib : boot.c.obj (.stack)
|
||||
000030b4 0000004c --HOLE--
|
||||
|
||||
.text:_isr
|
||||
* 0 00003100 0000002c
|
||||
00003100 0000001c rts430x_lc_rd_eabi.lib : boot.c.obj (.text:_isr:_c_int00_noargs)
|
||||
0000311c 00000008 Lab10_Part3.obj (.text:_isr:TA0_ISR)
|
||||
00003124 00000008 rts430x_lc_rd_eabi.lib : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP)
|
||||
|
||||
.cinit 0 0000312c 000007d6
|
||||
0000312c 000007c5 (.cinit..data.load) [load image, compression = lzss]
|
||||
000038f1 00000001 --HOLE-- [fill = 0]
|
||||
000038f2 00000008 (__TI_handler_table)
|
||||
000038fa 00000008 (__TI_cinit_table)
|
||||
|
||||
.binit 0 00003100 00000000
|
||||
|
||||
.init_array
|
||||
* 0 00003100 00000000 UNINITIALIZED
|
||||
|
||||
$fill000 0 0000ffbe 00000002
|
||||
0000ffbe 00000002 --HOLE-- [fill = ffff]
|
||||
|
||||
DAC12 0 0000ffdc 00000002
|
||||
0000ffdc 00000002 rts430x_lc_rd_eabi.lib : int14.asm.obj (.int14)
|
||||
|
||||
DMA 0 0000ffde 00000002
|
||||
0000ffde 00000002 rts430x_lc_rd_eabi.lib : int15.asm.obj (.int15)
|
||||
|
||||
BASICTIMER
|
||||
* 0 0000ffe0 00000002
|
||||
0000ffe0 00000002 rts430x_lc_rd_eabi.lib : int16.asm.obj (.int16)
|
||||
|
||||
PORT2 0 0000ffe2 00000002
|
||||
0000ffe2 00000002 rts430x_lc_rd_eabi.lib : int17.asm.obj (.int17)
|
||||
|
||||
USART1TX 0 0000ffe4 00000002
|
||||
0000ffe4 00000002 rts430x_lc_rd_eabi.lib : int18.asm.obj (.int18)
|
||||
|
||||
USART1RX 0 0000ffe6 00000002
|
||||
0000ffe6 00000002 rts430x_lc_rd_eabi.lib : int19.asm.obj (.int19)
|
||||
|
||||
PORT1 0 0000ffe8 00000002
|
||||
0000ffe8 00000002 rts430x_lc_rd_eabi.lib : int20.asm.obj (.int20)
|
||||
|
||||
TIMERA1 0 0000ffea 00000002
|
||||
0000ffea 00000002 rts430x_lc_rd_eabi.lib : int21.asm.obj (.int21)
|
||||
|
||||
TIMERA0 0 0000ffec 00000002
|
||||
0000ffec 00000002 Lab10_Part3.obj (.int22)
|
||||
|
||||
ADC12 0 0000ffee 00000002
|
||||
0000ffee 00000002 rts430x_lc_rd_eabi.lib : int23.asm.obj (.int23)
|
||||
|
||||
USCIAB0TX
|
||||
* 0 0000fff0 00000002
|
||||
0000fff0 00000002 rts430x_lc_rd_eabi.lib : int24.asm.obj (.int24)
|
||||
|
||||
USCIAB0RX
|
||||
* 0 0000fff2 00000002
|
||||
0000fff2 00000002 rts430x_lc_rd_eabi.lib : int25.asm.obj (.int25)
|
||||
|
||||
WDT 0 0000fff4 00000002
|
||||
0000fff4 00000002 rts430x_lc_rd_eabi.lib : int26.asm.obj (.int26)
|
||||
|
||||
COMPARATORA
|
||||
* 0 0000fff6 00000002
|
||||
0000fff6 00000002 rts430x_lc_rd_eabi.lib : int27.asm.obj (.int27)
|
||||
|
||||
TIMERB1 0 0000fff8 00000002
|
||||
0000fff8 00000002 rts430x_lc_rd_eabi.lib : int28.asm.obj (.int28)
|
||||
|
||||
TIMERB0 0 0000fffa 00000002
|
||||
0000fffa 00000002 rts430x_lc_rd_eabi.lib : int29.asm.obj (.int29)
|
||||
|
||||
NMI 0 0000fffc 00000002
|
||||
0000fffc 00000002 rts430x_lc_rd_eabi.lib : int30.asm.obj (.int30)
|
||||
|
||||
.reset 0 0000fffe 00000002
|
||||
0000fffe 00000002 rts430x_lc_rd_eabi.lib : boot.c.obj (.reset)
|
||||
|
||||
.text 0 00010000 00000184
|
||||
00010000 00000076 rts430x_lc_rd_eabi.lib : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss)
|
||||
00010076 0000005e Lab10_Part3.obj (.text:main)
|
||||
000100d4 00000054 rts430x_lc_rd_eabi.lib : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt)
|
||||
00010128 00000016 Lab10_Part3.obj (.text:DAC_setup)
|
||||
0001013e 00000014 Lab10_Part3.obj (.text:TimerA_setup)
|
||||
00010152 00000014 rts430x_lc_rd_eabi.lib : memcpy.c.obj (.text:memcpy)
|
||||
00010166 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none)
|
||||
00010178 00000006 : exit.c.obj (.text:abort)
|
||||
0001017e 00000004 : pre_init.c.obj (.text:_system_pre_init)
|
||||
00010182 00000002 : startup.c.obj (.text:_system_post_cinit)
|
||||
|
||||
MODULE SUMMARY
|
||||
|
||||
Module code ro data rw data
|
||||
------ ---- ------- -------
|
||||
.\
|
||||
Lab10_Part3.obj 144 2 2052
|
||||
+--+----------------------------+------+---------+---------+
|
||||
Total: 144 2 2052
|
||||
|
||||
C:\ti\ccs1040\ccs\tools\compiler\ti-cgt-msp430_20.2.5.LTS\lib\rts430x_lc_rd_eabi.lib
|
||||
copy_decompress_lzss.c.obj 118 0 0
|
||||
autoinit.c.obj 84 0 0
|
||||
boot.c.obj 28 2 0
|
||||
memcpy.c.obj 20 0 0
|
||||
copy_decompress_none.c.obj 18 0 0
|
||||
isr_trap.asm.obj 8 0 0
|
||||
exit.c.obj 6 0 0
|
||||
pre_init.c.obj 4 0 0
|
||||
int14.asm.obj 0 2 0
|
||||
int15.asm.obj 0 2 0
|
||||
int16.asm.obj 0 2 0
|
||||
int17.asm.obj 0 2 0
|
||||
int18.asm.obj 0 2 0
|
||||
int19.asm.obj 0 2 0
|
||||
int20.asm.obj 0 2 0
|
||||
int21.asm.obj 0 2 0
|
||||
int23.asm.obj 0 2 0
|
||||
int24.asm.obj 0 2 0
|
||||
int25.asm.obj 0 2 0
|
||||
int26.asm.obj 0 2 0
|
||||
int27.asm.obj 0 2 0
|
||||
int28.asm.obj 0 2 0
|
||||
int29.asm.obj 0 2 0
|
||||
int30.asm.obj 0 2 0
|
||||
startup.c.obj 2 0 0
|
||||
+--+----------------------------+------+---------+---------+
|
||||
Total: 288 34 0
|
||||
|
||||
Stack: 0 0 80
|
||||
Linker Generated: 0 2005 0
|
||||
+--+----------------------------+------+---------+---------+
|
||||
Grand Total: 432 2041 2132
|
||||
|
||||
|
||||
LINKER GENERATED COPY TABLES
|
||||
|
||||
__TI_cinit_table @ 000038fa records: 1, size/record: 8, table size: 8
|
||||
.data: load addr=0000312c, load size=000007c5 bytes, run addr=00001100, run size=00000804 bytes, compression=lzss
|
||||
|
||||
|
||||
LINKER GENERATED HANDLER TABLE
|
||||
|
||||
__TI_handler_table @ 000038f2 records: 2, size/record: 4, table size: 8
|
||||
index: 0, handler: __TI_decompress_lzss
|
||||
index: 1, handler: __TI_decompress_none
|
||||
|
||||
|
||||
GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
|
||||
|
||||
address name
|
||||
------- ----
|
||||
000001a0 ADC12CTL0
|
||||
000001a2 ADC12CTL1
|
||||
000001a6 ADC12IE
|
||||
000001a4 ADC12IFG
|
||||
000001a8 ADC12IV
|
||||
00000080 ADC12MCTL0
|
||||
00000081 ADC12MCTL1
|
||||
0000008a ADC12MCTL10
|
||||
0000008b ADC12MCTL11
|
||||
0000008c ADC12MCTL12
|
||||
0000008d ADC12MCTL13
|
||||
0000008e ADC12MCTL14
|
||||
0000008f ADC12MCTL15
|
||||
00000082 ADC12MCTL2
|
||||
00000083 ADC12MCTL3
|
||||
00000084 ADC12MCTL4
|
||||
00000085 ADC12MCTL5
|
||||
00000086 ADC12MCTL6
|
||||
00000087 ADC12MCTL7
|
||||
00000088 ADC12MCTL8
|
||||
00000089 ADC12MCTL9
|
||||
00000140 ADC12MEM0
|
||||
00000142 ADC12MEM1
|
||||
00000154 ADC12MEM10
|
||||
00000156 ADC12MEM11
|
||||
00000158 ADC12MEM12
|
||||
0000015a ADC12MEM13
|
||||
0000015c ADC12MEM14
|
||||
0000015e ADC12MEM15
|
||||
00000144 ADC12MEM2
|
||||
00000146 ADC12MEM3
|
||||
00000148 ADC12MEM4
|
||||
0000014a ADC12MEM5
|
||||
0000014c ADC12MEM6
|
||||
0000014e ADC12MEM7
|
||||
00000150 ADC12MEM8
|
||||
00000152 ADC12MEM9
|
||||
00000046 BTCNT1
|
||||
00000046 BTCNT12
|
||||
00000047 BTCNT2
|
||||
00000040 BTCTL
|
||||
00010178 C$$EXIT
|
||||
00000059 CACTL1
|
||||
0000005a CACTL2
|
||||
0000005b CAPD
|
||||
000001c0 DAC12_0CTL
|
||||
000001c8 DAC12_0DAT
|
||||
000001c2 DAC12_1CTL
|
||||
000001ca DAC12_1DAT
|
||||
00010128 DAC_setup
|
||||
000001d0 DMA0CTL
|
||||
000001d6 DMA0DA
|
||||
000001d6 DMA0DAL
|
||||
000001d2 DMA0SA
|
||||
000001d2 DMA0SAL
|
||||
000001da DMA0SZ
|
||||
000001dc DMA1CTL
|
||||
000001e2 DMA1DA
|
||||
000001e2 DMA1DAL
|
||||
000001de DMA1SA
|
||||
000001de DMA1SAL
|
||||
000001e6 DMA1SZ
|
||||
000001e8 DMA2CTL
|
||||
000001ee DMA2DA
|
||||
000001ee DMA2DAL
|
||||
000001ea DMA2SA
|
||||
000001ea DMA2SAL
|
||||
000001f2 DMA2SZ
|
||||
00000122 DMACTL0
|
||||
00000124 DMACTL1
|
||||
00000126 DMAIV
|
||||
00000128 FCTL1
|
||||
0000012a FCTL2
|
||||
0000012c FCTL3
|
||||
00000053 FLL_CTL0
|
||||
00000054 FLL_CTL1
|
||||
00000000 IE1
|
||||
00000001 IE2
|
||||
00000002 IFG1
|
||||
00000003 IFG2
|
||||
00000090 LCDACTL
|
||||
000000ac LCDAPCTL0
|
||||
000000ad LCDAPCTL1
|
||||
000000ae LCDAVCTL0
|
||||
000000af LCDAVCTL1
|
||||
00000091 LCDM1
|
||||
0000009a LCDM10
|
||||
0000009b LCDM11
|
||||
0000009c LCDM12
|
||||
0000009d LCDM13
|
||||
0000009e LCDM14
|
||||
0000009f LCDM15
|
||||
000000a0 LCDM16
|
||||
000000a1 LCDM17
|
||||
000000a2 LCDM18
|
||||
000000a3 LCDM19
|
||||
00000092 LCDM2
|
||||
000000a4 LCDM20
|
||||
00000093 LCDM3
|
||||
00000094 LCDM4
|
||||
00000095 LCDM5
|
||||
00000096 LCDM6
|
||||
00000097 LCDM7
|
||||
00000098 LCDM8
|
||||
00000099 LCDM9
|
||||
00000134 MAC
|
||||
00000136 MACS
|
||||
00000005 ME2
|
||||
00000130 MPY
|
||||
00000132 MPYS
|
||||
000000c0 OA0CTL0
|
||||
000000c1 OA0CTL1
|
||||
000000c2 OA1CTL0
|
||||
000000c3 OA1CTL1
|
||||
000000c4 OA2CTL0
|
||||
000000c5 OA2CTL1
|
||||
00000138 OP2
|
||||
0000000d P10DIR
|
||||
00000009 P10IN
|
||||
0000000b P10OUT
|
||||
0000000f P10SEL
|
||||
00000022 P1DIR
|
||||
00000025 P1IE
|
||||
00000024 P1IES
|
||||
00000023 P1IFG
|
||||
00000020 P1IN
|
||||
00000021 P1OUT
|
||||
00000026 P1SEL
|
||||
0000002a P2DIR
|
||||
0000002d P2IE
|
||||
0000002c P2IES
|
||||
0000002b P2IFG
|
||||
00000028 P2IN
|
||||
00000029 P2OUT
|
||||
0000002e P2SEL
|
||||
0000001a P3DIR
|
||||
00000018 P3IN
|
||||
00000019 P3OUT
|
||||
0000001b P3SEL
|
||||
0000001e P4DIR
|
||||
0000001c P4IN
|
||||
0000001d P4OUT
|
||||
0000001f P4SEL
|
||||
00000032 P5DIR
|
||||
00000030 P5IN
|
||||
00000031 P5OUT
|
||||
00000033 P5SEL
|
||||
00000036 P6DIR
|
||||
00000034 P6IN
|
||||
00000035 P6OUT
|
||||
00000037 P6SEL
|
||||
0000003c P7DIR
|
||||
00000038 P7IN
|
||||
0000003a P7OUT
|
||||
0000003e P7SEL
|
||||
0000003d P8DIR
|
||||
00000039 P8IN
|
||||
0000003b P8OUT
|
||||
0000003f P8SEL
|
||||
0000000c P9DIR
|
||||
00000008 P9IN
|
||||
0000000a P9OUT
|
||||
0000000e P9SEL
|
||||
0000003c PADIR
|
||||
00000038 PAIN
|
||||
0000003a PAOUT
|
||||
0000003e PASEL
|
||||
0000000c PBDIR
|
||||
00000008 PBIN
|
||||
0000000a PBOUT
|
||||
0000000e PBSEL
|
||||
0000013c RESHI
|
||||
0000013a RESLO
|
||||
00000041 RTCCTL
|
||||
0000004c RTCDATE
|
||||
0000004c RTCDAY
|
||||
0000004d RTCMON
|
||||
00000042 RTCNT1
|
||||
00000043 RTCNT2
|
||||
00000044 RTCNT3
|
||||
00000045 RTCNT4
|
||||
00000042 RTCTIM0
|
||||
00000044 RTCTIM1
|
||||
00000040 RTCTL
|
||||
0000004e RTCYEAR
|
||||
0000004f RTCYEARH
|
||||
0000004e RTCYEARL
|
||||
00000050 SCFI0
|
||||
00000051 SCFI1
|
||||
00000052 SCFQCTL
|
||||
0000013e SUMEXT
|
||||
00000056 SVSCTL
|
||||
0000311c TA0_ISR
|
||||
00000172 TACCR0
|
||||
00000174 TACCR1
|
||||
00000176 TACCR2
|
||||
00000162 TACCTL0
|
||||
00000164 TACCTL1
|
||||
00000166 TACCTL2
|
||||
00000160 TACTL
|
||||
0000012e TAIV
|
||||
00000170 TAR
|
||||
00000192 TBCCR0
|
||||
00000194 TBCCR1
|
||||
00000196 TBCCR2
|
||||
00000198 TBCCR3
|
||||
0000019a TBCCR4
|
||||
0000019c TBCCR5
|
||||
0000019e TBCCR6
|
||||
00000182 TBCCTL0
|
||||
00000184 TBCCTL1
|
||||
00000186 TBCCTL2
|
||||
00000188 TBCCTL3
|
||||
0000018a TBCCTL4
|
||||
0000018c TBCCTL5
|
||||
0000018e TBCCTL6
|
||||
00000180 TBCTL
|
||||
0000011e TBIV
|
||||
00000190 TBR
|
||||
0001013e TimerA_setup
|
||||
0000007c U1BR0
|
||||
0000007d U1BR1
|
||||
00000078 U1CTL
|
||||
0000007b U1MCTL
|
||||
0000007a U1RCTL
|
||||
0000007e U1RXBUF
|
||||
00000079 U1TCTL
|
||||
0000007f U1TXBUF
|
||||
0000005d UCA0ABCTL
|
||||
00000062 UCA0BR0
|
||||
00000063 UCA0BR1
|
||||
00000060 UCA0CTL0
|
||||
00000061 UCA0CTL1
|
||||
0000005f UCA0IRRCTL
|
||||
0000005e UCA0IRTCTL
|
||||
00000064 UCA0MCTL
|
||||
00000066 UCA0RXBUF
|
||||
00000065 UCA0STAT
|
||||
00000067 UCA0TXBUF
|
||||
0000006a UCB0BR0
|
||||
0000006b UCB0BR1
|
||||
00000068 UCB0CTL0
|
||||
00000069 UCB0CTL1
|
||||
0000006c UCB0I2CIE
|
||||
00000118 UCB0I2COA
|
||||
0000011a UCB0I2CSA
|
||||
0000006e UCB0RXBUF
|
||||
0000006d UCB0STAT
|
||||
0000006f UCB0TXBUF
|
||||
00000120 WDTCTL
|
||||
00003100 __STACK_END
|
||||
00000050 __STACK_SIZE
|
||||
000038fa __TI_CINIT_Base
|
||||
00003902 __TI_CINIT_Limit
|
||||
000038f2 __TI_Handler_Table_Base
|
||||
000038fa __TI_Handler_Table_Limit
|
||||
00003124 __TI_ISR_TRAP
|
||||
000100d4 __TI_auto_init_nobinit_nopinit_hold_wdt
|
||||
00010000 __TI_decompress_lzss
|
||||
00010166 __TI_decompress_none
|
||||
0000ffdc __TI_int14
|
||||
0000ffde __TI_int15
|
||||
0000ffe0 __TI_int16
|
||||
0000ffe2 __TI_int17
|
||||
0000ffe4 __TI_int18
|
||||
0000ffe6 __TI_int19
|
||||
0000ffe8 __TI_int20
|
||||
0000ffea __TI_int21
|
||||
0000ffec __TI_int22
|
||||
0000ffee __TI_int23
|
||||
0000fff0 __TI_int24
|
||||
0000fff2 __TI_int25
|
||||
0000fff4 __TI_int26
|
||||
0000fff6 __TI_int27
|
||||
0000fff8 __TI_int28
|
||||
0000fffa __TI_int29
|
||||
0000fffc __TI_int30
|
||||
ffffffff __TI_pprof_out_hndl
|
||||
ffffffff __TI_prof_data_size
|
||||
ffffffff __TI_prof_data_start
|
||||
ffffffff __c_args__
|
||||
00003100 _c_int00_noargs
|
||||
0000fffe _reset_vector
|
||||
000030b0 _stack
|
||||
00010182 _system_post_cinit
|
||||
0001017e _system_pre_init
|
||||
00010178 abort
|
||||
00010076 main
|
||||
00010152 memcpy
|
||||
00001100 sawtooth
|
||||
00001502 sine
|
||||
|
||||
|
||||
GLOBAL SYMBOLS: SORTED BY Symbol Address
|
||||
|
||||
address name
|
||||
------- ----
|
||||
00000000 IE1
|
||||
00000001 IE2
|
||||
00000002 IFG1
|
||||
00000003 IFG2
|
||||
00000005 ME2
|
||||
00000008 P9IN
|
||||
00000008 PBIN
|
||||
00000009 P10IN
|
||||
0000000a P9OUT
|
||||
0000000a PBOUT
|
||||
0000000b P10OUT
|
||||
0000000c P9DIR
|
||||
0000000c PBDIR
|
||||
0000000d P10DIR
|
||||
0000000e P9SEL
|
||||
0000000e PBSEL
|
||||
0000000f P10SEL
|
||||
00000018 P3IN
|
||||
00000019 P3OUT
|
||||
0000001a P3DIR
|
||||
0000001b P3SEL
|
||||
0000001c P4IN
|
||||
0000001d P4OUT
|
||||
0000001e P4DIR
|
||||
0000001f P4SEL
|
||||
00000020 P1IN
|
||||
00000021 P1OUT
|
||||
00000022 P1DIR
|
||||
00000023 P1IFG
|
||||
00000024 P1IES
|
||||
00000025 P1IE
|
||||
00000026 P1SEL
|
||||
00000028 P2IN
|
||||
00000029 P2OUT
|
||||
0000002a P2DIR
|
||||
0000002b P2IFG
|
||||
0000002c P2IES
|
||||
0000002d P2IE
|
||||
0000002e P2SEL
|
||||
00000030 P5IN
|
||||
00000031 P5OUT
|
||||
00000032 P5DIR
|
||||
00000033 P5SEL
|
||||
00000034 P6IN
|
||||
00000035 P6OUT
|
||||
00000036 P6DIR
|
||||
00000037 P6SEL
|
||||
00000038 P7IN
|
||||
00000038 PAIN
|
||||
00000039 P8IN
|
||||
0000003a P7OUT
|
||||
0000003a PAOUT
|
||||
0000003b P8OUT
|
||||
0000003c P7DIR
|
||||
0000003c PADIR
|
||||
0000003d P8DIR
|
||||
0000003e P7SEL
|
||||
0000003e PASEL
|
||||
0000003f P8SEL
|
||||
00000040 BTCTL
|
||||
00000040 RTCTL
|
||||
00000041 RTCCTL
|
||||
00000042 RTCNT1
|
||||
00000042 RTCTIM0
|
||||
00000043 RTCNT2
|
||||
00000044 RTCNT3
|
||||
00000044 RTCTIM1
|
||||
00000045 RTCNT4
|
||||
00000046 BTCNT1
|
||||
00000046 BTCNT12
|
||||
00000047 BTCNT2
|
||||
0000004c RTCDATE
|
||||
0000004c RTCDAY
|
||||
0000004d RTCMON
|
||||
0000004e RTCYEAR
|
||||
0000004e RTCYEARL
|
||||
0000004f RTCYEARH
|
||||
00000050 SCFI0
|
||||
00000050 __STACK_SIZE
|
||||
00000051 SCFI1
|
||||
00000052 SCFQCTL
|
||||
00000053 FLL_CTL0
|
||||
00000054 FLL_CTL1
|
||||
00000056 SVSCTL
|
||||
00000059 CACTL1
|
||||
0000005a CACTL2
|
||||
0000005b CAPD
|
||||
0000005d UCA0ABCTL
|
||||
0000005e UCA0IRTCTL
|
||||
0000005f UCA0IRRCTL
|
||||
00000060 UCA0CTL0
|
||||
00000061 UCA0CTL1
|
||||
00000062 UCA0BR0
|
||||
00000063 UCA0BR1
|
||||
00000064 UCA0MCTL
|
||||
00000065 UCA0STAT
|
||||
00000066 UCA0RXBUF
|
||||
00000067 UCA0TXBUF
|
||||
00000068 UCB0CTL0
|
||||
00000069 UCB0CTL1
|
||||
0000006a UCB0BR0
|
||||
0000006b UCB0BR1
|
||||
0000006c UCB0I2CIE
|
||||
0000006d UCB0STAT
|
||||
0000006e UCB0RXBUF
|
||||
0000006f UCB0TXBUF
|
||||
00000078 U1CTL
|
||||
00000079 U1TCTL
|
||||
0000007a U1RCTL
|
||||
0000007b U1MCTL
|
||||
0000007c U1BR0
|
||||
0000007d U1BR1
|
||||
0000007e U1RXBUF
|
||||
0000007f U1TXBUF
|
||||
00000080 ADC12MCTL0
|
||||
00000081 ADC12MCTL1
|
||||
00000082 ADC12MCTL2
|
||||
00000083 ADC12MCTL3
|
||||
00000084 ADC12MCTL4
|
||||
00000085 ADC12MCTL5
|
||||
00000086 ADC12MCTL6
|
||||
00000087 ADC12MCTL7
|
||||
00000088 ADC12MCTL8
|
||||
00000089 ADC12MCTL9
|
||||
0000008a ADC12MCTL10
|
||||
0000008b ADC12MCTL11
|
||||
0000008c ADC12MCTL12
|
||||
0000008d ADC12MCTL13
|
||||
0000008e ADC12MCTL14
|
||||
0000008f ADC12MCTL15
|
||||
00000090 LCDACTL
|
||||
00000091 LCDM1
|
||||
00000092 LCDM2
|
||||
00000093 LCDM3
|
||||
00000094 LCDM4
|
||||
00000095 LCDM5
|
||||
00000096 LCDM6
|
||||
00000097 LCDM7
|
||||
00000098 LCDM8
|
||||
00000099 LCDM9
|
||||
0000009a LCDM10
|
||||
0000009b LCDM11
|
||||
0000009c LCDM12
|
||||
0000009d LCDM13
|
||||
0000009e LCDM14
|
||||
0000009f LCDM15
|
||||
000000a0 LCDM16
|
||||
000000a1 LCDM17
|
||||
000000a2 LCDM18
|
||||
000000a3 LCDM19
|
||||
000000a4 LCDM20
|
||||
000000ac LCDAPCTL0
|
||||
000000ad LCDAPCTL1
|
||||
000000ae LCDAVCTL0
|
||||
000000af LCDAVCTL1
|
||||
000000c0 OA0CTL0
|
||||
000000c1 OA0CTL1
|
||||
000000c2 OA1CTL0
|
||||
000000c3 OA1CTL1
|
||||
000000c4 OA2CTL0
|
||||
000000c5 OA2CTL1
|
||||
00000118 UCB0I2COA
|
||||
0000011a UCB0I2CSA
|
||||
0000011e TBIV
|
||||
00000120 WDTCTL
|
||||
00000122 DMACTL0
|
||||
00000124 DMACTL1
|
||||
00000126 DMAIV
|
||||
00000128 FCTL1
|
||||
0000012a FCTL2
|
||||
0000012c FCTL3
|
||||
0000012e TAIV
|
||||
00000130 MPY
|
||||
00000132 MPYS
|
||||
00000134 MAC
|
||||
00000136 MACS
|
||||
00000138 OP2
|
||||
0000013a RESLO
|
||||
0000013c RESHI
|
||||
0000013e SUMEXT
|
||||
00000140 ADC12MEM0
|
||||
00000142 ADC12MEM1
|
||||
00000144 ADC12MEM2
|
||||
00000146 ADC12MEM3
|
||||
00000148 ADC12MEM4
|
||||
0000014a ADC12MEM5
|
||||
0000014c ADC12MEM6
|
||||
0000014e ADC12MEM7
|
||||
00000150 ADC12MEM8
|
||||
00000152 ADC12MEM9
|
||||
00000154 ADC12MEM10
|
||||
00000156 ADC12MEM11
|
||||
00000158 ADC12MEM12
|
||||
0000015a ADC12MEM13
|
||||
0000015c ADC12MEM14
|
||||
0000015e ADC12MEM15
|
||||
00000160 TACTL
|
||||
00000162 TACCTL0
|
||||
00000164 TACCTL1
|
||||
00000166 TACCTL2
|
||||
00000170 TAR
|
||||
00000172 TACCR0
|
||||
00000174 TACCR1
|
||||
00000176 TACCR2
|
||||
00000180 TBCTL
|
||||
00000182 TBCCTL0
|
||||
00000184 TBCCTL1
|
||||
00000186 TBCCTL2
|
||||
00000188 TBCCTL3
|
||||
0000018a TBCCTL4
|
||||
0000018c TBCCTL5
|
||||
0000018e TBCCTL6
|
||||
00000190 TBR
|
||||
00000192 TBCCR0
|
||||
00000194 TBCCR1
|
||||
00000196 TBCCR2
|
||||
00000198 TBCCR3
|
||||
0000019a TBCCR4
|
||||
0000019c TBCCR5
|
||||
0000019e TBCCR6
|
||||
000001a0 ADC12CTL0
|
||||
000001a2 ADC12CTL1
|
||||
000001a4 ADC12IFG
|
||||
000001a6 ADC12IE
|
||||
000001a8 ADC12IV
|
||||
000001c0 DAC12_0CTL
|
||||
000001c2 DAC12_1CTL
|
||||
000001c8 DAC12_0DAT
|
||||
000001ca DAC12_1DAT
|
||||
000001d0 DMA0CTL
|
||||
000001d2 DMA0SA
|
||||
000001d2 DMA0SAL
|
||||
000001d6 DMA0DA
|
||||
000001d6 DMA0DAL
|
||||
000001da DMA0SZ
|
||||
000001dc DMA1CTL
|
||||
000001de DMA1SA
|
||||
000001de DMA1SAL
|
||||
000001e2 DMA1DA
|
||||
000001e2 DMA1DAL
|
||||
000001e6 DMA1SZ
|
||||
000001e8 DMA2CTL
|
||||
000001ea DMA2SA
|
||||
000001ea DMA2SAL
|
||||
000001ee DMA2DA
|
||||
000001ee DMA2DAL
|
||||
000001f2 DMA2SZ
|
||||
00001100 sawtooth
|
||||
00001502 sine
|
||||
000030b0 _stack
|
||||
00003100 __STACK_END
|
||||
00003100 _c_int00_noargs
|
||||
0000311c TA0_ISR
|
||||
00003124 __TI_ISR_TRAP
|
||||
000038f2 __TI_Handler_Table_Base
|
||||
000038fa __TI_CINIT_Base
|
||||
000038fa __TI_Handler_Table_Limit
|
||||
00003902 __TI_CINIT_Limit
|
||||
0000ffdc __TI_int14
|
||||
0000ffde __TI_int15
|
||||
0000ffe0 __TI_int16
|
||||
0000ffe2 __TI_int17
|
||||
0000ffe4 __TI_int18
|
||||
0000ffe6 __TI_int19
|
||||
0000ffe8 __TI_int20
|
||||
0000ffea __TI_int21
|
||||
0000ffec __TI_int22
|
||||
0000ffee __TI_int23
|
||||
0000fff0 __TI_int24
|
||||
0000fff2 __TI_int25
|
||||
0000fff4 __TI_int26
|
||||
0000fff6 __TI_int27
|
||||
0000fff8 __TI_int28
|
||||
0000fffa __TI_int29
|
||||
0000fffc __TI_int30
|
||||
0000fffe _reset_vector
|
||||
00010000 __TI_decompress_lzss
|
||||
00010076 main
|
||||
000100d4 __TI_auto_init_nobinit_nopinit_hold_wdt
|
||||
00010128 DAC_setup
|
||||
0001013e TimerA_setup
|
||||
00010152 memcpy
|
||||
00010166 __TI_decompress_none
|
||||
00010178 C$$EXIT
|
||||
00010178 abort
|
||||
0001017e _system_pre_init
|
||||
00010182 _system_post_cinit
|
||||
ffffffff __TI_pprof_out_hndl
|
||||
ffffffff __TI_prof_data_size
|
||||
ffffffff __TI_prof_data_start
|
||||
ffffffff __c_args__
|
||||
|
||||
[291 symbols]
|
||||
BIN
CPE325/Lab10_Part3/Debug/Lab10_Part3.obj
Normal file
BIN
CPE325/Lab10_Part3/Debug/Lab10_Part3.obj
Normal file
Binary file not shown.
BIN
CPE325/Lab10_Part3/Debug/Lab10_Part3.out
Normal file
BIN
CPE325/Lab10_Part3/Debug/Lab10_Part3.out
Normal file
Binary file not shown.
4154
CPE325/Lab10_Part3/Debug/Lab10_Part3_linkInfo.xml
Normal file
4154
CPE325/Lab10_Part3/Debug/Lab10_Part3_linkInfo.xml
Normal file
File diff suppressed because it is too large
Load Diff
1
CPE325/Lab10_Part3/Debug/ccsObjs.opt
Normal file
1
CPE325/Lab10_Part3/Debug/ccsObjs.opt
Normal file
@ -0,0 +1 @@
|
||||
"./Lab10_Part3.obj" "../lnk_msp430fg4618.cmd" -llibc.a
|
||||
27
CPE325/Lab10_Part3/Debug/main.d
Normal file
27
CPE325/Lab10_Part3/Debug/main.d
Normal file
@ -0,0 +1,27 @@
|
||||
# FIXED
|
||||
|
||||
main.obj: ../main.c
|
||||
main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h
|
||||
main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h
|
||||
main.obj: C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h
|
||||
main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h
|
||||
main.obj: C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h
|
||||
main.obj: C:/CPE325_Workspace/Lab10_Part3/sawtooth.h
|
||||
main.obj: C:/CPE325_Workspace/Lab10_Part3/sine_lut_256.h
|
||||
|
||||
../main.c:
|
||||
|
||||
C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430.h:
|
||||
|
||||
C:/ti/ccs1040/ccs/ccs_base/msp430/include/msp430fg4618.h:
|
||||
|
||||
C:/ti/ccs1040/ccs/ccs_base/msp430/include/in430.h:
|
||||
|
||||
C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics.h:
|
||||
|
||||
C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include/intrinsics_legacy_undefs.h:
|
||||
|
||||
C:/CPE325_Workspace/Lab10_Part3/sawtooth.h:
|
||||
|
||||
C:/CPE325_Workspace/Lab10_Part3/sine_lut_256.h:
|
||||
|
||||
166
CPE325/Lab10_Part3/Debug/makefile
Normal file
166
CPE325/Lab10_Part3/Debug/makefile
Normal file
@ -0,0 +1,166 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
SHELL = cmd.exe
|
||||
|
||||
CG_TOOL_ROOT := C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS
|
||||
|
||||
GEN_OPTS__FLAG :=
|
||||
GEN_CMDS__FLAG :=
|
||||
|
||||
ORDERED_OBJS += \
|
||||
"./Lab10_Part3.obj" \
|
||||
"../lnk_msp430fg4618.cmd" \
|
||||
$(GEN_CMDS__FLAG) \
|
||||
-llibc.a \
|
||||
|
||||
-include ../makefile.init
|
||||
|
||||
RM := DEL /F
|
||||
RMDIR := RMDIR /S/Q
|
||||
|
||||
# All of the sources participating in the build are defined here
|
||||
-include sources.mk
|
||||
-include subdir_vars.mk
|
||||
-include subdir_rules.mk
|
||||
-include objects.mk
|
||||
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(C55_DEPS)),)
|
||||
-include $(C55_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C_UPPER_DEPS)),)
|
||||
-include $(C_UPPER_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S67_DEPS)),)
|
||||
-include $(S67_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S62_DEPS)),)
|
||||
-include $(S62_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S_DEPS)),)
|
||||
-include $(S_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(OPT_DEPS)),)
|
||||
-include $(OPT_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C??_DEPS)),)
|
||||
-include $(C??_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(ASM_UPPER_DEPS)),)
|
||||
-include $(ASM_UPPER_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S??_DEPS)),)
|
||||
-include $(S??_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C64_DEPS)),)
|
||||
-include $(C64_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CXX_DEPS)),)
|
||||
-include $(CXX_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S64_DEPS)),)
|
||||
-include $(S64_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(INO_DEPS)),)
|
||||
-include $(INO_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CLA_DEPS)),)
|
||||
-include $(CLA_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S55_DEPS)),)
|
||||
-include $(S55_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(SV7A_DEPS)),)
|
||||
-include $(SV7A_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C62_DEPS)),)
|
||||
-include $(C62_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C67_DEPS)),)
|
||||
-include $(C67_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(PDE_DEPS)),)
|
||||
-include $(PDE_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(K_DEPS)),)
|
||||
-include $(K_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C_DEPS)),)
|
||||
-include $(C_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CC_DEPS)),)
|
||||
-include $(CC_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C++_DEPS)),)
|
||||
-include $(C++_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C43_DEPS)),)
|
||||
-include $(C43_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S43_DEPS)),)
|
||||
-include $(S43_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(ASM_DEPS)),)
|
||||
-include $(ASM_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S_UPPER_DEPS)),)
|
||||
-include $(S_UPPER_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CPP_DEPS)),)
|
||||
-include $(CPP_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(SA_DEPS)),)
|
||||
-include $(SA_DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
-include ../makefile.defs
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
EXE_OUTPUTS += \
|
||||
Lab10_Part3.out \
|
||||
|
||||
EXE_OUTPUTS__QUOTED += \
|
||||
"Lab10_Part3.out" \
|
||||
|
||||
BIN_OUTPUTS += \
|
||||
Lab10_Part3.hex \
|
||||
|
||||
BIN_OUTPUTS__QUOTED += \
|
||||
"Lab10_Part3.hex" \
|
||||
|
||||
|
||||
# All Target
|
||||
all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
|
||||
@$(MAKE) --no-print-directory -Onone "Lab10_Part3.out"
|
||||
|
||||
# Tool invocations
|
||||
Lab10_Part3.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
|
||||
@echo 'Building target: "$@"'
|
||||
@echo 'Invoking: MSP430 Linker'
|
||||
"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 -z -m"Lab10_Part3.map" --heap_size=80 --stack_size=80 --cinit_hold_wdt=on -i"C:/ti/ccs1040/ccs/ccs_base/msp430/include" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/lib" -i"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="Lab10_Part3_linkInfo.xml" --use_hw_mpy=16 --rom_model -o "Lab10_Part3.out" $(ORDERED_OBJS)
|
||||
@echo 'Finished building target: "$@"'
|
||||
@echo ' '
|
||||
|
||||
Lab10_Part3.hex: $(EXE_OUTPUTS)
|
||||
@echo 'Building secondary target: "$@"'
|
||||
@echo 'Invoking: MSP430 Hex Utility'
|
||||
"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Lab10_Part3.hex" $(EXE_OUTPUTS__QUOTED)
|
||||
@echo 'Finished building secondary target: "$@"'
|
||||
@echo ' '
|
||||
|
||||
# Other Targets
|
||||
clean:
|
||||
-$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED)
|
||||
-$(RM) "Lab10_Part3.obj"
|
||||
-$(RM) "Lab10_Part3.d"
|
||||
-@echo 'Finished clean'
|
||||
-@echo ' '
|
||||
|
||||
.PHONY: all clean dependents
|
||||
.SECONDARY:
|
||||
|
||||
-include ../makefile.targets
|
||||
|
||||
8
CPE325/Lab10_Part3/Debug/objects.mk
Normal file
8
CPE325/Lab10_Part3/Debug/objects.mk
Normal file
@ -0,0 +1,8 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
USER_OBJS :=
|
||||
|
||||
LIBS := -llibc.a
|
||||
|
||||
115
CPE325/Lab10_Part3/Debug/sources.mk
Normal file
115
CPE325/Lab10_Part3/Debug/sources.mk
Normal file
@ -0,0 +1,115 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
C55_SRCS :=
|
||||
A_SRCS :=
|
||||
ASM_UPPER_SRCS :=
|
||||
EXE_SRCS :=
|
||||
LDS_UPPER_SRCS :=
|
||||
CPP_SRCS :=
|
||||
CMD_SRCS :=
|
||||
O_SRCS :=
|
||||
ELF_SRCS :=
|
||||
C??_SRCS :=
|
||||
C64_SRCS :=
|
||||
C67_SRCS :=
|
||||
SA_SRCS :=
|
||||
S64_SRCS :=
|
||||
OPT_SRCS :=
|
||||
CXX_SRCS :=
|
||||
S67_SRCS :=
|
||||
S??_SRCS :=
|
||||
PDE_SRCS :=
|
||||
SV7A_SRCS :=
|
||||
K_SRCS :=
|
||||
CLA_SRCS :=
|
||||
S55_SRCS :=
|
||||
LD_UPPER_SRCS :=
|
||||
OUT_SRCS :=
|
||||
INO_SRCS :=
|
||||
LIB_SRCS :=
|
||||
ASM_SRCS :=
|
||||
S_UPPER_SRCS :=
|
||||
S43_SRCS :=
|
||||
LD_SRCS :=
|
||||
CMD_UPPER_SRCS :=
|
||||
C_UPPER_SRCS :=
|
||||
C++_SRCS :=
|
||||
C43_SRCS :=
|
||||
OBJ_SRCS :=
|
||||
LDS_SRCS :=
|
||||
S_SRCS :=
|
||||
CC_SRCS :=
|
||||
S62_SRCS :=
|
||||
C62_SRCS :=
|
||||
C_SRCS :=
|
||||
C55_DEPS :=
|
||||
C_UPPER_DEPS :=
|
||||
S67_DEPS :=
|
||||
S62_DEPS :=
|
||||
S_DEPS :=
|
||||
OPT_DEPS :=
|
||||
C??_DEPS :=
|
||||
ASM_UPPER_DEPS :=
|
||||
S??_DEPS :=
|
||||
C64_DEPS :=
|
||||
CXX_DEPS :=
|
||||
S64_DEPS :=
|
||||
INO_DEPS :=
|
||||
CLA_DEPS :=
|
||||
S55_DEPS :=
|
||||
SV7A_DEPS :=
|
||||
EXE_OUTPUTS :=
|
||||
C62_DEPS :=
|
||||
C67_DEPS :=
|
||||
PDE_DEPS :=
|
||||
K_DEPS :=
|
||||
C_DEPS :=
|
||||
CC_DEPS :=
|
||||
BIN_OUTPUTS :=
|
||||
C++_DEPS :=
|
||||
C43_DEPS :=
|
||||
S43_DEPS :=
|
||||
OBJS :=
|
||||
ASM_DEPS :=
|
||||
S_UPPER_DEPS :=
|
||||
CPP_DEPS :=
|
||||
SA_DEPS :=
|
||||
C++_DEPS__QUOTED :=
|
||||
OPT_DEPS__QUOTED :=
|
||||
S_UPPER_DEPS__QUOTED :=
|
||||
SA_DEPS__QUOTED :=
|
||||
C??_DEPS__QUOTED :=
|
||||
S67_DEPS__QUOTED :=
|
||||
C55_DEPS__QUOTED :=
|
||||
CC_DEPS__QUOTED :=
|
||||
ASM_UPPER_DEPS__QUOTED :=
|
||||
SV7A_DEPS__QUOTED :=
|
||||
S??_DEPS__QUOTED :=
|
||||
OBJS__QUOTED :=
|
||||
C67_DEPS__QUOTED :=
|
||||
K_DEPS__QUOTED :=
|
||||
S55_DEPS__QUOTED :=
|
||||
INO_DEPS__QUOTED :=
|
||||
C62_DEPS__QUOTED :=
|
||||
C_DEPS__QUOTED :=
|
||||
C_UPPER_DEPS__QUOTED :=
|
||||
C43_DEPS__QUOTED :=
|
||||
CPP_DEPS__QUOTED :=
|
||||
BIN_OUTPUTS__QUOTED :=
|
||||
C64_DEPS__QUOTED :=
|
||||
CXX_DEPS__QUOTED :=
|
||||
CLA_DEPS__QUOTED :=
|
||||
S_DEPS__QUOTED :=
|
||||
ASM_DEPS__QUOTED :=
|
||||
S43_DEPS__QUOTED :=
|
||||
EXE_OUTPUTS__QUOTED :=
|
||||
S64_DEPS__QUOTED :=
|
||||
S62_DEPS__QUOTED :=
|
||||
PDE_DEPS__QUOTED :=
|
||||
|
||||
# Every subdirectory with source files must be described here
|
||||
SUBDIRS := \
|
||||
. \
|
||||
|
||||
15
CPE325/Lab10_Part3/Debug/subdir_rules.mk
Normal file
15
CPE325/Lab10_Part3/Debug/subdir_rules.mk
Normal file
@ -0,0 +1,15 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
SHELL = cmd.exe
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
|
||||
@echo 'Building file: "$<"'
|
||||
@echo 'Invoking: MSP430 Compiler'
|
||||
"C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=16 --include_path="C:/ti/ccs1040/ccs/ccs_base/msp430/include" --include_path="C:/CPE325_Workspace/Lab10_Part3" --include_path="C:/ti/ccs1040/ccs/tools/compiler/ti-cgt-msp430_20.2.5.LTS/include" --advice:power=all --define=__MSP430FG4618__ -g --printf_support=minimal --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU19 --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
|
||||
@echo 'Finished building: "$<"'
|
||||
@echo ' '
|
||||
|
||||
|
||||
29
CPE325/Lab10_Part3/Debug/subdir_vars.mk
Normal file
29
CPE325/Lab10_Part3/Debug/subdir_vars.mk
Normal file
@ -0,0 +1,29 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
SHELL = cmd.exe
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
CMD_SRCS += \
|
||||
../lnk_msp430fg4618.cmd
|
||||
|
||||
C_SRCS += \
|
||||
../Lab10_Part3.c
|
||||
|
||||
C_DEPS += \
|
||||
./Lab10_Part3.d
|
||||
|
||||
OBJS += \
|
||||
./Lab10_Part3.obj
|
||||
|
||||
OBJS__QUOTED += \
|
||||
"Lab10_Part3.obj"
|
||||
|
||||
C_DEPS__QUOTED += \
|
||||
"Lab10_Part3.d"
|
||||
|
||||
C_SRCS__QUOTED += \
|
||||
"../Lab10_Part3.c"
|
||||
|
||||
|
||||
77
CPE325/Lab10_Part3/Lab10_Part3.c
Normal file
77
CPE325/Lab10_Part3/Lab10_Part3.c
Normal file
@ -0,0 +1,77 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* File: Lab10_D3.c (CPE 325 Lab10 Demo code)
|
||||
* Function: Sinusoidal wave with DAC (MPS430FG4618)
|
||||
* Description: This C program reconstructs the sinusoidal wave (y=1.25(1+sin(x)))
|
||||
* from the samples using DAC and outputs at P6.6. WDT is used to
|
||||
* give an interrupt for every ~0.064ms to wake up the CPU and
|
||||
* feed the DAC with new value. Connect the oscilloscope to P6.6
|
||||
* to observe the signal. The interval used to read the samples
|
||||
* controls the frequency of output signal.
|
||||
* Clocks: ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO = default (~1MHz)
|
||||
* An external watch crystal between XIN & XOUT is required for ACLK
|
||||
*
|
||||
* MSP430xG461x
|
||||
* -------------------
|
||||
* /|\| XIN|-
|
||||
* | | | 32kHz
|
||||
* --|RST XOUT|-
|
||||
* | |
|
||||
* | DAC0/P6.6|--> sine (10Hz)
|
||||
* | |
|
||||
* Input: None
|
||||
* Output: Sinusoidal wave with 10Hz frequency at P6.6
|
||||
* Author: Aleksandar Milenkovic, milenkovic@computer.org
|
||||
* Max Avula, ma0004@uah.edu
|
||||
*------------------------------------------------------------------------------*/
|
||||
#include <msp430.h>
|
||||
#include <sawtooth.h> /*512 samples are stored in this table */
|
||||
#include <sine_lut_512.h> /*256 samples are stored in this table */
|
||||
|
||||
|
||||
#define SW1 ((P1IN&BIT0)==0) // Switch 1 status
|
||||
#define SW2 ((P1IN&BIT1)==0) // Switch 2 status
|
||||
|
||||
void TimerA_setup(void) {
|
||||
TACTL = TASSEL_2 + MC_1; // SMCLK, up mode
|
||||
TACCR0 = 164; // Sets Timer Freq (1048576*0.1sec/256)
|
||||
TACCTL0 = CCIE; // CCR0 interrupt enabled
|
||||
}
|
||||
|
||||
void DAC_setup(void) {
|
||||
ADC12CTL0 = REF2_5V + REFON; // Turn on 2.5V internal ref volage
|
||||
unsigned int i = 0;
|
||||
for (i = 50000; i > 0; i--); // Delay to allow Ref to settle
|
||||
DAC12_0CTL = DAC12IR + DAC12AMP_5 + DAC12ENC; //Sets DAC12
|
||||
}
|
||||
|
||||
void main(void) {
|
||||
P1DIR &= ~BIT0; // Set P1.1 to output direction
|
||||
P1DIR &= ~BIT1; // Set P1.0 to output direction
|
||||
FLL_CTL0 |= DCOPLUS + XCAP18PF; // DCO+ set, freq = xtal x D x N+1
|
||||
SCFI0 |= FN_4 + FLLD_2; // DCO range control, multiplier D
|
||||
SCFQCTL = 63; // (61+1) x 32768 x 2 = 4.19 MHz
|
||||
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
|
||||
TimerA_setup(); // Set timer to uniformly distribute the samples
|
||||
DAC_setup(); // Setup DAC
|
||||
unsigned int i = 0;
|
||||
unsigned int o = 0;
|
||||
while (1) {
|
||||
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
|
||||
if(SW1){
|
||||
o = sine[i];
|
||||
}
|
||||
else{
|
||||
o = sawtooth[i];
|
||||
}
|
||||
if(!SW2){
|
||||
o = o>>1;
|
||||
}
|
||||
DAC12_0DAT = o;
|
||||
i=(i+1)%512;
|
||||
}
|
||||
}
|
||||
|
||||
#pragma vector = TIMERA0_VECTOR
|
||||
__interrupt void TA0_ISR(void) {
|
||||
__bic_SR_register_on_exit(LPM0_bits); // Exit LPMx, interrupts enabled
|
||||
}
|
||||
184
CPE325/Lab10_Part3/lnk_msp430fg4618.cmd
Executable file
184
CPE325/Lab10_Part3/lnk_msp430fg4618.cmd
Executable file
@ -0,0 +1,184 @@
|
||||
/* ============================================================================ */
|
||||
/* Copyright (c) 2020, Texas Instruments Incorporated */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* * Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* * Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in the */
|
||||
/* documentation and/or other materials provided with the distribution. */
|
||||
/* */
|
||||
/* * Neither the name of Texas Instruments Incorporated nor the names of */
|
||||
/* its contributors may be used to endorse or promote products derived */
|
||||
/* from this software without specific prior written permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
|
||||
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
|
||||
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
|
||||
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
|
||||
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
|
||||
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
|
||||
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
|
||||
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
|
||||
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
|
||||
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
|
||||
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* ============================================================================ */
|
||||
|
||||
/******************************************************************************/
|
||||
/* lnk_msp430fg4618.cmd - LINKER COMMAND FILE FOR LINKING MSP430FG4618 PROGRAMS */
|
||||
/* */
|
||||
/* Usage: lnk430 <obj files...> -o <out file> -m <map file> lnk.cmd */
|
||||
/* cl430 <src files...> -z -o <out file> -m <map file> lnk.cmd */
|
||||
/* */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* These linker options are for command line linking only. For IDE linking, */
|
||||
/* you should set your linker options in Project Properties */
|
||||
/* -c LINK USING C CONVENTIONS */
|
||||
/* -stack 0x0100 SOFTWARE STACK SIZE */
|
||||
/* -heap 0x0100 HEAP AREA SIZE */
|
||||
/* */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Version: 1.211 */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/****************************************************************************/
|
||||
/* Specify the system memory map */
|
||||
/****************************************************************************/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
SFR : origin = 0x0000, length = 0x0010
|
||||
PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0
|
||||
PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100
|
||||
RAM : origin = 0x1100, length = 0x2000
|
||||
INFOA : origin = 0x1080, length = 0x0080
|
||||
INFOB : origin = 0x1000, length = 0x0080
|
||||
FLASH : origin = 0x3100, length = 0xCEBE
|
||||
FLASH2 : origin = 0x10000,length = 0x10000
|
||||
BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF
|
||||
INT00 : origin = 0xFFC0, length = 0x0002
|
||||
INT01 : origin = 0xFFC2, length = 0x0002
|
||||
INT02 : origin = 0xFFC4, length = 0x0002
|
||||
INT03 : origin = 0xFFC6, length = 0x0002
|
||||
INT04 : origin = 0xFFC8, length = 0x0002
|
||||
INT05 : origin = 0xFFCA, length = 0x0002
|
||||
INT06 : origin = 0xFFCC, length = 0x0002
|
||||
INT07 : origin = 0xFFCE, length = 0x0002
|
||||
INT08 : origin = 0xFFD0, length = 0x0002
|
||||
INT09 : origin = 0xFFD2, length = 0x0002
|
||||
INT10 : origin = 0xFFD4, length = 0x0002
|
||||
INT11 : origin = 0xFFD6, length = 0x0002
|
||||
INT12 : origin = 0xFFD8, length = 0x0002
|
||||
INT13 : origin = 0xFFDA, length = 0x0002
|
||||
INT14 : origin = 0xFFDC, length = 0x0002
|
||||
INT15 : origin = 0xFFDE, length = 0x0002
|
||||
INT16 : origin = 0xFFE0, length = 0x0002
|
||||
INT17 : origin = 0xFFE2, length = 0x0002
|
||||
INT18 : origin = 0xFFE4, length = 0x0002
|
||||
INT19 : origin = 0xFFE6, length = 0x0002
|
||||
INT20 : origin = 0xFFE8, length = 0x0002
|
||||
INT21 : origin = 0xFFEA, length = 0x0002
|
||||
INT22 : origin = 0xFFEC, length = 0x0002
|
||||
INT23 : origin = 0xFFEE, length = 0x0002
|
||||
INT24 : origin = 0xFFF0, length = 0x0002
|
||||
INT25 : origin = 0xFFF2, length = 0x0002
|
||||
INT26 : origin = 0xFFF4, length = 0x0002
|
||||
INT27 : origin = 0xFFF6, length = 0x0002
|
||||
INT28 : origin = 0xFFF8, length = 0x0002
|
||||
INT29 : origin = 0xFFFA, length = 0x0002
|
||||
INT30 : origin = 0xFFFC, length = 0x0002
|
||||
RESET : origin = 0xFFFE, length = 0x0002
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/* Specify the sections allocation into memory */
|
||||
/****************************************************************************/
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.bss : {} > RAM /* Global & static vars */
|
||||
.data : {} > RAM /* Global & static vars */
|
||||
.TI.noinit : {} > RAM /* For #pragma noinit */
|
||||
.sysmem : {} > RAM /* Dynamic memory allocation area */
|
||||
.stack : {} > RAM (HIGH) /* Software system stack */
|
||||
|
||||
#ifndef __LARGE_CODE_MODEL__
|
||||
.text : {} > FLASH /* Code */
|
||||
#else
|
||||
.text : {} >> FLASH2 | FLASH /* Code */
|
||||
#endif
|
||||
.text:_isr : {} > FLASH /* ISR Code space */
|
||||
.cinit : {} > FLASH /* Initialization tables */
|
||||
#ifndef __LARGE_DATA_MODEL__
|
||||
.const : {} > FLASH /* Constant data */
|
||||
#else
|
||||
.const : {} >> FLASH | FLASH2 /* Constant data */
|
||||
#endif
|
||||
.bslsignature : {} > BSLSIGNATURE /* BSL Signature */
|
||||
.cio : {} > RAM /* C I/O Buffer */
|
||||
|
||||
.pinit : {} > FLASH /* C++ Constructor tables */
|
||||
.binit : {} > FLASH /* Boot-time Initialization tables */
|
||||
.init_array : {} > FLASH /* C++ Constructor tables */
|
||||
.mspabi.exidx : {} > FLASH /* C++ Constructor tables */
|
||||
.mspabi.extab : {} > FLASH /* C++ Constructor tables */
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#ifndef __LARGE_CODE_MODEL__
|
||||
.TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT)
|
||||
#else
|
||||
.TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT)
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */
|
||||
.infoB : {} > INFOB
|
||||
|
||||
/* MSP430 Interrupt vectors */
|
||||
.int00 : {} > INT00
|
||||
.int01 : {} > INT01
|
||||
.int02 : {} > INT02
|
||||
.int03 : {} > INT03
|
||||
.int04 : {} > INT04
|
||||
.int05 : {} > INT05
|
||||
.int06 : {} > INT06
|
||||
.int07 : {} > INT07
|
||||
.int08 : {} > INT08
|
||||
.int09 : {} > INT09
|
||||
.int10 : {} > INT10
|
||||
.int11 : {} > INT11
|
||||
.int12 : {} > INT12
|
||||
.int13 : {} > INT13
|
||||
DAC12 : { * ( .int14 ) } > INT14 type = VECT_INIT
|
||||
DMA : { * ( .int15 ) } > INT15 type = VECT_INIT
|
||||
BASICTIMER : { * ( .int16 ) } > INT16 type = VECT_INIT
|
||||
PORT2 : { * ( .int17 ) } > INT17 type = VECT_INIT
|
||||
USART1TX : { * ( .int18 ) } > INT18 type = VECT_INIT
|
||||
USART1RX : { * ( .int19 ) } > INT19 type = VECT_INIT
|
||||
PORT1 : { * ( .int20 ) } > INT20 type = VECT_INIT
|
||||
TIMERA1 : { * ( .int21 ) } > INT21 type = VECT_INIT
|
||||
TIMERA0 : { * ( .int22 ) } > INT22 type = VECT_INIT
|
||||
ADC12 : { * ( .int23 ) } > INT23 type = VECT_INIT
|
||||
USCIAB0TX : { * ( .int24 ) } > INT24 type = VECT_INIT
|
||||
USCIAB0RX : { * ( .int25 ) } > INT25 type = VECT_INIT
|
||||
WDT : { * ( .int26 ) } > INT26 type = VECT_INIT
|
||||
COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT
|
||||
TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT
|
||||
TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT
|
||||
NMI : { * ( .int30 ) } > INT30 type = VECT_INIT
|
||||
.reset : {} > RESET /* MSP430 Reset vector */
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/* Include peripherals memory map */
|
||||
/****************************************************************************/
|
||||
|
||||
-l msp430fg4618.cmd
|
||||
|
||||
1
CPE325/Lab10_Part3/sawtooth.h
Normal file
1
CPE325/Lab10_Part3/sawtooth.h
Normal file
@ -0,0 +1 @@
|
||||
int sawtooth[] = {0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240,256,272,288,304,320,336,352,368,384,400,416,432,448,464,480,496,512,528,544,560,576,592,608,624,640,656,672,688,704,720,736,752,768,784,800,816,832,848,864,880,896,912,928,944,960,976,992,1008,1024,1040,1056,1072,1088,1104,1120,1136,1152,1168,1184,1200,1216,1232,1248,1264,1280,1296,1312,1328,1344,1360,1376,1392,1408,1424,1440,1456,1472,1488,1504,1520,1536,1552,1568,1584,1600,1616,1632,1648,1664,1680,1696,1712,1728,1744,1760,1776,1792,1808,1824,1840,1856,1872,1888,1904,1920,1936,1952,1968,1984,2000,2016,2032,2048,2063,2079,2095,2111,2127,2143,2159,2175,2191,2207,2223,2239,2255,2271,2287,2303,2319,2335,2351,2367,2383,2399,2415,2431,2447,2463,2479,2495,2511,2527,2543,2559,2575,2591,2607,2623,2639,2655,2671,2687,2703,2719,2735,2751,2767,2783,2799,2815,2831,2847,2863,2879,2895,2911,2927,2943,2959,2975,2991,3007,3023,3039,3055,3071,3087,3103,3119,3135,3151,3167,3183,3199,3215,3231,3247,3263,3279,3295,3311,3327,3343,3359,3375,3391,3407,3423,3439,3455,3471,3487,3503,3519,3535,3551,3567,3583,3599,3615,3631,3647,3663,3679,3695,3711,3727,3743,3759,3775,3791,3807,3823,3839,3855,3871,3887,3903,3919,3935,3951,3967,3983,3999,4015,4031,4047,4063,4079,4095,4079,4063,4047,4031,4015,3999,3983,3967,3951,3935,3919,3903,3887,3871,3855,3839,3823,3807,3791,3775,3759,3743,3727,3711,3695,3679,3663,3647,3631,3615,3599,3583,3567,3551,3535,3519,3503,3487,3471,3455,3439,3423,3407,3391,3375,3359,3343,3327,3311,3295,3279,3263,3247,3231,3215,3199,3183,3167,3151,3135,3119,3103,3087,3071,3055,3039,3023,3007,2991,2975,2959,2943,2927,2911,2895,2879,2863,2847,2831,2815,2799,2783,2767,2751,2735,2719,2703,2687,2671,2655,2639,2623,2607,2591,2575,2559,2543,2527,2511,2495,2479,2463,2447,2431,2415,2399,2383,2367,2351,2335,2319,2303,2287,2271,2255,2239,2223,2207,2191,2175,2159,2143,2127,2111,2095,2079,2063,2048,2032,2016,2000,1984,1968,1952,1936,1920,1904,1888,1872,1856,1840,1824,1808,1792,1776,1760,1744,1728,1712,1696,1680,1664,1648,1632,1616,1600,1584,1568,1552,1536,1520,1504,1488,1472,1456,1440,1424,1408,1392,1376,1360,1344,1328,1312,1296,1280,1264,1248,1232,1216,1200,1184,1168,1152,1136,1120,1104,1088,1072,1056,1040,1024,1008,992,976,960,944,928,912,896,880,864,848,832,816,800,784,768,752,736,720,704,688,672,656,640,624,608,592,576,560,544,528,512,496,480,464,448,432,416,400,384,368,352,336,320,304,288,272,256,240,224,208,192,176,160,144,128,112,96,80,64,48,32,16,0};
|
||||
1
CPE325/Lab10_Part3/sine_lut_256.h
Normal file
1
CPE325/Lab10_Part3/sine_lut_256.h
Normal file
@ -0,0 +1 @@
|
||||
int LUT256[] = { 2048, 2098, 2148, 2198, 2248, 2298, 2348, 2398, 2447, 2496, 2545, 2594, 2642, 2690, 2737, 2784, 2831, 2877, 2923, 2968, 3013, 3057, 3100, 3143, 3185, 3226, 3267, 3307, 3346, 3385, 3423, 3459, 3495, 3530, 3565, 3598, 3630, 3662, 3692, 3722, 3750, 3777, 3804, 3829, 3853, 3876, 3898, 3919, 3939, 3958, 3975, 3992, 4007, 4021, 4034, 4045, 4056, 4065, 4073, 4080, 4085, 4089, 4093, 4094, 4095, 4094, 4093, 4089, 4085, 4080, 4073, 4065, 4056, 4045, 4034, 4021, 4007, 3992, 3975, 3958, 3939, 3919, 3898, 3876, 3853, 3829, 3804, 3777, 3750, 3722, 3692, 3662, 3630, 3598, 3565, 3530, 3495, 3459, 3423, 3385, 3346, 3307, 3267, 3226, 3185, 3143, 3100, 3057, 3013, 2968, 2923, 2877, 2831, 2784, 2737, 2690, 2642, 2594, 2545, 2496, 2447, 2398, 2348, 2298, 2248, 2198, 2148, 2098, 2048, 1997, 1947, 1897, 1847, 1797, 1747, 1697, 1648, 1599, 1550, 1501, 1453, 1405, 1358, 1311, 1264, 1218, 1172, 1127, 1082, 1038, 995, 952, 910, 869, 828, 788, 749, 710, 672, 636, 600, 565, 530, 497, 465, 433, 403, 373, 345, 318, 291, 266, 242, 219, 197, 176, 156, 137, 120, 103, 88, 74, 61, 50, 39, 30, 22, 15, 10, 6, 2, 1, 0, 1, 2, 6, 10, 15, 22, 30, 39, 50, 61, 74, 88, 103, 120, 137, 156, 176, 197, 219, 242, 266, 291, 318, 345, 373, 403, 433, 465, 497, 530, 565, 600, 636, 672, 710, 749, 788, 828, 869, 910, 952, 995, 1038, 1082, 1127, 1172, 1218, 1264, 1311, 1358, 1405, 1453, 1501, 1550, 1599, 1648, 1697, 1747, 1797, 1847, 1897, 1947, 1997, 2047 };
|
||||
1
CPE325/Lab10_Part3/sine_lut_512.h
Normal file
1
CPE325/Lab10_Part3/sine_lut_512.h
Normal file
@ -0,0 +1 @@
|
||||
int sine[] = {2048,2073,2098,2123,2148,2173,2198,2223,2248,2273,2298,2323,2348,2373,2398,2422,2447,2472,2496,2521,2545,2569,2594,2618,2642,2666,2690,2714,2737,2761,2784,2808,2831,2854,2877,2900,2923,2946,2968,2990,3013,3035,3057,3078,3100,3122,3143,3164,3185,3206,3226,3247,3267,3287,3307,3327,3346,3366,3385,3404,3423,3441,3459,3477,3495,3513,3530,3548,3565,3581,3598,3614,3630,3646,3662,3677,3692,3707,3722,3736,3750,3764,3777,3791,3804,3816,3829,3841,3853,3865,3876,3888,3898,3909,3919,3929,3939,3949,3958,3967,3975,3984,3992,3999,4007,4014,4021,4027,4034,4040,4045,4051,4056,4060,4065,4069,4073,4076,4080,4083,4085,4087,4089,4091,4093,4094,4094,4095,4095,4095,4094,4094,4093,4091,4089,4087,4085,4083,4080,4076,4073,4069,4065,4060,4056,4051,4045,4040,4034,4027,4021,4014,4007,3999,3992,3984,3975,3967,3958,3949,3939,3929,3919,3909,3898,3888,3876,3865,3853,3841,3829,3816,3804,3791,3777,3764,3750,3736,3722,3707,3692,3677,3662,3646,3630,3614,3598,3581,3565,3548,3530,3513,3495,3477,3459,3441,3423,3404,3385,3366,3346,3327,3307,3287,3267,3247,3226,3206,3185,3164,3143,3122,3100,3078,3057,3035,3013,2990,2968,2946,2923,2900,2877,2854,2831,2808,2784,2761,2737,2714,2690,2666,2642,2618,2594,2569,2545,2521,2496,2472,2447,2422,2398,2373,2348,2323,2298,2273,2248,2223,2198,2173,2148,2123,2098,2073,2048,2022,1997,1972,1947,1922,1897,1872,1847,1822,1797,1772,1747,1722,1697,1673,1648,1623,1599,1574,1550,1526,1501,1477,1453,1429,1405,1381,1358,1334,1311,1287,1264,1241,1218,1195,1172,1149,1127,1105,1082,1060,1038,1017,995,973,952,931,910,889,869,848,828,808,788,768,749,729,710,691,672,654,636,618,600,582,565,547,530,514,497,481,465,449,433,418,403,388,373,359,345,331,318,304,291,279,266,254,242,230,219,207,197,186,176,166,156,146,137,128,120,111,103,96,88,81,74,68,61,55,50,44,39,35,30,26,22,19,15,12,10,8,6,4,2,1,1,0,0,0,1,1,2,4,6,8,10,12,15,19,22,26,30,35,39,44,50,55,61,68,74,81,88,96,103,111,120,128,137,146,156,166,176,186,197,207,219,230,242,254,266,279,291,304,318,331,345,359,373,388,403,418,433,449,465,481,497,514,530,547,565,582,600,618,636,654,672,691,710,729,749,768,788,808,828,848,869,889,910,931,952,973,995,1017,1038,1060,1082,1105,1127,1149,1172,1195,1218,1241,1264,1287,1311,1334,1358,1381,1405,1429,1453,1477,1501,1526,1550,1574,1599,1623,1648,1673,1697,1722,1747,1772,1797,1822,1847,1872,1897,1922,1947,1972,1997,2022,2047};
|
||||
12
CPE325/Lab10_Part3/targetConfigs/MSP430FG4618.ccxml
Normal file
12
CPE325/Lab10_Part3/targetConfigs/MSP430FG4618.ccxml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<configurations XML_version="1.2" id="configurations_0">
|
||||
<configuration XML_version="1.2" id="configuration_0">
|
||||
<instance XML_version="1.2" desc="TI MSP430 USB1" href="connections/TIMSP430-USB.xml" id="TI MSP430 USB1" xml="TIMSP430-USB.xml" xmlpath="connections"/>
|
||||
<connection XML_version="1.2" id="TI MSP430 USB1">
|
||||
<instance XML_version="1.2" href="drivers/msp430_emu.xml" id="drivers" xml="msp430_emu.xml" xmlpath="drivers"/>
|
||||
<platform XML_version="1.2" id="platform_0">
|
||||
<instance XML_version="1.2" desc="MSP430FG4618" href="devices/MSP430FG4618.xml" id="MSP430FG4618" xml="MSP430FG4618.xml" xmlpath="devices"/>
|
||||
</platform>
|
||||
</connection>
|
||||
</configuration>
|
||||
</configurations>
|
||||
9
CPE325/Lab10_Part3/targetConfigs/readme.txt
Normal file
9
CPE325/Lab10_Part3/targetConfigs/readme.txt
Normal file
@ -0,0 +1,9 @@
|
||||
The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
|
||||
on the device and connection settings specified in your project on the Properties > General page.
|
||||
|
||||
Please note that in automatic target-configuration management, changes to the project's device and/or
|
||||
connection settings will either modify an existing or generate a new target-configuration file. Thus,
|
||||
if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
|
||||
you may create your own target-configuration file for this project and manage it manually. You can
|
||||
always switch back to automatic target-configuration management by checking the "Manage the project's
|
||||
target-configuration automatically" checkbox on the project's Properties > General page.
|
||||
Reference in New Issue
Block a user