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Andrew W
2022-08-28 16:12:16 -05:00
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// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "01/21/2021 19:08:58"
// Verilog Test Bench (with test vectors) for design : class1-21-21
//
// Simulation tool : 3rd Party
//
`timescale 1 ps/ 1 ps
module class1-21-21_vlg_vec_tst();
// constants
// general purpose registers
reg in1;
reg in2;
// wires
wire out;
// assign statements (if any)
class1-21-21 i1 (
// port map - connection between master ports and signals/registers
.in1(in1),
.in2(in2),
.out(out)
);
initial
begin
#200000 $finish;
end
// in1
initial
begin
in1 = 1'b0;
in1 = #10000 1'b1;
in1 = #10000 1'b0;
in1 = #10000 1'b1;
in1 = #10000 1'b0;
in1 = #30000 1'b1;
in1 = #20000 1'b0;
in1 = #80000 1'b1;
in1 = #10000 1'b0;
end
// in2
initial
begin
in2 = 1'b0;
in2 = #30000 1'b1;
in2 = #10000 1'b0;
in2 = #20000 1'b1;
in2 = #10000 1'b0;
in2 = #50000 1'b1;
in2 = #10000 1'b0;
in2 = #20000 1'b1;
in2 = #10000 1'b0;
end
endmodule

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// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "01/21/2021 19:19:21"
// Verilog Test Bench (with test vectors) for design : class1-21-21
//
// Simulation tool : 3rd Party
//
`timescale 1 ps/ 1 ps
module class1-21-21_vlg_vec_tst();
// constants
// general purpose registers
reg in1;
reg in2;
// wires
wire out;
// assign statements (if any)
class1-21-21 i1 (
// port map - connection between master ports and signals/registers
.in1(in1),
.in2(in2),
.out(out)
);
initial
begin
#1000000 $finish;
end
// in1
initial
begin
in1 = 1'b0;
in1 = #80000 1'b1;
in1 = #220000 1'b0;
in1 = #440000 1'b1;
in1 = #40000 1'b0;
end
// in2
initial
begin
in2 = 1'b0;
in2 = #260000 1'b1;
in2 = #40000 1'b0;
in2 = #40000 1'b1;
in2 = #50000 1'b0;
in2 = #100000 1'b1;
in2 = #130000 1'b0;
end
endmodule

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onerror {exit -code 1}
vlib work
vlog -work work class1-21-21.vo
vlog -work work Waveform1.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.class1-21-21_vlg_vec_tst
vcd file -direction class1-21-21.msim.vcd
vcd add -internal class1-21-21_vlg_vec_tst/*
vcd add -internal class1-21-21_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f

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set tool_name "ModelSim-Altera (Verilog)"

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// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition"
// DATE "01/21/2021 19:19:22"
//
// Device: Altera 10M50DAF484C6GES Package FBGA484
//
//
// This Verilog file should be used for ModelSim-Altera (Verilog) only
//
`timescale 1 ps/ 1 ps
module \class1-21-21 (
out,
in1,
in2);
output out;
input in1;
input in2;
// Design Ports Information
// out => Location: PIN_W8, I/O Standard: 2.5 V, Current Strength: Default
// in1 => Location: PIN_AB4, I/O Standard: 2.5 V, Current Strength: Default
// in2 => Location: PIN_AA3, I/O Standard: 2.5 V, Current Strength: Default
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \~QUARTUS_CREATED_UNVM~~busy ;
wire \~QUARTUS_CREATED_ADC1~~eoc ;
wire \~QUARTUS_CREATED_ADC2~~eoc ;
wire \out~output_o ;
wire \in1~input_o ;
wire \in2~input_o ;
wire \inst~combout ;
hard_block auto_generated_inst(
.devpor(devpor),
.devclrn(devclrn),
.devoe(devoe));
// Location: LCCOMB_X44_Y52_N8
fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):
// \~QUARTUS_CREATED_GND~I_combout = GND
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.cin(gnd),
.combout(\~QUARTUS_CREATED_GND~I_combout ),
.cout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
// synopsys translate_on
// Location: IOOBUF_X24_Y0_N2
fiftyfivenm_io_obuf \out~output (
.i(\inst~combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\out~output_o ),
.obar());
// synopsys translate_off
defparam \out~output .bus_hold = "false";
defparam \out~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOIBUF_X26_Y0_N22
fiftyfivenm_io_ibuf \in1~input (
.i(in1),
.ibar(gnd),
.nsleep(vcc),
.o(\in1~input_o ));
// synopsys translate_off
defparam \in1~input .bus_hold = "false";
defparam \in1~input .listen_to_nsleep_signal = "false";
defparam \in1~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X26_Y0_N29
fiftyfivenm_io_ibuf \in2~input (
.i(in2),
.ibar(gnd),
.nsleep(vcc),
.o(\in2~input_o ));
// synopsys translate_off
defparam \in2~input .bus_hold = "false";
defparam \in2~input .listen_to_nsleep_signal = "false";
defparam \in2~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LCCOMB_X26_Y1_N0
fiftyfivenm_lcell_comb inst(
// Equation(s):
// \inst~combout = (\in1~input_o & \in2~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\in1~input_o ),
.datad(\in2~input_o ),
.cin(gnd),
.combout(\inst~combout ),
.cout());
// synopsys translate_off
defparam inst.lut_mask = 16'hF000;
defparam inst.sum_lutc_input = "datac";
// synopsys translate_on
// Location: UNVM_X0_Y40_N40
fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
.arclk(vcc),
.arshft(vcc),
.drclk(vcc),
.drshft(vcc),
.drdin(vcc),
.nprogram(vcc),
.nerase(vcc),
.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
.par_en(vcc),
.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
.se(\~QUARTUS_CREATED_GND~I_combout ),
.ardin(23'b11111111111111111111111),
.busy(\~QUARTUS_CREATED_UNVM~~busy ),
.osc(),
.bgpbusy(),
.sp_pass(),
.se_pass(),
.drdout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
// synopsys translate_on
// Location: ADCBLOCK_X43_Y52_N0
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
.soc(\~QUARTUS_CREATED_GND~I_combout ),
.usr_pwd(vcc),
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
.clkin_from_pll_c0(gnd),
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
.dout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
// synopsys translate_on
// Location: ADCBLOCK_X43_Y51_N0
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
.soc(\~QUARTUS_CREATED_GND~I_combout ),
.usr_pwd(vcc),
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
.clkin_from_pll_c0(gnd),
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
.dout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
// synopsys translate_on
assign out = \out~output_o ;
endmodule
module hard_block (
devpor,
devclrn,
devoe);
// Design Ports Information
// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
input devpor;
input devclrn;
input devoe;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
wire \~ALTERA_TMS~~padout ;
wire \~ALTERA_TCK~~padout ;
wire \~ALTERA_TDI~~padout ;
wire \~ALTERA_CONFIG_SEL~~padout ;
wire \~ALTERA_nCONFIG~~padout ;
wire \~ALTERA_nSTATUS~~padout ;
wire \~ALTERA_CONF_DONE~~padout ;
wire \~ALTERA_TMS~~ibuf_o ;
wire \~ALTERA_TCK~~ibuf_o ;
wire \~ALTERA_TDI~~ibuf_o ;
wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
wire \~ALTERA_nCONFIG~~ibuf_o ;
wire \~ALTERA_nSTATUS~~ibuf_o ;
wire \~ALTERA_CONF_DONE~~ibuf_o ;
endmodule

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vendor_name = ModelSim
source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/class1-21-21.bdf
source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/Waveform.vwf
source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/db/class1-21-21.cbx.xml
design_name = \class1-21-21
instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, \class1-21-21 , 1
instance = comp, \out~output , out~output, \class1-21-21 , 1
instance = comp, \in1~input , in1~input, \class1-21-21 , 1
instance = comp, \in2~input , in2~input, \class1-21-21 , 1
instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, \class1-21-21 , 1
instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, \class1-21-21 , 1
instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, \class1-21-21 , 1
design_name = hard_block
instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1
instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1
instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1
instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1
instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1
instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1
instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1

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# do class1-21-21.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 19:19:22 on Jan 21,2021
# vlog -work work class1-21-21.vo
# -- Compiling module \class1-21-21
# -- Compiling module hard_block
#
# Top level modules:
# \class1-21-21
# End time: 19:19:22 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 19:19:22 on Jan 21,2021
# vlog -work work Waveform1.vwf.vt
# ** Error: (vlog-13069) Waveform1.vwf.vt(30): near "-": syntax error, unexpected '-', expecting "SystemVerilog keyword 'import'" or ';' or '#' or '('.
# End time: 19:19:22 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./class1-21-21.do line 4

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m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/Users/anw0044/Desktop/Noah Woodlee/BasicGates/simulation/qsim
v\class1-21-21
Z1 !s110 1611278362
!i10b 1
!s100 jJQkb4bY@EOnS7>4kW[N?3
I22ORzOonmkC=^2kBCmCMe0
Z2 VDg1SIo80bB@j0V0VzS_@n1
R0
Z3 w1611278362
Z4 8class1-21-21.vo
Z5 Fclass1-21-21.vo
L0 32
Z6 OV;L;10.5b;63
r1
!s85 0
31
Z7 !s108 1611278362.000000
Z8 !s107 class1-21-21.vo|
Z9 !s90 -work|work|class1-21-21.vo|
!i113 1
Z10 o-work work
Z11 tCvgOpt 0
n@134class1-21-21@040
vhard_block
R1
!i10b 1
!s100 M`VFZU>cQ=@9Z4Cck8KGo1
IK8Ki:eNcRfd6F_3a<8Ff^0
R2
R0
R3
R4
R5
L0 228
R6
r1
!s85 0
31
R7
R8
R9
!i113 1
R10
R11

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m255
K4
z0
cModel Technology