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Andrew W
2022-08-28 16:12:16 -05:00
parent 5a2894ed1b
commit 7dabaef6f6
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EE203/Noah Woodlee/BasicGates/simulation/qsim/transcript Normal file
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# do class1-21-21.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 19:19:22 on Jan 21,2021
# vlog -work work class1-21-21.vo
# -- Compiling module \class1-21-21
# -- Compiling module hard_block
#
# Top level modules:
# \class1-21-21
# End time: 19:19:22 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 19:19:22 on Jan 21,2021
# vlog -work work Waveform1.vwf.vt
# ** Error: (vlog-13069) Waveform1.vwf.vt(30): near "-": syntax error, unexpected '-', expecting "SystemVerilog keyword 'import'" or ';' or '#' or '('.
# End time: 19:19:22 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./class1-21-21.do line 4