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Andrew W
2022-08-28 16:12:16 -05:00
parent 5a2894ed1b
commit 7dabaef6f6
2345 changed files with 1343530 additions and 0 deletions
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264
EE203/Noah Woodlee/Decoder/Waveform.vwf Normal file
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vlog -work work decoder.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst
vcd file -direction decoder.msim.vcd
vcd add -internal decoder_vlg_vec_tst/*
vcd add -internal decoder_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vlog -work work decoder.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst
vcd file -direction decoder.msim.vcd
vcd add -internal decoder_vlg_vec_tst/*
vcd add -internal decoder_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 200.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("A")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("B")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Q0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q3")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("A")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 40.0;
}
}
TRANSITION_LIST("B")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 40.0;
}
}
TRANSITION_LIST("Q0")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 200.0;
}
}
TRANSITION_LIST("Q1")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 200.0;
}
}
TRANSITION_LIST("Q2")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 200.0;
}
}
TRANSITION_LIST("Q3")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 200.0;
}
}
DISPLAY_LINE
{
CHANNEL = "A";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "B";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Q0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Q1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Q2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Q3";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611280915611 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611280915615 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:01:55 2021 " "Processing started: Thu Jan 21 20:01:55 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611280915615 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611280915615 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611280915615 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1611280915826 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611280917012 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611280917103 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611280917813 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:01:57 2021 " "Processing ended: Thu Jan 21 20:01:57 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611280917813 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611280917813 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611280917813 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611280917813 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="decoder">
</PROJECT>
</LOG_ROOT>

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v1
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,0;0;0;0;0;6;0;0;6;6;0;4;0;0;2;0;4;2;0;0;0;4;0;0;0;0;0;6;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,6;6;6;6;6;0;6;6;0;0;6;2;6;6;4;6;2;4;6;6;6;2;6;6;6;6;6;0;6;6,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Q0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Q1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Q2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Q3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,B,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,A,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,

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Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Version_Index = 419480576
Creation_Time = Thu Jan 21 19:32:30 2021

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611281531256 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2016 Intel Corporation. All rights reserved. " "Copyright (C) 2016 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic " "and other software and tools, and its AMPP partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel MegaCore Function License Agreement, or other " "the Intel MegaCore Function License Agreement, or other " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable license agreement, including, without limitation, " "applicable license agreement, including, without limitation, " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "that your use is for the sole purpose of programming logic " "that your use is for the sole purpose of programming logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "devices manufactured by Intel and sold by Intel or its " "devices manufactured by Intel and sold by Intel or its " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "authorized distributors. Please refer to the applicable " "authorized distributors. Please refer to the applicable " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement for further details. " "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:12:11 2021 " "Processing started: Thu Jan 21 20:12:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531260 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/\" decoder -c decoder " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/\" decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531261 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1611281531461 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder.vo C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim// simulation " "Generated file decoder.vo in folder \"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1611281531492 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4641 " "Peak virtual memory: 4641 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:12:11 2021 " "Processing ended: Thu Jan 21 20:12:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531521 ""}

53
EE203/Noah Woodlee/Decoder/db/decoder.fit.qmsg Normal file
View File

@ -0,0 +1,53 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1611280909024 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1611280909025 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "decoder 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"decoder\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611280909028 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611280909057 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611280909057 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1611280909212 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611280909217 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611280909289 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611280909289 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 26 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 28 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 30 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 32 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 34 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 36 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 38 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 40 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611280909290 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1611280909290 ""}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611280909290 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611280909290 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611280909290 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611280909290 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1611280909291 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "6 6 " "No exact pin location assignment(s) for 6 pins of 6 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1611280909442 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "decoder.sdc " "Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611280909603 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611280909603 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611280909603 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611280909603 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1611280909603 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1611280909603 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1611280909603 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 2.5V 2 4 0 " "Number of I/O pins in group: 6 (unused VREF, 2.5V VCCIO, 2 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 20 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 36 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 48 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 48 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 40 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 60 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 60 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 52 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 32 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 32 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1611280909603 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1611280909603 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280909613 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1611280909613 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1611280910413 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280910449 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1611280910463 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1611280910737 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280910737 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1611280912422 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X33_Y44 X44_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y44 to location X44_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y44 to location X44_Y54"} { { 12 { 0 ""} 33 44 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1611280913340 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1611280913340 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1611280913399 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1611280913399 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1611280913399 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280913402 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1611280913546 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611280913551 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611280913709 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611280913709 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611280913928 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611280914229 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1611280914419 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5902 " "Peak virtual memory: 5902 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611280914763 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:01:54 2021 " "Processing ended: Thu Jan 21 20:01:54 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611280914763 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611280914763 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611280914763 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1611280914763 ""}

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|decoder
Q0 <= inst.DB_MAX_OUTPUT_PORT_TYPE
B => inst7.IN0
B => inst1.IN1
B => inst3.IN1
A => inst5.IN0
A => inst2.IN0
A => inst3.IN0
Q1 <= inst1.DB_MAX_OUTPUT_PORT_TYPE
Q2 <= inst2.DB_MAX_OUTPUT_PORT_TYPE
Q3 <= inst3.DB_MAX_OUTPUT_PORT_TYPE

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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611280900987 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611280900991 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:01:40 2021 " "Processing started: Thu Jan 21 20:01:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611280900991 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611280900991 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611280900991 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1611280901215 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1611280901215 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Found entity 1: decoder" { } { { "decoder.bdf" "" { Schematic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611280907273 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611280907273 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "decoder " "Elaborating entity \"decoder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1611280907290 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1611280907580 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1611280907858 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611280907858 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1611280907897 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1611280907897 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1611280907897 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1611280907897 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4788 " "Peak virtual memory: 4788 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611280907912 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:01:47 2021 " "Processing ended: Thu Jan 21 20:01:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611280907912 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611280907912 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611280907912 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1611280907912 ""}

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SOURCE

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611280918793 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611280918797 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:01:58 2021 " "Processing started: Thu Jan 21 20:01:58 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611280918797 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280918797 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta decoder -c decoder " "Command: quartus_sta decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280918797 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280918863 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280918987 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280918987 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919013 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919013 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "decoder.sdc " "Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919199 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919199 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919199 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919200 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919200 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919200 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280919200 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919202 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280919202 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919202 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1611280919202 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919215 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919219 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919223 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919227 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919230 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280919236 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280919255 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920275 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920322 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920333 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920337 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920341 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920343 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920343 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1611280920353 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920476 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920476 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920477 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920477 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920481 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920485 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920489 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920493 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280920497 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280921050 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280921050 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4872 " "Peak virtual memory: 4872 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611280921083 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:02:01 2021 " "Processing ended: Thu Jan 21 20:02:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611280921083 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611280921083 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611280921083 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1611280921083 ""}

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start_analysis_synthesis:s:00:00:08-start_full_compilation
start_analysis_elaboration:s-start_full_compilation

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EE203/Noah Woodlee/Decoder/db/decoder_partition_pins.json Normal file
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@ -0,0 +1,33 @@
{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "Q0",
"strict" : false
},
{
"name" : "Q1",
"strict" : false
},
{
"name" : "Q2",
"strict" : false
},
{
"name" : "Q3",
"strict" : false
},
{
"name" : "B",
"strict" : false
},
{
"name" : "A",
"strict" : false
}
]
}
]
}

409
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@ -0,0 +1,409 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
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(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(connector
(pt 568 248)
(pt 560 248)
)
(connector
(pt 560 248)
(pt 560 304)
)
(connector
(pt 304 280)
(pt 336 280)
)
(connector
(pt 336 304)
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)
(connector
(pt 568 232)
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(connector
(pt 360 512)
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)
(connector
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)
(connector
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)
(connector
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(connector
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(pt 336 464)
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(connector
(pt 568 464)
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)
(connector
(pt 488 464)
(pt 488 416)
)
(connector
(pt 488 416)
(pt 568 416)
)
(connector
(pt 336 464)
(pt 488 464)
)
(connector
(pt 488 464)
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)
(connector
(pt 568 432)
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)
(connector
(pt 456 432)
(pt 456 408)
)
(connector
(pt 480 408)
(pt 456 408)
)
(connector
(pt 456 408)
(pt 432 408)
)
(connector
(pt 568 320)
(pt 528 320)
)
(connector
(pt 528 320)
(pt 528 304)
)
(connector
(pt 560 304)
(pt 528 304)
)
(connector
(pt 528 304)
(pt 432 304)
)
(connector
(pt 360 336)
(pt 568 336)
)
(connector
(pt 360 336)
(pt 360 408)
)
(connector
(pt 360 408)
(pt 360 512)
)
(junction (pt 360 408))
(junction (pt 336 304))
(junction (pt 488 464))
(junction (pt 456 408))
(junction (pt 528 304))

31
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 19:32:30 January 21, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.1"
DATE = "19:32:30 January 21, 2021"
# Revisions
PROJECT_REVISION = "decoder"

61
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 19:32:30 January 21, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# decoder_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY decoder
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:32:30 JANUARY 21, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name BDF_FILE decoder.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_C10 -to A
set_location_assignment PIN_C11 -to B
set_location_assignment PIN_A8 -to Q0
set_location_assignment PIN_A9 -to Q1
set_location_assignment PIN_A10 -to Q2
set_location_assignment PIN_B10 -to Q3
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf

BIN
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
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Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Version_Index = 419480576
Creation_Time = Thu Jan 21 20:01:47 2021

BIN
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v1

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1
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fa8634a97a99232bb4bb1c2e0a376209

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93
EE203/Noah Woodlee/Decoder/output_files/decoder.asm.rpt Normal file
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Assembler report for decoder
Thu Jan 21 20:01:57 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Jan 21 20:01:57 2021 ;
; Revision Name ; decoder ;
; Top-level Entity Name ; decoder ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C7G ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+------------------------------------------------------------------------+
; Assembler Generated Files ;
+------------------------------------------------------------------------+
; File Name ;
+------------------------------------------------------------------------+
; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof ;
+------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof ;
+----------------+---------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------------------------------+
; Device ; 10M50DAF484C7G ;
; JTAG usercode ; 0x0026FF7D ;
; Checksum ; 0x0026FF7D ;
+----------------+---------------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Processing started: Thu Jan 21 20:01:55 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4685 megabytes
Info: Processing ended: Thu Jan 21 20:01:57 2021
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02

1
EE203/Noah Woodlee/Decoder/output_files/decoder.done Normal file
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Thu Jan 21 20:02:01 2021

108
EE203/Noah Woodlee/Decoder/output_files/decoder.eda.rpt Normal file
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@ -0,0 +1,108 @@
EDA Netlist Writer report for decoder
Thu Jan 21 20:12:11 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Thu Jan 21 20:12:11 2021 ;
; Revision Name ; decoder ;
; Top-level Entity Name ; decoder ;
; Family ; MAX 10 ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name ; ModelSim-Altera (Verilog) ;
; Generate functional simulation netlist ; On ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+---------------------------+
+---------------------------------------------------------------------------+
; Simulation Generated Files ;
+---------------------------------------------------------------------------+
; Generated Files ;
+---------------------------------------------------------------------------+
; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//decoder.vo ;
+---------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Intel and sold by Intel or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Thu Jan 21 20:12:11 2021
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file decoder.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4641 megabytes
Info: Processing ended: Thu Jan 21 20:12:11 2021
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

1215
EE203/Noah Woodlee/Decoder/output_files/decoder.fit.rpt Normal file
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8
EE203/Noah Woodlee/Decoder/output_files/decoder.fit.smsg Normal file
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Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

18
EE203/Noah Woodlee/Decoder/output_files/decoder.fit.summary Normal file
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@ -0,0 +1,18 @@
Fitter Status : Successful - Thu Jan 21 20:01:54 2021
Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Revision Name : decoder
Top-level Entity Name : decoder
Family : MAX 10
Device : 10M50DAF484C7G
Timing Models : Final
Total logic elements : 5 / 49,760 ( < 1 % )
Total combinational functions : 5 / 49,760 ( < 1 % )
Dedicated logic registers : 0 / 49,760 ( 0 % )
Total registers : 0
Total pins : 6 / 360 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 1,677,312 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
UFM blocks : 0 / 1 ( 0 % )
ADC blocks : 0 / 2 ( 0 % )

137
EE203/Noah Woodlee/Decoder/output_files/decoder.flow.rpt Normal file
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@ -0,0 +1,137 @@
Flow report for decoder
Thu Jan 21 20:12:11 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Jan 21 20:12:11 2021 ;
; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Revision Name ; decoder ;
; Top-level Entity Name ; decoder ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C7G ;
; Timing Models ; Final ;
; Total logic elements ; 5 / 49,760 ( < 1 % ) ;
; Total combinational functions ; 5 / 49,760 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 6 / 360 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 1,677,312 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 01/21/2021 20:01:41 ;
; Main task ; Compilation ;
; Revision Name ; decoder ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 189559947077153.161128090107632 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 4788 MB ; 00:00:16 ;
; Fitter ; 00:00:06 ; 1.0 ; 5902 MB ; 00:00:08 ;
; Assembler ; 00:00:02 ; 1.0 ; 4685 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4872 MB ; 00:00:02 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:00 ;
; Total ; 00:00:18 ; -- ; -- ; 00:00:28 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+-----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
+---------------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder
quartus_fit --read_settings_files=off --write_settings_files=off decoder -c decoder
quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder
quartus_sta decoder -c decoder
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder

8
EE203/Noah Woodlee/Decoder/output_files/decoder.jdi Normal file
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@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="0c72437d6d88147662ca"/>
</project>
<file_info>
<file device="10M50DAF484C7G" path="decoder.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

284
EE203/Noah Woodlee/Decoder/output_files/decoder.map.rpt Normal file
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@ -0,0 +1,284 @@
Analysis & Synthesis report for decoder
Thu Jan 21 20:01:47 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Post-Synthesis Netlist Statistics for Top Partition
10. Elapsed Time Per Partition
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Jan 21 20:01:47 2021 ;
; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Revision Name ; decoder ;
; Top-level Entity Name ; decoder ;
; Family ; MAX 10 ;
; Total logic elements ; 4 ;
; Total combinational functions ; 4 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 6 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; UFM blocks ; 0 ;
; ADC blocks ; 0 ;
+------------------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 10M50DAF484C7G ; ;
; Top-level entity name ; decoder ; decoder ;
; Family name ; MAX 10 ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; OpenCore Plus hardware evaluation ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 8 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+
; decoder.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf ; ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+
+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
; Estimated Total logic elements ; 4 ;
; ; ;
; Total combinational functions ; 4 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 4 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 4 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 6 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; B~input ;
; Maximum fan-out ; 4 ;
; Total fan-out ; 18 ;
; Average fan-out ; 1.13 ;
+---------------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
; |decoder ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; |decoder ; decoder ; work ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 6 ;
; cycloneiii_lcell_comb ; 5 ;
; normal ; 5 ;
; 1 data inputs ; 1 ;
; 2 data inputs ; 4 ;
; ; ;
; Max LUT depth ; 2.00 ;
; Average LUT depth ; 1.57 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Processing started: Thu Jan 21 20:01:40 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file decoder.bdf
Info (12023): Found entity 1: decoder
Info (12127): Elaborating entity "decoder" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 10 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 4 output pins
Info (21061): Implemented 4 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4788 megabytes
Info: Processing ended: Thu Jan 21 20:01:47 2021
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:16

16
EE203/Noah Woodlee/Decoder/output_files/decoder.map.summary Normal file
View File

@ -0,0 +1,16 @@
Analysis & Synthesis Status : Successful - Thu Jan 21 20:01:47 2021
Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Revision Name : decoder
Top-level Entity Name : decoder
Family : MAX 10
Total logic elements : 4
Total combinational functions : 4
Dedicated logic registers : 0
Total registers : 0
Total pins : 6
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0
UFM blocks : 0
ADC blocks : 0

556
EE203/Noah Woodlee/Decoder/output_files/decoder.pin Normal file
View File

@ -0,0 +1,556 @@
-- Copyright (C) 2016 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Intel and sold by Intel or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1A: 2.5V
-- Bank 1B: 2.5V
-- Bank 2: 2.5V
-- Bank 3: 2.5V
-- Bank 4: 2.5V
-- Bank 5: 2.5V
-- Bank 6: 2.5V
-- Bank 7: 2.5V
-- Bank 8: 2.5V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
CHIP "decoder" ASSIGNED TO AN: 10M50DAF484C7G
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 :
GND : A22 : gnd : : : :
Q1 : AA1 : output : 2.5 V : : 3 : N
Q2 : AA2 : output : 2.5 V : : 3 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 :
GND : AA4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
GND : AA18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
GND : AB1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
GND : AB22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 :
GND : B6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 :
GND : B9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 :
GND : B13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
GND : B18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B :
GND : D4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
GND : D11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
GND : D16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 :
GND : D20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B :
GND : E2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A :
NC : E5 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 :
GND : E7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A :
NC : F6 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N
VCCIO8 : F9 : power : : 2.5V : 8 :
GND : F10 : gnd : : : :
VCCIO8 : F11 : power : : 2.5V : 8 :
VCCIO7 : F12 : power : : 2.5V : 7 :
GND : F13 : gnd : : : :
VCCIO7 : F14 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B :
~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A :
ANAIN1 : G5 : : : : :
GND : G6 : gnd : : : :
VCCD_PLL3 : G7 : power : : 1.2V : :
GND : G8 : gnd : : : :
~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N
VCCIO8 : G10 : power : : 2.5V : 8 :
VCCIO8 : G11 : power : : 2.5V : 8 :
VCCIO7 : G12 : power : : 2.5V : 7 :
VCCIO7 : G13 : power : : 2.5V : 7 :
VCCIO7 : G14 : power : : 2.5V : 7 :
GND : G15 : gnd : : : :
VCCD_PLL2 : G16 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 :
GND : G18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 :
GND : G21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B :
~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A :
REFGND : H5 : : : : :
ADC_VREF : H6 : : : : :
VCCA_ADC : H7 : power : : 2.5V : :
VCCA3 : H8 : power : : 2.5V : :
~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N
~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 :
VCCA2 : H15 : power : : 2.5V : :
VCCIO6 : H16 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B :
GND : J2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A :
ANAIN2 : J5 : : : : :
GND : J6 : gnd : : : :
VCCINT : J7 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 :
GND : J16 : gnd : : : :
VCCIO6 : J17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 :
GND : J19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B :
GND : K3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A :
VCCIO1A : K7 : power : : 2.5V : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B :
GND : K10 : gnd : : : :
VCC : K11 : power : : 1.2V : :
GND : K12 : gnd : : : :
VCC : K13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 :
VCCIO6 : K16 : power : : 2.5V : 6 :
VCCIO6 : K17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B :
DNU : L3 : : : : :
~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N
GND : L5 : gnd : : : :
VCCIO1A : L6 : power : : 2.5V : 1A :
VCCIO1B : L7 : power : : 2.5V : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B :
VCC : L10 : power : : 1.2V : :
VCC : L11 : power : : 1.2V : :
VCC : L12 : power : : 1.2V : :
GND : L13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 :
VCCIO6 : L16 : power : : 2.5V : 6 :
GND : L17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 :
GND : L21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B :
~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N
VCCIO1B : M6 : power : : 2.5V : 1B :
GND : M7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 :
GND : M10 : gnd : : : :
VCC : M11 : power : : 1.2V : :
VCC : M12 : power : : 1.2V : :
VCC : M13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 :
GND : M16 : gnd : : : :
VCCIO6 : M17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 :
GND : M19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 :
VCCIO2 : N6 : power : : 2.5V : 2 :
VCCIO2 : N7 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 :
VCC : N10 : power : : 1.2V : :
GND : N11 : gnd : : : :
VCC : N12 : power : : 1.2V : :
GND : N13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 :
VCCIO5 : N16 : power : : 2.5V : 5 :
VCCIO6 : N17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 :
GND : P2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 :
GND : P6 : gnd : : : :
VCCIO2 : P7 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 :
VCCIO5 : P16 : power : : 2.5V : 5 :
GND : P17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
VCCIO2 : R6 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
VCCA1 : R8 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 :
VCCIO5 : R16 : power : : 2.5V : 5 :
VCCIO5 : R17 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 :
GND : R19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 :
GND : R21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
GND : T4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 :
VCCD_PLL1 : T7 : power : : 1.2V : :
GND : T8 : gnd : : : :
VCCIO3 : T9 : power : : 2.5V : 3 :
VCCIO3 : T10 : power : : 2.5V : 3 :
VCCIO3 : T11 : power : : 2.5V : 3 :
VCCIO4 : T12 : power : : 2.5V : 4 :
VCCIO4 : T13 : power : : 2.5V : 4 :
GND : T14 : gnd : : : :
VCCA4 : T15 : power : : 2.5V : :
GND : T16 : gnd : : : :
VCCIO5 : T17 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 :
Q3 : U7 : output : 2.5 V : : 3 : N
VCCIO3 : U8 : power : : 2.5V : 3 :
VCCIO3 : U9 : power : : 2.5V : 3 :
GND : U10 : gnd : : : :
VCCIO4 : U11 : power : : 2.5V : 4 :
VCCIO4 : U12 : power : : 2.5V : 4 :
GND : U13 : gnd : : : :
VCCIO4 : U14 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 :
VCCD_PLL4 : U16 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
GND : V2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 :
GND : V6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 :
GND : V19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
B : W3 : input : 2.5 V : : 3 : N
A : W4 : input : 2.5 V : : 3 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 :
GND : W21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 :
Q0 : Y2 : output : 2.5 V : : 3 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 :
GND : Y9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 :
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 :
GND : Y15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :

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<sld_project_info/>

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TimeQuest Timing Analyzer report for decoder
Thu Jan 21 20:02:01 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1200mV 85C Model Fmax Summary
6. Slow 1200mV 85C Model Setup Summary
7. Slow 1200mV 85C Model Hold Summary
8. Slow 1200mV 85C Model Recovery Summary
9. Slow 1200mV 85C Model Removal Summary
10. Slow 1200mV 85C Model Minimum Pulse Width Summary
11. Slow 1200mV 85C Model Metastability Summary
12. Slow 1200mV 0C Model Fmax Summary
13. Slow 1200mV 0C Model Setup Summary
14. Slow 1200mV 0C Model Hold Summary
15. Slow 1200mV 0C Model Recovery Summary
16. Slow 1200mV 0C Model Removal Summary
17. Slow 1200mV 0C Model Minimum Pulse Width Summary
18. Slow 1200mV 0C Model Metastability Summary
19. Fast 1200mV 0C Model Setup Summary
20. Fast 1200mV 0C Model Hold Summary
21. Fast 1200mV 0C Model Recovery Summary
22. Fast 1200mV 0C Model Removal Summary
23. Fast 1200mV 0C Model Minimum Pulse Width Summary
24. Fast 1200mV 0C Model Metastability Summary
25. Multicorner Timing Analysis Summary
26. Board Trace Model Assignments
27. Input Transition Times
28. Signal Integrity Metrics (Slow 1200mv 0c Model)
29. Signal Integrity Metrics (Slow 1200mv 85c Model)
30. Signal Integrity Metrics (Fast 1200mv 0c Model)
31. Clock Transfers
32. Report TCCS
33. Report RSKM
34. Unconstrained Paths Summary
35. Unconstrained Input Ports
36. Unconstrained Output Ports
37. Unconstrained Input Ports
38. Unconstrained Output Ports
39. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-----------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Timing Analyzer ; TimeQuest ;
; Revision Name ; decoder ;
; Device Family ; MAX 10 ;
; Device Name ; 10M50DAF484C7G ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 8 ;
; ; ;
; Average used ; 1.01 ;
; Maximum used ; 8 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-8 ; 0.2% ;
+----------------------------+-------------+
----------
; Clocks ;
----------
No clocks to report.
--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Q0 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; Q1 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; Q2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; Q3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+---------------------------------------------------------------------------------+
; Input Transition Times ;
+---------------------+-----------------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------------+-----------------------+-----------------+-----------------+
; B ; 2.5 V ; 2000 ps ; 2000 ps ;
; A ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
+---------------------+-----------------------+-----------------+-----------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ;
; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ;
; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ;
; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 2 ; 2 ;
; Unconstrained Input Port Paths ; 8 ; 8 ;
; Unconstrained Output Ports ; 4 ; 4 ;
; Unconstrained Output Port Paths ; 8 ; 8 ;
+---------------------------------+-------+------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; Q0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; Q0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Processing started: Thu Jan 21 20:01:58 2021
Info: Command: quartus_sta decoder -c decoder
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1200mV 85C Model
Info (332140): No fmax paths to report
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1200mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 4872 megabytes
Info: Processing ended: Thu Jan 21 20:02:01 2021
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02

5
EE203/Noah Woodlee/Decoder/output_files/decoder.sta.summary Normal file
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@ -0,0 +1,5 @@
------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
------------------------------------------------------------

80
EE203/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt Normal file
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@ -0,0 +1,80 @@
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "01/21/2021 20:12:10"
// Verilog Test Bench (with test vectors) for design : decoder
//
// Simulation tool : 3rd Party
//
`timescale 1 ps/ 1 ps
module decoder_vlg_vec_tst();
// constants
// general purpose registers
reg A;
reg B;
// wires
wire Q0;
wire Q1;
wire Q2;
wire Q3;
// assign statements (if any)
decoder i1 (
// port map - connection between master ports and signals/registers
.A(A),
.B(B),
.Q0(Q0),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3)
);
initial
begin
#200000 $finish;
end
// A
initial
begin
A = 1'b0;
A = #10000 1'b1;
A = #20000 1'b0;
A = #30000 1'b1;
A = #30000 1'b0;
A = #60000 1'b1;
A = #10000 1'b0;
end
// B
initial
begin
B = 1'b0;
B = #60000 1'b1;
B = #30000 1'b0;
B = #20000 1'b1;
B = #10000 1'b0;
B = #30000 1'b1;
B = #10000 1'b0;
end
endmodule

17
EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.do Normal file
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@ -0,0 +1,17 @@
onerror {exit -code 1}
vlib work
vlog -work work decoder.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst
vcd file -direction decoder.msim.vcd
vcd add -internal decoder_vlg_vec_tst/*
vcd add -internal decoder_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f

156
EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.msim.vcd Normal file
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@ -0,0 +1,156 @@
$comment
File created using the following command:
vcd file decoder.msim.vcd -direction
$end
$date
Thu Jan 21 20:12:12 2021
$end
$version
ModelSim Version 10.5b
$end
$timescale
1ps
$end
$scope module decoder_vlg_vec_tst $end
$var reg 1 ! A $end
$var reg 1 " B $end
$var wire 1 # Q0 $end
$var wire 1 $ Q1 $end
$var wire 1 % Q2 $end
$var wire 1 & Q3 $end
$scope module i1 $end
$var wire 1 ' gnd $end
$var wire 1 ( vcc $end
$var wire 1 ) unknown $end
$var tri1 1 * devclrn $end
$var tri1 1 + devpor $end
$var tri1 1 , devoe $end
$var wire 1 - ~QUARTUS_CREATED_GND~I_combout $end
$var wire 1 . ~QUARTUS_CREATED_UNVM~~busy $end
$var wire 1 / ~QUARTUS_CREATED_ADC1~~eoc $end
$var wire 1 0 ~QUARTUS_CREATED_ADC2~~eoc $end
$var wire 1 1 Q0~output_o $end
$var wire 1 2 Q1~output_o $end
$var wire 1 3 Q2~output_o $end
$var wire 1 4 Q3~output_o $end
$var wire 1 5 B~input_o $end
$var wire 1 6 A~input_o $end
$var wire 1 7 inst~combout $end
$var wire 1 8 inst2~0_combout $end
$var wire 1 9 inst2~1_combout $end
$var wire 1 : inst2~2_combout $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0!
0"
1#
0$
0%
0&
0'
1(
x)
1*
1+
1,
0-
z.
z/
z0
11
02
03
04
05
06
07
08
09
0:
$end
#10000
1!
16
17
19
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01
0#
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#30000
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06
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09
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11
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#60000
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#90000
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#110000
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15
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#150000
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15
16
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#160000
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06
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04
11
1#
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#200000

1
EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.sft Normal file
View File

@ -0,0 +1 @@
set tool_name "ModelSim-Altera (Verilog)"

383
EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.vo Normal file
View File

@ -0,0 +1,383 @@
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition"
// DATE "01/21/2021 20:12:11"
//
// Device: Altera 10M50DAF484C7G Package FBGA484
//
//
// This Verilog file should be used for ModelSim-Altera (Verilog) only
//
`timescale 1 ps/ 1 ps
module decoder (
Q0,
B,
A,
Q1,
Q2,
Q3);
output Q0;
input B;
input A;
output Q1;
output Q2;
output Q3;
// Design Ports Information
// Q0 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
// Q1 => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default
// Q2 => Location: PIN_AA2, I/O Standard: 2.5 V, Current Strength: Default
// Q3 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default
// B => Location: PIN_W3, I/O Standard: 2.5 V, Current Strength: Default
// A => Location: PIN_W4, I/O Standard: 2.5 V, Current Strength: Default
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \~QUARTUS_CREATED_UNVM~~busy ;
wire \~QUARTUS_CREATED_ADC1~~eoc ;
wire \~QUARTUS_CREATED_ADC2~~eoc ;
wire \Q0~output_o ;
wire \Q1~output_o ;
wire \Q2~output_o ;
wire \Q3~output_o ;
wire \B~input_o ;
wire \A~input_o ;
wire \inst~combout ;
wire \inst2~0_combout ;
wire \inst2~1_combout ;
wire \inst2~2_combout ;
hard_block auto_generated_inst(
.devpor(devpor),
.devclrn(devclrn),
.devoe(devoe));
// Location: LCCOMB_X44_Y42_N8
fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):
// \~QUARTUS_CREATED_GND~I_combout = GND
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.cin(gnd),
.combout(\~QUARTUS_CREATED_GND~I_combout ),
.cout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
// synopsys translate_on
// Location: IOOBUF_X16_Y0_N16
fiftyfivenm_io_obuf \Q0~output (
.i(!\inst~combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\Q0~output_o ),
.obar());
// synopsys translate_off
defparam \Q0~output .bus_hold = "false";
defparam \Q0~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X18_Y0_N30
fiftyfivenm_io_obuf \Q1~output (
.i(\inst2~0_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\Q1~output_o ),
.obar());
// synopsys translate_off
defparam \Q1~output .bus_hold = "false";
defparam \Q1~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X18_Y0_N23
fiftyfivenm_io_obuf \Q2~output (
.i(\inst2~1_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\Q2~output_o ),
.obar());
// synopsys translate_off
defparam \Q2~output .bus_hold = "false";
defparam \Q2~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X16_Y0_N2
fiftyfivenm_io_obuf \Q3~output (
.i(\inst2~2_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\Q3~output_o ),
.obar());
// synopsys translate_off
defparam \Q3~output .bus_hold = "false";
defparam \Q3~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOIBUF_X18_Y0_N8
fiftyfivenm_io_ibuf \B~input (
.i(B),
.ibar(gnd),
.nsleep(vcc),
.o(\B~input_o ));
// synopsys translate_off
defparam \B~input .bus_hold = "false";
defparam \B~input .listen_to_nsleep_signal = "false";
defparam \B~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X18_Y0_N15
fiftyfivenm_io_ibuf \A~input (
.i(A),
.ibar(gnd),
.nsleep(vcc),
.o(\A~input_o ));
// synopsys translate_off
defparam \A~input .bus_hold = "false";
defparam \A~input .listen_to_nsleep_signal = "false";
defparam \A~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LCCOMB_X18_Y1_N0
fiftyfivenm_lcell_comb inst(
// Equation(s):
// \inst~combout = (\B~input_o ) # (\A~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\B~input_o ),
.datad(\A~input_o ),
.cin(gnd),
.combout(\inst~combout ),
.cout());
// synopsys translate_off
defparam inst.lut_mask = 16'hFFF0;
defparam inst.sum_lutc_input = "datac";
// synopsys translate_on
// Location: LCCOMB_X18_Y1_N2
fiftyfivenm_lcell_comb \inst2~0 (
// Equation(s):
// \inst2~0_combout = (\B~input_o & !\A~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\B~input_o ),
.datad(\A~input_o ),
.cin(gnd),
.combout(\inst2~0_combout ),
.cout());
// synopsys translate_off
defparam \inst2~0 .lut_mask = 16'h00F0;
defparam \inst2~0 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: LCCOMB_X18_Y1_N4
fiftyfivenm_lcell_comb \inst2~1 (
// Equation(s):
// \inst2~1_combout = (!\B~input_o & \A~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\B~input_o ),
.datad(\A~input_o ),
.cin(gnd),
.combout(\inst2~1_combout ),
.cout());
// synopsys translate_off
defparam \inst2~1 .lut_mask = 16'h0F00;
defparam \inst2~1 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: LCCOMB_X18_Y1_N6
fiftyfivenm_lcell_comb \inst2~2 (
// Equation(s):
// \inst2~2_combout = (\B~input_o & \A~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\B~input_o ),
.datad(\A~input_o ),
.cin(gnd),
.combout(\inst2~2_combout ),
.cout());
// synopsys translate_off
defparam \inst2~2 .lut_mask = 16'hF000;
defparam \inst2~2 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: UNVM_X0_Y40_N40
fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
.arclk(vcc),
.arshft(vcc),
.drclk(vcc),
.drshft(vcc),
.drdin(vcc),
.nprogram(vcc),
.nerase(vcc),
.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
.par_en(vcc),
.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
.se(\~QUARTUS_CREATED_GND~I_combout ),
.ardin(23'b11111111111111111111111),
.busy(\~QUARTUS_CREATED_UNVM~~busy ),
.osc(),
.bgpbusy(),
.sp_pass(),
.se_pass(),
.drdout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
// synopsys translate_on
// Location: ADCBLOCK_X43_Y52_N0
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
.soc(\~QUARTUS_CREATED_GND~I_combout ),
.usr_pwd(vcc),
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
.clkin_from_pll_c0(gnd),
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
.dout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
// synopsys translate_on
// Location: ADCBLOCK_X43_Y51_N0
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
.soc(\~QUARTUS_CREATED_GND~I_combout ),
.usr_pwd(vcc),
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
.clkin_from_pll_c0(gnd),
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
.dout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
// synopsys translate_on
assign Q0 = \Q0~output_o ;
assign Q1 = \Q1~output_o ;
assign Q2 = \Q2~output_o ;
assign Q3 = \Q3~output_o ;
endmodule
module hard_block (
devpor,
devclrn,
devoe);
// Design Ports Information
// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
input devpor;
input devclrn;
input devoe;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
wire \~ALTERA_TMS~~padout ;
wire \~ALTERA_TCK~~padout ;
wire \~ALTERA_TDI~~padout ;
wire \~ALTERA_CONFIG_SEL~~padout ;
wire \~ALTERA_nCONFIG~~padout ;
wire \~ALTERA_nSTATUS~~padout ;
wire \~ALTERA_CONF_DONE~~padout ;
wire \~ALTERA_TMS~~ibuf_o ;
wire \~ALTERA_TCK~~ibuf_o ;
wire \~ALTERA_TDI~~ibuf_o ;
wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
wire \~ALTERA_nCONFIG~~ibuf_o ;
wire \~ALTERA_nSTATUS~~ibuf_o ;
wire \~ALTERA_CONF_DONE~~ibuf_o ;
endmodule

255
EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201117.sim.vwf Normal file
View File

@ -0,0 +1,255 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 200.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("A")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("B")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Q0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q3")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("A")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 40.0;
}
}
}
TRANSITION_LIST("B")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 40.0;
}
}
}
TRANSITION_LIST("Q0")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 40.0;
}
}
}
TRANSITION_LIST("Q1")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 200.0;
}
}
}
TRANSITION_LIST("Q2")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 170.0;
}
}
}
TRANSITION_LIST("Q3")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 40.0;
}
}
}
DISPLAY_LINE
{
CHANNEL = "A";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "B";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Q0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Q1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Q2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Q3";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

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